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[PPC] Change the register constraint of the first source operand of instruction mtvsrdd to g8rc_nox0
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Authored by Carrot on May 4 2017, 2:01 PM.

Details

Summary

According to Power ISA V3.0 document, the first source operand of mtvsrdd is constant 0 if r0 is specified. So the corresponding register constraint should be g8rc_nox0.

This bug caused wrong output generated by 401.bzip2 when -mcpu=power9 and fdo are specified.

Diff Detail

Event Timeline

Carrot created this revision.May 4 2017, 2:01 PM

We should definitely get this committed. Is it of any value to add a test case for the changes to the disassembler?

lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
207

How come this wasn't needed before and is needed now?

echristo edited edge metadata.May 9 2017, 3:04 PM

Seems useful for a disassembler change (feel free to make it separately as well if there's no visible change here).

-eric

Carrot updated this revision to Diff 98542.May 10 2017, 3:14 PM

Add a test case for disassembling mtvsrdd.

lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
207

I don't know.
After making the instruction pattern change, I got a compile time error, it complained function DecodeG8RC_NOX0RegisterClass not found. So I made the disassembler change.

If you can come up with a .ll testcase for the register class change that would be good. I'd like to get this in so don't spend a huge amount of time trying to reduce something.

Carrot updated this revision to Diff 98669.May 11 2017, 1:09 PM

Add a test case for mtvsrdd.

This revision was automatically updated to reflect the committed changes.