[PPC] Change the register constraint of the first source operand of instruction mtvsrdd to g8rc_nox0

[Carrot]

Summary

According to Power ISA V3.0 document, the first source operand of mtvsrdd is constant 0 if r0 is specified. So the corresponding register constraint should be g8rc_nox0.

This bug caused wrong output generated by 401.bzip2 when -mcpu=power9 and fdo are specified.

[nemanjai]

We should definitely get this committed. Is it of any value to add a test case for the changes to the disassembler?

lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp

207 ↗

(On Diff #97872)

How come this wasn't needed before and is needed now?

[echristo]

Seems useful for a disassembler change (feel free to make it separately as well if there's no visible change here).

-eric

[Carrot]

Add a test case for disassembling mtvsrdd.

lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp

207 ↗

(On Diff #97872)

I don't know.
After making the instruction pattern change, I got a compile time error, it complained function DecodeG8RC_NOX0RegisterClass not found. So I made the disassembler change.

[echristo]

If you can come up with a .ll testcase for the register class change that would be good. I'd like to get this in so don't spend a huge amount of time trying to reduce something.

[Carrot]

Add a test case for mtvsrdd.

llvm/trunk/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp

static const unsigned G8Regs[] = {
   PPC::X8, PPC::X9, PPC::X10, PPC::X11,
   PPC::X12, PPC::X13, PPC::X14, PPC::X15,
   PPC::X16, PPC::X17, PPC::X18, PPC::X19,
   PPC::X20, PPC::X21, PPC::X22, PPC::X23,
   PPC::X24, PPC::X25, PPC::X26, PPC::X27,
   PPC::X28, PPC::X29, PPC::X30, PPC::X31
 };
 
+static const unsigned G80Regs[] = {
+  PPC::ZERO8, PPC::X1, PPC::X2, PPC::X3,
+  PPC::X4, PPC::X5, PPC::X6, PPC::X7,
+  PPC::X8, PPC::X9, PPC::X10, PPC::X11,
+  PPC::X12, PPC::X13, PPC::X14, PPC::X15,
+  PPC::X16, PPC::X17, PPC::X18, PPC::X19,
+  PPC::X20, PPC::X21, PPC::X22, PPC::X23,
+  PPC::X24, PPC::X25, PPC::X26, PPC::X27,
+  PPC::X28, PPC::X29, PPC::X30, PPC::X31
+};
+
 static const unsigned QFRegs[] = {
   PPC::QF0, PPC::QF1, PPC::QF2, PPC::QF3,
   PPC::QF4, PPC::QF5, PPC::QF6, PPC::QF7,
   PPC::QF8, PPC::QF9, PPC::QF10, PPC::QF11,
   PPC::QF12, PPC::QF13, PPC::QF14, PPC::QF15,
   PPC::QF16, PPC::QF17, PPC::QF18, PPC::QF19,
   PPC::QF20, PPC::QF21, PPC::QF22, PPC::QF23,
   PPC::QF24, PPC::QF25, PPC::QF26, PPC::QF27,

 }
 
 static DecodeStatus DecodeG8RCRegisterClass(MCInst &Inst, uint64_t RegNo,
                                             uint64_t Address,
                                             const void *Decoder) {
   return decodeRegisterClass(Inst, RegNo, G8Regs);
 }
 
+static DecodeStatus DecodeG8RC_NOX0RegisterClass(MCInst &Inst, uint64_t RegNo,
+                                            uint64_t Address,
+                                            const void *Decoder) {
+  return decodeRegisterClass(Inst, RegNo, G80Regs);
+}
+
 #define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass
 #define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass
 
 static DecodeStatus DecodeQFRCRegisterClass(MCInst &Inst, uint64_t RegNo,
                                             uint64_t Address,
                                             const void *Decoder) {
   return decodeRegisterClass(Inst, RegNo, QFRegs);
 }

llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td

def MTVSRWZ : XX1_RS6_RD5_XO<31, 243, (outs vsfrc:$XT), (ins gprc:$rA),
                                "mtvsrwz $XT, $rA", IIC_VecGeneral,
                                [(set f64:$XT, (PPCmtvsrz i32:$rA))]>;
 } // HasDirectMove
 
 let Predicates = [IsISA3_0, HasDirectMove] in {
   def MTVSRWS: XX1_RS6_RD5_XO<31, 403, (outs vsrc:$XT), (ins gprc:$rA),
                               "mtvsrws $XT, $rA", IIC_VecGeneral, []>;
 
-  def MTVSRDD: XX1Form<31, 435, (outs vsrc:$XT), (ins g8rc:$rA, g8rc:$rB),
+  def MTVSRDD: XX1Form<31, 435, (outs vsrc:$XT), (ins g8rc_nox0:$rA, g8rc:$rB),
                        "mtvsrdd $XT, $rA, $rB", IIC_VecGeneral,
                        []>, Requires<[In64BitMode]>;
 
   def MFVSRLD: XX1_RS6_RD5_XO<31, 307, (outs g8rc:$rA), (ins vsrc:$XT),
                               "mfvsrld $rA, $XT", IIC_VecGeneral,
                               []>, Requires<[In64BitMode]>;
 
 } // IsISA3_0, HasDirectMove

llvm/trunk/test/CodeGen/PowerPC/mtvsrdd.ll

+; RUN: llc -mcpu=pwr9 -ppc-vsr-nums-as-vr -mtriple=powerpc64le-unknown-unknown \
+; RUN:   < %s | FileCheck %s
+
+; This test case checks r0 is used as constant 0 in instruction mtvsrdd.
+
+define <2 x i64> @const0(i64 %a) {
+  %vecinit = insertelement <2 x i64> undef, i64 %a, i32 0
+  %vecinit1 = insertelement <2 x i64> %vecinit, i64 0, i32 1
+  ret <2 x i64> %vecinit1
+; CHECK-LABEL: const0
+; CHECK: mtvsrdd v2, 0, r3
+}
+
+define <2 x i64> @noconst0(i64* %a, i64* %b) {
+  %1 = load i64, i64* %a, align 8
+  %2 = load i64, i64* %b, align 8
+  %vecinit = insertelement <2 x i64> undef, i64 %2, i32 0
+  %vecinit1 = insertelement <2 x i64> %vecinit, i64 %1, i32 1
+  ret <2 x i64> %vecinit1
+; CHECK-LABEL: noconst0
+; CHECK: mtvsrdd v2, {{r[0-9]+}}, {{r[0-9]+}}
+}

llvm/trunk/test/MC/Disassembler/PowerPC/ppc64-encoding-p9vector.txt

+# RUN: llvm-mc --disassemble %s -triple powerpc64le-unknown-unknown -mcpu=pwr9 | FileCheck %s
+
+# CHECK: mtvsrdd 6, 0, 3
+0x66 0x1b 0xc0 0x7c