Reduce printing values with default in MIR based codegen testing YAML

[vivekvpandya]

Summary

I found that all values that have optional mapping will not be printed by YAML Output if its value is equal to default value.
So I have tried out this on MachineFrameInfo object and this works as per expectation.
It just prints 'frameInfo:' tag in YAML file with out any fields.
If we are agree on this I will update other objects mapping to have similar behavior.
I will update this patch so that if all properties of object is not printed then its name should not be printed as that causes MIR test failure in llvm-lit.

[MatzeB]

Yes this looks like a good way to reduce the output and like a sensible first step.

I tried this patch and it obviously needs some test cases adjusted. It also seems that printing frameInfo: without any following fields is invalid YAML so that we probably need some fixes in YamlIO to leave out the complete frameInfo: header in case all fields have their default values.

(And for long term/later commits: Some properties like "hasStackMap", "hasPatchPoint", "hasCalls"... look like we should be able to just compute them instead of printing/reading them.)

[vivekvpandya]

As YAML will first process frameInfo object so it is not easy to remove "frameInfo" from output after finding it's empty. However if we provide default value for frameInfo mapping in MachineFunction class then we can eliminate it from output if entire frameInfo is having default value. So I have update the patch accordingly. If this approach seems good then I can send updated patch for all option mapping.

[vivekvpandya]

This comment was removed by vivekvpandya.

[MatzeB]

LGTM, provided it passes the lit tests.

[vivekvpandya]

Ok I will update this for all optional mapping and then do testing on existing mir test files in various target folders.

[vivekvpandya]

Hi Matthias,

I have updated this patch to all optional mappings in MIR-YAML mapping. I have also updated X86 MIR test-cases which were failing as default values not getting printed. How ever there may be some code which is not really required. Also I will update the patch after testing it for other targets. But in meantime kindly look at changes and provide your feedbacks.

[MatzeB]

include/llvm/CodeGen/MIRYamlMapping.h

75

This can be const. Same thing for several of the following operator== implementations.

test/CodeGen/MIR/Generic/frame-info.mir

35–45

So nice to see this all go away :)

[qcolombet]

Hi guys,

I am not sure I like the approach.
I agree that as a human the among of MIR we need to write to make it work should be minimal. However, I believe the printer should be as dumb as possible. Printing is cheap and also, anytime the default changes, the printed output would still work.

I have the same reasoning for anything that can be computed from the input, like the live-ins, successors and so on.

The bottom line is I am in favor of a smart parser, but not a smart printer.

Cheers,
-Quentin

test/CodeGen/MIR/Generic/frame-info.mir

35–45

FWIW, it could go away in the test without having it go away from the printed output.

[vivekvpandya]

In D32304#742192, @qcolombet wrote:

Hi guys,

Hello @qcolombet

I am not sure I like the approach.
I agree that as a human the among of MIR we need to write to make it work should be minimal. However, I believe the printer should be as dumb as possible. Printing is cheap and also, anytime the default changes, the printed output would still work.

I am new to this thing but I would like to have my input from what ever I have understood till now.
I think not printing entities which have default value is useful when someone wants to write a new MIR test file by starting with llc generating a initial version, adding required check statements and other commands to it.
Also if someone prefers to have default values printed then we can provide a flag in llc that will map to WriteDefaultValues in YAMLTraits ( as llvm-pdbdump tool does it currently).
After having quick look at MIRParser I feel that with syntactically correct YAML it will create MachineFunction , entities which are missing from YAML input will have default value.
If default value changes then printer will just print it (as it may not be updated in MIRYAMLMapping.h ) but nothing will break.
I feel that challenges with default value will come when it is not possible to get default value for some target specific entity.

Sincerely,
Vivek

I have the same reasoning for anything that can be computed from the input, like the live-ins, successors and so on.

The bottom line is I am in favor of a smart parser, but not a smart printer.

Cheers,
-Quentin

[vivekvpandya]

Update the patch as per discussion.

[qcolombet]

lib/CodeGen/MIRPrintingPass.cpp

27 ↗

(On Diff #97716)

@MatzeB already created an option in D31262. Sync your patch with that one.

[vivekvpandya]

-simplify-mir is not true by default so there is no need to change mir test cases which were modified previously.

[vivekvpandya]

ping!

[qcolombet]

LGTM

[vivekvpandya]

I don't have commit access. Kindly commit it. Sorry for the trouble.

[MatzeB]

In D32304#752441, @vivekvpandya wrote:

I don't have commit access. Kindly commit it. Sorry for the trouble.

I think it's time that you ask Chris for it as you have a few patches in by now (see http://llvm.org/docs/DeveloperPolicy.html#obtaining-commit-access )

[nemanjai]

This appears to have broken MANY buildbots due to some compilation error that I haven't really looked at. I'll wait a bit longer to see if you (@vivekvpandya) pull it out/fix it and if it doesn't happen soon, I'll probably just pull it out.

[vivekvpandya]

In D32304#754075, @nemanjai wrote:

This appears to have broken MANY buildbots due to some compilation error that I haven't really looked at. I'll wait a bit longer to see if you (@vivekvpandya) pull it out/fix it and if it doesn't happen soon, I'll probably just pull it out.

I have reverted it on my SVN. Should I commit again with message "Revert my revisionID" to reflect that on llvm.org/svn ?

[vivekvpandya]

In previous patch constant used to set default value for object property of type int64_t , uint64_t was not portable.
Due to

if (!SimplifyMIR)
      Out.setWriteDefaultValues(true);

some test cases need to be updated. Sorry previously I didn't run llvm-lit on whole test folder.

Please provide reviews.
-Vivek

[vivekvpandya]

Also is there any way to test patch on build bot with out committing changes specially on different hardware?

[MatzeB]

In D32304#754327, @vivekvpandya wrote:

Also is there any way to test patch on build bot with out committing changes specially on different hardware?

No, we don't have infrastructure for pre-commit testing. It usually comes down to:

• Ensure that your patches are correct before committing. This of course can only be done up to some reasonable level, this usually means running ninja check-llvm if your patch is more complicated or touches unusual corner cases then it may be a good idea to think about what else you could test.
• Watch the buildbot emails coming back. It is sometimes tricky to figure out if it was really your patch that broke it. If in doubt talk with the other people on the blamelist, check the bot history for similar failures in case of flaky tests, ...
• If you believe your commit may be responsible: If you have a safe easy fix that you can apply within a short time (I usually aim for no longer than an hour) then go for that. In all other cases revert your commit! The goal here must be to get the bot back to green as fast as possible to avoid other errors going by unnoticed because the bot was red anyway.

[MatzeB]

In D32304#754324, @vivekvpandya wrote:

In previous patch constant used to set default value for object property of type int64_t , uint64_t was not portable.
Due to

if (!SimplifyMIR)
      Out.setWriteDefaultValues(true);

some test cases need to be updated. Sorry previously I didn't run llvm-lit on whole test folder.

I don't understand this explanation. Can you give some example? It feels odd that you had to add -simplify-mir to all of those tests...

[vivekvpandya]

In D32304#755329, @MatzeB wrote:

In D32304#754324, @vivekvpandya wrote:

In previous patch constant used to set default value for object property of type int64_t , uint64_t was not portable.
Due to

if (!SimplifyMIR)
      Out.setWriteDefaultValues(true);

some test cases need to be updated. Sorry previously I didn't run llvm-lit on whole test folder.

I don't understand this explanation. Can you give some example? It feels odd that you had to add -simplify-mir to all of those tests...

If we make YAML:IO to write default values it will print every things including empty strings, for example consider test/CodeGen/X86/virtual-registers*.ll in that if we don't use -simplify-mir it will generate - { reg: '%edi', virtual-reg: '' } which makes POST-RA-NEXT check failed. This is why I have added -simplify-mir where required.
However in test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll I think adding -simplify-mir is not correct because it also removes basic block printing and for that particular case it is required that only one successor is present after certain statement so for that case I need to add fields which were not getting printed before but now they are getting printed.
Also before this patch we already do not print string with empty value so all these test-cases have been written in such manner that check for filed with empty string is not done so to preserve that I added -simplify-mir. Or we need to other way around.

I will keep your suggestions related to testing and committing in mind.

[vivekvpandya]

ping!

[vivekvpandya]

Ping!

[MatzeB]

If we make YAML:IO to write default values it will print every things including empty strings, for example consider test/CodeGen/X86/virtual-registers*.ll in that if we don't use -simplify-mir it will generate - { reg: '%edi', virtual-reg: '' } which makes POST-RA-NEXT check failed. This is why I have added -simplify-mir where required.
However in test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll I think adding -simplify-mir is not correct because it also removes basic block printing and for that particular case it is required that only one successor is present after certain statement so for that case I need to add fields which were not getting printed before but now they are getting printed.
Also before this patch we already do not print string with empty value so all these test-cases have been written in such manner that check for filed with empty string is not done so to preserve that I added -simplify-mir. Or we need to other way around.

Argh that is unfortunate. However after settling on printing everything by default I think the conclusion here is to rather adapt the CHECK: statements in the tests than switching a whole lot of tests to a non-default output mode. Of course we should keep some test with -simplify-mir around to make sure that mode works.

I will keep your suggestions related to testing and committing in mind.

Sure, we are all breaking the build from time to time. Good that you reverted in time.

[vivekvpandya]

@MatzeB sorry for the delay I was on vacation. I have updated the patch as per your suggestion. Due to GlobalIsel related work some test cases have some updates frequently so it is better to close this as earliest as possible.

[MatzeB]

LGTM, thanks for doing all those fixups in the tests!

include/llvm/CodeGen/MIRYamlMapping.h

static StringRef input(StringRef Scalar, void *Ctx, FlowStringValue &S) {
     return ScalarTraits<StringValue>::input(Scalar, Ctx, S);
   }
 
   static bool mustQuote(StringRef Scalar) { return needsQuotes(Scalar); }
 };
 
 struct BlockStringValue {
   StringValue Value;
+  bool operator==(const BlockStringValue &Other) const {
+    return Value == Other.Value;
+  }
 };
 
 template <> struct BlockScalarTraits<BlockStringValue> {
   static void output(const BlockStringValue &S, void *Ctx, raw_ostream &OS) {
     return ScalarTraits<StringValue>::output(S.Value, Ctx, OS);
   }
 
   static StringRef input(StringRef Scalar, void *Ctx, BlockStringValue &S) {

 namespace llvm {
 namespace yaml {
 
 struct VirtualRegisterDefinition {
   UnsignedValue ID;
   StringValue Class;
   StringValue PreferredRegister;
   // TODO: Serialize the target specific register hints.
+  bool operator==(const VirtualRegisterDefinition &Other) const {
+    return ID == Other.ID && Class == Other.Class &&
+           PreferredRegister == Other.PreferredRegister;
+  }
 };
 
 template <> struct MappingTraits<VirtualRegisterDefinition> {
   static void mapping(IO &YamlIO, VirtualRegisterDefinition &Reg) {
     YamlIO.mapRequired("id", Reg.ID);
     YamlIO.mapRequired("class", Reg.Class);
     YamlIO.mapOptional("preferred-register", Reg.PreferredRegister,
                        StringValue()); // Don't print out when it's empty.
   }
 
   static const bool flow = true;
 };
 
 struct MachineFunctionLiveIn {
   StringValue Register;
   StringValue VirtualRegister;
+  bool operator==(const MachineFunctionLiveIn &Other) const {
+    return Register == Other.Register &&
+           VirtualRegister == Other.VirtualRegister;
+  }
 };
 
 template <> struct MappingTraits<MachineFunctionLiveIn> {
   static void mapping(IO &YamlIO, MachineFunctionLiveIn &LiveIn) {
     YamlIO.mapRequired("reg", LiveIn.Register);
     YamlIO.mapOptional(
         "virtual-reg", LiveIn.VirtualRegister,
         StringValue()); // Don't print the virtual register when it's empty.
struct MachineStackObject {
   int64_t Offset = 0;
   uint64_t Size = 0;
   unsigned Alignment = 0;
   StringValue CalleeSavedRegister;
   Optional<int64_t> LocalOffset;
   StringValue DebugVar;
   StringValue DebugExpr;
   StringValue DebugLoc;
+  bool operator==(const MachineStackObject &Other) const {
+    return ID == Other.ID && Name == Other.Name && Type == Other.Type &&
+           Offset == Other.Offset && Size == Other.Size &&
+           Alignment == Other.Alignment &&
+           CalleeSavedRegister == Other.CalleeSavedRegister &&
+           LocalOffset == Other.LocalOffset && DebugVar == Other.DebugVar &&
+           DebugExpr == Other.DebugExpr && DebugLoc == Other.DebugLoc;
+  }
 };
 
 template <> struct ScalarEnumerationTraits<MachineStackObject::ObjectType> {
   static void enumeration(yaml::IO &IO, MachineStackObject::ObjectType &Type) {
     IO.enumCase(Type, "default", MachineStackObject::DefaultType);
     IO.enumCase(Type, "spill-slot", MachineStackObject::SpillSlot);
     IO.enumCase(Type, "variable-sized", MachineStackObject::VariableSized);
   }
 };
 
 template <> struct MappingTraits<MachineStackObject> {
   static void mapping(yaml::IO &YamlIO, MachineStackObject &Object) {
     YamlIO.mapRequired("id", Object.ID);
     YamlIO.mapOptional("name", Object.Name,
                        StringValue()); // Don't print out an empty name.
     YamlIO.mapOptional(
         "type", Object.Type,
         MachineStackObject::DefaultType); // Don't print the default type.
-    YamlIO.mapOptional("offset", Object.Offset);
+    YamlIO.mapOptional("offset", Object.Offset, (int64_t)0);
     if (Object.Type != MachineStackObject::VariableSized)
       YamlIO.mapRequired("size", Object.Size);
-    YamlIO.mapOptional("alignment", Object.Alignment);
+    YamlIO.mapOptional("alignment", Object.Alignment, (unsigned)0);
     YamlIO.mapOptional("callee-saved-register", Object.CalleeSavedRegister,
                        StringValue()); // Don't print it out when it's empty.
-    YamlIO.mapOptional("local-offset", Object.LocalOffset);
+    YamlIO.mapOptional("local-offset", Object.LocalOffset, Optional<int64_t>());
     YamlIO.mapOptional("di-variable", Object.DebugVar,
                        StringValue()); // Don't print it out when it's empty.
     YamlIO.mapOptional("di-expression", Object.DebugExpr,
                        StringValue()); // Don't print it out when it's empty.
     YamlIO.mapOptional("di-location", Object.DebugLoc,
                        StringValue()); // Don't print it out when it's empty.
   }
 
   static const bool flow = true;
 };
 
 /// Serializable representation of the fixed stack object from the
 /// MachineFrameInfo class.
 struct FixedMachineStackObject {
   enum ObjectType { DefaultType, SpillSlot };
   UnsignedValue ID;
   ObjectType Type = DefaultType;
   int64_t Offset = 0;
   uint64_t Size = 0;
   unsigned Alignment = 0;
   bool IsImmutable = false;
   bool IsAliased = false;
   StringValue CalleeSavedRegister;
+  bool operator==(const FixedMachineStackObject &Other) const {
+    return ID == Other.ID && Type == Other.Type && Offset == Other.Offset &&
+           Size == Other.Size && Alignment == Other.Alignment &&
+           IsImmutable == Other.IsImmutable && IsAliased == Other.IsAliased &&
+           CalleeSavedRegister == Other.CalleeSavedRegister;
+  }
 };
 
 template <>
 struct ScalarEnumerationTraits<FixedMachineStackObject::ObjectType> {
   static void enumeration(yaml::IO &IO,
                           FixedMachineStackObject::ObjectType &Type) {
     IO.enumCase(Type, "default", FixedMachineStackObject::DefaultType);
     IO.enumCase(Type, "spill-slot", FixedMachineStackObject::SpillSlot);
   }
 };
 
 template <> struct MappingTraits<FixedMachineStackObject> {
   static void mapping(yaml::IO &YamlIO, FixedMachineStackObject &Object) {
     YamlIO.mapRequired("id", Object.ID);
     YamlIO.mapOptional(
         "type", Object.Type,
         FixedMachineStackObject::DefaultType); // Don't print the default type.
-    YamlIO.mapOptional("offset", Object.Offset);
-    YamlIO.mapOptional("size", Object.Size);
-    YamlIO.mapOptional("alignment", Object.Alignment);
+    YamlIO.mapOptional("offset", Object.Offset, (int64_t)0);
+    YamlIO.mapOptional("size", Object.Size, (uint64_t)0);
+    YamlIO.mapOptional("alignment", Object.Alignment, (unsigned)0);
     if (Object.Type != FixedMachineStackObject::SpillSlot) {
-      YamlIO.mapOptional("isImmutable", Object.IsImmutable);
-      YamlIO.mapOptional("isAliased", Object.IsAliased);
+      YamlIO.mapOptional("isImmutable", Object.IsImmutable, false);
+      YamlIO.mapOptional("isAliased", Object.IsAliased, false);
     }
     YamlIO.mapOptional("callee-saved-register", Object.CalleeSavedRegister,
                        StringValue()); // Don't print it out when it's empty.
   }
 
   static const bool flow = true;
 };
 
 struct MachineConstantPoolValue {
   UnsignedValue ID;
   StringValue Value;
   unsigned Alignment = 0;
+  bool operator==(const MachineConstantPoolValue &Other) const {
+    return ID == Other.ID && Value == Other.Value &&
+           Alignment == Other.Alignment;
+  }
 };
 
 template <> struct MappingTraits<MachineConstantPoolValue> {
   static void mapping(IO &YamlIO, MachineConstantPoolValue &Constant) {
     YamlIO.mapRequired("id", Constant.ID);
-    YamlIO.mapOptional("value", Constant.Value);
-    YamlIO.mapOptional("alignment", Constant.Alignment);
+    YamlIO.mapOptional("value", Constant.Value, StringValue());
+    YamlIO.mapOptional("alignment", Constant.Alignment, (unsigned)0);
   }
 };
 
 struct MachineJumpTable {
   struct Entry {
     UnsignedValue ID;
     std::vector<FlowStringValue> Blocks;
+    bool operator==(const Entry &Other) const {
+      return ID == Other.ID && Blocks == Other.Blocks;
+    }
   };
 
   MachineJumpTableInfo::JTEntryKind Kind = MachineJumpTableInfo::EK_Custom32;
   std::vector<Entry> Entries;
+  bool operator==(const MachineJumpTable &Other) const {
+    return Kind == Other.Kind && Entries == Other.Entries;
+  }
 };
 
 template <> struct MappingTraits<MachineJumpTable::Entry> {
   static void mapping(IO &YamlIO, MachineJumpTable::Entry &Entry) {
     YamlIO.mapRequired("id", Entry.ID);
-    YamlIO.mapOptional("blocks", Entry.Blocks);
+    YamlIO.mapOptional("blocks", Entry.Blocks, std::vector<FlowStringValue>());
   }
 };
 
 } // end namespace yaml
 } // end namespace llvm
 
 LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::yaml::MachineFunctionLiveIn)
 LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::yaml::VirtualRegisterDefinition)
 LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::yaml::MachineStackObject)
 LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::yaml::FixedMachineStackObject)
 LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::yaml::MachineConstantPoolValue)
 LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::yaml::MachineJumpTable::Entry)
 
 namespace llvm {
 namespace yaml {
 
 template <> struct MappingTraits<MachineJumpTable> {
   static void mapping(IO &YamlIO, MachineJumpTable &JT) {
     YamlIO.mapRequired("kind", JT.Kind);
-    YamlIO.mapOptional("entries", JT.Entries);
+    YamlIO.mapOptional("entries", JT.Entries,
+                       std::vector<MachineJumpTable::Entry>());
   }
 };
 
 /// Serializable representation of MachineFrameInfo.
 ///
 /// Doesn't serialize attributes like 'StackAlignment', 'IsStackRealignable' and
 /// 'RealignOption' as they are determined by the target and LLVM function
 /// attributes.
struct MachineFrameInfo {
   StringValue StackProtector;
   // TODO: Serialize FunctionContextIdx
   unsigned MaxCallFrameSize = ~0u; ///< ~0u means: not computed yet.
   bool HasOpaqueSPAdjustment = false;
   bool HasVAStart = false;
   bool HasMustTailInVarArgFunc = false;
   StringValue SavePoint;
   StringValue RestorePoint;
+  bool operator==(const MachineFrameInfo &Other) const {
+    return IsFrameAddressTaken == Other.IsFrameAddressTaken &&
+           IsReturnAddressTaken == Other.IsReturnAddressTaken &&
+           HasStackMap == Other.HasStackMap &&
+           HasPatchPoint == Other.HasPatchPoint &&
+           StackSize == Other.StackSize &&
+           OffsetAdjustment == Other.OffsetAdjustment &&
+           MaxAlignment == Other.MaxAlignment &&
+           AdjustsStack == Other.AdjustsStack && HasCalls == Other.HasCalls &&
+           StackProtector == Other.StackProtector &&
+           MaxCallFrameSize == Other.MaxCallFrameSize &&
+           HasOpaqueSPAdjustment == Other.HasOpaqueSPAdjustment &&
+           HasVAStart == Other.HasVAStart &&
+           HasMustTailInVarArgFunc == Other.HasMustTailInVarArgFunc &&
+           SavePoint == Other.SavePoint && RestorePoint == Other.RestorePoint;
+  }
 };
 
 template <> struct MappingTraits<MachineFrameInfo> {
   static void mapping(IO &YamlIO, MachineFrameInfo &MFI) {
-    YamlIO.mapOptional("isFrameAddressTaken", MFI.IsFrameAddressTaken);
-    YamlIO.mapOptional("isReturnAddressTaken", MFI.IsReturnAddressTaken);
-    YamlIO.mapOptional("hasStackMap", MFI.HasStackMap);
-    YamlIO.mapOptional("hasPatchPoint", MFI.HasPatchPoint);
-    YamlIO.mapOptional("stackSize", MFI.StackSize);
-    YamlIO.mapOptional("offsetAdjustment", MFI.OffsetAdjustment);
-    YamlIO.mapOptional("maxAlignment", MFI.MaxAlignment);
-    YamlIO.mapOptional("adjustsStack", MFI.AdjustsStack);
-    YamlIO.mapOptional("hasCalls", MFI.HasCalls);
+    YamlIO.mapOptional("isFrameAddressTaken", MFI.IsFrameAddressTaken, false);
+    YamlIO.mapOptional("isReturnAddressTaken", MFI.IsReturnAddressTaken, false);
+    YamlIO.mapOptional("hasStackMap", MFI.HasStackMap, false);
+    YamlIO.mapOptional("hasPatchPoint", MFI.HasPatchPoint, false);
+    YamlIO.mapOptional("stackSize", MFI.StackSize, (uint64_t)0);
+    YamlIO.mapOptional("offsetAdjustment", MFI.OffsetAdjustment, (int)0);
+    YamlIO.mapOptional("maxAlignment", MFI.MaxAlignment, (unsigned)0);
+    YamlIO.mapOptional("adjustsStack", MFI.AdjustsStack, false);
+    YamlIO.mapOptional("hasCalls", MFI.HasCalls, false);
     YamlIO.mapOptional("stackProtector", MFI.StackProtector,
                        StringValue()); // Don't print it out when it's empty.
-    YamlIO.mapOptional("maxCallFrameSize", MFI.MaxCallFrameSize, ~0u);
-    YamlIO.mapOptional("hasOpaqueSPAdjustment", MFI.HasOpaqueSPAdjustment);
-    YamlIO.mapOptional("hasVAStart", MFI.HasVAStart);
-    YamlIO.mapOptional("hasMustTailInVarArgFunc", MFI.HasMustTailInVarArgFunc);
+    YamlIO.mapOptional("maxCallFrameSize", MFI.MaxCallFrameSize, (unsigned)~0);
+    YamlIO.mapOptional("hasOpaqueSPAdjustment", MFI.HasOpaqueSPAdjustment,
+                       false);
+    YamlIO.mapOptional("hasVAStart", MFI.HasVAStart, false);
+    YamlIO.mapOptional("hasMustTailInVarArgFunc", MFI.HasMustTailInVarArgFunc,
+                       false);
     YamlIO.mapOptional("savePoint", MFI.SavePoint,
                        StringValue()); // Don't print it out when it's empty.
     YamlIO.mapOptional("restorePoint", MFI.RestorePoint,
                        StringValue()); // Don't print it out when it's empty.
   }
 };
 
 struct MachineFunction {
struct MachineFunction {
   std::vector<MachineConstantPoolValue> Constants; /// Constant pool.
   MachineJumpTable JumpTableInfo;
   BlockStringValue Body;
 };
 
 template <> struct MappingTraits<MachineFunction> {
   static void mapping(IO &YamlIO, MachineFunction &MF) {
     YamlIO.mapRequired("name", MF.Name);
-    YamlIO.mapOptional("alignment", MF.Alignment);
-    YamlIO.mapOptional("exposesReturnsTwice", MF.ExposesReturnsTwice);
-    YamlIO.mapOptional("legalized", MF.Legalized);
-    YamlIO.mapOptional("regBankSelected", MF.RegBankSelected);
-    YamlIO.mapOptional("selected", MF.Selected);
-    YamlIO.mapOptional("tracksRegLiveness", MF.TracksRegLiveness);
-    YamlIO.mapOptional("registers", MF.VirtualRegisters);
-    YamlIO.mapOptional("liveins", MF.LiveIns);
-    YamlIO.mapOptional("calleeSavedRegisters", MF.CalleeSavedRegisters);
-    YamlIO.mapOptional("frameInfo", MF.FrameInfo);
-    YamlIO.mapOptional("fixedStack", MF.FixedStackObjects);
-    YamlIO.mapOptional("stack", MF.StackObjects);
-    YamlIO.mapOptional("constants", MF.Constants);
+    YamlIO.mapOptional("alignment", MF.Alignment, (unsigned)0);
+    YamlIO.mapOptional("exposesReturnsTwice", MF.ExposesReturnsTwice, false);
+    YamlIO.mapOptional("legalized", MF.Legalized, false);
+    YamlIO.mapOptional("regBankSelected", MF.RegBankSelected, false);
+    YamlIO.mapOptional("selected", MF.Selected, false);
+    YamlIO.mapOptional("tracksRegLiveness", MF.TracksRegLiveness, false);
+    YamlIO.mapOptional("registers", MF.VirtualRegisters,
+                       std::vector<VirtualRegisterDefinition>());
+    YamlIO.mapOptional("liveins", MF.LiveIns,
+                       std::vector<MachineFunctionLiveIn>());
+    YamlIO.mapOptional("calleeSavedRegisters", MF.CalleeSavedRegisters,
+                       Optional<std::vector<FlowStringValue>>());
+    YamlIO.mapOptional("frameInfo", MF.FrameInfo, MachineFrameInfo());
+    YamlIO.mapOptional("fixedStack", MF.FixedStackObjects,
+                       std::vector<FixedMachineStackObject>());
+    YamlIO.mapOptional("stack", MF.StackObjects,
+                       std::vector<MachineStackObject>());
+    YamlIO.mapOptional("constants", MF.Constants,
+                       std::vector<MachineConstantPoolValue>());
     if (!YamlIO.outputting() || !MF.JumpTableInfo.Entries.empty())
-      YamlIO.mapOptional("jumpTable", MF.JumpTableInfo);
-    YamlIO.mapOptional("body", MF.Body);
+      YamlIO.mapOptional("jumpTable", MF.JumpTableInfo, MachineJumpTable());
+    YamlIO.mapOptional("body", MF.Body, BlockStringValue());
   }
 };
 
 } // end namespace yaml
 } // end namespace llvm
 
 #endif

lib/CodeGen/MIRPrinter.cpp

for (const auto &MBB : MF) {
     if (IsNewlineNeeded)
       StrOS << "\n";
     MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
         .print(MBB);
     IsNewlineNeeded = true;
   }
   StrOS.flush();
   yaml::Output Out(OS);
+  if (!SimplifyMIR)
+      Out.setWriteDefaultValues(true);
   Out << YamlMF;
 }
 
 static void printCustomRegMask(const uint32_t *RegMask, raw_ostream &OS,
                                const TargetRegisterInfo *TRI) {
   assert(RegMask && "Can't print an empty register mask");
   OS << StringRef("CustomRegMask(");
 

test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-stackprotect.ll

 ; RUN: llc -verify-machineinstrs -mtriple=aarch64-apple-ios %s -stop-after=irtranslator -o - -global-isel | FileCheck %s
 
 
 ; CHECK: name: test_stack_guard
 
 ; CHECK: stack:
-; CHECK:  - { id: 0, name: StackGuardSlot, offset: 0, size: 8, alignment: 8 }
+; CHECK:  - { id: 0, name: StackGuardSlot,  type: default, offset: 0, size: 8, alignment: 8,
 ; CHECK-NOT: id: 1
 
 ; CHECK: [[GUARD_SLOT:%[0-9]+]](p0) = G_FRAME_INDEX %stack.0.StackGuardSlot
 ; CHECK: [[GUARD:%[0-9]+]](p0) = LOAD_STACK_GUARD :: (dereferenceable invariant load 8 from @__stack_chk_guard)
 ; CHECK: G_STORE [[GUARD]](p0), [[GUARD_SLOT]](p0) :: (volatile store 8 into %stack.0.StackGuardSlot)
 declare void @llvm.stackprotector(i8*, i8**)
 define void @test_stack_guard_remat2() {
   %StackGuardSlot = alloca i8*
   call void @llvm.stackprotector(i8* undef, i8** %StackGuardSlot)
   ret void
 }
 
 @__stack_chk_guard = external global i64*

test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll

 define i64 @muli64(i64 %arg1, i64 %arg2) {
   %res = mul i64 %arg1, %arg2
   ret i64 %res
 }
 
 ; Tests for alloca
 ; CHECK-LABEL: name: allocai64
 ; CHECK: stack:
-; CHECK-NEXT:   - { id: 0, name: ptr1, offset: 0, size: 8, alignment: 8 }
-; CHECK-NEXT:   - { id: 1, name: ptr2, offset: 0, size: 8, alignment: 1 }
-; CHECK-NEXT:   - { id: 2, name: ptr3, offset: 0, size: 128, alignment: 8 }
-; CHECK-NEXT:   - { id: 3, name: ptr4, offset: 0, size: 1, alignment: 8 }
+; CHECK-NEXT:   - { id: 0, name: ptr1, type: default, offset: 0, size: 8, alignment: 8,
+; CHECK-NEXT:       callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
+; CHECK-NEXT:   - { id: 1, name: ptr2, type: default, offset: 0, size: 8, alignment: 1,
+; CHECK-NEXT:       callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
+; CHECK-NEXT:   - { id: 2, name: ptr3, type: default, offset: 0, size: 128, alignment: 8,
+; CHECK-NEXT:       callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
+; CHECK-NEXT:   - { id: 3, name: ptr4, type: default, offset: 0, size: 1, alignment: 8,
 ; CHECK: %{{[0-9]+}}(p0) = G_FRAME_INDEX %stack.0.ptr1
 ; CHECK: %{{[0-9]+}}(p0) = G_FRAME_INDEX %stack.1.ptr2
 ; CHECK: %{{[0-9]+}}(p0) = G_FRAME_INDEX %stack.2.ptr3
 ; CHECK: %{{[0-9]+}}(p0) = G_FRAME_INDEX %stack.3.ptr4
 define void @allocai64() {
   %ptr1 = alloca i64
   %ptr2 = alloca i64, align 1
   %ptr3 = alloca i64, i32 16

test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir

 
 ---
 # Check that we assign a relevant register bank for %0.
 # Based on the type i32, this should be gpr.
 name:            defaultMapping
 legalized:       true
 # CHECK-LABEL: name: defaultMapping
 # CHECK:      registers:
-# CHECK:   - { id: 0, class: gpr }
-# CHECK:   - { id: 1, class: gpr }
+# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
+# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0.entry:
     liveins: %x0
     ; CHECK:      %1(s32) = G_ADD %0
     %0(s32) = COPY %w0
     %1(s32) = G_ADD %0, %0
 ...
 
 ---
 # Check that we assign a relevant register bank for %0.
 # Based on the type <2 x i32>, this should be fpr.
 # FPR is used for both floating point and vector registers.
 name:            defaultMappingVector
 legalized:       true
 # CHECK-LABEL: name: defaultMappingVector
 # CHECK:      registers:
-# CHECK:   - { id: 0, class: fpr }
-# CHECK:   - { id: 1, class: fpr }
+# CHECK:   - { id: 0, class: fpr, preferred-register: '' }
+# CHECK:   - { id: 1, class: fpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0.entry:
     liveins: %d0
     ; CHECK:      %0(<2 x s32>) = COPY %d0
     ; CHECK:      %1(<2 x s32>) = G_ADD %0
     %0(<2 x s32>) = COPY %d0
     %1(<2 x s32>) = G_ADD %0, %0
 ...
 
 ---
 # Check that we repair the assignment for %0.
 # Indeed based on the source of the copy it should live
 # in FPR, but at the use, it should be GPR.
 name:            defaultMapping1Repair
 legalized:       true
 # CHECK-LABEL: name: defaultMapping1Repair
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: fpr }
-# CHECK-NEXT:   - { id: 1, class: gpr }
-# CHECK-NEXT:   - { id: 2, class: gpr }
-# CHECK-NEXT:   - { id: 3, class: gpr }
+# CHECK-NEXT:   - { id: 0, class: fpr, preferred-register: '' }
+# CHECK-NEXT:   - { id: 1, class: gpr, preferred-register: '' }
+# CHECK-NEXT:   - { id: 2, class: gpr, preferred-register: '' }
+# CHECK-NEXT:   - { id: 3, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body: |
   bb.0.entry:
     liveins: %s0, %x0
     ; CHECK:           %0(s32) = COPY %s0
     ; CHECK-NEXT:      %1(s32) = COPY %w0
     ; CHECK-NEXT:      %3(s32) = COPY %0
     ; CHECK-NEXT:      %2(s32) = G_ADD %3, %1
     %0(s32) = COPY %s0
     %1(s32) = COPY %w0
     %2(s32) = G_ADD %0, %1
 ...
 
 # Check that we repair the assignment for %0 differently for both uses.
 name:            defaultMapping2Repairs
 legalized:       true
 # CHECK-LABEL: name: defaultMapping2Repairs
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: fpr }
-# CHECK-NEXT:   - { id: 1, class: gpr }
-# CHECK-NEXT:   - { id: 2, class: gpr }
-# CHECK-NEXT:   - { id: 3, class: gpr }
+# CHECK-NEXT:   - { id: 0, class: fpr, preferred-register: '' }
+# CHECK-NEXT:   - { id: 1, class: gpr, preferred-register: '' }
+# CHECK-NEXT:   - { id: 2, class: gpr, preferred-register: '' }
+# CHECK-NEXT:   - { id: 3, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0.entry:
     liveins: %s0, %x0
     ; CHECK:           %0(s32) = COPY %s0
     ; CHECK-NEXT:      %2(s32) = COPY %0
     ; CHECK-NEXT:      %3(s32) = COPY %0
     ; CHECK-NEXT:      %1(s32) = G_ADD %2, %3
     %0(s32) = COPY %s0
     %1(s32) = G_ADD %0, %0
 ...
 
 ---
 # Check that we repair the definition of %1.
 # %1 is forced to be into FPR, but its definition actually
 # requires that it lives in GPR. Make sure regbankselect
 # fixes that.
 name:            defaultMappingDefRepair
 legalized:       true
 # CHECK-LABEL: name: defaultMappingDefRepair
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gpr }
-# CHECK-NEXT:   - { id: 1, class: fpr }
-# CHECK-NEXT:   - { id: 2, class: gpr }
+# CHECK-NEXT:   - { id: 0, class: gpr, preferred-register: '' }
+# CHECK-NEXT:   - { id: 1, class: fpr, preferred-register: '' }
+# CHECK-NEXT:   - { id: 2, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: fpr }
 body: |
   bb.0.entry:
     liveins: %w0
     ; CHECK:           %0(s32) = COPY %w0
     ; CHECK-NEXT:      %2(s32) = G_ADD %0, %0
     ; CHECK-NEXT:      %1(s32) = COPY %2
     %0(s32) = COPY %w0
     %1(s32) = G_ADD %0, %0
 ...
 
 ---
 # Check that we are able to propagate register banks from phis.
 name:            phiPropagation
 legalized:       true
 tracksRegLiveness:   true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gpr32 }
-# CHECK-NEXT:   - { id: 1, class: gpr64sp }
-# CHECK-NEXT:   - { id: 2, class: gpr32 }
-# CHECK-NEXT:   - { id: 3, class: gpr }
-# CHECK-NEXT:   - { id: 4, class: gpr }
+# CHECK-NEXT:   - { id: 0, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 1, class: gpr64sp, preferred-register: '' }
+# CHECK-NEXT:   - { id: 2, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 3, class: gpr, preferred-register: '' }
+# CHECK-NEXT:   - { id: 4, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: gpr32 }
   - { id: 1, class: gpr64sp }
   - { id: 2, class: gpr32 }
   - { id: 3, class: _ }
   - { id: 4, class: _ }
   - { id: 5, class: _ }
 body: |

 ...
 
 ---
 # Make sure we can repair physical register uses as well.
 name:            defaultMappingUseRepairPhysReg
 legalized:       true
 # CHECK-LABEL: name: defaultMappingUseRepairPhysReg
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gpr }
-# CHECK-NEXT:   - { id: 1, class: fpr }
-# CHECK-NEXT:   - { id: 2, class: gpr }
-# CHECK-NEXT:   - { id: 3, class: gpr }
+# CHECK-NEXT:   - { id: 0, class: gpr, preferred-register: '' }
+# CHECK-NEXT:   - { id: 1, class: fpr, preferred-register: '' }
+# CHECK-NEXT:   - { id: 2, class: gpr, preferred-register: '' }
+# CHECK-NEXT:   - { id: 3, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body: |
   bb.0.entry:
     liveins: %w0, %s0
     ; CHECK:           %0(s32) = COPY %w0
     ; CHECK-NEXT:      %1(s32) = COPY %s0
     ; CHECK-NEXT:      %3(s32) = COPY %1
     ; CHECK-NEXT:      %2(s32) = G_ADD %0, %3
     %0(s32) = COPY %w0
     %1(s32) = COPY %s0
     %2(s32) = G_ADD %0, %1
 ...
 
 ---
 # Make sure we can repair physical register defs.
 name:            defaultMappingDefRepairPhysReg
 legalized:       true
 # CHECK-LABEL: name: defaultMappingDefRepairPhysReg
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gpr }
-# CHECK-NEXT:   - { id: 1, class: gpr }
+# CHECK-NEXT:   - { id: 0, class: gpr, preferred-register: '' }
+# CHECK-NEXT:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0.entry:
     liveins: %w0
     ; CHECK:           %0(s32) = COPY %w0
     ; CHECK-NEXT:      %1(s32) = G_ADD %0, %0
     ; CHECK-NEXT:      %s0 = COPY %1
     %0(s32) = COPY %w0
     %1(s32) = G_ADD %0, %0
     %s0 = COPY %1
 ...
 
 ---
 # Check that the greedy mode is able to switch the
 # G_OR instruction from fpr to gpr.
 name:            greedyMappingOr
 legalized:       true
 # CHECK-LABEL: name: greedyMappingOr
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr }
-# CHECK-NEXT:  - { id: 1, class: gpr }
+# CHECK-NEXT:  - { id: 0, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
 
 # Fast mode maps vector instruction on FPR.
-# FAST-NEXT:  - { id: 2, class: fpr }
+# FAST-NEXT:  - { id: 2, class: fpr, preferred-register: '' }
 # Fast mode needs two extra copies.
-# FAST-NEXT:  - { id: 3, class: fpr }
-# FAST-NEXT:  - { id: 4, class: fpr }
+# FAST-NEXT:  - { id: 3, class: fpr, preferred-register: '' }
+# FAST-NEXT:  - { id: 4, class: fpr, preferred-register: '' }
 
 # Greedy mode coalesce the computation on the GPR register
 # because it is the cheapest.
-# GREEDY-NEXT:  - { id: 2, class: gpr }
+# GREEDY-NEXT:  - { id: 2, class: gpr, preferred-register: '' }
 
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body: |
   bb.0.entry:
     liveins: %x0, %x1

 ---
 # Check that the greedy mode is able to switch the
 # G_OR instruction from fpr to gpr, while still honoring
 # %2 constraint.
 name:            greedyMappingOrWithConstraints
 legalized:       true
 # CHECK-LABEL: name: greedyMappingOrWithConstraints
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr }
-# CHECK-NEXT:  - { id: 1, class: gpr }
-# CHECK-NEXT:  - { id: 2, class: fpr }
+# CHECK-NEXT:  - { id: 0, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: fpr, preferred-register: '' }
 
 # Fast mode maps vector instruction on FPR.
 # Fast mode needs two extra copies.
-# FAST-NEXT:  - { id: 3, class: fpr }
-# FAST-NEXT:  - { id: 4, class: fpr }
+# FAST-NEXT:  - { id: 3, class: fpr, preferred-register: '' }
+# FAST-NEXT:  - { id: 4, class: fpr, preferred-register: '' }
 
 # Greedy mode coalesce the computation on the GPR register because it
 # is the cheapest, but will need one extra copy to materialize %2 into a FPR.
-# GREEDY-NEXT:  - { id: 3, class: gpr }
+# GREEDY-NEXT:  - { id: 3, class: gpr, preferred-register: '' }
 
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: fpr }
 body: |
   bb.0.entry:
     liveins: %x0, %x1
bb.0.entry:
     %2(<2 x s32>) = G_OR %0, %1
 ...
 
 ---
 # CHECK-LABEL: name: ignoreTargetSpecificInst
 name:            ignoreTargetSpecificInst
 legalized:       true
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64 }
-# CHECK-NEXT:  - { id: 1, class: gpr64 }
+# CHECK-NEXT:  - { id: 0, class: gpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr64 }
   - { id: 1, class: gpr64 }
 body: |
   bb.0:
     liveins: %x0
 
     ; CHECK: %0 = COPY %x0

 ...
 
 ---
 # CHECK-LABEL: name: bitcast_s32_gpr
 name:            bitcast_s32_gpr
 legalized:       true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr }
-# CHECK-NEXT:  - { id: 1, class: gpr }
+# CHECK-NEXT:  - { id: 0, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 
 # CHECK:  body:
 # CHECK:    %0(s32) = COPY %w0
 # CHECK:    %1(s32) = G_BITCAST %0
 body:             |
   bb.0:
     liveins: %w0
 
     %0(s32) = COPY %w0
     %1(s32) = G_BITCAST %0
 ...
 
 ---
 # CHECK-LABEL: name: bitcast_s32_fpr
 name:            bitcast_s32_fpr
 legalized:       true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr }
-# CHECK-NEXT:  - { id: 1, class: fpr }
+# CHECK-NEXT:  - { id: 0, class: fpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: fpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 
 # CHECK:  body:
 # CHECK:    %0(<2 x s16>) = COPY %s0
 # CHECK:    %1(<2 x s16>) = G_BITCAST %0
 body:             |
   bb.0:
     liveins: %s0
 
     %0(<2 x s16>) = COPY %s0
     %1(<2 x s16>) = G_BITCAST %0
 ...
 
 ---
 # CHECK-LABEL: name: bitcast_s32_gpr_fpr
 name:            bitcast_s32_gpr_fpr
 legalized:       true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr }
-# FAST-NEXT:  - { id: 1, class: fpr }
-# GREEDY-NEXT:  - { id: 1, class: gpr }
+# CHECK-NEXT:  - { id: 0, class: gpr, preferred-register: '' }
+# FAST-NEXT:  - { id: 1, class: fpr, preferred-register: '' }
+# GREEDY-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 
 # CHECK:  body:
 # CHECK:    %0(s32) = COPY %w0
 # CHECK:    %1(<2 x s16>) = G_BITCAST %0
 body:             |
   bb.0:
     liveins: %w0
 
     %0(s32) = COPY %w0
     %1(<2 x s16>) = G_BITCAST %0
 ...
 
 ---
 # CHECK-LABEL: name: bitcast_s32_fpr_gpr
 name:            bitcast_s32_fpr_gpr
 legalized:       true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr }
-# FAST-NEXT:  - { id: 1, class: gpr }
-# GREEDY-NEXT:  - { id: 1, class: fpr }
+# CHECK-NEXT:  - { id: 0, class: fpr, preferred-register: '' }
+# FAST-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
+# GREEDY-NEXT:  - { id: 1, class: fpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 
 # CHECK:  body:
 # CHECK:    %0(<2 x s16>) = COPY %s0
 # CHECK:    %1(s32) = G_BITCAST %0
 body:             |
   bb.0:
     liveins: %s0
 
     %0(<2 x s16>) = COPY %s0
     %1(s32) = G_BITCAST %0
 ...
 
 ---
 # CHECK-LABEL: name: bitcast_s64_gpr
 name:            bitcast_s64_gpr
 legalized:       true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr }
-# CHECK-NEXT:  - { id: 1, class: gpr }
+# CHECK-NEXT:  - { id: 0, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 
 # CHECK:  body:
 # CHECK:    %0(s64) = COPY %x0
 # CHECK:    %1(s64) = G_BITCAST %0
 body:             |
   bb.0:
     liveins: %x0
 
     %0(s64) = COPY %x0
     %1(s64) = G_BITCAST %0
 ...
 
 ---
 # CHECK-LABEL: name: bitcast_s64_fpr
 name:            bitcast_s64_fpr
 legalized:       true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr }
-# CHECK-NEXT:  - { id: 1, class: fpr }
+# CHECK-NEXT:  - { id: 0, class: fpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: fpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 
 # CHECK:  body:
 # CHECK:    %0(<2 x s32>) = COPY %d0
 # CHECK:    %1(<2 x s32>) = G_BITCAST %0
 body:             |
   bb.0:
     liveins: %d0
 
     %0(<2 x s32>) = COPY %d0
     %1(<2 x s32>) = G_BITCAST %0
 ...
 
 ---
 # CHECK-LABEL: name: bitcast_s64_gpr_fpr
 name:            bitcast_s64_gpr_fpr
 legalized:       true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr }
-# FAST-NEXT:  - { id: 1, class: fpr }
-# GREEDY-NEXT:  - { id: 1, class: gpr }
+# CHECK-NEXT:  - { id: 0, class: gpr, preferred-register: '' }
+# FAST-NEXT:  - { id: 1, class: fpr, preferred-register: '' }
+# GREEDY-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 # CHECK:  body:
 # CHECK:    %0(s64) = COPY %x0
 # CHECK:    %1(<2 x s32>) = G_BITCAST %0
 body:             |
   bb.0:
     liveins: %x0
 
     %0(s64) = COPY %x0
     %1(<2 x s32>) = G_BITCAST %0
 ...
 
 ---
 # CHECK-LABEL: name: bitcast_s64_fpr_gpr
 name:            bitcast_s64_fpr_gpr
 legalized:       true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr }
-# FAST-NEXT:  - { id: 1, class: gpr }
-# GREEDY-NEXT:  - { id: 1, class: fpr }
+# CHECK-NEXT:  - { id: 0, class: fpr, preferred-register: '' }
+# FAST-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
+# GREEDY-NEXT:  - { id: 1, class: fpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 
 # CHECK:  body:
 # CHECK:    %0(<2 x s32>) = COPY %d0
 # CHECK:    %1(s64) = G_BITCAST %0
 body:             |
   bb.0:
     liveins: %d0
 
     %0(<2 x s32>) = COPY %d0
     %1(s64) = G_BITCAST %0
 ...
 
 ---
 # Make sure the greedy mode is able to take advantage of the
 # alternative mappings of G_LOAD to coalesce the whole chain
 # of computation on GPR.
 # CHECK-LABEL: name: greedyWithChainOfComputation
 name:            greedyWithChainOfComputation
 legalized:       true
 
 # CHECK: registers:
-# CHECK-NEXT:  - { id: 0, class: gpr }
-# CHECK-NEXT:  - { id: 1, class: gpr }
-# FAST-NEXT:   - { id: 2, class: fpr }
-# FAST-NEXT:   - { id: 3, class: fpr }
-# FAST-NEXT:   - { id: 4, class: fpr }
-# GREEDY-NEXT: - { id: 2, class: gpr }
-# GREEDY-NEXT: - { id: 3, class: gpr }
-# GREEDY-NEXT: - { id: 4, class: gpr }
-# CHECK-NEXT:  - { id: 5, class: gpr }
+# CHECK-NEXT:  - { id: 0, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
+# FAST-NEXT:   - { id: 2, class: fpr, preferred-register: '' }
+# FAST-NEXT:   - { id: 3, class: fpr, preferred-register: '' }
+# FAST-NEXT:   - { id: 4, class: fpr, preferred-register: '' }
+# GREEDY-NEXT: - { id: 2, class: gpr, preferred-register: '' }
+# GREEDY-NEXT: - { id: 3, class: gpr, preferred-register: '' }
+# GREEDY-NEXT: - { id: 4, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 5, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
   - { id: 3, class: _ }
   - { id: 4, class: _ }
   - { id: 5, class: _ }
 

 ---
 # Make sure we map what looks like floating point
 # loads to floating point register bank.
 # CHECK-LABEL: name: floatingPointLoad
 name:            floatingPointLoad
 legalized:       true
 
 # CHECK: registers:
-# CHECK-NEXT:  - { id: 0, class: gpr }
-# CHECK-NEXT:  - { id: 1, class: gpr }
-# CHECK-NEXT:   - { id: 2, class: fpr }
-# CHECK-NEXT:   - { id: 3, class: fpr }
-# CHECK-NEXT:   - { id: 4, class: fpr }
+# CHECK-NEXT:  - { id: 0, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
+# CHECK-NEXT:   - { id: 2, class: fpr, preferred-register: '' }
+# CHECK-NEXT:   - { id: 3, class: fpr, preferred-register: '' }
+# CHECK-NEXT:   - { id: 4, class: fpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
   - { id: 3, class: _ }
 
 # No repairing should be necessary for both modes.
 # CHECK:         %0(s64) = COPY %x0

 ---
 # Make sure we map what looks like floating point
 # stores to floating point register bank.
 # CHECK-LABEL: name: floatingPointStore
 name:            floatingPointStore
 legalized:       true
 
 # CHECK: registers:
-# CHECK-NEXT:  - { id: 0, class: gpr }
-# CHECK-NEXT:  - { id: 1, class: gpr }
-# CHECK-NEXT:   - { id: 2, class: fpr }
-# CHECK-NEXT:   - { id: 3, class: fpr }
-# CHECK-NEXT:   - { id: 4, class: fpr }
+# CHECK-NEXT:  - { id: 0, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
+# CHECK-NEXT:   - { id: 2, class: fpr, preferred-register: '' }
+# CHECK-NEXT:   - { id: 3, class: fpr, preferred-register: '' }
+# CHECK-NEXT:   - { id: 4, class: fpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 
 # CHECK:         %0(s64) = COPY %x0
 # CHECK-NEXT:    %1(p0) = COPY %x1
 # %0 has been mapped to GPR, we need to repair to match FPR.

test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll

 ; RUN: llc -mtriple=aarch64-apple-ios -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
 
 
 ; CHECK-LABEL: name: test_stack_slots
 ; CHECK: fixedStack:
-; CHECK-DAG:  - { id: [[STACK0:[0-9]+]], offset: 0, size: 1
-; CHECK-DAG:  - { id: [[STACK8:[0-9]+]], offset: 1, size: 1
+; CHECK-DAG:  - { id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 1,
+; CHECK-DAG:  - { id: [[STACK8:[0-9]+]], type: default, offset: 1, size: 1,
 ; CHECK: [[LHS_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
 ; CHECK: [[LHS:%[0-9]+]](s8) = G_LOAD [[LHS_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK0]], align 0)
 ; CHECK: [[RHS_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK8]]
 ; CHECK: [[RHS:%[0-9]+]](s8) = G_LOAD [[RHS_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK8]], align 0)
 ; CHECK: [[SUM:%[0-9]+]](s8) = G_ADD [[LHS]], [[RHS]]
 ; CHECK: [[SUM32:%[0-9]+]](s32) = G_SEXT [[SUM]](s8)
 ; CHECK: %w0 = COPY [[SUM32]](s32)
 define signext i8 @test_stack_slots([8 x i64], i8 signext %lhs, i8 signext %rhs) {

test/CodeGen/AArch64/GlobalISel/call-translator.ll

 define void @test_simple_arg(i32 %in) {
   call void @simple_arg_callee(i32 %in)
   ret void
 }
 
 ; CHECK-LABEL: name: test_indirect_call
 ; CHECK: registers:
 ; Make sure the register feeding the indirect call is properly constrained.
-; CHECK: - { id: [[FUNC:[0-9]+]], class: gpr64 }
+; CHECK: - { id: [[FUNC:[0-9]+]], class: gpr64, preferred-register: '' }
 ; CHECK: %[[FUNC]](p0) = COPY %x0
 ; CHECK: BLR %[[FUNC]](p0), csr_aarch64_aapcs, implicit-def %lr, implicit %sp
 ; CHECK: RET_ReallyLR
 define void @test_indirect_call(void()* %func) {
   call void %func()
   ret void
 }
 

 ; CHECK: RET_ReallyLR implicit %w0
 define zeroext i8 @test_abi_zext_ret(i8* %addr) {
   %val = load i8, i8* %addr
   ret i8 %val
 }
 
 ; CHECK-LABEL: name: test_stack_slots
 ; CHECK: fixedStack:
-; CHECK-DAG:  - { id: [[STACK0:[0-9]+]], offset: 0, size: 8
-; CHECK-DAG:  - { id: [[STACK8:[0-9]+]], offset: 8, size: 8
-; CHECK-DAG:  - { id: [[STACK16:[0-9]+]], offset: 16, size: 8
+; CHECK-DAG:  - { id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 8,
+; CHECK-DAG:  - { id: [[STACK8:[0-9]+]], type: default, offset: 8, size: 8,
+; CHECK-DAG:  - { id: [[STACK16:[0-9]+]], type: default, offset: 16, size: 8,
 ; CHECK: [[LHS_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
 ; CHECK: [[LHS:%[0-9]+]](s64) = G_LOAD [[LHS_ADDR]](p0) :: (invariant load 8 from %fixed-stack.[[STACK0]], align 0)
 ; CHECK: [[RHS_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK8]]
 ; CHECK: [[RHS:%[0-9]+]](s64) = G_LOAD [[RHS_ADDR]](p0) :: (invariant load 8 from %fixed-stack.[[STACK8]], align 0)
 ; CHECK: [[ADDR_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK16]]
 ; CHECK: [[ADDR:%[0-9]+]](p0) = G_LOAD [[ADDR_ADDR]](p0) :: (invariant load 8 from %fixed-stack.[[STACK16]], align 0)
 ; CHECK: [[SUM:%[0-9]+]](s64) = G_ADD [[LHS]], [[RHS]]
 ; CHECK: G_STORE [[SUM]](s64), [[ADDR]](p0)

 ; CHECK: ADJCALLSTACKUP 24, 0, implicit-def %sp, implicit %sp
 define void @test_call_stack() {
   call void @test_stack_slots([8 x i64] undef, i64 42, i64 12, i64* null)
   ret void
 }
 
 ; CHECK-LABEL: name: test_mem_i1
 ; CHECK: fixedStack:
-; CHECK-NEXT: - { id: [[SLOT:[0-9]+]], offset: 0, size: 1, alignment: 16, isImmutable: true, isAliased: false }
+; CHECK-NEXT: - { id: [[SLOT:[0-9]+]], type: default, offset: 0, size: 1, alignment: 16, isImmutable: true,
 ; CHECK: [[ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[SLOT]]
 ; CHECK: {{%[0-9]+}}(s1) = G_LOAD [[ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[SLOT]], align 0)
 define void @test_mem_i1([8 x i64], i1 %in) {
   ret void
 }

test/CodeGen/AArch64/GlobalISel/debug-insts.ll

 ; RUN: llc -global-isel -mtriple=aarch64 %s -stop-after=irtranslator -o - | FileCheck %s
 ; RUN: llc -mtriple=aarch64 -global-isel --global-isel-abort=0 -o /dev/null
 
 ; CHECK-LABEL: name: debug_declare
 ; CHECK: stack:
-; CHECK:    - { id: {{.*}}, name: in.addr, offset: {{.*}}, size: {{.*}}, alignment: {{.*}}, di-variable: '!11',
-; CHECK-NEXT:   di-expression: '!12', di-location: '!13' }
+; CHECK:    - { id: {{.*}}, name: in.addr, type: default, offset: 0, size: {{.*}}, alignment: {{.*}}, 
+; CHECK-NEXT: callee-saved-register: '', di-variable: '!11', di-expression: '!12',
 ; CHECK: DBG_VALUE debug-use %0(s32), debug-use _, !11, !12, debug-location !13
 define void @debug_declare(i32 %in) #0 !dbg !7 {
 entry:
   %in.addr = alloca i32, align 4
   store i32 %in, i32* %in.addr, align 4
   call void @llvm.dbg.declare(metadata i32* %in.addr, metadata !11, metadata !12), !dbg !13
   call void @llvm.dbg.declare(metadata i32 %in, metadata !11, metadata !12), !dbg !13
   ret void, !dbg !13

test/CodeGen/AArch64/GlobalISel/localizer-in-O0-pipeline.mir

 # CHECK-LABEL: name: foo
 name:            foo
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
 # CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: fpr }
-# CHECK-NEXT: - { id: 1, class: gpr }
-# CHECK-NEXT: - { id: 2, class: fpr }
-# CHECK-NEXT: - { id: 3, class: fpr }
-# CHECK-NEXT: - { id: 4, class: fpr }
-# CHECK-NEXT: - { id: 5, class: fpr }
+# CHECK-NEXT: - { id: 0, class: fpr, preferred-register: '' }
+# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
+# CHECK-NEXT: - { id: 2, class: fpr, preferred-register: '' }
+# CHECK-NEXT: - { id: 3, class: fpr, preferred-register: '' }
+# CHECK-NEXT: - { id: 4, class: fpr, preferred-register: '' }
+# CHECK-NEXT: - { id: 5, class: fpr, preferred-register: '' }
 # The localizer will create two new values to materialize the constants.
-# OPTNONE-NEXT:  - { id: 6, class: fpr }
-# OPTNONE-NEXT:  - { id: 7, class: fpr }
+# OPTNONE-NEXT:  - { id: 6, class: fpr, preferred-register: '' }
+# OPTNONE-NEXT:  - { id: 7, class: fpr, preferred-register: '' }
   - { id: 0, class: fpr }
   - { id: 1, class: gpr }
   - { id: 2, class: fpr }
   - { id: 3, class: fpr }
   - { id: 4, class: fpr }
   - { id: 5, class: fpr }
 
 # First block remains untouched

test/CodeGen/AArch64/GlobalISel/localizer.mir

 ---
 # CHECK-LABEL: name: non_local_1use
 name:            non_local_1use
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
 # Existing registers should be left untouched
-# CHECK:  - { id: 0, class: gpr }
-#CHECK-NEXT:  - { id: 1, class: gpr }
-#CHECK-NEXT:  - { id: 2, class: gpr }
+# CHECK:  - { id: 0, class: gpr, preferred-register: '' }
+#CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
+#CHECK-NEXT:  - { id: 2, class: gpr, preferred-register: '' }
 # The newly created reg should be on the same regbank/regclass as its origin.
-#CHECK-NEXT:  - { id: 3, class: gpr }
+#CHECK-NEXT:  - { id: 3, class: gpr, preferred-register: '' }
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %0(s32) = G_CONSTANT 1

 ---
 # CHECK-LABEL: name: non_local_2uses
 name:            non_local_2uses
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
 # Existing registers should be left untouched
-# CHECK:  - { id: 0, class: gpr }
-#CHECK-NEXT:  - { id: 1, class: gpr }
-#CHECK-NEXT:  - { id: 2, class: gpr }
+# CHECK:  - { id: 0, class: gpr, preferred-register: '' }
+#CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
+#CHECK-NEXT:  - { id: 2, class: gpr, preferred-register: '' }
 # The newly created reg should be on the same regbank/regclass as its origin.
-#CHECK-NEXT:  - { id: 3, class: gpr }
+#CHECK-NEXT:  - { id: 3, class: gpr, preferred-register: '' }
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %0(s32) = G_CONSTANT 1

 # CHECK-LABEL: name: non_local_phi_use
 name:            non_local_phi_use
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 
 # CHECK:      registers:
 # Existing registers should be left untouched
-# CHECK:  - { id: 0, class: gpr }
-#CHECK-NEXT:  - { id: 1, class: gpr }
-#CHECK-NEXT:  - { id: 2, class: gpr }
-#CHECK-NEXT:  - { id: 3, class: gpr }
-#CHECK-NEXT:  - { id: 4, class: gpr }
+# CHECK:  - { id: 0, class: gpr, preferred-register: '' }
+#CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
+#CHECK-NEXT:  - { id: 2, class: gpr, preferred-register: '' }
+#CHECK-NEXT:  - { id: 3, class: gpr, preferred-register: '' }
+#CHECK-NEXT:  - { id: 4, class: gpr, preferred-register: '' }
 # The newly created reg should be on the same regbank/regclass as its origin.
-#CHECK-NEXT:  - { id: 5, class: gpr }
+#CHECK-NEXT:  - { id: 5, class: gpr, preferred-register: '' }
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
   - { id: 4, class: gpr }
 

 # CHECK-LABEL: name: non_local_phi_use_followed_by_use
 name:            non_local_phi_use_followed_by_use
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 
 # CHECK:      registers:
 # Existing registers should be left untouched
-# CHECK:  - { id: 0, class: gpr }
-#CHECK-NEXT:  - { id: 1, class: gpr }
-#CHECK-NEXT:  - { id: 2, class: gpr }
-#CHECK-NEXT:  - { id: 3, class: gpr }
-#CHECK-NEXT:  - { id: 4, class: gpr }
+# CHECK:  - { id: 0, class: gpr, preferred-register: '' }
+#CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
+#CHECK-NEXT:  - { id: 2, class: gpr, preferred-register: '' }
+#CHECK-NEXT:  - { id: 3, class: gpr, preferred-register: '' }
+#CHECK-NEXT:  - { id: 4, class: gpr, preferred-register: '' }
 # The newly created regs should be on the same regbank/regclass as its origin.
-#CHECK-NEXT:  - { id: 5, class: gpr }
-#CHECK-NEXT:  - { id: 6, class: gpr }
+#CHECK-NEXT:  - { id: 5, class: gpr, preferred-register: '' }
+#CHECK-NEXT:  - { id: 6, class: gpr, preferred-register: '' }
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
   - { id: 4, class: gpr }
 

 # CHECK-LABEL: name: non_local_phi_use_followed_by_use_fi
 name:            non_local_phi_use_followed_by_use_fi
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 
 # CHECK:      registers:
 # Existing registers should be left untouched
-# CHECK:  - { id: 0, class: gpr }
-#CHECK-NEXT:  - { id: 1, class: gpr }
-#CHECK-NEXT:  - { id: 2, class: gpr }
-#CHECK-NEXT:  - { id: 3, class: gpr }
-#CHECK-NEXT:  - { id: 4, class: gpr }
+# CHECK:  - { id: 0, class: gpr, preferred-register: '' }
+#CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
+#CHECK-NEXT:  - { id: 2, class: gpr, preferred-register: '' }
+#CHECK-NEXT:  - { id: 3, class: gpr, preferred-register: '' }
+#CHECK-NEXT:  - { id: 4, class: gpr, preferred-register: '' }
 # The newly created reg should be on the same regbank/regclass as its origin.
-#CHECK-NEXT:  - { id: 5, class: gpr }
-#CHECK-NEXT:  - { id: 6, class: gpr }
+#CHECK-NEXT:  - { id: 5, class: gpr, preferred-register: '' }
+#CHECK-NEXT:  - { id: 6, class: gpr, preferred-register: '' }
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
   - { id: 4, class: gpr }
 

 # CHECK-LABEL: name: float_non_local_phi_use_followed_by_use_fi
 name:            float_non_local_phi_use_followed_by_use_fi
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 
 # CHECK:      registers:
 # Existing registers should be left untouched
-# CHECK:  - { id: 0, class: fpr }
-#CHECK-NEXT:  - { id: 1, class: fpr }
-#CHECK-NEXT:  - { id: 2, class: fpr }
-#CHECK-NEXT:  - { id: 3, class: fpr }
-#CHECK-NEXT:  - { id: 4, class: fpr }
+# CHECK:  - { id: 0, class: fpr, preferred-register: '' }
+#CHECK-NEXT:  - { id: 1, class: fpr, preferred-register: '' }
+#CHECK-NEXT:  - { id: 2, class: fpr, preferred-register: '' }
+#CHECK-NEXT:  - { id: 3, class: fpr, preferred-register: '' }
+#CHECK-NEXT:  - { id: 4, class: fpr, preferred-register: '' }
 # The newly created reg should be on the same regbank/regclass as its origin.
-#CHECK-NEXT:  - { id: 5, class: fpr }
-#CHECK-NEXT:  - { id: 6, class: fpr }
+#CHECK-NEXT:  - { id: 5, class: fpr, preferred-register: '' }
+#CHECK-NEXT:  - { id: 6, class: fpr, preferred-register: '' }
 
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
   - { id: 2, class: fpr }
   - { id: 3, class: fpr }
   - { id: 4, class: fpr }
 

 # CHECK-LABEL: name: non_local_phi
 name:            non_local_phi
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 
 # CHECK:      registers:
 # Existing registers should be left untouched
-# CHECK:  - { id: 0, class: fpr }
-#CHECK-NEXT:  - { id: 1, class: fpr }
-#CHECK-NEXT:  - { id: 2, class: fpr }
-#CHECK-NEXT:  - { id: 3, class: fpr }
+# CHECK:  - { id: 0, class: fpr, preferred-register: '' }
+#CHECK-NEXT:  - { id: 1, class: fpr, preferred-register: '' }
+#CHECK-NEXT:  - { id: 2, class: fpr, preferred-register: '' }
+#CHECK-NEXT:  - { id: 3, class: fpr, preferred-register: '' }
 # The newly created reg should be on the same regbank/regclass as its origin.
-#CHECK-NEXT:  - { id: 4, class: fpr }
+#CHECK-NEXT:  - { id: 4, class: fpr, preferred-register: '' }
 
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
   - { id: 2, class: fpr }
   - { id: 3, class: fpr }
 
 # CHECK:  body:

test/CodeGen/AArch64/GlobalISel/regbankselect-dbg-value.mir

--- |
   !10 = !DILocation(line: 1, column: 1, scope: !5)
 ...
 
 ---
 # CHECK-LABEL: name: test_dbg_value
 name:            test_dbg_value
 legalized:       true
 # CHECK: registers:
-# CHECK-NEXT:  - { id: 0, class: gpr }
+# CHECK-NEXT:  - { id: 0, class: gpr, preferred-register: '' }
 body: |
   bb.0:
     liveins: %w0
     %0:_(s32) = COPY %w0
     ; CHECK: DBG_VALUE debug-use %0(s32), debug-use _, !7, !9, debug-location !10
     DBG_VALUE debug-use %0(s32), debug-use _, !7, !9, debug-location !10
 
     ; CHECK: DBG_VALUE _, 0, !7, !9, debug-location !10
     DBG_VALUE _, 0, !7, !9, debug-location !10
 ...

test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir

--- |
   define void @test_fptoui_s32_s64() { ret void }
 ...
 
 ---
 # CHECK-LABEL: name: test_add_s32
 name:            test_add_s32
 legalized:       true
 # CHECK: registers:
-# CHECK:   - { id: 0, class: gpr }
-# CHECK:   - { id: 1, class: gpr }
+# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
+# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %w0
     ; CHECK:      %0(s32) = COPY %w0
     ; CHECK:      %1(s32) = G_ADD %0, %0
     %0(s32) = COPY %w0
     %1(s32) = G_ADD %0, %0
 ...
 
 ---
 # CHECK-LABEL: name: test_add_v4s32
 name:            test_add_v4s32
 legalized:       true
 # CHECK: registers:
-# CHECK:   - { id: 0, class: fpr }
-# CHECK:   - { id: 1, class: fpr }
+# CHECK:   - { id: 0, class: fpr, preferred-register: '' }
+# CHECK:   - { id: 1, class: fpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %q0
     ; CHECK:      %0(<4 x s32>) = COPY %q0
     ; CHECK:      %1(<4 x s32>) = G_ADD %0, %0
     %0(<4 x s32>) = COPY %q0
     %1(<4 x s32>) = G_ADD %0, %0
 ...
 
 ---
 # CHECK-LABEL: name: test_sub_s32
 name:            test_sub_s32
 legalized:       true
 # CHECK: registers:
-# CHECK:   - { id: 0, class: gpr }
-# CHECK:   - { id: 1, class: gpr }
+# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
+# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %w0
     ; CHECK:      %0(s32) = COPY %w0
     ; CHECK:      %1(s32) = G_SUB %0, %0
     %0(s32) = COPY %w0
     %1(s32) = G_SUB %0, %0
 ...
 
 ---
 # CHECK-LABEL: name: test_sub_v4s32
 name:            test_sub_v4s32
 legalized:       true
 # CHECK: registers:
-# CHECK:   - { id: 0, class: fpr }
-# CHECK:   - { id: 1, class: fpr }
+# CHECK:   - { id: 0, class: fpr, preferred-register: '' }
+# CHECK:   - { id: 1, class: fpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %q0
     ; CHECK:      %0(<4 x s32>) = COPY %q0
     ; CHECK:      %1(<4 x s32>) = G_SUB %0, %0
     %0(<4 x s32>) = COPY %q0
     %1(<4 x s32>) = G_SUB %0, %0
 ...
 
 ---
 # CHECK-LABEL: name: test_mul_s32
 name:            test_mul_s32
 legalized:       true
 # CHECK: registers:
-# CHECK:   - { id: 0, class: gpr }
-# CHECK:   - { id: 1, class: gpr }
+# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
+# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %w0
     ; CHECK:      %0(s32) = COPY %w0
     ; CHECK:      %1(s32) = G_MUL %0, %0
     %0(s32) = COPY %w0
     %1(s32) = G_MUL %0, %0
 ...
 
 ---
 # CHECK-LABEL: name: test_mul_v4s32
 name:            test_mul_v4s32
 legalized:       true
 # CHECK: registers:
-# CHECK:   - { id: 0, class: fpr }
-# CHECK:   - { id: 1, class: fpr }
+# CHECK:   - { id: 0, class: fpr, preferred-register: '' }
+# CHECK:   - { id: 1, class: fpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %q0
     ; CHECK:      %0(<4 x s32>) = COPY %q0
     ; CHECK:      %1(<4 x s32>) = G_MUL %0, %0
     %0(<4 x s32>) = COPY %q0
     %1(<4 x s32>) = G_MUL %0, %0
 ...
 
 ---
 # CHECK-LABEL: name: test_and_s32
 name:            test_and_s32
 legalized:       true
 # CHECK: registers:
-# CHECK:   - { id: 0, class: gpr }
-# CHECK:   - { id: 1, class: gpr }
+# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
+# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %w0
     ; CHECK:      %0(s32) = COPY %w0
     ; CHECK:      %1(s32) = G_AND %0, %0
     %0(s32) = COPY %w0
     %1(s32) = G_AND %0, %0
 ...
 
 ---
 # CHECK-LABEL: name: test_and_v4s32
 name:            test_and_v4s32
 legalized:       true
 # CHECK: registers:
-# CHECK:   - { id: 0, class: fpr }
-# CHECK:   - { id: 1, class: fpr }
+# CHECK:   - { id: 0, class: fpr, preferred-register: '' }
+# CHECK:   - { id: 1, class: fpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %q0
     ; CHECK:      %0(<4 x s32>) = COPY %q0
     ; CHECK:      %1(<4 x s32>) = G_AND %0, %0
     %0(<4 x s32>) = COPY %q0
     %1(<4 x s32>) = G_AND %0, %0
 ...
 
 ---
 # CHECK-LABEL: name: test_or_s32
 name:            test_or_s32
 legalized:       true
 # CHECK: registers:
-# CHECK:   - { id: 0, class: gpr }
-# CHECK:   - { id: 1, class: gpr }
+# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
+# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %w0
     ; CHECK:      %0(s32) = COPY %w0
     ; CHECK:      %1(s32) = G_OR %0, %0
     %0(s32) = COPY %w0
     %1(s32) = G_OR %0, %0
 ...
 
 ---
 # CHECK-LABEL: name: test_or_v4s32
 name:            test_or_v4s32
 legalized:       true
 # CHECK: registers:
-# CHECK:   - { id: 0, class: fpr }
-# CHECK:   - { id: 1, class: fpr }
+# CHECK:   - { id: 0, class: fpr, preferred-register: '' }
+# CHECK:   - { id: 1, class: fpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %q0
     ; CHECK:      %0(<4 x s32>) = COPY %q0
     ; CHECK:      %1(<4 x s32>) = G_OR %0, %0
     %0(<4 x s32>) = COPY %q0
     %1(<4 x s32>) = G_OR %0, %0
 ...
 
 ---
 # CHECK-LABEL: name: test_xor_s32
 name:            test_xor_s32
 legalized:       true
 # CHECK: registers:
-# CHECK:   - { id: 0, class: gpr }
-# CHECK:   - { id: 1, class: gpr }
+# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
+# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %w0
     ; CHECK:      %0(s32) = COPY %w0
     ; CHECK:      %1(s32) = G_XOR %0, %0
     %0(s32) = COPY %w0
     %1(s32) = G_XOR %0, %0
 ...
 
 ---
 # CHECK-LABEL: name: test_xor_v4s32
 name:            test_xor_v4s32
 legalized:       true
 # CHECK: registers:
-# CHECK:   - { id: 0, class: fpr }
-# CHECK:   - { id: 1, class: fpr }
+# CHECK:   - { id: 0, class: fpr, preferred-register: '' }
+# CHECK:   - { id: 1, class: fpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %q0
     ; CHECK:      %0(<4 x s32>) = COPY %q0
     ; CHECK:      %1(<4 x s32>) = G_XOR %0, %0
     %0(<4 x s32>) = COPY %q0
     %1(<4 x s32>) = G_XOR %0, %0
 ...
 
 ---
 # CHECK-LABEL: name: test_shl_s32
 name:            test_shl_s32
 legalized:       true
 # CHECK: registers:
-# CHECK:   - { id: 0, class: gpr }
-# CHECK:   - { id: 1, class: gpr }
+# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
+# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %w0
     ; CHECK:      %0(s32) = COPY %w0
     ; CHECK:      %1(s32) = G_SHL %0, %0
     %0(s32) = COPY %w0
     %1(s32) = G_SHL %0, %0
 ...
 
 ---
 # CHECK-LABEL: name: test_shl_v4s32
 name:            test_shl_v4s32
 legalized:       true
 # CHECK: registers:
-# CHECK:   - { id: 0, class: fpr }
-# CHECK:   - { id: 1, class: fpr }
+# CHECK:   - { id: 0, class: fpr, preferred-register: '' }
+# CHECK:   - { id: 1, class: fpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %q0
     ; CHECK:      %0(<4 x s32>) = COPY %q0
     ; CHECK:      %1(<4 x s32>) = G_SHL %0, %0
     %0(<4 x s32>) = COPY %q0
     %1(<4 x s32>) = G_SHL %0, %0
 ...
 
 ---
 # CHECK-LABEL: name: test_lshr_s32
 name:            test_lshr_s32
 legalized:       true
 # CHECK: registers:
-# CHECK:   - { id: 0, class: gpr }
-# CHECK:   - { id: 1, class: gpr }
+# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
+# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %w0
     ; CHECK:      %0(s32) = COPY %w0
     ; CHECK:      %1(s32) = G_LSHR %0, %0
     %0(s32) = COPY %w0
     %1(s32) = G_LSHR %0, %0
 ...
 
 ---
 # CHECK-LABEL: name: test_ashr_s32
 name:            test_ashr_s32
 legalized:       true
 # CHECK: registers:
-# CHECK:   - { id: 0, class: gpr }
-# CHECK:   - { id: 1, class: gpr }
+# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
+# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %w0
     ; CHECK:      %0(s32) = COPY %w0
     ; CHECK:      %1(s32) = G_ASHR %0, %0
     %0(s32) = COPY %w0
     %1(s32) = G_ASHR %0, %0
 ...
 
 ---
 # CHECK-LABEL: name: test_sdiv_s32
 name:            test_sdiv_s32
 legalized:       true
 # CHECK: registers:
-# CHECK:   - { id: 0, class: gpr }
-# CHECK:   - { id: 1, class: gpr }
+# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
+# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %w0
     ; CHECK:      %0(s32) = COPY %w0
     ; CHECK:      %1(s32) = G_SDIV %0, %0
     %0(s32) = COPY %w0
     %1(s32) = G_SDIV %0, %0
 ...
 
 ---
 # CHECK-LABEL: name: test_udiv_s32
 name:            test_udiv_s32
 legalized:       true
 # CHECK: registers:
-# CHECK:   - { id: 0, class: gpr }
-# CHECK:   - { id: 1, class: gpr }
+# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
+# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %w0
     ; CHECK:      %0(s32) = COPY %w0
     ; CHECK:      %1(s32) = G_UDIV %0, %0
     %0(s32) = COPY %w0
     %1(s32) = G_UDIV %0, %0
 ...
 
 ---
 # CHECK-LABEL: name: test_anyext_s64_s32
 name:            test_anyext_s64_s32
 legalized:       true
 # CHECK: registers:
-# CHECK:   - { id: 0, class: gpr }
-# CHECK:   - { id: 1, class: gpr }
+# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
+# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %w0
     ; CHECK:      %0(s32) = COPY %w0
     ; CHECK:      %1(s64) = G_ANYEXT %0
     %0(s32) = COPY %w0
     %1(s64) = G_ANYEXT %0
 ...
 
 ---
 # CHECK-LABEL: name: test_sext_s64_s32
 name:            test_sext_s64_s32
 legalized:       true
 # CHECK: registers:
-# CHECK:   - { id: 0, class: gpr }
-# CHECK:   - { id: 1, class: gpr }
+# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
+# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %w0
     ; CHECK:      %0(s32) = COPY %w0
     ; CHECK:      %1(s64) = G_SEXT %0
     %0(s32) = COPY %w0
     %1(s64) = G_SEXT %0
 ...
 
 ---
 # CHECK-LABEL: name: test_zext_s64_s32
 name:            test_zext_s64_s32
 legalized:       true
 # CHECK: registers:
-# CHECK:   - { id: 0, class: gpr }
-# CHECK:   - { id: 1, class: gpr }
+# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
+# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %w0
     ; CHECK:      %0(s32) = COPY %w0
     ; CHECK:      %1(s64) = G_ZEXT %0
     %0(s32) = COPY %w0
     %1(s64) = G_ZEXT %0
 ...
 
 ---
 # CHECK-LABEL: name: test_trunc_s32_s64
 name:            test_trunc_s32_s64
 legalized:       true
 # CHECK: registers:
-# CHECK:   - { id: 0, class: gpr }
-# CHECK:   - { id: 1, class: gpr }
+# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
+# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %x0
     ; CHECK:      %0(s64) = COPY %x0
     ; CHECK:      %1(s32) = G_TRUNC %0
     %0(s64) = COPY %x0
     %1(s32) = G_TRUNC %0
 ...
 
 ---
 # CHECK-LABEL: name: test_constant_s32
 name:            test_constant_s32
 legalized:       true
 # CHECK: registers:
-# CHECK:   - { id: 0, class: gpr }
+# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
 body: |
   bb.0:
     ; CHECK:      %0(s32) = G_CONSTANT 123
     %0(s32) = G_CONSTANT 123
 ...
 
 ---
 # CHECK-LABEL: name: test_constant_p0
 name:            test_constant_p0
 legalized:       true
 # CHECK: registers:
-# CHECK:   - { id: 0, class: gpr }
+# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
 body: |
   bb.0:
     ; CHECK:      %0(p0) = G_CONSTANT 0
     %0(p0) = G_CONSTANT 0
 ...
 
 ---
 # CHECK-LABEL: name: test_icmp_s32
 name:            test_icmp_s32
 legalized:       true
 # CHECK: registers:
-# CHECK:   - { id: 0, class: gpr }
-# CHECK:   - { id: 1, class: gpr }
+# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
+# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %w0
     ; CHECK:      %0(s32) = COPY %w0
     ; CHECK:      %1(s1) = G_ICMP intpred(ne), %0(s32), %0
     %0(s32) = COPY %w0
     %1(s1) = G_ICMP intpred(ne), %0, %0
 ...
 
 ---
 # CHECK-LABEL: name: test_icmp_p0
 name:            test_icmp_p0
 legalized:       true
 # CHECK: registers:
-# CHECK:   - { id: 0, class: gpr }
-# CHECK:   - { id: 1, class: gpr }
+# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
+# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %x0
     ; CHECK:      %0(p0) = COPY %x0
     ; CHECK:      %1(s1) = G_ICMP intpred(ne), %0(p0), %0
     %0(p0) = COPY %x0
     %1(s1) = G_ICMP intpred(ne), %0, %0
 ...
 
 ---
 # CHECK-LABEL: name: test_frame_index_p0
 name:            test_frame_index_p0
 legalized:       true
 # CHECK: registers:
-# CHECK:   - { id: 0, class: gpr }
+# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
 stack:
   - { id: 0, name: ptr0, offset: 0, size: 8, alignment: 8 }
 body: |
   bb.0:
     ; CHECK:      %0(p0) = G_FRAME_INDEX %stack.0.ptr0
     %0(p0) = G_FRAME_INDEX %stack.0.ptr0
 ...
 
 ---
 # CHECK-LABEL: name: test_ptrtoint_s64_p0
 name:            test_ptrtoint_s64_p0
 legalized:       true
 # CHECK: registers:
-# CHECK:   - { id: 0, class: gpr }
-# CHECK:   - { id: 1, class: gpr }
+# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
+# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %x0
     ; CHECK:      %0(p0) = COPY %x0
     ; CHECK:      %1(s64) = G_PTRTOINT %0
     %0(p0) = COPY %x0
     %1(s64) = G_PTRTOINT %0
 ...
 
 ---
 # CHECK-LABEL: name: test_inttoptr_p0_s64
 name:            test_inttoptr_p0_s64
 legalized:       true
 # CHECK: registers:
-# CHECK:   - { id: 0, class: gpr }
-# CHECK:   - { id: 1, class: gpr }
+# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
+# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %x0
     ; CHECK:      %0(s64) = COPY %x0
     ; CHECK:      %1(p0) = G_INTTOPTR %0
     %0(s64) = COPY %x0
     %1(p0) = G_INTTOPTR %0
 ...
 
 ---
 # CHECK-LABEL: name: test_load_s32_p0
 name:            test_load_s32_p0
 legalized:       true
 # CHECK: registers:
-# CHECK:   - { id: 0, class: gpr }
-# CHECK:   - { id: 1, class: gpr }
+# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
+# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %x0
     ; CHECK:      %0(p0) = COPY %x0
     ; CHECK:      %1(s32) = G_LOAD %0
     %0(p0) = COPY %x0
     %1(s32) = G_LOAD %0 :: (load 4)
 ...
 
 ---
 # CHECK-LABEL: name: test_store_s32_p0
 name:            test_store_s32_p0
 legalized:       true
 # CHECK: registers:
-# CHECK:   - { id: 0, class: gpr }
-# CHECK:   - { id: 1, class: gpr }
+# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
+# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %x0, %w1
     ; CHECK:      %0(p0) = COPY %x0
     ; CHECK:      %1(s32) = COPY %w1
     ; CHECK:      G_STORE %1(s32), %0(p0)
     %0(p0) = COPY %x0
     %1(s32) = COPY %w1
     G_STORE %1, %0 :: (store 4)
 ...
 
 ---
 # CHECK-LABEL: name: test_fadd_s32
 name:            test_fadd_s32
 legalized:       true
 # CHECK: registers:
-# CHECK:   - { id: 0, class: fpr }
-# CHECK:   - { id: 1, class: fpr }
+# CHECK:   - { id: 0, class: fpr, preferred-register: '' }
+# CHECK:   - { id: 1, class: fpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %s0
     ; CHECK:      %0(s32) = COPY %s0
     ; CHECK:      %1(s32) = G_FADD %0, %0
     %0(s32) = COPY %s0
     %1(s32) = G_FADD %0, %0
 ...
 
 ---
 # CHECK-LABEL: name: test_fsub_s32
 name:            test_fsub_s32
 legalized:       true
 # CHECK: registers:
-# CHECK:   - { id: 0, class: fpr }
-# CHECK:   - { id: 1, class: fpr }
+# CHECK:   - { id: 0, class: fpr, preferred-register: '' }
+# CHECK:   - { id: 1, class: fpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %s0
     ; CHECK:      %0(s32) = COPY %s0
     ; CHECK:      %1(s32) = G_FSUB %0, %0
     %0(s32) = COPY %s0
     %1(s32) = G_FSUB %0, %0
 ...
 
 ---
 # CHECK-LABEL: name: test_fmul_s32
 name:            test_fmul_s32
 legalized:       true
 # CHECK: registers:
-# CHECK:   - { id: 0, class: fpr }
-# CHECK:   - { id: 1, class: fpr }
+# CHECK:   - { id: 0, class: fpr, preferred-register: '' }
+# CHECK:   - { id: 1, class: fpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %s0
     ; CHECK:      %0(s32) = COPY %s0
     ; CHECK:      %1(s32) = G_FMUL %0, %0
     %0(s32) = COPY %s0
     %1(s32) = G_FMUL %0, %0
 ...
 
 ---
 # CHECK-LABEL: name: test_fdiv_s32
 name:            test_fdiv_s32
 legalized:       true
 # CHECK: registers:
-# CHECK:   - { id: 0, class: fpr }
-# CHECK:   - { id: 1, class: fpr }
+# CHECK:   - { id: 0, class: fpr, preferred-register: '' }
+# CHECK:   - { id: 1, class: fpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %s0
     ; CHECK:      %0(s32) = COPY %s0
     ; CHECK:      %1(s32) = G_FDIV %0, %0
     %0(s32) = COPY %s0
     %1(s32) = G_FDIV %0, %0
 ...
 
 ---
 # CHECK-LABEL: name: test_fpext_s64_s32
 name:            test_fpext_s64_s32
 legalized:       true
 # CHECK: registers:
-# CHECK:   - { id: 0, class: fpr }
-# CHECK:   - { id: 1, class: fpr }
+# CHECK:   - { id: 0, class: fpr, preferred-register: '' }
+# CHECK:   - { id: 1, class: fpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %s0
     ; CHECK:      %0(s32) = COPY %s0
     ; CHECK:      %1(s64) = G_FPEXT %0
     %0(s32) = COPY %s0
     %1(s64) = G_FPEXT %0
 ...
 
 ---
 # CHECK-LABEL: name: test_fptrunc_s32_s64
 name:            test_fptrunc_s32_s64
 legalized:       true
 # CHECK: registers:
-# CHECK:   - { id: 0, class: fpr }
-# CHECK:   - { id: 1, class: fpr }
+# CHECK:   - { id: 0, class: fpr, preferred-register: '' }
+# CHECK:   - { id: 1, class: fpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %d0
     ; CHECK:      %0(s64) = COPY %d0
     ; CHECK:      %1(s32) = G_FPTRUNC %0
     %0(s64) = COPY %d0
     %1(s32) = G_FPTRUNC %0
 ...
 
 ---
 # CHECK-LABEL: name: test_fconstant_s32
 name:            test_fconstant_s32
 legalized:       true
 # CHECK: registers:
-# CHECK:   - { id: 0, class: fpr }
+# CHECK:   - { id: 0, class: fpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
 body: |
   bb.0:
     ; CHECK:      %0(s32) = G_FCONSTANT float 1.0
     %0(s32) = G_FCONSTANT float 1.0
 ...
 
 ---
 # CHECK-LABEL: name: test_fcmp_s32
 name:            test_fcmp_s32
 legalized:       true
 # CHECK: registers:
-# CHECK:   - { id: 0, class: fpr }
-# CHECK:   - { id: 1, class: gpr }
+# CHECK:   - { id: 0, class: fpr, preferred-register: '' }
+# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %s0
     ; CHECK:      %0(s32) = COPY %s0
     ; CHECK:      %1(s1) = G_FCMP floatpred(olt), %0(s32), %0
     %0(s32) = COPY %s0
     %1(s1) = G_FCMP floatpred(olt), %0, %0
 ...
 
 ---
 # CHECK-LABEL: name: test_sitofp_s64_s32
 name:            test_sitofp_s64_s32
 legalized:       true
 # CHECK: registers:
-# CHECK:   - { id: 0, class: gpr }
-# CHECK:   - { id: 1, class: fpr }
+# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
+# CHECK:   - { id: 1, class: fpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %w0
     ; CHECK:      %0(s32) = COPY %w0
     ; CHECK:      %1(s64) = G_SITOFP %0
     %0(s32) = COPY %w0
     %1(s64) = G_SITOFP %0
 ...
 
 ---
 # CHECK-LABEL: name: test_uitofp_s32_s64
 name:            test_uitofp_s32_s64
 legalized:       true
 # CHECK: registers:
-# CHECK:   - { id: 0, class: gpr }
-# CHECK:   - { id: 1, class: fpr }
+# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
+# CHECK:   - { id: 1, class: fpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %x0
     ; CHECK:      %0(s64) = COPY %x0
     ; CHECK:      %1(s32) = G_UITOFP %0
     %0(s64) = COPY %x0
     %1(s32) = G_UITOFP %0
 ...
 
 ---
 # CHECK-LABEL: name: test_fptosi_s64_s32
 name:            test_fptosi_s64_s32
 legalized:       true
 # CHECK: registers:
-# CHECK:   - { id: 0, class: fpr }
-# CHECK:   - { id: 1, class: gpr }
+# CHECK:   - { id: 0, class: fpr, preferred-register: '' }
+# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %s0
     ; CHECK:      %0(s32) = COPY %s0
     ; CHECK:      %1(s64) = G_FPTOSI %0
     %0(s32) = COPY %s0
     %1(s64) = G_FPTOSI %0
 ...
 
 ---
 # CHECK-LABEL: name: test_fptoui_s32_s64
 name:            test_fptoui_s32_s64
 legalized:       true
 # CHECK: registers:
-# CHECK:   - { id: 0, class: fpr }
-# CHECK:   - { id: 1, class: gpr }
+# CHECK:   - { id: 0, class: fpr, preferred-register: '' }
+# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %d0
     ; CHECK:      %0(s64) = COPY %d0
     ; CHECK:      %1(s32) = G_FPTOUI %0
     %0(s64) = COPY %d0
     %1(s32) = G_FPTOUI %0
 ...

test/CodeGen/AArch64/GlobalISel/select-binop.mir

 # Check that we select a 32-bit GPR G_ADD into ADDWrr on GPR32.
 # Also check that we constrain the register class of the COPY to GPR32.
 # CHECK-LABEL: name: add_s32_gpr
 name:            add_s32_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32 }
-# CHECK-NEXT:  - { id: 1, class: gpr32 }
-# CHECK-NEXT:  - { id: 2, class: gpr32 }
+# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %w0
 # CHECK:    %1 = COPY %w1

 ---
 # Same as add_s32_gpr, for 64-bit operations.
 # CHECK-LABEL: name: add_s64_gpr
 name:            add_s64_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64 }
-# CHECK-NEXT:  - { id: 1, class: gpr64 }
-# CHECK-NEXT:  - { id: 2, class: gpr64 }
+# CHECK-NEXT:  - { id: 0, class: gpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: gpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %x0
 # CHECK:    %1 = COPY %x1

 
 ---
 # CHECK-LABEL: name: add_imm_s32_gpr
 name:            add_imm_s32_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32sp }
-# CHECK-NEXT:  - { id: 1, class: gpr }
-# CHECK-NEXT:  - { id: 2, class: gpr32sp }
+# CHECK-NEXT:  - { id: 0, class: gpr32sp, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: gpr32sp, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %w0
 # CHECK:    %2 = ADDWri %0, 1, 0

 
 ---
 # CHECK-LABEL: name: add_imm_s64_gpr
 name:            add_imm_s64_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp }
-# CHECK-NEXT:  - { id: 1, class: gpr }
-# CHECK-NEXT:  - { id: 2, class: gpr64sp }
+# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: gpr64sp, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %x0
 # CHECK:    %2 = ADDXri %0, 1, 0

 
 ---
 # CHECK-LABEL: name: add_imm_s32_gpr_bb
 name:            add_imm_s32_gpr_bb
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32sp }
-# CHECK-NEXT:  - { id: 1, class: gpr }
-# CHECK-NEXT:  - { id: 2, class: gpr32sp }
+# CHECK-NEXT:  - { id: 0, class: gpr32sp, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: gpr32sp, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %w0
 # CHECK:  bb.1:

 ---
 # Same as add_s32_gpr, for G_SUB operations.
 # CHECK-LABEL: name: sub_s32_gpr
 name:            sub_s32_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32 }
-# CHECK-NEXT:  - { id: 1, class: gpr32 }
-# CHECK-NEXT:  - { id: 2, class: gpr32 }
+# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %w0
 # CHECK:    %1 = COPY %w1

 ---
 # Same as add_s64_gpr, for G_SUB operations.
 # CHECK-LABEL: name: sub_s64_gpr
 name:            sub_s64_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64 }
-# CHECK-NEXT:  - { id: 1, class: gpr64 }
-# CHECK-NEXT:  - { id: 2, class: gpr64 }
+# CHECK-NEXT:  - { id: 0, class: gpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: gpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %x0
 # CHECK:    %1 = COPY %x1

 ---
 # Same as add_s32_gpr, for G_OR operations.
 # CHECK-LABEL: name: or_s32_gpr
 name:            or_s32_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32 }
-# CHECK-NEXT:  - { id: 1, class: gpr32 }
-# CHECK-NEXT:  - { id: 2, class: gpr32 }
+# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %w0
 # CHECK:    %1 = COPY %w1

 ---
 # Same as add_s64_gpr, for G_OR operations.
 # CHECK-LABEL: name: or_s64_gpr
 name:            or_s64_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64 }
-# CHECK-NEXT:  - { id: 1, class: gpr64 }
-# CHECK-NEXT:  - { id: 2, class: gpr64 }
+# CHECK-NEXT:  - { id: 0, class: gpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: gpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %x0
 # CHECK:    %1 = COPY %x1

 ---
 # 64-bit G_OR on vector registers.
 # CHECK-LABEL: name: or_v2s32_fpr
 name:            or_v2s32_fpr
 legalized:       true
 regBankSelected: true
 #
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr64 }
-# CHECK-NEXT:  - { id: 1, class: fpr64 }
-# CHECK-NEXT:  - { id: 2, class: fpr64 }
+# CHECK-NEXT:  - { id: 0, class: fpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: fpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: fpr64, preferred-register: '' }
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
   - { id: 2, class: fpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %d0
 # CHECK:    %1 = COPY %d1

 ---
 # Same as add_s32_gpr, for G_AND operations.
 # CHECK-LABEL: name: and_s32_gpr
 name:            and_s32_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32 }
-# CHECK-NEXT:  - { id: 1, class: gpr32 }
-# CHECK-NEXT:  - { id: 2, class: gpr32 }
+# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %w0
 # CHECK:    %1 = COPY %w1

 ---
 # Same as add_s64_gpr, for G_AND operations.
 # CHECK-LABEL: name: and_s64_gpr
 name:            and_s64_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64 }
-# CHECK-NEXT:  - { id: 1, class: gpr64 }
-# CHECK-NEXT:  - { id: 2, class: gpr64 }
+# CHECK-NEXT:  - { id: 0, class: gpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: gpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %x0
 # CHECK:    %1 = COPY %x1

 ---
 # Same as add_s32_gpr, for G_SHL operations.
 # CHECK-LABEL: name: shl_s32_gpr
 name:            shl_s32_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32 }
-# CHECK-NEXT:  - { id: 1, class: gpr32 }
-# CHECK-NEXT:  - { id: 2, class: gpr32 }
+# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %w0
 # CHECK:    %1 = COPY %w1

 ---
 # Same as add_s64_gpr, for G_SHL operations.
 # CHECK-LABEL: name: shl_s64_gpr
 name:            shl_s64_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64 }
-# CHECK-NEXT:  - { id: 1, class: gpr64 }
-# CHECK-NEXT:  - { id: 2, class: gpr64 }
+# CHECK-NEXT:  - { id: 0, class: gpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: gpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %x0
 # CHECK:    %1 = COPY %x1

 ---
 # Same as add_s32_gpr, for G_LSHR operations.
 # CHECK-LABEL: name: lshr_s32_gpr
 name:            lshr_s32_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32 }
-# CHECK-NEXT:  - { id: 1, class: gpr32 }
-# CHECK-NEXT:  - { id: 2, class: gpr32 }
+# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %w0
 # CHECK:    %1 = COPY %w1

 ---
 # Same as add_s64_gpr, for G_LSHR operations.
 # CHECK-LABEL: name: lshr_s64_gpr
 name:            lshr_s64_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64 }
-# CHECK-NEXT:  - { id: 1, class: gpr64 }
-# CHECK-NEXT:  - { id: 2, class: gpr64 }
+# CHECK-NEXT:  - { id: 0, class: gpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: gpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %x0
 # CHECK:    %1 = COPY %x1

 ---
 # Same as add_s32_gpr, for G_ASHR operations.
 # CHECK-LABEL: name: ashr_s32_gpr
 name:            ashr_s32_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32 }
-# CHECK-NEXT:  - { id: 1, class: gpr32 }
-# CHECK-NEXT:  - { id: 2, class: gpr32 }
+# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %w0
 # CHECK:    %1 = COPY %w1

 ---
 # Same as add_s64_gpr, for G_ASHR operations.
 # CHECK-LABEL: name: ashr_s64_gpr
 name:            ashr_s64_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64 }
-# CHECK-NEXT:  - { id: 1, class: gpr64 }
-# CHECK-NEXT:  - { id: 2, class: gpr64 }
+# CHECK-NEXT:  - { id: 0, class: gpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: gpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %x0
 # CHECK:    %1 = COPY %x1

 # Check that we select s32 GPR G_MUL. This is trickier than other binops because
 # there is only MADDWrrr, and we have to use the WZR physreg.
 # CHECK-LABEL: name: mul_s32_gpr
 name:            mul_s32_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32 }
-# CHECK-NEXT:  - { id: 1, class: gpr32 }
-# CHECK-NEXT:  - { id: 2, class: gpr32 }
+# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %w0
 # CHECK:    %1 = COPY %w1

 ---
 # Same as mul_s32_gpr for the s64 type.
 # CHECK-LABEL: name: mul_s64_gpr
 name:            mul_s64_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64 }
-# CHECK-NEXT:  - { id: 1, class: gpr64 }
-# CHECK-NEXT:  - { id: 2, class: gpr64 }
+# CHECK-NEXT:  - { id: 0, class: gpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: gpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %x0
 # CHECK:    %1 = COPY %x1

 ---
 # Same as mul_s32_gpr for the s64 type.
 # CHECK-LABEL: name: mulh_s64_gpr
 name:            mulh_s64_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64 }
-# CHECK-NEXT:  - { id: 1, class: gpr64 }
-# CHECK-NEXT:  - { id: 2, class: gpr64 }
-# CHECK-NEXT:  - { id: 3, class: gpr64 }
+# CHECK-NEXT:  - { id: 0, class: gpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: gpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 3, class: gpr64, preferred-register: '' }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %x0
 # CHECK:    %1 = COPY %x1
 # CHECK:    %2 = SMULHrr %0, %1
 # CHECK:    %3 = UMULHrr %0, %1
 body:             |
   bb.0:

 ---
 # Same as add_s32_gpr, for G_SDIV operations.
 # CHECK-LABEL: name: sdiv_s32_gpr
 name:            sdiv_s32_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32 }
-# CHECK-NEXT:  - { id: 1, class: gpr32 }
-# CHECK-NEXT:  - { id: 2, class: gpr32 }
+# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %w0
 # CHECK:    %1 = COPY %w1

 ---
 # Same as add_s64_gpr, for G_SDIV operations.
 # CHECK-LABEL: name: sdiv_s64_gpr
 name:            sdiv_s64_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64 }
-# CHECK-NEXT:  - { id: 1, class: gpr64 }
-# CHECK-NEXT:  - { id: 2, class: gpr64 }
+# CHECK-NEXT:  - { id: 0, class: gpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: gpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %x0
 # CHECK:    %1 = COPY %x1

 ---
 # Same as add_s32_gpr, for G_UDIV operations.
 # CHECK-LABEL: name: udiv_s32_gpr
 name:            udiv_s32_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32 }
-# CHECK-NEXT:  - { id: 1, class: gpr32 }
-# CHECK-NEXT:  - { id: 2, class: gpr32 }
+# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %w0
 # CHECK:    %1 = COPY %w1

 ---
 # Same as add_s64_gpr, for G_UDIV operations.
 # CHECK-LABEL: name: udiv_s64_gpr
 name:            udiv_s64_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64 }
-# CHECK-NEXT:  - { id: 1, class: gpr64 }
-# CHECK-NEXT:  - { id: 2, class: gpr64 }
+# CHECK-NEXT:  - { id: 0, class: gpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: gpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %x0
 # CHECK:    %1 = COPY %x1

 ---
 # Check that we select a s32 FPR G_FADD into FADDSrr.
 # CHECK-LABEL: name: fadd_s32_fpr
 name:            fadd_s32_fpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr32 }
-# CHECK-NEXT:  - { id: 1, class: fpr32 }
-# CHECK-NEXT:  - { id: 2, class: fpr32 }
+# CHECK-NEXT:  - { id: 0, class: fpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: fpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: fpr32, preferred-register: '' }
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
   - { id: 2, class: fpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %s0
 # CHECK:    %1 = COPY %s1

 
 ---
 # CHECK-LABEL: name: fadd_s64_fpr
 name:            fadd_s64_fpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr64 }
-# CHECK-NEXT:  - { id: 1, class: fpr64 }
-# CHECK-NEXT:  - { id: 2, class: fpr64 }
+# CHECK-NEXT:  - { id: 0, class: fpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: fpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: fpr64, preferred-register: '' }
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
   - { id: 2, class: fpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %d0
 # CHECK:    %1 = COPY %d1

 
 ---
 # CHECK-LABEL: name: fsub_s32_fpr
 name:            fsub_s32_fpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr32 }
-# CHECK-NEXT:  - { id: 1, class: fpr32 }
-# CHECK-NEXT:  - { id: 2, class: fpr32 }
+# CHECK-NEXT:  - { id: 0, class: fpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: fpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: fpr32, preferred-register: '' }
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
   - { id: 2, class: fpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %s0
 # CHECK:    %1 = COPY %s1

 
 ---
 # CHECK-LABEL: name: fsub_s64_fpr
 name:            fsub_s64_fpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr64 }
-# CHECK-NEXT:  - { id: 1, class: fpr64 }
-# CHECK-NEXT:  - { id: 2, class: fpr64 }
+# CHECK-NEXT:  - { id: 0, class: fpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: fpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: fpr64, preferred-register: '' }
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
   - { id: 2, class: fpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %d0
 # CHECK:    %1 = COPY %d1

 
 ---
 # CHECK-LABEL: name: fmul_s32_fpr
 name:            fmul_s32_fpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr32 }
-# CHECK-NEXT:  - { id: 1, class: fpr32 }
-# CHECK-NEXT:  - { id: 2, class: fpr32 }
+# CHECK-NEXT:  - { id: 0, class: fpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: fpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: fpr32, preferred-register: '' }
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
   - { id: 2, class: fpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %s0
 # CHECK:    %1 = COPY %s1

 
 ---
 # CHECK-LABEL: name: fmul_s64_fpr
 name:            fmul_s64_fpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr64 }
-# CHECK-NEXT:  - { id: 1, class: fpr64 }
-# CHECK-NEXT:  - { id: 2, class: fpr64 }
+# CHECK-NEXT:  - { id: 0, class: fpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: fpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: fpr64, preferred-register: '' }
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
   - { id: 2, class: fpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %d0
 # CHECK:    %1 = COPY %d1

 
 ---
 # CHECK-LABEL: name: fdiv_s32_fpr
 name:            fdiv_s32_fpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr32 }
-# CHECK-NEXT:  - { id: 1, class: fpr32 }
-# CHECK-NEXT:  - { id: 2, class: fpr32 }
+# CHECK-NEXT:  - { id: 0, class: fpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: fpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: fpr32, preferred-register: '' }
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
   - { id: 2, class: fpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %s0
 # CHECK:    %1 = COPY %s1

 
 ---
 # CHECK-LABEL: name: fdiv_s64_fpr
 name:            fdiv_s64_fpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr64 }
-# CHECK-NEXT:  - { id: 1, class: fpr64 }
-# CHECK-NEXT:  - { id: 2, class: fpr64 }
+# CHECK-NEXT:  - { id: 0, class: fpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: fpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: fpr64, preferred-register: '' }
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
   - { id: 2, class: fpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %d0
 # CHECK:    %1 = COPY %d1

test/CodeGen/AArch64/GlobalISel/select-bitcast.mir

 ...
 
 ---
 # CHECK-LABEL: name: bitcast_s32_gpr
 name:            bitcast_s32_gpr
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32all }
-# CHECK-NEXT:  - { id: 1, class: gpr32all }
+# CHECK-NEXT:  - { id: 0, class: gpr32all, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr32all, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %w0
 # CHECK:    %1 = COPY %0
 body:             |
   bb.0:
     liveins: %w0
 
     %0(s32) = COPY %w0
     %1(s32) = G_BITCAST %0
     %w0 = COPY %1(s32)
 ...
 
 ---
 # CHECK-LABEL: name: bitcast_s32_fpr
 name:            bitcast_s32_fpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr32 }
-# CHECK-NEXT:  - { id: 1, class: fpr32 }
+# CHECK-NEXT:  - { id: 0, class: fpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: fpr32, preferred-register: '' }
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %s0
 # CHECK:    %1 = COPY %0
 body:             |
   bb.0:
     liveins: %s0
 
     %0(s32) = COPY %s0
     %1(s32) = G_BITCAST %0
     %s0 = COPY %1(s32)
 ...
 
 ---
 # CHECK-LABEL: name: bitcast_s32_gpr_fpr
 name:            bitcast_s32_gpr_fpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32all }
-# CHECK-NEXT:  - { id: 1, class: fpr32 }
+# CHECK-NEXT:  - { id: 0, class: gpr32all, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: fpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: fpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %w0
 # CHECK:    %1 = COPY %0
 body:             |
   bb.0:
     liveins: %w0
 
     %0(s32) = COPY %w0
     %1(s32) = G_BITCAST %0
     %s0 = COPY %1(s32)
 ...
 
 ---
 # CHECK-LABEL: name: bitcast_s32_fpr_gpr
 name:            bitcast_s32_fpr_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr32 }
-# CHECK-NEXT:  - { id: 1, class: gpr32all }
+# CHECK-NEXT:  - { id: 0, class: fpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr32all, preferred-register: '' }
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %s0
 # CHECK:    %1 = COPY %0
 body:             |
   bb.0:
     liveins: %s0
 
     %0(s32) = COPY %s0
     %1(s32) = G_BITCAST %0
     %w0 = COPY %1(s32)
 ...
 
 ---
 # CHECK-LABEL: name: bitcast_s64_gpr
 name:            bitcast_s64_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64all }
-# CHECK-NEXT:  - { id: 1, class: gpr64all }
+# CHECK-NEXT:  - { id: 0, class: gpr64all, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr64all, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %x0
 # CHECK:    %1 = COPY %0
 body:             |
   bb.0:
     liveins: %x0
 
     %0(s64) = COPY %x0
     %1(s64) = G_BITCAST %0
     %x0 = COPY %1(s64)
 ...
 
 ---
 # CHECK-LABEL: name: bitcast_s64_fpr
 name:            bitcast_s64_fpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr64 }
-# CHECK-NEXT:  - { id: 1, class: fpr64 }
+# CHECK-NEXT:  - { id: 0, class: fpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: fpr64, preferred-register: '' }
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %d0
 # CHECK:    %1 = COPY %0
 body:             |
   bb.0:
     liveins: %d0
 
     %0(s64) = COPY %d0
     %1(s64) = G_BITCAST %0
     %d0 = COPY %1(s64)
 ...
 
 ---
 # CHECK-LABEL: name: bitcast_s64_gpr_fpr
 name:            bitcast_s64_gpr_fpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64all }
-# CHECK-NEXT:  - { id: 1, class: fpr64 }
+# CHECK-NEXT:  - { id: 0, class: gpr64all, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: fpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: fpr }
 # CHECK:  body:
 # CHECK:    %0 = COPY %x0
 # CHECK:    %1 = COPY %0
 body:             |
   bb.0:
     liveins: %x0
 
     %0(s64) = COPY %x0
     %1(s64) = G_BITCAST %0
     %d0 = COPY %1(s64)
 ...
 
 ---
 # CHECK-LABEL: name: bitcast_s64_fpr_gpr
 name:            bitcast_s64_fpr_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr64 }
-# CHECK-NEXT:  - { id: 1, class: gpr64all }
+# CHECK-NEXT:  - { id: 0, class: fpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr64all, preferred-register: '' }
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %d0
 # CHECK:    %1 = COPY %0
 body:             |
   bb.0:
     liveins: %d0
 
     %0(s64) = COPY %d0
     %1(s64) = G_BITCAST %0
     %x0 = COPY %1(s64)
 ...

test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir

 
 ---
 # CHECK-LABEL: name: fptrunc
 name:            fptrunc
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK: - { id: 0, class: fpr64 }
-# CHECK: - { id: 1, class: fpr32 }
+# CHECK: - { id: 0, class: fpr64, preferred-register: '' }
+# CHECK: - { id: 1, class: fpr32, preferred-register: '' }
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %d0
 # CHECK:    %1 = FCVTSDr %0
 body:             |
   bb.0:
     liveins: %d0
 
     %0(s64) = COPY %d0
     %1(s32) = G_FPTRUNC %0
     %s0 = COPY %1(s32)
 ...
 
 ---
 # CHECK-LABEL: name: fpext
 name:            fpext
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK: - { id: 0, class: fpr32 }
-# CHECK: - { id: 1, class: fpr64 }
+# CHECK: - { id: 0, class: fpr32, preferred-register: '' }
+# CHECK: - { id: 1, class: fpr64, preferred-register: '' }
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %s0
 # CHECK:    %1 = FCVTDSr %0
 body:             |
   bb.0:
     liveins: %d0
 
     %0(s32) = COPY %s0
     %1(s64) = G_FPEXT %0
     %d0 = COPY %1(s64)
 ...
 
 ---
 # CHECK-LABEL: name: sitofp_s32_s32_fpr
 name:            sitofp_s32_s32_fpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32 }
-# CHECK-NEXT:  - { id: 1, class: fpr32 }
+# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: fpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: fpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %w0
 # CHECK:    %1 = SCVTFUWSri %0
 body:             |
   bb.0:
     liveins: %w0
 
     %0(s32) = COPY %w0
     %1(s32) = G_SITOFP %0
     %s0 = COPY %1(s32)
 ...
 
 ---
 # CHECK-LABEL: name: sitofp_s32_s64_fpr
 name:            sitofp_s32_s64_fpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64 }
-# CHECK-NEXT:  - { id: 1, class: fpr32 }
+# CHECK-NEXT:  - { id: 0, class: gpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: fpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: fpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %x0
 # CHECK:    %1 = SCVTFUXSri %0
 body:             |
   bb.0:
     liveins: %x0
 
     %0(s64) = COPY %x0
     %1(s32) = G_SITOFP %0
     %s0 = COPY %1(s32)
 ...
 
 ---
 # CHECK-LABEL: name: sitofp_s64_s32_fpr
 name:            sitofp_s64_s32_fpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32 }
-# CHECK-NEXT:  - { id: 1, class: fpr64 }
+# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: fpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: fpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %w0
 # CHECK:    %1 = SCVTFUWDri %0
 body:             |
   bb.0:
     liveins: %w0
 
     %0(s32) = COPY %w0
     %1(s64) = G_SITOFP %0
     %d0 = COPY %1(s64)
 ...
 
 ---
 # CHECK-LABEL: name: sitofp_s64_s64_fpr
 name:            sitofp_s64_s64_fpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64 }
-# CHECK-NEXT:  - { id: 1, class: fpr64 }
+# CHECK-NEXT:  - { id: 0, class: gpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: fpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: fpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %x0
 # CHECK:    %1 = SCVTFUXDri %0
 body:             |
   bb.0:
     liveins: %x0
 
     %0(s64) = COPY %x0
     %1(s64) = G_SITOFP %0
     %d0 = COPY %1(s64)
 ...
 
 ---
 # CHECK-LABEL: name: uitofp_s32_s32_fpr
 name:            uitofp_s32_s32_fpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32 }
-# CHECK-NEXT:  - { id: 1, class: fpr32 }
+# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: fpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: fpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %w0
 # CHECK:    %1 = UCVTFUWSri %0
 body:             |
   bb.0:
     liveins: %w0
 
     %0(s32) = COPY %w0
     %1(s32) = G_UITOFP %0
     %s0 = COPY %1(s32)
 ...
 
 ---
 # CHECK-LABEL: name: uitofp_s32_s64_fpr
 name:            uitofp_s32_s64_fpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64 }
-# CHECK-NEXT:  - { id: 1, class: fpr32 }
+# CHECK-NEXT:  - { id: 0, class: gpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: fpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: fpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %x0
 # CHECK:    %1 = UCVTFUXSri %0
 body:             |
   bb.0:
     liveins: %x0
 
     %0(s64) = COPY %x0
     %1(s32) = G_UITOFP %0
     %s0 = COPY %1(s32)
 ...
 
 ---
 # CHECK-LABEL: name: uitofp_s64_s32_fpr
 name:            uitofp_s64_s32_fpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32 }
-# CHECK-NEXT:  - { id: 1, class: fpr64 }
+# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: fpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: fpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %w0
 # CHECK:    %1 = UCVTFUWDri %0
 body:             |
   bb.0:
     liveins: %w0
 
     %0(s32) = COPY %w0
     %1(s64) = G_UITOFP %0
     %d0 = COPY %1(s64)
 ...
 
 ---
 # CHECK-LABEL: name: uitofp_s64_s64_fpr
 name:            uitofp_s64_s64_fpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64 }
-# CHECK-NEXT:  - { id: 1, class: fpr64 }
+# CHECK-NEXT:  - { id: 0, class: gpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: fpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: fpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %x0
 # CHECK:    %1 = UCVTFUXDri %0
 body:             |
   bb.0:
     liveins: %x0
 
     %0(s64) = COPY %x0
     %1(s64) = G_UITOFP %0
     %d0 = COPY %1(s64)
 ...
 
 ---
 # CHECK-LABEL: name: fptosi_s32_s32_gpr
 name:            fptosi_s32_s32_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr32 }
-# CHECK-NEXT:  - { id: 1, class: gpr32 }
+# CHECK-NEXT:  - { id: 0, class: fpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %s0
 # CHECK:    %1 = FCVTZSUWSr %0
 body:             |
   bb.0:
     liveins: %s0
 
     %0(s32) = COPY %s0
     %1(s32) = G_FPTOSI %0
     %w0 = COPY %1(s32)
 ...
 
 ---
 # CHECK-LABEL: name: fptosi_s32_s64_gpr
 name:            fptosi_s32_s64_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr64 }
-# CHECK-NEXT:  - { id: 1, class: gpr32 }
+# CHECK-NEXT:  - { id: 0, class: fpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %d0
 # CHECK:    %1 = FCVTZSUWDr %0
 body:             |
   bb.0:
     liveins: %d0
 
     %0(s64) = COPY %d0
     %1(s32) = G_FPTOSI %0
     %w0 = COPY %1(s32)
 ...
 
 ---
 # CHECK-LABEL: name: fptosi_s64_s32_gpr
 name:            fptosi_s64_s32_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr32 }
-# CHECK-NEXT:  - { id: 1, class: gpr64 }
+# CHECK-NEXT:  - { id: 0, class: fpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr64, preferred-register: '' }
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %s0
 # CHECK:    %1 = FCVTZSUXSr %0
 body:             |
   bb.0:
     liveins: %s0
 
     %0(s32) = COPY %s0
     %1(s64) = G_FPTOSI %0
     %x0 = COPY %1(s64)
 ...
 
 ---
 # CHECK-LABEL: name: fptosi_s64_s64_gpr
 name:            fptosi_s64_s64_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr64 }
-# CHECK-NEXT:  - { id: 1, class: gpr64 }
+# CHECK-NEXT:  - { id: 0, class: fpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr64, preferred-register: '' }
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %d0
 # CHECK:    %1 = FCVTZSUXDr %0
 body:             |
   bb.0:
     liveins: %d0
 
     %0(s64) = COPY %d0
     %1(s64) = G_FPTOSI %0
     %x0 = COPY %1(s64)
 ...
 
 ---
 # CHECK-LABEL: name: fptoui_s32_s32_gpr
 name:            fptoui_s32_s32_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr32 }
-# CHECK-NEXT:  - { id: 1, class: gpr32 }
+# CHECK-NEXT:  - { id: 0, class: fpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %s0
 # CHECK:    %1 = FCVTZUUWSr %0
 body:             |
   bb.0:
     liveins: %s0
 
     %0(s32) = COPY %s0
     %1(s32) = G_FPTOUI %0
     %w0 = COPY %1(s32)
 ...
 
 ---
 # CHECK-LABEL: name: fptoui_s32_s64_gpr
 name:            fptoui_s32_s64_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr64 }
-# CHECK-NEXT:  - { id: 1, class: gpr32 }
+# CHECK-NEXT:  - { id: 0, class: fpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %d0
 # CHECK:    %1 = FCVTZUUWDr %0
 body:             |
   bb.0:
     liveins: %d0
 
     %0(s64) = COPY %d0
     %1(s32) = G_FPTOUI %0
     %w0 = COPY %1(s32)
 ...
 
 ---
 # CHECK-LABEL: name: fptoui_s64_s32_gpr
 name:            fptoui_s64_s32_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr32 }
-# CHECK-NEXT:  - { id: 1, class: gpr64 }
+# CHECK-NEXT:  - { id: 0, class: fpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr64, preferred-register: '' }
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %s0
 # CHECK:    %1 = FCVTZUUXSr %0
 body:             |
   bb.0:
     liveins: %s0
 
     %0(s32) = COPY %s0
     %1(s64) = G_FPTOUI %0
     %x0 = COPY %1(s64)
 ...
 
 ---
 # CHECK-LABEL: name: fptoui_s64_s64_gpr
 name:            fptoui_s64_s64_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr64 }
-# CHECK-NEXT:  - { id: 1, class: gpr64 }
+# CHECK-NEXT:  - { id: 0, class: fpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr64, preferred-register: '' }
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %d0
 # CHECK:    %1 = FCVTZUUXDr %0
 body:             |
   bb.0:
     liveins: %d0
 
     %0(s64) = COPY %d0
     %1(s64) = G_FPTOUI %0
     %x0 = COPY %1(s64)
 ...

test/CodeGen/AArch64/GlobalISel/select-int-ext.mir

 
 ---
 # CHECK-LABEL: name: anyext_s64_from_s32
 name:            anyext_s64_from_s32
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32all }
-# CHECK-NEXT:  - { id: 1, class: gpr64all }
-# CHECK-NEXT:  - { id: 2, class: gpr64all }
+# CHECK-NEXT:  - { id: 0, class: gpr32all, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr64all, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: gpr64all, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %w0
 # CHECK:    %2 = SUBREG_TO_REG 0, %0, 15
 # CHECK:    %1 = COPY %2
 body:             |
   bb.0:
     liveins: %w0
 
     %0(s32) = COPY %w0
     %1(s64) = G_ANYEXT %0
     %x0 = COPY %1(s64)
 ...
 
 ---
 # CHECK-LABEL: name: anyext_s32_from_s8
 name:            anyext_s32_from_s8
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32all }
-# CHECK-NEXT:  - { id: 1, class: gpr32all }
+# CHECK-NEXT:  - { id: 0, class: gpr32all, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr32all, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %w0
 # CHECK:    %1 = COPY %0
 body:             |
   bb.0:
     liveins: %w0
 
     %0(s8) = COPY %w0
     %1(s32) = G_ANYEXT %0
     %w0 = COPY %1(s32)
 ...
 
 ---
 # CHECK-LABEL: name: zext_s64_from_s32
 name:            zext_s64_from_s32
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32 }
-# CHECK-NEXT:  - { id: 1, class: gpr64 }
-# CHECK-NEXT:  - { id: 2, class: gpr64 }
+# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: gpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %w0
 # CHECK:    %2 = SUBREG_TO_REG 0, %0, 15
 # CHECK:    %1 = UBFMXri %2, 0, 31
 body:             |
   bb.0:
     liveins: %w0
 
     %0(s32) = COPY %w0
     %1(s64) = G_ZEXT %0
     %x0 = COPY %1(s64)
 ...
 
 ---
 # CHECK-LABEL: name: zext_s32_from_s16
 name:            zext_s32_from_s16
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32 }
-# CHECK-NEXT:  - { id: 1, class: gpr32 }
+# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %w0
 # CHECK:    %1 = UBFMWri %0, 0, 15
 body:             |
   bb.0:
     liveins: %w0
 
     %0(s16) = COPY %w0
     %1(s32) = G_ZEXT %0
     %w0 = COPY %1
 ...
 
 ---
 # CHECK-LABEL: name: zext_s32_from_s8
 name:            zext_s32_from_s8
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32 }
-# CHECK-NEXT:  - { id: 1, class: gpr32 }
+# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %w0
 # CHECK:    %1 = UBFMWri %0, 0, 7
 body:             |
   bb.0:
     liveins: %w0
 
     %0(s8) = COPY %w0
     %1(s32) = G_ZEXT %0
     %w0 = COPY %1(s32)
 ...
 
 ---
 # CHECK-LABEL: name: zext_s16_from_s8
 name:            zext_s16_from_s8
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32 }
-# CHECK-NEXT:  - { id: 1, class: gpr32 }
+# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %w0
 # CHECK:    %1 = UBFMWri %0, 0, 7
 body:             |
   bb.0:
     liveins: %w0
 
     %0(s8) = COPY %w0
     %1(s16) = G_ZEXT %0
     %w0 = COPY %1(s16)
 ...
 
 ---
 # CHECK-LABEL: name: sext_s64_from_s32
 name:            sext_s64_from_s32
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32 }
-# CHECK-NEXT:  - { id: 1, class: gpr64 }
-# CHECK-NEXT:  - { id: 2, class: gpr64 }
+# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: gpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %w0
 # CHECK:    %2 = SUBREG_TO_REG 0, %0, 15
 # CHECK:    %1 = SBFMXri %2, 0, 31
 body:             |
   bb.0:
     liveins: %w0
 
     %0(s32) = COPY %w0
     %1(s64) = G_SEXT %0
     %x0 = COPY %1(s64)
 ...
 
 ---
 # CHECK-LABEL: name: sext_s32_from_s16
 name:            sext_s32_from_s16
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32 }
-# CHECK-NEXT:  - { id: 1, class: gpr32 }
+# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %w0
 # CHECK:    %1 = SBFMWri %0, 0, 15
 body:             |
   bb.0:
     liveins: %w0
 
     %0(s16) = COPY %w0
     %1(s32) = G_SEXT %0
     %w0 = COPY %1
 ...
 
 ---
 # CHECK-LABEL: name: sext_s32_from_s8
 name:            sext_s32_from_s8
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32 }
-# CHECK-NEXT:  - { id: 1, class: gpr32 }
+# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %w0
 # CHECK:    %1 = SBFMWri %0, 0, 7
 body:             |
   bb.0:
     liveins: %w0
 
     %0(s8) = COPY %w0
     %1(s32) = G_SEXT %0
     %w0 = COPY %1(s32)
 ...
 
 ---
 # CHECK-LABEL: name: sext_s16_from_s8
 name:            sext_s16_from_s8
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32 }
-# CHECK-NEXT:  - { id: 1, class: gpr32 }
+# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %w0
 # CHECK:    %1 = SBFMWri %0, 0, 7
 body:             |
   bb.0:
     liveins: %w0
 
     %0(s8) = COPY %w0
     %1(s16) = G_SEXT %0
     %w0 = COPY %1(s16)
 ...

test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir

 
 ---
 # CHECK-LABEL: name: inttoptr_p0_s64
 name:            inttoptr_p0_s64
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64all }
-# CHECK-NEXT:  - { id: 1, class: gpr64all }
+# CHECK-NEXT:  - { id: 0, class: gpr64all, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr64all, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 # CHECK:  body:
 # CHECK:    %0 = COPY %x0
 # CHECK:    %1 = COPY %0
 body:             |
   bb.0:
     liveins: %x0
     %0(s64) = COPY %x0
     %1(p0) = G_INTTOPTR %0
     %x0 = COPY %1(p0)
 ...
 
 ---
 # CHECK-LABEL: name: ptrtoint_s64_p0
 name:            ptrtoint_s64_p0
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64 }
-# CHECK-NEXT:  - { id: 1, class: gpr64 }
+# CHECK-NEXT:  - { id: 0, class: gpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 # CHECK:  body:
 # CHECK:    %0 = COPY %x0
 # CHECK:    %1 = COPY %0
 body:             |
   bb.0:
     liveins: %x0
     %0(p0) = COPY %x0
     %1(s64) = G_PTRTOINT %0
     %x0 = COPY %1(s64)
 ...
 
 ---
 # CHECK-LABEL: name: ptrtoint_s32_p0
 name:            ptrtoint_s32_p0
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64 }
-# CHECK-NEXT:  - { id: 1, class: gpr32 }
+# CHECK-NEXT:  - { id: 0, class: gpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 # CHECK:  body:
 # CHECK:    %0 = COPY %x0
 # CHECK:    %1 = COPY %0.sub_32
 body:             |
   bb.0:
     liveins: %x0
     %0(p0) = COPY %x0
     %1(s32) = G_PTRTOINT %0
     %w0 = COPY %1(s32)
 ...
 
 ---
 # CHECK-LABEL: name: ptrtoint_s16_p0
 name:            ptrtoint_s16_p0
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64 }
-# CHECK-NEXT:  - { id: 1, class: gpr32 }
+# CHECK-NEXT:  - { id: 0, class: gpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 # CHECK:  body:
 # CHECK:    %0 = COPY %x0
 # CHECK:    %1 = COPY %0.sub_32
 body:             |
   bb.0:
     liveins: %x0
     %0(p0) = COPY %x0
     %1(s16) = G_PTRTOINT %0
     %w0 = COPY %1(s16)
 ...
 
 ---
 # CHECK-LABEL: name: ptrtoint_s8_p0
 name:            ptrtoint_s8_p0
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64 }
-# CHECK-NEXT:  - { id: 1, class: gpr32 }
+# CHECK-NEXT:  - { id: 0, class: gpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 # CHECK:  body:
 # CHECK:    %0 = COPY %x0
 # CHECK:    %1 = COPY %0.sub_32
 body:             |
   bb.0:
     liveins: %x0
     %0(p0) = COPY %x0
     %1(s8) = G_PTRTOINT %0
     %w0 = COPY %1(s8)
 ...
 
 ---
 # CHECK-LABEL: name: ptrtoint_s1_p0
 name:            ptrtoint_s1_p0
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64 }
-# CHECK-NEXT:  - { id: 1, class: gpr32 }
+# CHECK-NEXT:  - { id: 0, class: gpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 # CHECK:  body:
 # CHECK:    %0 = COPY %x0
 # CHECK:    %1 = COPY %0.sub_32
 body:             |
   bb.0:
     liveins: %x0
     %0(p0) = COPY %x0
     %1(s1) = G_PTRTOINT %0
     %w0 = COPY %1(s1)
 ...

test/CodeGen/AArch64/GlobalISel/select-load.mir

 
 ---
 # CHECK-LABEL: name: load_s64_gpr
 name:            load_s64_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp }
-# CHECK-NEXT:  - { id: 1, class: gpr64 }
+# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
 # CHECK:  body:
 # CHECK: %0 = COPY %x0
 # CHECK: %1 = LDRXui %0, 0 :: (load 8 from %ir.addr)
 body:             |
   bb.0:
     liveins: %x0
 
     %0(p0) = COPY %x0
     %1(s64) = G_LOAD  %0 :: (load 8 from %ir.addr)
     %x0 = COPY %1(s64)
 ...
 
 ---
 # CHECK-LABEL: name: load_s32_gpr
 name:            load_s32_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp }
-# CHECK-NEXT:  - { id: 1, class: gpr32 }
+# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
 # CHECK:  body:
 # CHECK: %0 = COPY %x0
 # CHECK: %1 = LDRWui %0, 0 :: (load 4 from %ir.addr)
 body:             |
   bb.0:
     liveins: %x0
 
     %0(p0) = COPY %x0
     %1(s32) = G_LOAD  %0 :: (load 4 from %ir.addr)
     %w0 = COPY %1(s32)
 ...
 
 ---
 # CHECK-LABEL: name: load_s16_gpr
 name:            load_s16_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp }
-# CHECK-NEXT:  - { id: 1, class: gpr32 }
+# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
 # CHECK:  body:
 # CHECK: %0 = COPY %x0
 # CHECK: %1 = LDRHHui %0, 0 :: (load 2 from %ir.addr)
 body:             |
   bb.0:
     liveins: %x0
 
     %0(p0) = COPY %x0
     %1(s16) = G_LOAD  %0 :: (load 2 from %ir.addr)
     %w0 = COPY %1(s16)
 ...
 
 ---
 # CHECK-LABEL: name: load_s8_gpr
 name:            load_s8_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp }
-# CHECK-NEXT:  - { id: 1, class: gpr32 }
+# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
 # CHECK:  body:
 # CHECK: %0 = COPY %x0
 # CHECK: %1 = LDRBBui %0, 0 :: (load 1 from %ir.addr)
 body:             |
   bb.0:
     liveins: %x0
 
     %0(p0) = COPY %x0
     %1(s8) = G_LOAD  %0 :: (load 1 from %ir.addr)
     %w0 = COPY %1(s8)
 ...
 
 ---
 # CHECK-LABEL: name: load_fi_s64_gpr
 name:            load_fi_s64_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr }
-# CHECK-NEXT:  - { id: 1, class: gpr64 }
+# CHECK-NEXT:  - { id: 0, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
 stack:
   - { id: 0, name: ptr0, offset: 0, size: 8, alignment: 8 }
 
 # CHECK:  body:

 
 ---
 # CHECK-LABEL: name: load_gep_128_s64_gpr
 name:            load_gep_128_s64_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp }
-# CHECK-NEXT:  - { id: 1, class: gpr }
-# CHECK-NEXT:  - { id: 2, class: gpr }
-# CHECK-NEXT:  - { id: 3, class: gpr64 }
+# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 3, class: gpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 
 # CHECK:  body:
 # CHECK: %0 = COPY %x0

 
 ---
 # CHECK-LABEL: name: load_gep_512_s32_gpr
 name:            load_gep_512_s32_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp }
-# CHECK-NEXT:  - { id: 1, class: gpr }
-# CHECK-NEXT:  - { id: 2, class: gpr }
-# CHECK-NEXT:  - { id: 3, class: gpr32 }
+# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 3, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 
 # CHECK:  body:
 # CHECK: %0 = COPY %x0

 
 ---
 # CHECK-LABEL: name: load_gep_64_s16_gpr
 name:            load_gep_64_s16_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp }
-# CHECK-NEXT:  - { id: 1, class: gpr }
-# CHECK-NEXT:  - { id: 2, class: gpr }
-# CHECK-NEXT:  - { id: 3, class: gpr32 }
+# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 3, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 
 # CHECK:  body:
 # CHECK: %0 = COPY %x0

 
 ---
 # CHECK-LABEL: name: load_gep_1_s8_gpr
 name:            load_gep_1_s8_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp }
-# CHECK-NEXT:  - { id: 1, class: gpr }
-# CHECK-NEXT:  - { id: 2, class: gpr }
-# CHECK-NEXT:  - { id: 3, class: gpr32 }
+# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 3, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 
 # CHECK:  body:
 # CHECK: %0 = COPY %x0

 
 ---
 # CHECK-LABEL: name: load_s64_fpr
 name:            load_s64_fpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp }
-# CHECK-NEXT:  - { id: 1, class: fpr64 }
+# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: fpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: fpr }
 
 # CHECK:  body:
 # CHECK: %0 = COPY %x0
 # CHECK: %1 = LDRDui %0, 0 :: (load 8 from %ir.addr)
 body:             |
   bb.0:
     liveins: %x0
 
     %0(p0) = COPY %x0
     %1(s64) = G_LOAD  %0 :: (load 8 from %ir.addr)
     %d0 = COPY %1(s64)
 ...
 
 ---
 # CHECK-LABEL: name: load_s32_fpr
 name:            load_s32_fpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp }
-# CHECK-NEXT:  - { id: 1, class: fpr32 }
+# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: fpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: fpr }
 
 # CHECK:  body:
 # CHECK: %0 = COPY %x0
 # CHECK: %1 = LDRSui %0, 0 :: (load 4 from %ir.addr)
 body:             |
   bb.0:
     liveins: %x0
 
     %0(p0) = COPY %x0
     %1(s32) = G_LOAD  %0 :: (load 4 from %ir.addr)
     %s0 = COPY %1(s32)
 ...
 
 ---
 # CHECK-LABEL: name: load_s16_fpr
 name:            load_s16_fpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp }
-# CHECK-NEXT:  - { id: 1, class: fpr16 }
+# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: fpr16, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: fpr }
 
 # CHECK:  body:
 # CHECK: %0 = COPY %x0
 # CHECK: %1 = LDRHui %0, 0 :: (load 2 from %ir.addr)
 body:             |
   bb.0:
     liveins: %x0
 
     %0(p0) = COPY %x0
     %1(s16) = G_LOAD  %0 :: (load 2 from %ir.addr)
     %h0 = COPY %1(s16)
 ...
 
 ---
 # CHECK-LABEL: name: load_s8_fpr
 name:            load_s8_fpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp }
-# CHECK-NEXT:  - { id: 1, class: fpr8 }
+# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: fpr8, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: fpr }
 
 # CHECK:  body:
 # CHECK: %0 = COPY %x0
 # CHECK: %1 = LDRBui %0, 0 :: (load 1 from %ir.addr)
 body:             |
   bb.0:
     liveins: %x0
 
     %0(p0) = COPY %x0
     %1(s8) = G_LOAD  %0 :: (load 1 from %ir.addr)
     %b0 = COPY %1(s8)
 ...
 
 ---
 # CHECK-LABEL: name: load_gep_8_s64_fpr
 name:            load_gep_8_s64_fpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp }
-# CHECK-NEXT:  - { id: 1, class: gpr }
-# CHECK-NEXT:  - { id: 2, class: gpr }
-# CHECK-NEXT:  - { id: 3, class: fpr64 }
+# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 3, class: fpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: fpr }
 
 # CHECK:  body:
 # CHECK: %0 = COPY %x0

 
 ---
 # CHECK-LABEL: name: load_gep_16_s32_fpr
 name:            load_gep_16_s32_fpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp }
-# CHECK-NEXT:  - { id: 1, class: gpr }
-# CHECK-NEXT:  - { id: 2, class: gpr }
-# CHECK-NEXT:  - { id: 3, class: fpr32 }
+# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 3, class: fpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: fpr }
 
 # CHECK:  body:
 # CHECK: %0 = COPY %x0

 
 ---
 # CHECK-LABEL: name: load_gep_64_s16_fpr
 name:            load_gep_64_s16_fpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp }
-# CHECK-NEXT:  - { id: 1, class: gpr }
-# CHECK-NEXT:  - { id: 2, class: gpr }
-# CHECK-NEXT:  - { id: 3, class: fpr16 }
+# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 3, class: fpr16, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: fpr }
 
 # CHECK:  body:
 # CHECK: %0 = COPY %x0

 
 ---
 # CHECK-LABEL: name: load_gep_32_s8_fpr
 name:            load_gep_32_s8_fpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp }
-# CHECK-NEXT:  - { id: 1, class: gpr }
-# CHECK-NEXT:  - { id: 2, class: gpr }
-# CHECK-NEXT:  - { id: 3, class: fpr8 }
+# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 3, class: fpr8, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: fpr }
 
 # CHECK:  body:
 # CHECK: %0 = COPY %x0

test/CodeGen/AArch64/GlobalISel/select-muladd.mir

 # RUN: llc -O0 -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
 
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
 
   define void @SMADDLrrr_gpr() { ret void }
 ...
 
 ---
 # CHECK-LABEL: name: SMADDLrrr_gpr
 name:            SMADDLrrr_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64 }
-# CHECK-NEXT:  - { id: 1, class: gpr32 }
-# CHECK-NEXT:  - { id: 2, class: gpr32 }
-# CHECK-NEXT:  - { id: 3, class: gpr }
-# CHECK-NEXT:  - { id: 4, class: gpr }
-# CHECK-NEXT:  - { id: 5, class: gpr }
-# CHECK-NEXT:  - { id: 6, class: gpr64 }
+# CHECK-NEXT:  - { id: 0, class: gpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 3, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 4, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 5, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 6, class: gpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
   - { id: 4, class: gpr }
   - { id: 5, class: gpr }
   - { id: 6, class: gpr }

test/CodeGen/AArch64/GlobalISel/select-store.mir

 
 ---
 # CHECK-LABEL: name: store_s64_gpr
 name:            store_s64_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp }
-# CHECK-NEXT:  - { id: 1, class: gpr64 }
+# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
 # CHECK:  body:
 # CHECK: %0 = COPY %x0
 # CHECK: %1 = COPY %x1
 # CHECK: STRXui %1, %0, 0 :: (store 8 into %ir.addr)

 
 ---
 # CHECK-LABEL: name: store_s32_gpr
 name:            store_s32_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp }
-# CHECK-NEXT:  - { id: 1, class: gpr32 }
+# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
 # CHECK:  body:
 # CHECK: %0 = COPY %x0
 # CHECK: %1 = COPY %w1
 # CHECK: STRWui %1, %0, 0 :: (store 4 into %ir.addr)

 
 ---
 # CHECK-LABEL: name: store_s16_gpr
 name:            store_s16_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp }
-# CHECK-NEXT:  - { id: 1, class: gpr32 }
+# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
 # CHECK:  body:
 # CHECK: %0 = COPY %x0
 # CHECK: %1 = COPY %w1
 # CHECK: STRHHui %1, %0, 0 :: (store 2 into %ir.addr)

 
 ---
 # CHECK-LABEL: name: store_s8_gpr
 name:            store_s8_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp }
-# CHECK-NEXT:  - { id: 1, class: gpr32 }
+# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
 # CHECK:  body:
 # CHECK: %0 = COPY %x0
 # CHECK: %1 = COPY %w1
 # CHECK: STRBBui %1, %0, 0 :: (store 1 into %ir.addr)

 
 ---
 # CHECK-LABEL: name: store_zero_s64_gpr
 name:            store_zero_s64_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp }
-# CHECK-NEXT:  - { id: 1, class: gpr }
+# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
 # CHECK:  body:
 # CHECK: %0 = COPY %x0
 # CHECK: STRXui %xzr, %0, 0 :: (store 8 into %ir.addr)
 body:             |
   bb.0:
     liveins: %x0, %x1
 
     %0(p0) = COPY %x0
     %1(s64) = G_CONSTANT i64 0
     G_STORE  %1, %0 :: (store 8 into %ir.addr)
 
 ...
 
 ---
 # CHECK-LABEL: name: store_zero_s32_gpr
 name:            store_zero_s32_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp }
-# CHECK-NEXT:  - { id: 1, class: gpr }
+# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
 # CHECK:  body:
 # CHECK: %0 = COPY %x0
 # CHECK: STRWui %wzr, %0, 0 :: (store 4 into %ir.addr)
 body:             |
   bb.0:
     liveins: %x0
 
     %0(p0) = COPY %x0
     %1(s32) = G_CONSTANT i32 0
     G_STORE  %1, %0 :: (store 4 into %ir.addr)
 
 ...
 
 ---
 # CHECK-LABEL: name: store_fi_s64_gpr
 name:            store_fi_s64_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64 }
-# CHECK-NEXT:  - { id: 1, class: gpr }
+# CHECK-NEXT:  - { id: 0, class: gpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
 stack:
   - { id: 0, name: ptr0, offset: 0, size: 8, alignment: 8 }
 
 # CHECK:  body:

 
 ---
 # CHECK-LABEL: name: store_gep_128_s64_gpr
 name:            store_gep_128_s64_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp }
-# CHECK-NEXT:  - { id: 1, class: gpr64 }
-# CHECK-NEXT:  - { id: 2, class: gpr }
-# CHECK-NEXT:  - { id: 3, class: gpr }
+# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 3, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 
 # CHECK:  body:
 # CHECK: %0 = COPY %x0

 
 ---
 # CHECK-LABEL: name: store_gep_512_s32_gpr
 name:            store_gep_512_s32_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp }
-# CHECK-NEXT:  - { id: 1, class: gpr32 }
-# CHECK-NEXT:  - { id: 2, class: gpr }
-# CHECK-NEXT:  - { id: 3, class: gpr }
+# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 3, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 
 # CHECK:  body:
 # CHECK: %0 = COPY %x0

 
 ---
 # CHECK-LABEL: name: store_gep_64_s16_gpr
 name:            store_gep_64_s16_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp }
-# CHECK-NEXT:  - { id: 1, class: gpr32 }
-# CHECK-NEXT:  - { id: 2, class: gpr }
-# CHECK-NEXT:  - { id: 3, class: gpr }
+# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 3, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 
 # CHECK:  body:
 # CHECK: %0 = COPY %x0

 
 ---
 # CHECK-LABEL: name: store_gep_1_s8_gpr
 name:            store_gep_1_s8_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp }
-# CHECK-NEXT:  - { id: 1, class: gpr32 }
-# CHECK-NEXT:  - { id: 2, class: gpr }
-# CHECK-NEXT:  - { id: 3, class: gpr }
+# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 3, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 
 # CHECK:  body:
 # CHECK: %0 = COPY %x0

 
 ---
 # CHECK-LABEL: name: store_s64_fpr
 name:            store_s64_fpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp }
-# CHECK-NEXT:  - { id: 1, class: fpr64 }
+# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: fpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: fpr }
 
 # CHECK:  body:
 # CHECK: %0 = COPY %x0
 # CHECK: %1 = COPY %d1
 # CHECK: STRDui %1, %0, 0 :: (store 8 into %ir.addr)

 
 ---
 # CHECK-LABEL: name: store_s32_fpr
 name:            store_s32_fpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp }
-# CHECK-NEXT:  - { id: 1, class: fpr32 }
+# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: fpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: fpr }
 
 # CHECK:  body:
 # CHECK: %0 = COPY %x0
 # CHECK: %1 = COPY %s1
 # CHECK: STRSui %1, %0, 0 :: (store 4 into %ir.addr)

 
 ---
 # CHECK-LABEL: name: store_gep_8_s64_fpr
 name:            store_gep_8_s64_fpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp }
-# CHECK-NEXT:  - { id: 1, class: fpr64 }
-# CHECK-NEXT:  - { id: 2, class: gpr }
-# CHECK-NEXT:  - { id: 3, class: gpr }
+# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: fpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 3, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: fpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 
 # CHECK:  body:
 # CHECK: %0 = COPY %x0

 
 ---
 # CHECK-LABEL: name: store_gep_8_s32_fpr
 name:            store_gep_8_s32_fpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp }
-# CHECK-NEXT:  - { id: 1, class: fpr32 }
-# CHECK-NEXT:  - { id: 2, class: gpr }
-# CHECK-NEXT:  - { id: 3, class: gpr }
+# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: fpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 3, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: fpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 
 # CHECK:  body:
 # CHECK: %0 = COPY %x0

test/CodeGen/AArch64/GlobalISel/select-trunc.mir

 
 ---
 # CHECK-LABEL: name: trunc_s32_s64
 name:            trunc_s32_s64
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64 }
-# CHECK-NEXT:  - { id: 1, class: gpr32 }
+# CHECK-NEXT:  - { id: 0, class: gpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %1 = COPY %0.sub_32
 body:             |
   bb.0:
     liveins: %x0
 
     %0(s64) = COPY %x0
     %1(s32) = G_TRUNC %0
     %w0 = COPY %1(s32)
 ...
 
 ---
 # CHECK-LABEL: name: trunc_s8_s64
 name:            trunc_s8_s64
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64 }
-# CHECK-NEXT:  - { id: 1, class: gpr32 }
+# CHECK-NEXT:  - { id: 0, class: gpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %1 = COPY %0.sub_32
 body:             |
   bb.0:
     liveins: %x0
 
     %0(s64) = COPY %x0
     %1(s8) = G_TRUNC %0
     %w0 = COPY %1(s8)
 ...
 
 ---
 # CHECK-LABEL: name: trunc_s1_s32
 name:            trunc_s1_s32
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32 }
-# CHECK-NEXT:  - { id: 1, class: gpr32 }
+# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %1 = COPY %0
 body:             |
   bb.0:
     liveins: %w0
 
     %0(s32) = COPY %w0
     %1(s1) = G_TRUNC %0
     %w0 = COPY %1(s1)
 ...

test/CodeGen/AArch64/GlobalISel/select-xor.mir

 # Check that we select a 32-bit GPR G_XOR into EORWrr on GPR32.
 # Also check that we constrain the register class of the COPY to GPR32.
 # CHECK-LABEL: name: xor_s32_gpr
 name:            xor_s32_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32 }
-# CHECK-NEXT:  - { id: 1, class: gpr32 }
-# CHECK-NEXT:  - { id: 2, class: gpr32 }
+# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %w0
 # CHECK:    %1 = COPY %w1

 ---
 # Same as xor_s64_gpr, for 64-bit operations.
 # CHECK-LABEL: name: xor_s64_gpr
 name:            xor_s64_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64 }
-# CHECK-NEXT:  - { id: 1, class: gpr64 }
-# CHECK-NEXT:  - { id: 2, class: gpr64 }
+# CHECK-NEXT:  - { id: 0, class: gpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: gpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %x0
 # CHECK:    %1 = COPY %x1

 # Check that we select a 32-bit GPR G_XOR into EORWrr on GPR32.
 # Also check that we constrain the register class of the COPY to GPR32.
 # CHECK-LABEL: name: xor_constant_n1_s32_gpr
 name:            xor_constant_n1_s32_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32 }
-# CHECK-NEXT:  - { id: 1, class: gpr }
-# CHECK-NEXT:  - { id: 2, class: gpr32 }
+# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %w0
 # CHECK:    %2 = ORNWrr %wzr, %0

 ---
 # Same as xor_constant_n1_s64_gpr, for 64-bit operations.
 # CHECK-LABEL: name: xor_constant_n1_s64_gpr
 name:            xor_constant_n1_s64_gpr
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64 }
-# CHECK-NEXT:  - { id: 1, class: gpr }
-# CHECK-NEXT:  - { id: 2, class: gpr64 }
+# CHECK-NEXT:  - { id: 0, class: gpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: gpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %0 = COPY %x0
 # CHECK:    %2 = ORNXrr %xzr, %0

 ---
 # Check that we can obtain constants from other basic blocks.
 # CHECK-LABEL: name: xor_constant_n1_s32_gpr_2bb
 name:            xor_constant_n1_s32_gpr_2bb
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32 }
-# CHECK-NEXT:  - { id: 1, class: gpr }
-# CHECK-NEXT:  - { id: 2, class: gpr32 }
+# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 # CHECK:  body:
 # CHECK:    B %bb.1
 # CHECK:    %0 = COPY %w0

test/CodeGen/AArch64/GlobalISel/select.mir

 
 ---
 # CHECK-LABEL: name: frame_index
 name:            frame_index
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp }
+# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
 
 stack:
   - { id: 0, name: ptr0, offset: 0, size: 8, alignment: 8 }
 
 # CHECK:  body:
 # CHECK: %0 = ADDXri %stack.0.ptr0, 0, 0

 
 ---
 # CHECK-LABEL: name: icmp
 name:            icmp
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32 }
-# CHECK-NEXT:  - { id: 1, class: gpr32 }
-# CHECK-NEXT:  - { id: 2, class: gpr64 }
-# CHECK-NEXT:  - { id: 3, class: gpr32 }
-# CHECK-NEXT:  - { id: 4, class: gpr64 }
-# CHECK-NEXT:  - { id: 5, class: gpr32 }
+# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: gpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 3, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 4, class: gpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 5, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
   - { id: 4, class: gpr }
   - { id: 5, class: gpr }
 

 
 ---
 # CHECK-LABEL: name: fcmp
 name:            fcmp
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr32 }
-# CHECK-NEXT:  - { id: 1, class: gpr32 }
-# CHECK-NEXT:  - { id: 2, class: fpr64 }
-# CHECK-NEXT:  - { id: 3, class: gpr32 }
-# CHECK-NEXT:  - { id: 4, class: gpr32 }
-# CHECK-NEXT:  - { id: 5, class: gpr32 }
+# CHECK-NEXT:  - { id: 0, class: fpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: fpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 3, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 4, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 5, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: gpr }
   - { id: 2, class: fpr }
   - { id: 3, class: gpr }
 
 # CHECK:  body:
 # CHECK:    FCMPSrr %0, %0, implicit-def %nzcv

 ---
 # CHECK-LABEL: name: phi
 name:            phi
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr32 }
-# CHECK-NEXT:  - { id: 1, class: gpr32 }
-# CHECK-NEXT:  - { id: 2, class: fpr32 }
+# CHECK-NEXT:  - { id: 0, class: fpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: fpr32, preferred-register: '' }
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: gpr }
   - { id: 2, class: fpr }
 
 # CHECK:  body:
 # CHECK:    bb.1:
 # CHECK:      %2 = PHI %0, %bb.0, %2, %bb.1

 ---
 # CHECK-LABEL: name: select
 name:            select
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32 }
-# CHECK-NEXT:  - { id: 1, class: gpr32 }
-# CHECK-NEXT:  - { id: 2, class: gpr32 }
-# CHECK-NEXT:  - { id: 3, class: gpr32 }
-# CHECK-NEXT:  - { id: 4, class: gpr64 }
-# CHECK-NEXT:  - { id: 5, class: gpr64 }
-# CHECK-NEXT:  - { id: 6, class: gpr64 }
-# CHECK-NEXT:  - { id: 7, class: gpr64 }
-# CHECK-NEXT:  - { id: 8, class: gpr64 }
-# CHECK-NEXT:  - { id: 9, class: gpr64 }
+# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 3, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 4, class: gpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 5, class: gpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 6, class: gpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 7, class: gpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 8, class: gpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 9, class: gpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
   - { id: 4, class: gpr }
   - { id: 5, class: gpr }
   - { id: 6, class: gpr }

test/CodeGen/AArch64/GlobalISel/varargs-ios-translator.ll

 ; RUN: llc -mtriple=aarch64-apple-ios -stop-after=instruction-select -global-isel -verify-machineinstrs %s -o - | FileCheck %s
 
 define void @test_varargs_sentinel(i8* %list, i64, i64, i64, i64, i64, i64, i64,
                                    i32, ...) {
 ; CHECK-LABEL: name: test_varargs_sentinel
 ; CHECK: fixedStack:
-; CHECK:   - { id: [[VARARGS_SLOT:[0-9]+]], offset: 8
+; CHECK:   - { id: [[VARARGS_SLOT:[0-9]+]], type: default, offset: 8
 ; CHECK: body:
 ; CHECK:   [[LIST:%[0-9]+]] = COPY %x0
 ; CHECK:   [[VARARGS_AREA:%[0-9]+]] = ADDXri %fixed-stack.[[VARARGS_SLOT]], 0, 0
 ; CHECK:   STRXui [[VARARGS_AREA]], [[LIST]], 0 :: (store 8 into %ir.list, align 0)
   call void @llvm.va_start(i8* %list)
   ret void
 }
 
 declare void @llvm.va_start(i8*)

test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir

 ...
 
 ---
 name : load_constant
 legalized: true
 
 # CHECK-LABEL: name: load_constant
 # CHECK: registers:
-# CHECK: - { id: 0, class: sgpr }
-# CHECK: - { id: 1, class: sgpr }
+# CHECK: - { id: 0, class: sgpr, preferred-register: '' }
+# CHECK: - { id: 1, class: sgpr, preferred-register: '' }
 
 body: |
   bb.0:
     liveins: %sgpr0_sgpr1
     %0:_(p2) = COPY %sgpr0_sgpr1
     %1:_(s32) = G_LOAD %0 :: (load 4 from %ir.ptr0)
 ...
 
 ---
 name: load_global_uniform
 legalized: true
 
 # CHECK-LABEL: name: load_global_uniform
 # CHECK: registers:
-# CHECK: - { id: 0, class: sgpr }
-# CHECK: - { id: 1, class: sgpr }
+# CHECK: - { id: 0, class: sgpr, preferred-register: '' }
+# CHECK: - { id: 1, class: sgpr, preferred-register: '' }
 
 body: |
   bb.0:
     liveins: %sgpr0_sgpr1
     %0:_(p1) = COPY %sgpr0_sgpr1
     %1:_(s32) = G_LOAD %0 :: (load 4 from %ir.ptr1)
 ...
 
 ---
 name: load_global_non_uniform
 legalized: true
 
 # CHECK-LABEL: name: load_global_non_uniform
 # CHECK: registers:
-# CHECK: - { id: 0, class: sgpr }
-# CHECK: - { id: 1, class: vgpr }
-# CHECK: - { id: 2, class: vgpr }
+# CHECK: - { id: 0, class: sgpr, preferred-register: '' }
+# CHECK: - { id: 1, class: vgpr, preferred-register: '' }
+# CHECK: - { id: 2, class: vgpr, preferred-register: '' }
 
 
 body: |
   bb.0:
     liveins: %sgpr0_sgpr1
     %0:_(p1) = COPY %sgpr0_sgpr1
     %1:_(s32) = G_LOAD %0 :: (load 4 from %ir.tmp1)
 ...

test/CodeGen/AMDGPU/limit-coalesce.mir

 # RUN: llc -march=amdgcn -run-pass simple-register-coalescing -o - %s | FileCheck %s
 
 # Check that coalescer does not create wider register tuple than in source
 
-# CHECK:  - { id: 2, class: vreg_64 }
-# CHECK:  - { id: 3, class: vreg_64 }
-# CHECK:  - { id: 4, class: vreg_64 }
-# CHECK:  - { id: 5, class: vreg_96 }
-# CHECK:  - { id: 6, class: vreg_96 }
-# CHECK:  - { id: 7, class: vreg_128 }
-# CHECK:  - { id: 8, class: vreg_128 }
+# CHECK:  - { id: 2, class: vreg_64, preferred-register: '' }
+# CHECK:  - { id: 3, class: vreg_64, preferred-register: '' }
+# CHECK:  - { id: 4, class: vreg_64, preferred-register: '' }
+# CHECK:  - { id: 5, class: vreg_96, preferred-register: '' }
+# CHECK:  - { id: 6, class: vreg_96, preferred-register: '' }
+# CHECK:  - { id: 7, class: vreg_128, preferred-register: '' }
+# CHECK:  - { id: 8, class: vreg_128, preferred-register: '' }
 # No more registers shall be defined
 # CHECK-NEXT: liveins:
 # CHECK:    FLAT_STORE_DWORDX2 %vgpr0_vgpr1, %4,
 # CHECK:    FLAT_STORE_DWORDX3 %vgpr0_vgpr1, %6,
 
 ---
 name:            main
 alignment:       0

test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir

 # CHECK-DAG: id: 0, class: gpr
 # CHECK-DAG: id: 1, class: gpr
 # CHECK-DAG: id: 2, class: gpr
 # CHECK-DAG: id: 3, class: gpr
 fixedStack:
   - { id: 0, offset: 0, size: 1, alignment: 4, isImmutable: true, isAliased: false }
   - { id: 1, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false }
   - { id: 2, offset: 8, size: 4, alignment: 4, isImmutable: true, isAliased: false }
-# CHECK-DAG: id: [[FI1:[0-9]+]], offset: 0
-# CHECK-DAG: id: [[FI32:[0-9]+]], offset: 8
+# CHECK-DAG: id: [[FI1:[0-9]+]], type: default, offset: 0, size: 1
+# CHECK-DAG: id: [[FI32:[0-9]+]], type: default, offset: 8
 body:             |
   bb.0:
     liveins: %r0, %r1, %r2, %r3
 
     %0(p0) = G_FRAME_INDEX %fixed-stack.2
     ; CHECK: [[FI32VREG:%[0-9]+]] = ADDri %fixed-stack.[[FI32]], 0, 14, _, _
 
     %1(s32) = G_LOAD %0(p0) :: (load 4)

test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll

 
 declare arm_aapcscc void @large_int_arrays_target([20 x i32])
 
 define arm_aapcscc void @test_large_int_arrays([20 x i32] %arr) {
 ; CHECK-LABEL: name: test_large_int_arrays
 ; CHECK: fixedStack:
 ; The parameters live in separate stack locations, one for each element that
 ; doesn't fit in the registers.
-; CHECK-DAG: id: [[FIRST_STACK_ID:[0-9]+]], offset: 0, size: 4
-; CHECK-DAG: id: [[LAST_STACK_ID:[-0]+]], offset: 60, size: 4
+; CHECK-DAG: id: [[FIRST_STACK_ID:[0-9]+]], type: default, offset: 0, size: 4,
+; CHECK-DAG: id: [[LAST_STACK_ID:[-0]+]], type: default, offset: 60, size: 4
 ; CHECK: liveins: %r0, %r1, %r2, %r3
 ; CHECK-DAG: [[R0:%[0-9]+]](s32) = COPY %r0
 ; CHECK-DAG: [[R1:%[0-9]+]](s32) = COPY %r1
 ; CHECK-DAG: [[R2:%[0-9]+]](s32) = COPY %r2
 ; CHECK-DAG: [[R3:%[0-9]+]](s32) = COPY %r3
 ; CHECK: [[FIRST_STACK_ELEMENT_FI:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[FIRST_STACK_ID]]
 ; CHECK: [[FIRST_STACK_ELEMENT:%[0-9]+]](s32) = G_LOAD [[FIRST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[FIRST_STACK_ID]]
 ; CHECK: [[LAST_STACK_ELEMENT_FI:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[LAST_STACK_ID]]
entry:
   ret void
 }
 
 declare arm_aapcscc [2 x float] @fp_arrays_aapcs_target([3 x double])
 
 define arm_aapcscc [2 x float] @test_fp_arrays_aapcs([3 x double] %arr) {
 ; CHECK-LABEL: name: test_fp_arrays_aapcs
 ; CHECK: fixedStack:
-; CHECK: id: [[ARR2_ID:[0-9]+]], offset: 0, size: 8
+; CHECK: id: [[ARR2_ID:[0-9]+]], type: default, offset: 0, size: 8,
 ; CHECK: liveins: %r0, %r1, %r2, %r3
 ; CHECK: [[ARR0_0:%[0-9]+]](s32) = COPY %r0
 ; CHECK: [[ARR0_1:%[0-9]+]](s32) = COPY %r1
 ; LITTLE: [[ARR0:%[0-9]+]](s64) = G_SEQUENCE [[ARR0_0]](s32), 0, [[ARR0_1]](s32), 32
 ; BIG: [[ARR0:%[0-9]+]](s64) = G_SEQUENCE [[ARR0_1]](s32), 0, [[ARR0_0]](s32), 32
 ; CHECK: [[ARR1_0:%[0-9]+]](s32) = COPY %r2
 ; CHECK: [[ARR1_1:%[0-9]+]](s32) = COPY %r3
 ; LITTLE: [[ARR1:%[0-9]+]](s64) = G_SEQUENCE [[ARR1_0]](s32), 0, [[ARR1_1]](s32), 32
entry:
   ret [2 x float] %r
 }
 
 declare arm_aapcs_vfpcc [4 x float] @fp_arrays_aapcs_vfp_target([3 x double], [3 x float], [4 x double])
 
 define arm_aapcs_vfpcc [4 x float] @test_fp_arrays_aapcs_vfp([3 x double] %x, [3 x float] %y, [4 x double] %z) {
 ; CHECK-LABEL: name: test_fp_arrays_aapcs_vfp
 ; CHECK: fixedStack:
-; CHECK-DAG: id: [[Z0_ID:[0-9]+]], offset: 0, size: 8
-; CHECK-DAG: id: [[Z1_ID:[0-9]+]], offset: 8, size: 8
-; CHECK-DAG: id: [[Z2_ID:[0-9]+]], offset: 16, size: 8
-; CHECK-DAG: id: [[Z3_ID:[0-9]+]], offset: 24, size: 8
+; CHECK-DAG: id: [[Z0_ID:[0-9]+]], type: default, offset: 0, size: 8,
+; CHECK-DAG: id: [[Z1_ID:[0-9]+]], type: default, offset: 8, size: 8,
+; CHECK-DAG: id: [[Z2_ID:[0-9]+]], type: default, offset: 16, size: 8,
+; CHECK-DAG: id: [[Z3_ID:[0-9]+]], type: default, offset: 24, size: 8,
 ; CHECK: liveins: %d0, %d1, %d2, %s6, %s7, %s8
 ; CHECK: [[X0:%[0-9]+]](s64) = COPY %d0
 ; CHECK: [[X1:%[0-9]+]](s64) = COPY %d1
 ; CHECK: [[X2:%[0-9]+]](s64) = COPY %d2
 ; CHECK: [[Y0:%[0-9]+]](s32) = COPY %s6
 ; CHECK: [[Y1:%[0-9]+]](s32) = COPY %s7
 ; CHECK: [[Y2:%[0-9]+]](s32) = COPY %s8
 ; CHECK: [[Z0_FI:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[Z0_ID]]

 
 declare arm_aapcscc [2 x i32*] @tough_arrays_target([6 x [4 x i32]] %arr)
 
 define arm_aapcscc [2 x i32*] @test_tough_arrays([6 x [4 x i32]] %arr) {
 ; CHECK-LABEL: name: test_tough_arrays
 ; CHECK: fixedStack:
 ; The parameters live in separate stack locations, one for each element that
 ; doesn't fit in the registers.
-; CHECK-DAG: id: [[FIRST_STACK_ID:[0-9]+]], offset: 0, size: 4
-; CHECK-DAG: id: [[LAST_STACK_ID:[-0]+]], offset: 76, size: 4
+; CHECK-DAG: id: [[FIRST_STACK_ID:[0-9]+]], type: default, offset: 0, size: 4,
+; CHECK-DAG: id: [[LAST_STACK_ID:[-0]+]], type: default, offset: 76, size: 4
 ; CHECK: liveins: %r0, %r1, %r2, %r3
 ; CHECK-DAG: [[R0:%[0-9]+]](s32) = COPY %r0
 ; CHECK-DAG: [[R1:%[0-9]+]](s32) = COPY %r1
 ; CHECK-DAG: [[R2:%[0-9]+]](s32) = COPY %r2
 ; CHECK-DAG: [[R3:%[0-9]+]](s32) = COPY %r3
 ; CHECK: [[FIRST_STACK_ELEMENT_FI:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[FIRST_STACK_ID]]
 ; CHECK: [[FIRST_STACK_ELEMENT:%[0-9]+]](s32) = G_LOAD [[FIRST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[FIRST_STACK_ID]]
 ; CHECK: [[LAST_STACK_ELEMENT_FI:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[LAST_STACK_ID]]
entry:
   ret [2 x i32*] %r
 }
 
 declare arm_aapcscc {i32, i32} @structs_target({i32, i32}, {i32*, float, i32, double})
 
 define arm_aapcscc {i32, i32} @test_structs({i32, i32} %x, {i32*, float, i32, double} %y) {
 ; CHECK-LABEL: test_structs
 ; CHECK: fixedStack:
-; CHECK-DAG: id: [[Y2_ID:[0-9]+]], offset: 0, size: 4
-; CHECK-DAG: id: [[Y3_ID:[0-9]+]], offset: 8, size: 8
+; CHECK-DAG: id: [[Y2_ID:[0-9]+]], type: default, offset: 0, size: 4,
+; CHECK-DAG: id: [[Y3_ID:[0-9]+]], type: default, offset: 8, size: 8,
 ; CHECK: liveins: %r0, %r1, %r2, %r3
 ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
 ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
 ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
 ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
 ; CHECK: [[Y2_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[Y2_ID]]
 ; CHECK: [[Y2:%[0-9]+]](s32) = G_LOAD [[Y2_ADDR]](p0){{.*}}load 4
 ; CHECK: [[Y3_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[Y3_ID]]

test/CodeGen/ARM/GlobalISel/arm-legalizer.mir

registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
   - { id: 3, class: _ }
 fixedStack:
   - { id: 0, offset: 0, size: 4, alignment: 4, isImmutable: true, isAliased: false }
   - { id: 1, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false }
   - { id: 2, offset: 8, size: 4, alignment: 4, isImmutable: true, isAliased: false }
-  # CHECK: id: [[FRAME_INDEX:[0-9]+]], offset: 8
+  # CHECK: id: [[FRAME_INDEX:[0-9]+]], type: default, offset: 8
 body:             |
   bb.0:
     liveins: %r0, %r1, %r2, %r3
 
     ; This is legal, so we should find it unchanged in the output
     ; CHECK: [[FIVREG:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[FRAME_INDEX]]
     ; CHECK: {{%[0-9]+}}(s32) = G_LOAD [[FIVREG]](p0) :: (load 4)
     %0(p0) = G_FRAME_INDEX %fixed-stack.2

test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir

 ...
 ---
 name:            test_add_s32
 # CHECK-LABEL: name: test_add_s32
 legalized:       true
 regBankSelected: false
 selected:        false
 # CHECK: registers:
-# CHECK: - { id: 0, class: gprb }
-# CHECK: - { id: 1, class: gprb }
-# CHECK: - { id: 2, class: gprb }
+# CHECK: - { id: 0, class: gprb, preferred-register: '' }
+# CHECK: - { id: 1, class: gprb, preferred-register: '' }
+# CHECK: - { id: 2, class: gprb, preferred-register: '' }
 
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body:             |
   bb.0:
     liveins: %r0, %r1
 
     %0(s32) = COPY %r0
     %1(s32) = COPY %r1
     %2(s32) = G_ADD %0, %1
     %r0 = COPY %2(s32)
     BX_RET 14, _, implicit %r0
 
 ...
 ---
 name:            test_add_s16
 # CHECK-LABEL: name: test_add_s16
 legalized:       true
 regBankSelected: false
 selected:        false
 # CHECK: registers:
-# CHECK: - { id: 0, class: gprb }
-# CHECK: - { id: 1, class: gprb }
-# CHECK: - { id: 2, class: gprb }
-# CHECK: - { id: 3, class: gprb }
-# CHECK: - { id: 4, class: gprb }
-# CHECK: - { id: 5, class: gprb }
+# CHECK: - { id: 0, class: gprb, preferred-register: '' }
+# CHECK: - { id: 1, class: gprb, preferred-register: '' }
+# CHECK: - { id: 2, class: gprb, preferred-register: '' }
+# CHECK: - { id: 3, class: gprb, preferred-register: '' }
+# CHECK: - { id: 4, class: gprb, preferred-register: '' }
+# CHECK: - { id: 5, class: gprb, preferred-register: '' }
 
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
   - { id: 3, class: _ }
   - { id: 4, class: _ }
   - { id: 5, class: _ }

 ...
 ---
 name:            test_add_s8
 # CHECK-LABEL: name: test_add_s8
 legalized:       true
 regBankSelected: false
 selected:        false
 # CHECK: registers:
-# CHECK: - { id: 0, class: gprb }
-# CHECK: - { id: 1, class: gprb }
-# CHECK: - { id: 2, class: gprb }
-# CHECK: - { id: 3, class: gprb }
-# CHECK: - { id: 4, class: gprb }
-# CHECK: - { id: 5, class: gprb }
+# CHECK: - { id: 0, class: gprb, preferred-register: '' }
+# CHECK: - { id: 1, class: gprb, preferred-register: '' }
+# CHECK: - { id: 2, class: gprb, preferred-register: '' }
+# CHECK: - { id: 3, class: gprb, preferred-register: '' }
+# CHECK: - { id: 4, class: gprb, preferred-register: '' }
+# CHECK: - { id: 5, class: gprb, preferred-register: '' }
 
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
   - { id: 3, class: _ }
   - { id: 4, class: _ }
   - { id: 5, class: _ }

 ...
 ---
 name:            test_add_s1
 # CHECK-LABEL: name: test_add_s1
 legalized:       true
 regBankSelected: false
 selected:        false
 # CHECK: registers:
-# CHECK: - { id: 0, class: gprb }
-# CHECK: - { id: 1, class: gprb }
-# CHECK: - { id: 2, class: gprb }
-# CHECK: - { id: 3, class: gprb }
-# CHECK: - { id: 4, class: gprb }
-# CHECK: - { id: 5, class: gprb }
+# CHECK: - { id: 0, class: gprb, preferred-register: '' }
+# CHECK: - { id: 1, class: gprb, preferred-register: '' }
+# CHECK: - { id: 2, class: gprb, preferred-register: '' }
+# CHECK: - { id: 3, class: gprb, preferred-register: '' }
+# CHECK: - { id: 4, class: gprb, preferred-register: '' }
+# CHECK: - { id: 5, class: gprb, preferred-register: '' }
 
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
   - { id: 3, class: _ }
   - { id: 4, class: _ }
   - { id: 5, class: _ }

 ...
 ---
 name:            test_sub_s32
 # CHECK-LABEL: name: test_sub_s32
 legalized:       true
 regBankSelected: false
 selected:        false
 # CHECK: registers:
-# CHECK: - { id: 0, class: gprb }
-# CHECK: - { id: 1, class: gprb }
-# CHECK: - { id: 2, class: gprb }
+# CHECK: - { id: 0, class: gprb, preferred-register: '' }
+# CHECK: - { id: 1, class: gprb, preferred-register: '' }
+# CHECK: - { id: 2, class: gprb, preferred-register: '' }
 
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body:             |
   bb.0:
     liveins: %r0, %r1
 
     %0(s32) = COPY %r0
     %1(s32) = COPY %r1
     %2(s32) = G_SUB %0, %1
     %r0 = COPY %2(s32)
     BX_RET 14, _, implicit %r0
 
 ...
 ---
 name:            test_sub_s16
 # CHECK-LABEL: name: test_sub_s16
 legalized:       true
 regBankSelected: false
 selected:        false
 # CHECK: registers:
-# CHECK: - { id: 0, class: gprb }
-# CHECK: - { id: 1, class: gprb }
-# CHECK: - { id: 2, class: gprb }
-# CHECK: - { id: 3, class: gprb }
-# CHECK: - { id: 4, class: gprb }
-# CHECK: - { id: 5, class: gprb }
+# CHECK: - { id: 0, class: gprb, preferred-register: '' }
+# CHECK: - { id: 1, class: gprb, preferred-register: '' }
+# CHECK: - { id: 2, class: gprb, preferred-register: '' }
+# CHECK: - { id: 3, class: gprb, preferred-register: '' }
+# CHECK: - { id: 4, class: gprb, preferred-register: '' }
+# CHECK: - { id: 5, class: gprb, preferred-register: '' }
 
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
   - { id: 3, class: _ }
   - { id: 4, class: _ }
   - { id: 5, class: _ }

 ...
 ---
 name:            test_sub_s8
 # CHECK-LABEL: name: test_sub_s8
 legalized:       true
 regBankSelected: false
 selected:        false
 # CHECK: registers:
-# CHECK: - { id: 0, class: gprb }
-# CHECK: - { id: 1, class: gprb }
-# CHECK: - { id: 2, class: gprb }
-# CHECK: - { id: 3, class: gprb }
-# CHECK: - { id: 4, class: gprb }
-# CHECK: - { id: 5, class: gprb }
+# CHECK: - { id: 0, class: gprb, preferred-register: '' }
+# CHECK: - { id: 1, class: gprb, preferred-register: '' }
+# CHECK: - { id: 2, class: gprb, preferred-register: '' }
+# CHECK: - { id: 3, class: gprb, preferred-register: '' }
+# CHECK: - { id: 4, class: gprb, preferred-register: '' }
+# CHECK: - { id: 5, class: gprb, preferred-register: '' }
 
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
   - { id: 3, class: _ }
   - { id: 4, class: _ }
   - { id: 5, class: _ }

 ...
 ---
 name:            test_mul_s32
 # CHECK-LABEL: name: test_mul_s32
 legalized:       true
 regBankSelected: false
 selected:        false
 # CHECK: registers:
-# CHECK: - { id: 0, class: gprb }
-# CHECK: - { id: 1, class: gprb }
-# CHECK: - { id: 2, class: gprb }
+# CHECK: - { id: 0, class: gprb, preferred-register: '' }
+# CHECK: - { id: 1, class: gprb, preferred-register: '' }
+# CHECK: - { id: 2, class: gprb, preferred-register: '' }
 
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body:             |
   bb.0:
     liveins: %r0, %r1
 
     %0(s32) = COPY %r0
     %1(s32) = COPY %r1
     %2(s32) = G_MUL %0, %1
     %r0 = COPY %2(s32)
     BX_RET 14, _, implicit %r0
 
 ...
 ---
 name:            test_mul_s16
 # CHECK-LABEL: name: test_mul_s16
 legalized:       true
 regBankSelected: false
 selected:        false
 # CHECK: registers:
-# CHECK: - { id: 0, class: gprb }
-# CHECK: - { id: 1, class: gprb }
-# CHECK: - { id: 2, class: gprb }
-# CHECK: - { id: 3, class: gprb }
-# CHECK: - { id: 4, class: gprb }
-# CHECK: - { id: 5, class: gprb }
+# CHECK: - { id: 0, class: gprb, preferred-register: '' }
+# CHECK: - { id: 1, class: gprb, preferred-register: '' }
+# CHECK: - { id: 2, class: gprb, preferred-register: '' }
+# CHECK: - { id: 3, class: gprb, preferred-register: '' }
+# CHECK: - { id: 4, class: gprb, preferred-register: '' }
+# CHECK: - { id: 5, class: gprb, preferred-register: '' }
 
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
   - { id: 3, class: _ }
   - { id: 4, class: _ }
   - { id: 5, class: _ }

 ...
 ---
 name:            test_mul_s8
 # CHECK-LABEL: name: test_mul_s8
 legalized:       true
 regBankSelected: false
 selected:        false
 # CHECK: registers:
-# CHECK: - { id: 0, class: gprb }
-# CHECK: - { id: 1, class: gprb }
-# CHECK: - { id: 2, class: gprb }
-# CHECK: - { id: 3, class: gprb }
-# CHECK: - { id: 4, class: gprb }
-# CHECK: - { id: 5, class: gprb }
+# CHECK: - { id: 0, class: gprb, preferred-register: '' }
+# CHECK: - { id: 1, class: gprb, preferred-register: '' }
+# CHECK: - { id: 2, class: gprb, preferred-register: '' }
+# CHECK: - { id: 3, class: gprb, preferred-register: '' }
+# CHECK: - { id: 4, class: gprb, preferred-register: '' }
+# CHECK: - { id: 5, class: gprb, preferred-register: '' }
 
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
   - { id: 3, class: _ }
   - { id: 4, class: _ }
   - { id: 5, class: _ }

 ...
 ---
 name:            test_sdiv_s32
 # CHECK-LABEL: name: test_sdiv_s32
 legalized:       true
 regBankSelected: false
 selected:        false
 # CHECK: registers:
-# CHECK: - { id: 0, class: gprb }
-# CHECK: - { id: 1, class: gprb }
-# CHECK: - { id: 2, class: gprb }
+# CHECK: - { id: 0, class: gprb, preferred-register: '' }
+# CHECK: - { id: 1, class: gprb, preferred-register: '' }
+# CHECK: - { id: 2, class: gprb, preferred-register: '' }
 
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body:             |
   bb.0:
     liveins: %r0, %r1
 
     %0(s32) = COPY %r0
     %1(s32) = COPY %r1
     %2(s32) = G_SDIV %0, %1
     %r0 = COPY %2(s32)
     BX_RET 14, _, implicit %r0
 
 ...
 ---
 name:            test_udiv_s32
 # CHECK-LABEL: name: test_udiv_s32
 legalized:       true
 regBankSelected: false
 selected:        false
 # CHECK: registers:
-# CHECK: - { id: 0, class: gprb }
-# CHECK: - { id: 1, class: gprb }
-# CHECK: - { id: 2, class: gprb }
+# CHECK: - { id: 0, class: gprb, preferred-register: '' }
+# CHECK: - { id: 1, class: gprb, preferred-register: '' }
+# CHECK: - { id: 2, class: gprb, preferred-register: '' }
 
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body:             |
   bb.0:
     liveins: %r0, %r1
 
     %0(s32) = COPY %r0
     %1(s32) = COPY %r1
     %2(s32) = G_UDIV %0, %1
     %r0 = COPY %2(s32)
     BX_RET 14, _, implicit %r0
 
 ...
 ---
 name:            test_loads
 # CHECK-LABEL: name: test_loads
 legalized:       true
 regBankSelected: false
 selected:        false
 # CHECK: registers:
-# CHECK: - { id: 0, class: gprb }
-# CHECK: - { id: 1, class: gprb }
-# CHECK: - { id: 2, class: gprb }
-# CHECK: - { id: 3, class: gprb }
-# CHECK: - { id: 4, class: gprb }
-# CHECK: - { id: 5, class: gprb }
-# CHECK: - { id: 6, class: fprb }
+# CHECK: - { id: 0, class: gprb, preferred-register: '' }
+# CHECK: - { id: 1, class: gprb, preferred-register: '' }
+# CHECK: - { id: 2, class: gprb, preferred-register: '' }
+# CHECK: - { id: 3, class: gprb, preferred-register: '' }
+# CHECK: - { id: 4, class: gprb, preferred-register: '' }
+# CHECK: - { id: 5, class: gprb, preferred-register: '' }
+# CHECK: - { id: 6, class: fprb, preferred-register: '' }
 
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
   - { id: 3, class: _ }
   - { id: 4, class: _ }
   - { id: 5, class: _ }

 ...
 ---
 name:            test_stores
 # CHECK-LABEL: name: test_stores
 legalized:       true
 regBankSelected: false
 selected:        false
 # CHECK: registers:
-# CHECK: - { id: 0, class: gprb }
-# CHECK: - { id: 1, class: gprb }
-# CHECK: - { id: 2, class: gprb }
-# CHECK: - { id: 3, class: gprb }
-# CHECK: - { id: 4, class: gprb }
-# CHECK: - { id: 5, class: gprb }
-# CHECK: - { id: 6, class: fprb }
+# CHECK: - { id: 0, class: gprb, preferred-register: '' }
+# CHECK: - { id: 1, class: gprb, preferred-register: '' }
+# CHECK: - { id: 2, class: gprb, preferred-register: '' }
+# CHECK: - { id: 3, class: gprb, preferred-register: '' }
+# CHECK: - { id: 4, class: gprb, preferred-register: '' }
+# CHECK: - { id: 5, class: gprb, preferred-register: '' }
+# CHECK: - { id: 6, class: fprb, preferred-register: '' }
 
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
   - { id: 3, class: _ }
   - { id: 4, class: _ }
   - { id: 5, class: _ }

 ...
 ---
 name:            test_stack
 # CHECK-LABEL: name: test_stack
 legalized:       true
 regBankSelected: false
 selected:        false
 # CHECK: registers:
-# CHECK: - { id: 0, class: gprb }
-# CHECK: - { id: 1, class: gprb }
-# CHECK: - { id: 2, class: gprb }
-# CHECK: - { id: 3, class: gprb }
-# CHECK: - { id: 4, class: gprb }
+# CHECK: - { id: 0, class: gprb, preferred-register: '' }
+# CHECK: - { id: 1, class: gprb, preferred-register: '' }
+# CHECK: - { id: 2, class: gprb, preferred-register: '' }
+# CHECK: - { id: 3, class: gprb, preferred-register: '' }
+# CHECK: - { id: 4, class: gprb, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
   - { id: 3, class: _ }
   - { id: 4, class: _ }
 fixedStack:
   - { id: 0, offset: 0, size: 4, alignment: 4, isImmutable: true, isAliased: false }

 ...
 ---
 name:            test_gep
 # CHECK-LABEL: name: test_gep
 legalized:       true
 regBankSelected: false
 selected:        false
 # CHECK: registers:
-# CHECK: - { id: 0, class: gprb }
-# CHECK: - { id: 1, class: gprb }
-# CHECK: - { id: 2, class: gprb }
+# CHECK: - { id: 0, class: gprb, preferred-register: '' }
+# CHECK: - { id: 1, class: gprb, preferred-register: '' }
+# CHECK: - { id: 2, class: gprb, preferred-register: '' }
 
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body:             |
   bb.0:
     liveins: %r0, %r1
 
     %0(p0) = COPY %r0
     %1(s32) = COPY %r1
     %2(p0) = G_GEP %0, %1(s32)
     %r0 = COPY %2(p0)
     BX_RET 14, _, implicit %r0
 ...
 ---
 name:            test_constants
 # CHECK-LABEL: name: test_constants
 legalized:       true
 regBankSelected: false
 selected:        false
 # CHECK: registers:
-# CHECK: - { id: 0, class: gprb }
+# CHECK: - { id: 0, class: gprb, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
 body:             |
   bb.0:
     %0(s32) = G_CONSTANT 42
     %r0 = COPY %0(s32)
     BX_RET 14, _, implicit %r0
 ...
 ---
 name:            test_anyext_s8_32
 # CHECK-LABEL: name: test_anyext_s8_32
 legalized:       true
 regBankSelected: false
 selected:        false
 # CHECK: registers:
-# CHECK: - { id: 0, class: gprb }
-# CHECK: - { id: 1, class: gprb }
+# CHECK: - { id: 0, class: gprb, preferred-register: '' }
+# CHECK: - { id: 1, class: gprb, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body:             |
   bb.0:
     liveins: %r0
 
     %0(s8) = COPY %r0
     %1(s32) = G_ANYEXT %0(s8)
     %r0 = COPY %1(s32)
     BX_RET 14, _, implicit %r0
 ...
 ---
 name:            test_anyext_s16_32
 # CHECK-LABEL: name: test_anyext_s16_32
 legalized:       true
 regBankSelected: false
 selected:        false
 # CHECK: registers:
-# CHECK: - { id: 0, class: gprb }
-# CHECK: - { id: 1, class: gprb }
+# CHECK: - { id: 0, class: gprb, preferred-register: '' }
+# CHECK: - { id: 1, class: gprb, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body:             |
   bb.0:
     liveins: %r0
 
     %0(s16) = COPY %r0
     %1(s32) = G_ANYEXT %0(s16)
     %r0 = COPY %1(s32)
     BX_RET 14, _, implicit %r0
 ...
 ---
 name:            test_trunc_s32_16
 # CHECK-LABEL: name: test_trunc_s32_16
 legalized:       true
 regBankSelected: false
 selected:        false
 # CHECK: registers:
-# CHECK: - { id: 0, class: gprb }
-# CHECK: - { id: 1, class: gprb }
+# CHECK: - { id: 0, class: gprb, preferred-register: '' }
+# CHECK: - { id: 1, class: gprb, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body:             |
   bb.0:
     liveins: %r0
 
     %0(s32) = COPY %r0
     %1(s16) = G_TRUNC %0(s32)
     %r0 = COPY %1(s16)
     BX_RET 14, _, implicit %r0
 ...
 ---
 name:            test_fadd_s32
 # CHECK-LABEL: name: test_fadd_s32
 legalized:       true
 regBankSelected: false
 selected:        false
 # CHECK: registers:
-# CHECK: - { id: 0, class: fprb }
-# CHECK: - { id: 1, class: fprb }
-# CHECK: - { id: 2, class: fprb }
+# CHECK: - { id: 0, class: fprb, preferred-register: '' }
+# CHECK: - { id: 1, class: fprb, preferred-register: '' }
+# CHECK: - { id: 2, class: fprb, preferred-register: '' }
 
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body:             |
   bb.0:
     liveins: %s0, %s1
 
     %0(s32) = COPY %s0
     %1(s32) = COPY %s1
     %2(s32) = G_FADD %0, %1
     %s0 = COPY %2(s32)
     BX_RET 14, _, implicit %s0
 
 ...
 ---
 name:            test_fadd_s64
 # CHECK-LABEL: name: test_fadd_s64
 legalized:       true
 regBankSelected: false
 selected:        false
 # CHECK: registers:
-# CHECK: - { id: 0, class: fprb }
-# CHECK: - { id: 1, class: fprb }
-# CHECK: - { id: 2, class: fprb }
+# CHECK: - { id: 0, class: fprb, preferred-register: '' }
+# CHECK: - { id: 1, class: fprb, preferred-register: '' }
+# CHECK: - { id: 2, class: fprb, preferred-register: '' }
 
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body:             |
   bb.0:
     liveins: %d0, %d1
 
     %0(s64) = COPY %d0
     %1(s64) = COPY %d1
     %2(s64) = G_FADD %0, %1
     %d0 = COPY %2(s64)
     BX_RET 14, _, implicit %d0
 
 ...
 ---
 name:            test_soft_fp_s64
 # CHECK-LABEL: name: test_soft_fp_s64
 legalized:       true
 regBankSelected: false
 selected:        false
 # CHECK: registers:
-# CHECK: - { id: 0, class: gprb }
-# CHECK: - { id: 1, class: gprb }
-# CHECK: - { id: 2, class: fprb }
-# CHECK: - { id: 3, class: gprb }
-# CHECK: - { id: 4, class: gprb }
+# CHECK: - { id: 0, class: gprb, preferred-register: '' }
+# CHECK: - { id: 1, class: gprb, preferred-register: '' }
+# CHECK: - { id: 2, class: fprb, preferred-register: '' }
+# CHECK: - { id: 3, class: gprb, preferred-register: '' }
+# CHECK: - { id: 4, class: gprb, preferred-register: '' }
 
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
   - { id: 3, class: _ }
   - { id: 4, class: _ }
 body:             |

test/CodeGen/ARM/invalidated-save-point.ll

 ; RUN: llc -mtriple thumbv7 -stop-after=if-converter < %s 2>&1 | FileCheck %s
 
 ; Make sure the save point and restore point are dropped from MFI at
 ; this point. Notably, if it isn't is will be invalid and reference a
 ; deleted block (%bb.-1.if.end)
 
-; CHECK-NOT: savePoint:
-; CHECK-NOT: restorePoint:
+; CHECK: savePoint: ''
+; CHECK: restorePoint: ''
 
 target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
 target triple = "thumbv7"
 
 define i32 @f(i32 %n) {
 entry:
   %cmp = icmp ult i32 %n, 4
   br i1 %cmp, label %return, label %if.end

test/CodeGen/MIR/AArch64/register-operand-bank.mir

 # RUN: llc -o - %s -mtriple=aarch64-- -run-pass=none | FileCheck %s
 # REQUIRES: global-isel
 # Test various aspects of register bank specification on machine operands.
 --- |
   define void @func() { ret void }
 ...
 ---
 # CHECK-LABEL: name: func
 # CHECK: registers:
-# CHECK:   - { id: 0, class: gpr }
-# CHECK:   - { id: 1, class: fpr }
+# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
+# CHECK:   - { id: 1, class: fpr, preferred-register: '' }
 name: func
 body: |
   bb.0:
     %0 : gpr(s64) = COPY %x9
     %x9 = COPY %0
 
     %3 : fpr(s64) = COPY %d0
     %d1 = COPY %3 : fpr
 ...

test/CodeGen/MIR/AArch64/stack-object-local-offset.mir

registers:
   - { id: 0, class: gpr64common }
   - { id: 1, class: gpr64 }
   - { id: 2, class: gpr64common }
   - { id: 3, class: gpr64common }
 frameInfo:
   maxAlignment:    8
 # CHECK-LABEL: stack_local
 # CHECK: stack:
-# CHECK-NEXT: { id: 0, name: local_var, offset: 0, size: 8, alignment: 8, local-offset: -8 }
+# CHECK-NEXT: { id: 0, name: local_var, type: default, offset: 0, size: 8, alignment: 8,
+# CHECK-NEXT: callee-saved-register: '', local-offset: -8, di-variable: '', di-expression: '',
+# CHECK-NEXT: di-location: '' }
 stack:
   - { id: 0,name: local_var,offset: 0,size: 8,alignment: 8, local-offset: -8 }
 body: |
   bb.0.entry:
     %0 = ADRP @var
     %1 = LDRXui killed %0, @var :: (load 8 from @var)
     STRXui killed %1, %stack.0.local_var, 0 :: (store 8 into %ir.local_var)
     %2 = ADRP @local_addr
     %3 = ADDXri %stack.0.local_var, 0, 0
     STRXui killed %3, killed %2, @local_addr :: (store 8 into @local_addr)
     RET_ReallyLR
 ...

test/CodeGen/MIR/Generic/frame-info.mir

 
 # CHECK: frameInfo:
 # CHECK-NEXT: isFrameAddressTaken: false
 # CHECK-NEXT: isReturnAddressTaken: false
 # CHECK-NEXT: hasStackMap: false
 # CHECK-NEXT: hasPatchPoint: false
 # CHECK-NEXT: stackSize: 0
 # CHECK-NEXT: offsetAdjustment: 0
 # Note: max alignment can be target specific when printed.
 # CHECK-NEXT: maxAlignment:
 # CHECK-NEXT: adjustsStack: false
 # CHECK-NEXT: hasCalls: false
+# CHECK-NEXT: stackProtector:  ''
+# CHECK-NEXT: maxCallFrameSize:
 # CHECK-NEXT: hasOpaqueSPAdjustment: false
 # CHECK-NEXT: hasVAStart: false
 # CHECK-NEXT: hasMustTailInVarArgFunc: false
+# CHECK-NEXT: savePoint:       ''
+# CHECK-NEXT: restorePoint:    ''
 # CHECK: body
 frameInfo:
   maxAlignment:    4
 body: |
   bb.0.entry:
 ...
 ---
 name:            test2
 tracksRegLiveness: true
 
 # CHECK: test2
 # CHECK: frameInfo:
 # CHECK-NEXT: isFrameAddressTaken: true
 # CHECK-NEXT: isReturnAddressTaken: true
 # CHECK-NEXT: hasStackMap: true
 # CHECK-NEXT: hasPatchPoint: true
 # CHECK-NEXT: stackSize: 4
 # CHECK-NEXT: offsetAdjustment: 4
 # Note: max alignment can be target specific when printed.
 # CHECK-NEXT: maxAlignment:
 # CHECK-NEXT: adjustsStack: true
 # CHECK-NEXT: hasCalls: true
+# CHECK-NEXT: stackProtector:  ''
 # CHECK-NEXT: maxCallFrameSize: 4
 # CHECK-NEXT: hasOpaqueSPAdjustment: true
 # CHECK-NEXT: hasVAStart: true
 # CHECK-NEXT: hasMustTailInVarArgFunc: true
 # CHECK: body
 frameInfo:
   isFrameAddressTaken: true
   isReturnAddressTaken: true

test/CodeGen/MIR/X86/callee-saved-info.mir

 name:            func
 tracksRegLiveness: true
 frameInfo:
   stackSize:       24
   maxAlignment:    4
   adjustsStack:    true
   hasCalls:        true
 # CHECK: fixedStack:
-# CHECK-NEXT: , callee-saved-register: '%rbx' }
+# CHECK: , callee-saved-register: '%rbx' }
 fixedStack:
   - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '%rbx' }
 # CHECK: stack:
 # CHECK-NEXT: - { id: 0
-# CHECK-NEXT: , callee-saved-register: '%edi' }
+# CHECK: callee-saved-register: '%edi'
 stack:
   - { id: 0, name: b, offset: -20, size: 4, alignment: 4 }
   - { id: 1, offset: -24, size: 4, alignment: 4, callee-saved-register: '%edi' }
 body: |
   bb.0.entry:
     successors: %bb.1.check
     liveins: %edi, %rbx
 

test/CodeGen/MIR/X86/fixed-stack-objects.mir

 
 ...
 ---
 name:            test
 frameInfo:
   stackSize:       4
   maxAlignment:    4
 # CHECK: fixedStack:
-# CHECK-NEXT: - { id: 0, offset: 0, size: 4, alignment: 4, isImmutable: true, isAliased: false }
+# CHECK-NEXT: - { id: 0, type: default, offset: 0, size: 4, alignment: 4, isImmutable: true,
 fixedStack:
   - { id: 0, offset: 0, size: 4, alignment: 4, isImmutable: true, isAliased: false }
 stack:
   - { id: 0, offset: -8, size: 4, alignment: 4 }
 body: |
   bb.0.entry:
     %eax = MOV32rm %esp, 1, _, 8, _
     MOV32mr %esp, 1, _, 0, _, %eax
     RETL %eax
 ...

test/CodeGen/MIR/X86/generic-instr-type.mir

define void @test_unsized() {
     ret void
   }
 
 ...
 
 ---
 name:            test_vregs
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: _ }
-# CHECK-NEXT:   - { id: 1, class: _ }
-# CHECK-NEXT:   - { id: 2, class: _ }
-# CHECK-NEXT:   - { id: 3, class: _ }
-# CHECK-NEXT:   - { id: 4, class: _ }
+# CHECK-NEXT:   - { id: 0, class: _, preferred-register: '' }
+# CHECK-NEXT:   - { id: 1, class: _, preferred-register: '' }
+# CHECK-NEXT:   - { id: 2, class: _, preferred-register: '' }
+# CHECK-NEXT:   - { id: 3, class: _, preferred-register: '' }
+# CHECK-NEXT:   - { id: 4, class: _, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
   - { id: 3, class: _ }
   - { id: 4, class: _ }
   - { id: 5, class: _ }
   - { id: 6, class: _ }

test/CodeGen/MIR/X86/register-operand-class.mir

-# RUN: llc -o - %s -march=x86-64 -run-pass none | FileCheck %s
+# RUN: llc  -o - %s -march=x86-64 -run-pass none | FileCheck %s
 # Test various aspects of register class specification on machine operands.
 --- |
   define void @func() { ret void }
 ...
 ---
 # CHECK-LABEL: name: func
 # CHECK: registers:
-# CHECK:   - { id: 0, class: gr32 }
-# CHECK:   - { id: 1, class: gr64 }
-# CHECK:   - { id: 2, class: gr32 }
-# CHECK:   - { id: 3, class: gr16 }
-# CHECK:   - { id: 4, class: _ }
+# CHECK:   - { id: 0, class: gr32, preferred-register: '' }
+# CHECK:   - { id: 1, class: gr64, preferred-register: '' }
+# CHECK:   - { id: 2, class: gr32, preferred-register: '' }
+# CHECK:   - { id: 3, class: gr16, preferred-register: '' }
+# CHECK:   - { id: 4, class: _, preferred-register: '' }
 name: func
 body: |
   bb.0:
     %0 : gr32 = COPY %rax
     %1.sub_32bit : gr64 = COPY %eax
     %rdx = COPY %1
     %2 = COPY %ecx
     %ecx = COPY %2 : gr32
 
     %3 : gr16 = COPY %bx
     %bx = COPY %3 : gr16
 
     %4 : _(s32) = COPY %edx
 ...

test/CodeGen/MIR/X86/simple-register-allocation-hints.mir

body:
     ret i32 %c
   }
 
 ...
 ---
 name:            test
 tracksRegLiveness: true
 # CHECK: registers:
-# CHECK-NEXT:  - { id: 0, class: gr32 }
+# CHECK-NEXT:  - { id: 0, class: gr32, preferred-register: '' }
 # CHECK-NEXT:  - { id: 1, class: gr32, preferred-register: '%esi' }
 # CHECK-NEXT:  - { id: 2, class: gr32, preferred-register: '%edi' }
 registers:
   - { id: 0, class: gr32 }
   - { id: 1, class: gr32, preferred-register: '%esi' }
   - { id: 2, class: gr32, preferred-register: '%edi' }
 body: |
   bb.0.body:
     liveins: %edi, %esi
 
     %1 = COPY %esi
     %2 = COPY %edi
     %2 = IMUL32rr %2, %1, implicit-def dead %eflags
     %eax = COPY %2
     RETQ killed %eax
 ...

test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir

--- |
   attributes #0 = { "no-frame-pointer-elim"="false" }
 
 ...
 ---
 name:            test
 frameInfo:
   maxAlignment:    4
 # CHECK: fixedStack:
-# CHECK-NEXT: - { id: 0, type: spill-slot, offset: 0, size: 4, alignment: 4 }
+# CHECK-NEXT: - { id: 0, type: spill-slot, offset: 0, size: 4, alignment: 4, callee-saved-register: '' }
 fixedStack:
   - { id: 0, type: spill-slot, offset: 0, size: 4, alignment: 4 }
 stack:
   - { id: 0, offset: -12, size: 4, alignment: 4 }
 body: |
   bb.0.entry:
     MOV32mr %rsp, 1, _, -4, _, %edi
     %eax = COPY %edi
     RETQ %eax
 ...

test/CodeGen/MIR/X86/stack-object-debug-info.mir

 ...
 ---
 name:            foo
 tracksRegLiveness: true
 frameInfo:
   maxAlignment:    16
 # CHECK-LABEL: foo
 # CHECK: stack:
-# CHECK:  - { id: 0, name: y.i, offset: 0, size: 256, alignment: 16, di-variable: '!4',
-# CHECK-NEXT: di-expression: '!10', di-location: '!11' }
+# CHECK:  - { id: 0, name: y.i, type: default, offset: 0, size: 256, alignment: 16,
+# CHECK-NEXT: callee-saved-register: '', di-variable: '!4', di-expression: '!10',
+# CHECK-NEXT: di-location: '!11' }
 stack:
   - { id: 0, name: y.i, offset: 0, size: 256, alignment: 16, di-variable: '!4',
       di-expression: '!7', di-location: '!8' }
 body: |
   bb.0.entry:
     successors: %bb.1.for.body
   bb.1.for.body:
     successors: %bb.1.for.body
 
     DBG_VALUE %stack.0.y.i, 0, !4, !7, debug-location !8
     JMP_1 %bb.1.for.body
 ...

test/CodeGen/MIR/X86/stack-objects.mir

--- |
   attributes #0 = { "no-frame-pointer-elim"="false" }
 
 ...
 ---
 name:            test
 frameInfo:
   maxAlignment:    8
 # CHECK: stack:
-# CHECK-NEXT: - { id: 0, name: b, offset: -12, size: 4, alignment: 4 }
-# CHECK-NEXT: - { id: 1, name: x, offset: -24, size: 8, alignment: 8 }
-# CHECK-NEXT: - { id: 2, type: spill-slot, offset: -32, size: 4, alignment: 4 }
+# CHECK-NEXT: - { id: 0, name: b, type: default, offset: -12, size: 4, alignment: 4,
+# CHECK-NEXT: callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
+# CHECK-NEXT: - { id: 1, name: x, type: default, offset: -24, size: 8, alignment: 8,
+# CHECK-NEXT: callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
+# CHECK-NEXT: - { id: 2, name: '', type: spill-slot, offset: -32, size: 4, alignment: 4,
+# CHECK-NEXT: callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
 stack:
   - { id: 0, name: b, offset: -12, size: 4, alignment: 4 }
   - { id: 1, name: x, offset: -24, size: 8, alignment: 8 }
   - { id: 2, type: spill-slot, offset: -32, size: 4, alignment: 4 }
 body: |
   bb.0.entry:
     MOV32mr %rsp, 1, _, -4, _, %edi
     MOV64mi32 %rsp, 1, _, -16, _, 2
     %eax = MOV32rm %rsp, 1, _, -4, _
     RETQ %eax
 ...

test/CodeGen/MIR/X86/variable-sized-stack-objects.mir

 ---
 name:            test
 frameInfo:
   stackSize:       24
   offsetAdjustment: -16
   maxAlignment:    8
   adjustsStack:    true
 # CHECK: stack:
-# CHECK-NEXT: - { id: 0, offset: -20, size: 4, alignment: 4 }
-# CHECK-NEXT: - { id: 1, offset: -32, size: 8, alignment: 8 }
-# CHECK-NEXT: - { id: 2, name: y, type: variable-sized, offset: -32, alignment: 1 }
+# CHECK-NEXT: - { id: 0, name: '', type: default, offset: -20, size: 4, alignment: 4,
+# CHECK-NEXT:  callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
+# CHECK-NEXT: - { id: 1, name: '', type: default, offset: -32, size: 8, alignment: 8,
+# CHECK-NEXT:  callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
+# CHECK-NEXT: - { id: 2, name: y, type: variable-sized, offset: -32, alignment: 1,
 stack:
   - { id: 0, offset: -20, size: 4, alignment: 4 }
   - { id: 1, offset: -32, size: 8, alignment: 8 }
   - { id: 2, name: y, type: variable-sized, offset: -32, alignment: 1 }
 body: |
   bb.0.entry:
     MOV32mr %rsp, 1, _, -4, _, %edi
     MOV64mi32 %rsp, 1, _, -16, _, 2
     %eax = MOV32rm %rsp, 1, _, -4, _
     RETQ %eax
 ...

test/CodeGen/MIR/X86/virtual-registers.mir

exit:
     ret i32 %a
   }
 
 ...
 ---
 name:            bar
 tracksRegLiveness: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gr32 }
-# CHECK-NEXT:   - { id: 1, class: gr32 }
-# CHECK-NEXT:   - { id: 2, class: gr32 }
+# CHECK-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 2, class: gr32, preferred-register: '' }
 registers:
   - { id: 0, class: gr32 }
   - { id: 1, class: gr32 }
   - { id: 2, class: gr32 }
 body: |
   bb.0.entry:
     successors: %bb.2.exit, %bb.1.less
     liveins: %edi
bb.2.exit:
     %eax = COPY %0
     RETQ %eax
 ...
 ---
 name:            foo
 tracksRegLiveness: true
 # CHECK: name: foo
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gr32 }
-# CHECK-NEXT:   - { id: 1, class: gr32 }
-# CHECK-NEXT:   - { id: 2, class: gr32 }
+# CHECK-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 2, class: gr32, preferred-register: '' }
 registers:
   - { id: 2, class: gr32 }
   - { id: 0, class: gr32 }
   - { id: 10, class: gr32 }
 body: |
   bb.0.entry:
     successors: %bb.2.exit, %bb.1.less
     liveins: %edi

test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll

 ; RUN: llc -mtriple=i386-linux-gnu   -mattr=+sse2 -global-isel -stop-after=irtranslator < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X32
 ; RUN: llc -mtriple=x86_64-linux-gnu              -global-isel -stop-after=irtranslator < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64
 
 @a1_8bit = external global i8
 @a7_8bit = external global i8
 @a8_8bit = external global i8
 
 define i8 @test_i8_args_8(i8 %arg1, i8 %arg2, i8 %arg3, i8 %arg4,
                           i8 %arg5, i8 %arg6, i8 %arg7, i8 %arg8) {
 
 ; ALL-LABEL: name:            test_i8_args_8
 
 ; X64: fixedStack:
-; X64:  id: [[STACK8:[0-9]+]], offset: 8, size: 1, alignment: 8, isImmutable: true, isAliased: false
-; X64:  id: [[STACK0:[0-9]+]], offset: 0, size: 1, alignment: 16, isImmutable: true, isAliased: false
+; X64:  id: [[STACK8:[0-9]+]], type: default, offset: 8, size: 1, alignment: 8, isImmutable: true,
+; X64:  id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 1, alignment: 16, isImmutable: true,
 ; X64: liveins: %ecx, %edi, %edx, %esi, %r8d, %r9d
 ; X64:      [[ARG1:%[0-9]+]](s8) = COPY %edi
 ; X64-NEXT: %{{[0-9]+}}(s8) = COPY %esi
 ; X64-NEXT: %{{[0-9]+}}(s8) = COPY %edx
 ; X64-NEXT: %{{[0-9]+}}(s8) = COPY %ecx
 ; X64-NEXT: %{{[0-9]+}}(s8) = COPY %r8d
 ; X64-NEXT: %{{[0-9]+}}(s8) = COPY %r9d
 ; X64-NEXT: [[ARG7_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
 ; X64-NEXT: [[ARG7:%[0-9]+]](s8) = G_LOAD [[ARG7_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK0]], align 0)
 ; X64-NEXT: [[ARG8_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK8]]
 ; X64-NEXT: [[ARG8:%[0-9]+]](s8) = G_LOAD [[ARG8_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK8]], align 0)
 
 ; X32: fixedStack:
-; X32:  id: [[STACK28:[0-9]+]], offset: 28, size: 1, alignment: 4, isImmutable: true, isAliased: false }
-; X32:  id: [[STACK24:[0-9]+]], offset: 24, size: 1, alignment: 8, isImmutable: true, isAliased: false }
-; X32:  id: [[STACK20:[0-9]+]], offset: 20, size: 1, alignment: 4, isImmutable: true, isAliased: false }
-; X32:  id: [[STACK16:[0-9]+]], offset: 16, size: 1, alignment: 16, isImmutable: true, isAliased: false }
-; X32:  id: [[STACK12:[0-9]+]], offset: 12, size: 1, alignment: 4, isImmutable: true, isAliased: false }
-; X32:  id: [[STACK8:[0-9]+]],  offset: 8, size: 1, alignment: 8, isImmutable: true, isAliased: false }
-; X32:  id: [[STACK4:[0-9]+]],  offset: 4, size: 1, alignment: 4, isImmutable: true, isAliased: false }
-; X32:  id: [[STACK0:[0-9]+]],  offset: 0, size: 1, alignment: 16, isImmutable: true, isAliased: false }
+; X32:  id: [[STACK28:[0-9]+]], type: default, offset: 28, size: 1, alignment: 4, isImmutable: true,
+; X32:  id: [[STACK24:[0-9]+]], type: default, offset: 24, size: 1, alignment: 8, isImmutable: true,
+; X32:  id: [[STACK20:[0-9]+]], type: default, offset: 20, size: 1, alignment: 4, isImmutable: true,
+; X32:  id: [[STACK16:[0-9]+]], type: default, offset: 16, size: 1, alignment: 16, isImmutable: true,
+; X32:  id: [[STACK12:[0-9]+]], type: default, offset: 12, size: 1, alignment: 4, isImmutable: true,
+; X32:  id: [[STACK8:[0-9]+]], type: default, offset: 8, size: 1, alignment: 8, isImmutable: true,
+; X32:  id: [[STACK4:[0-9]+]], type: default, offset: 4, size: 1, alignment: 4, isImmutable: true,
+; X32:  id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 1, alignment: 16, isImmutable: true,
 ; X32:       [[ARG1_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
 ; X32-NEXT:  [[ARG1:%[0-9]+]](s8) = G_LOAD [[ARG1_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK0]], align 0)
 ; X32-NEXT:  [[ARG2_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK4]]
 ; X32-NEXT:  [[ARG2:%[0-9]+]](s8) = G_LOAD [[ARG2_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK4]], align 0)
 ; X32-NEXT:  [[ARG3_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK8]]
 ; X32-NEXT:  [[ARG3:%[0-9]+]](s8) = G_LOAD [[ARG3_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK8]], align 0)
 ; X32-NEXT:  [[ARG4_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK12]]
 ; X32-NEXT:  [[ARG4:%[0-9]+]](s8) = G_LOAD [[ARG4_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK12]], align 0)

 @a8_32bit = external global i32
 
 define i32 @test_i32_args_8(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4,
                             i32 %arg5, i32 %arg6, i32 %arg7, i32 %arg8) {
 
 ; ALL-LABEL: name:            test_i32_args_8
 
 ; X64: fixedStack:
-; X64:  id: [[STACK8:[0-9]+]], offset: 8, size: 4, alignment: 8, isImmutable: true, isAliased: false
-; X64:  id: [[STACK0:[0-9]+]], offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false
+; X64:  id: [[STACK8:[0-9]+]], type: default, offset: 8, size: 4, alignment: 8, isImmutable: true,
+; X64:  id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 4, alignment: 16, isImmutable: true,
 ; X64: liveins: %ecx, %edi, %edx, %esi, %r8d, %r9d
 ; X64:      [[ARG1:%[0-9]+]](s32) = COPY %edi
 ; X64-NEXT: %{{[0-9]+}}(s32) = COPY %esi
 ; X64-NEXT: %{{[0-9]+}}(s32) = COPY %edx
 ; X64-NEXT: %{{[0-9]+}}(s32) = COPY %ecx
 ; X64-NEXT: %{{[0-9]+}}(s32) = COPY %r8d
 ; X64-NEXT: %{{[0-9]+}}(s32) = COPY %r9d
 ; X64-NEXT: [[ARG7_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
 ; X64-NEXT: [[ARG7:%[0-9]+]](s32) = G_LOAD [[ARG7_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK0]], align 0)
 ; X64-NEXT: [[ARG8_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK8]]
 ; X64-NEXT: [[ARG8:%[0-9]+]](s32) = G_LOAD [[ARG8_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK8]], align 0)
 
 ; X32: fixedStack:
-; X32:  id: [[STACK28:[0-9]+]], offset: 28, size: 4, alignment: 4, isImmutable: true, isAliased: false }
-; X32:  id: [[STACK24:[0-9]+]], offset: 24, size: 4, alignment: 8, isImmutable: true, isAliased: false }
-; X32:  id: [[STACK20:[0-9]+]], offset: 20, size: 4, alignment: 4, isImmutable: true, isAliased: false }
-; X32:  id: [[STACK16:[0-9]+]], offset: 16, size: 4, alignment: 16, isImmutable: true, isAliased: false }
-; X32:  id: [[STACK12:[0-9]+]], offset: 12, size: 4, alignment: 4, isImmutable: true, isAliased: false }
-; X32:  id: [[STACK8:[0-9]+]],  offset: 8, size: 4, alignment: 8, isImmutable: true, isAliased: false }
-; X32:  id: [[STACK4:[0-9]+]],  offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false }
-; X32:  id: [[STACK0:[0-9]+]],  offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false }
+; X32:  id: [[STACK28:[0-9]+]], type: default, offset: 28, size: 4, alignment: 4, isImmutable: true,
+; X32:  id: [[STACK24:[0-9]+]], type: default, offset: 24, size: 4, alignment: 8, isImmutable: true,
+; X32:  id: [[STACK20:[0-9]+]], type: default, offset: 20, size: 4, alignment: 4, isImmutable: true,
+; X32:  id: [[STACK16:[0-9]+]], type: default, offset: 16, size: 4, alignment: 16, isImmutable: true,
+; X32:  id: [[STACK12:[0-9]+]], type: default, offset: 12, size: 4, alignment: 4, isImmutable: true,
+; X32:  id: [[STACK8:[0-9]+]], type: default, offset: 8, size: 4, alignment: 8, isImmutable: true,
+; X32:  id: [[STACK4:[0-9]+]], type: default, offset: 4, size: 4, alignment: 4, isImmutable: true,
+; X32:  id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 4, alignment: 16, isImmutable: true,
 ; X32:       [[ARG1_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
 ; X32-NEXT:  [[ARG1:%[0-9]+]](s32) = G_LOAD [[ARG1_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK0]], align 0)
 ; X32-NEXT:  [[ARG2_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK4]]
 ; X32-NEXT:  [[ARG2:%[0-9]+]](s32) = G_LOAD [[ARG2_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK4]], align 0)
 ; X32-NEXT:  [[ARG3_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK8]]
 ; X32-NEXT:  [[ARG3:%[0-9]+]](s32) = G_LOAD [[ARG3_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK8]], align 0)
 ; X32-NEXT:  [[ARG4_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK12]]
 ; X32-NEXT:  [[ARG4:%[0-9]+]](s32) = G_LOAD [[ARG4_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK12]], align 0)

 @a7_64bit = external global i64
 @a8_64bit = external global i64
 
 define i64 @test_i64_args_8(i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4,
                             i64 %arg5, i64 %arg6, i64 %arg7, i64 %arg8) {
 
 ; ALL-LABEL: name:            test_i64_args_8
 ; X64: fixedStack:
-; X64:  id: [[STACK8:[0-9]+]], offset: 8, size: 8, alignment: 8, isImmutable: true, isAliased: false
-; X64:  id: [[STACK0:[0-9]+]], offset: 0, size: 8, alignment: 16, isImmutable: true, isAliased: false
+; X64:  id: [[STACK8:[0-9]+]], type: default, offset: 8, size: 8, alignment: 8, isImmutable: true,
+; X64:  id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 8, alignment: 16, isImmutable: true,
 ; X64: liveins: %rcx, %rdi, %rdx, %rsi, %r8, %r9
 ; X64:      [[ARG1:%[0-9]+]](s64) = COPY %rdi
 ; X64-NEXT: %{{[0-9]+}}(s64) = COPY %rsi
 ; X64-NEXT: %{{[0-9]+}}(s64) = COPY %rdx
 ; X64-NEXT: %{{[0-9]+}}(s64) = COPY %rcx
 ; X64-NEXT: %{{[0-9]+}}(s64) = COPY %r8
 ; X64-NEXT: %{{[0-9]+}}(s64) = COPY %r9
 ; X64-NEXT: [[ARG7_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
 ; X64-NEXT: [[ARG7:%[0-9]+]](s64) = G_LOAD [[ARG7_ADDR]](p0) :: (invariant load 8 from %fixed-stack.[[STACK0]], align 0)
 ; X64-NEXT: [[ARG8_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK8]]
 ; X64-NEXT: [[ARG8:%[0-9]+]](s64) = G_LOAD [[ARG8_ADDR]](p0) :: (invariant load 8 from %fixed-stack.[[STACK8]], align 0)
 
 ; X32: fixedStack:
-; X32:  id: [[STACK60:[0-9]+]], offset: 60, size: 4, alignment: 4, isImmutable: true, isAliased: false }
-; X32:  id: [[STACK56:[0-9]+]], offset: 56, size: 4, alignment: 8, isImmutable: true, isAliased: false }
-; X32:  id: [[STACK52:[0-9]+]], offset: 52, size: 4, alignment: 4, isImmutable: true, isAliased: false }
-; X32:  id: [[STACK48:[0-9]+]], offset: 48, size: 4, alignment: 16, isImmutable: true, isAliased: false }
-; X32:  id: [[STACK44:[0-9]+]], offset: 44, size: 4, alignment: 4, isImmutable: true, isAliased: false }
-; X32:  id: [[STACK40:[0-9]+]], offset: 40, size: 4, alignment: 8, isImmutable: true, isAliased: false }
-; X32:  id: [[STACK36:[0-9]+]], offset: 36, size: 4, alignment: 4, isImmutable: true, isAliased: false }
-; X32:  id: [[STACK32:[0-9]+]], offset: 32, size: 4, alignment: 16, isImmutable: true, isAliased: false }
-; X32:  id: [[STACK28:[0-9]+]], offset: 28, size: 4, alignment: 4, isImmutable: true, isAliased: false }
-; X32:  id: [[STACK24:[0-9]+]], offset: 24, size: 4, alignment: 8, isImmutable: true, isAliased: false }
-; X32:  id: [[STACK20:[0-9]+]], offset: 20, size: 4, alignment: 4, isImmutable: true, isAliased: false }
-; X32:  id: [[STACK16:[0-9]+]], offset: 16, size: 4, alignment: 16, isImmutable: true, isAliased: false }
-; X32:  id: [[STACK12:[0-9]+]], offset: 12, size: 4, alignment: 4, isImmutable: true, isAliased: false }
-; X32:  id: [[STACK8:[0-9]+]], offset: 8, size: 4, alignment: 8, isImmutable: true, isAliased: false }
-; X32:  id: [[STACK4:[0-9]+]], offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false }
-; X32:  id: [[STACK0:[0-9]+]], offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false }
+; X32:  id: [[STACK60:[0-9]+]], type: default, offset: 60, size: 4, alignment: 4, isImmutable: true,
+; X32:  id: [[STACK56:[0-9]+]], type: default, offset: 56, size: 4, alignment: 8, isImmutable: true,
+; X32:  id: [[STACK52:[0-9]+]], type: default, offset: 52, size: 4, alignment: 4, isImmutable: true,
+; X32:  id: [[STACK48:[0-9]+]], type: default, offset: 48, size: 4, alignment: 16, isImmutable: true,
+; X32:  id: [[STACK44:[0-9]+]], type: default, offset: 44, size: 4, alignment: 4, isImmutable: true,
+; X32:  id: [[STACK40:[0-9]+]], type: default, offset: 40, size: 4, alignment: 8, isImmutable: true,
+; X32:  id: [[STACK36:[0-9]+]], type: default, offset: 36, size: 4, alignment: 4, isImmutable: true,
+; X32:  id: [[STACK32:[0-9]+]], type: default, offset: 32, size: 4, alignment: 16, isImmutable: true,
+; X32:  id: [[STACK28:[0-9]+]], type: default, offset: 28, size: 4, alignment: 4, isImmutable: true,
+; X32:  id: [[STACK24:[0-9]+]], type: default, offset: 24, size: 4, alignment: 8, isImmutable: true,
+; X32:  id: [[STACK20:[0-9]+]], type: default, offset: 20, size: 4, alignment: 4, isImmutable: true,
+; X32:  id: [[STACK16:[0-9]+]], type: default, offset: 16, size: 4, alignment: 16, isImmutable: true,
+; X32:  id: [[STACK12:[0-9]+]], type: default, offset: 12, size: 4, alignment: 4, isImmutable: true,
+; X32:  id: [[STACK8:[0-9]+]], type: default, offset: 8, size: 4, alignment: 8, isImmutable: true,
+; X32:  id: [[STACK4:[0-9]+]], type: default, offset: 4, size: 4, alignment: 4, isImmutable: true,
+; X32:  id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 4, alignment: 16, isImmutable: true,
 
 ; X32:      [[ARG1L_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
 ; X32-NEXT: [[ARG1L:%[0-9]+]](s32) = G_LOAD [[ARG1L_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK0]], align 0)
 ; X32-NEXT: [[ARG1H_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK4]]
 ; X32-NEXT: [[ARG1H:%[0-9]+]](s32) = G_LOAD [[ARG1H_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK4]], align 0)
 ; X32-NEXT: %{{[0-9]+}}(p0) = G_FRAME_INDEX %fixed-stack.[[STACK8]]
 ; X32-NEXT: %{{[0-9]+}}(s32) = G_LOAD %{{[0-9]+}}(p0) :: (invariant load 4 from %fixed-stack.[[STACK8]], align 0)
 ; X32-NEXT: %{{[0-9]+}}(p0) = G_FRAME_INDEX %fixed-stack.[[STACK12]]

 
 ; X64: liveins: %xmm0, %xmm1
 ; X64:      [[ARG1:%[0-9]+]](s32) = COPY %xmm0
 ; X64-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %xmm1
 ; X64-NEXT: %xmm0 = COPY [[ARG2:%[0-9]+]](s32)
 ; X64-NEXT: RET 0, implicit %xmm0
 
 ; X32: fixedStack:
-; X32:  id: [[STACK4:[0-9]+]], offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false }
-; X32:  id: [[STACK0:[0-9]+]], offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false }
+; X32:  id: [[STACK4:[0-9]+]], type: default, offset: 4, size: 4, alignment: 4, isImmutable: true,
+; X32:  id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 4, alignment: 16, isImmutable: true,
 ; X32:       [[ARG1_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
 ; X32-NEXT:  [[ARG1:%[0-9]+]](s32) = G_LOAD [[ARG1_ADDR:%[0-9]+]](p0) :: (invariant load 4 from %fixed-stack.[[STACK0]], align 0)
 ; X32-NEXT:  [[ARG2_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK4]]
 ; X32-NEXT:  [[ARG2:%[0-9]+]](s32) = G_LOAD [[ARG2_ADDR:%[0-9]+]](p0) :: (invariant load 4 from %fixed-stack.[[STACK4]], align 0)
 ; X32-NEXT:  %fp0 = COPY [[ARG2:%[0-9]+]](s32)
 ; X32-NEXT:  RET 0, implicit %fp0
 
   ret float %arg2
 }
 
 define double @test_double_args(double %arg1, double %arg2) {
 ; ALL-LABEL:name:            test_double_args
 ; X64: liveins: %xmm0, %xmm1
 ; X64:     [[ARG1:%[0-9]+]](s64) = COPY %xmm0
 ; X64-NEXT: [[ARG2:%[0-9]+]](s64) = COPY %xmm1
 ; X64-NEXT: %xmm0 = COPY [[ARG2:%[0-9]+]](s64)
 ; X64-NEXT: RET 0, implicit %xmm0
 
 ; X32: fixedStack:
-; X32:  id: [[STACK4:[0-9]+]], offset: 8, size: 8, alignment: 8, isImmutable: true, isAliased: false }
-; X32:  id: [[STACK0:[0-9]+]], offset: 0, size: 8, alignment: 16, isImmutable: true, isAliased: false }
+; X32:  id: [[STACK4:[0-9]+]], type: default, offset: 8, size: 8, alignment: 8, isImmutable: true,
+; X32:  id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 8, alignment: 16, isImmutable: true,
 ; X32:       [[ARG1_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
 ; X32-NEXT:  [[ARG1:%[0-9]+]](s64) = G_LOAD [[ARG1_ADDR:%[0-9]+]](p0) :: (invariant load 8 from %fixed-stack.[[STACK0]], align 0)
 ; X32-NEXT:  [[ARG2_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK4]]
 ; X32-NEXT:  [[ARG2:%[0-9]+]](s64) = G_LOAD [[ARG2_ADDR:%[0-9]+]](p0) :: (invariant load 8 from %fixed-stack.[[STACK4]], align 0)
 ; X32-NEXT:  %fp0 = COPY [[ARG2:%[0-9]+]](s64)
 ; X32-NEXT:  RET 0, implicit %fp0
 
   ret double %arg2

 define i32 * @test_memop_i32(i32 * %p1) {
 ; ALL-LABEL:name:            test_memop_i32
 ;X64    liveins: %rdi
 ;X64:       %0(p0) = COPY %rdi
 ;X64-NEXT:  %rax = COPY %0(p0)
 ;X64-NEXT:  RET 0, implicit %rax
 
 ;X32: fixedStack:
-;X32:  id: [[STACK0:[0-9]+]], offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false }
+;X32:  id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 4, alignment: 16, isImmutable: true,
 ;X32:         %1(p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
 ;X32-NEXT:    %0(p0) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.[[STACK0]], align 0)
 ;X32-NEXT:    %eax = COPY %0(p0)
 ;X32-NEXT:    RET 0, implicit %eax
 
   ret i32 * %p1;
 }
 No newline at end of file

test/CodeGen/X86/GlobalISel/legalize-mul-scalar.mir

 ...
 ---
 name:            test_mul_i16
 # CHECK-LABEL: name:  test_mul_i16
 alignment:       4
 legalized:       false
 regBankSelected: false
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: _ }
-# CHECK-NEXT:   - { id: 1, class: _ }
-# CHECK-NEXT:   - { id: 2, class: _ }
+# CHECK-NEXT:   - { id: 0, class: _, preferred-register: '' }
+# CHECK-NEXT:   - { id: 1, class: _, preferred-register: '' }
+# CHECK-NEXT:   - { id: 2, class: _, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 # CHECK:      body:             |
 # CHECK-NEXT:   bb.0 (%ir-block.0):
 # CHECK-NEXT:     %0(s16) = COPY %edi
 # CHECK-NEXT:     %1(s16) = COPY %esi

 ...
 ---
 name:            test_mul_i32
 # CHECK-LABEL: name:  test_mul_i32
 alignment:       4
 legalized:       false
 regBankSelected: false
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: _ }
-# CHECK-NEXT:   - { id: 1, class: _ }
-# CHECK-NEXT:   - { id: 2, class: _ }
+# CHECK-NEXT:   - { id: 0, class: _, preferred-register: '' }
+# CHECK-NEXT:   - { id: 1, class: _, preferred-register: '' }
+# CHECK-NEXT:   - { id: 2, class: _, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 # CHECK:      body:             |
 # CHECK-NEXT:   bb.0 (%ir-block.0):
 # CHECK-NEXT:     %0(s32) = COPY %edi
 # CHECK-NEXT:     %1(s32) = COPY %esi

 ...
 ---
 name:            test_mul_i64
 # CHECK-LABEL: name:  test_mul_i64
 alignment:       4
 legalized:       false
 regBankSelected: false
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: _ }
-# CHECK-NEXT:   - { id: 1, class: _ }
-# CHECK-NEXT:   - { id: 2, class: _ }
+# CHECK-NEXT:   - { id: 0, class: _, preferred-register: '' }
+# CHECK-NEXT:   - { id: 1, class: _, preferred-register: '' }
+# CHECK-NEXT:   - { id: 2, class: _, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 # CHECK:      body:             |
 # CHECK-NEXT:   bb.0 (%ir-block.0):
 # CHECK-NEXT:     %0(s64) = COPY %rdi
 # CHECK-NEXT:     %1(s64) = COPY %rsi

test/CodeGen/X86/GlobalISel/legalize-mul-v128.mir

 ...
 ---
 name:            test_mul_v8i16
 # ALL-LABEL: name:  test_mul_v8i16
 alignment:       4
 legalized:       false
 regBankSelected: false
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: _ }
-# ALL-NEXT:   - { id: 1, class: _ }
-# ALL-NEXT:   - { id: 2, class: _ }
+# ALL-NEXT:   - { id: 0, class: _, preferred-register: '' }
+# ALL-NEXT:   - { id: 1, class: _, preferred-register: '' }
+# ALL-NEXT:   - { id: 2, class: _, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 # ALL:          %0(<8 x s16>) = COPY %xmm0
 # ALL-NEXT:     %1(<8 x s16>) = COPY %xmm1
 # ALL-NEXT:     %2(<8 x s16>) = G_MUL %0, %1
 # ALL-NEXT:     %xmm0 = COPY %2(<8 x s16>)

 ...
 ---
 name:            test_mul_v4i32
 # ALL-LABEL: name:  test_mul_v4i32
 alignment:       4
 legalized:       false
 regBankSelected: false
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: _ }
-# ALL-NEXT:   - { id: 1, class: _ }
-# ALL-NEXT:   - { id: 2, class: _ }
+# ALL-NEXT:   - { id: 0, class: _, preferred-register: '' }
+# ALL-NEXT:   - { id: 1, class: _, preferred-register: '' }
+# ALL-NEXT:   - { id: 2, class: _, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 # ALL:          %0(<4 x s32>) = COPY %xmm0
 # ALL-NEXT:     %1(<4 x s32>) = COPY %xmm1
 # ALL-NEXT:     %2(<4 x s32>) = G_MUL %0, %1
 # ALL-NEXT:     %xmm0 = COPY %2(<4 x s32>)

 ...
 ---
 name:            test_mul_v2i64
 # ALL-LABEL: name:  test_mul_v2i64
 alignment:       4
 legalized:       false
 regBankSelected: false
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: _ }
-# ALL-NEXT:   - { id: 1, class: _ }
-# ALL-NEXT:   - { id: 2, class: _ }
+# ALL-NEXT:   - { id: 0, class: _, preferred-register: '' }
+# ALL-NEXT:   - { id: 1, class: _, preferred-register: '' }
+# ALL-NEXT:   - { id: 2, class: _, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 # ALL:          %0(<2 x s64>) = COPY %xmm0
 # ALL-NEXT:     %1(<2 x s64>) = COPY %xmm1
 # ALL-NEXT:     %2(<2 x s64>) = G_MUL %0, %1
 # ALL-NEXT:     %xmm0 = COPY %2(<2 x s64>)

test/CodeGen/X86/GlobalISel/legalize-mul-v256.mir

 ...
 ---
 name:            test_mul_v16i16
 # ALL-LABEL: name:  test_mul_v16i16
 alignment:       4
 legalized:       false
 regBankSelected: false
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: _ }
-# ALL-NEXT:   - { id: 1, class: _ }
-# ALL-NEXT:   - { id: 2, class: _ }
+# ALL-NEXT:   - { id: 0, class: _, preferred-register: '' }
+# ALL-NEXT:   - { id: 1, class: _, preferred-register: '' }
+# ALL-NEXT:   - { id: 2, class: _, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 # ALL:          %0(<16 x s16>) = COPY %ymm0
 # ALL-NEXT:     %1(<16 x s16>) = COPY %ymm1
 # ALL-NEXT:     %2(<16 x s16>) = G_MUL %0, %1
 # ALL-NEXT:     %ymm0 = COPY %2(<16 x s16>)

 ...
 ---
 name:            test_mul_v8i32
 # ALL-LABEL: name:  test_mul_v8i32
 alignment:       4
 legalized:       false
 regBankSelected: false
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: _ }
-# ALL-NEXT:   - { id: 1, class: _ }
-# ALL-NEXT:   - { id: 2, class: _ }
+# ALL-NEXT:   - { id: 0, class: _, preferred-register: '' }
+# ALL-NEXT:   - { id: 1, class: _, preferred-register: '' }
+# ALL-NEXT:   - { id: 2, class: _, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 # ALL:          %0(<8 x s32>) = COPY %ymm0
 # ALL-NEXT:     %1(<8 x s32>) = COPY %ymm1
 # ALL-NEXT:     %2(<8 x s32>) = G_MUL %0, %1
 # ALL-NEXT:     %ymm0 = COPY %2(<8 x s32>)

 ...
 ---
 name:            test_mul_v4i64
 # ALL-LABEL: name:  test_mul_v4i64
 alignment:       4
 legalized:       false
 regBankSelected: false
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: _ }
-# ALL-NEXT:   - { id: 1, class: _ }
-# ALL-NEXT:   - { id: 2, class: _ }
+# ALL-NEXT:   - { id: 0, class: _, preferred-register: '' }
+# ALL-NEXT:   - { id: 1, class: _, preferred-register: '' }
+# ALL-NEXT:   - { id: 2, class: _, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 # ALL:          %0(<4 x s64>) = COPY %ymm0
 # ALL-NEXT:     %1(<4 x s64>) = COPY %ymm1
 # ALL-NEXT:     %2(<4 x s64>) = G_MUL %0, %1
 # ALL-NEXT:     %ymm0 = COPY %2(<4 x s64>)

test/CodeGen/X86/GlobalISel/legalize-mul-v512.mir

 ...
 ---
 name:            test_mul_v32i16
 # ALL-LABEL: name:  test_mul_v32i16
 alignment:       4
 legalized:       false
 regBankSelected: false
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: _ }
-# ALL-NEXT:   - { id: 1, class: _ }
-# ALL-NEXT:   - { id: 2, class: _ }
+# ALL-NEXT:   - { id: 0, class: _, preferred-register: '' }
+# ALL-NEXT:   - { id: 1, class: _, preferred-register: '' }
+# ALL-NEXT:   - { id: 2, class: _, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 # ALL:          %0(<32 x s16>) = COPY %zmm0
 # ALL-NEXT:     %1(<32 x s16>) = COPY %zmm1
 # ALL-NEXT:     %2(<32 x s16>) = G_MUL %0, %1
 # ALL-NEXT:     %zmm0 = COPY %2(<32 x s16>)

 ...
 ---
 name:            test_mul_v16i32
 # ALL-LABEL: name:  test_mul_v16i32
 alignment:       4
 legalized:       false
 regBankSelected: false
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: _ }
-# ALL-NEXT:   - { id: 1, class: _ }
-# ALL-NEXT:   - { id: 2, class: _ }
+# ALL-NEXT:   - { id: 0, class: _, preferred-register: '' }
+# ALL-NEXT:   - { id: 1, class: _, preferred-register: '' }
+# ALL-NEXT:   - { id: 2, class: _, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 # ALL:          %0(<16 x s32>) = COPY %zmm0
 # ALL-NEXT:     %1(<16 x s32>) = COPY %zmm1
 # ALL-NEXT:     %2(<16 x s32>) = G_MUL %0, %1
 # ALL-NEXT:     %zmm0 = COPY %2(<16 x s32>)

 ...
 ---
 name:            test_mul_v8i64
 # ALL-LABEL: name:  test_mul_v8i64
 alignment:       4
 legalized:       false
 regBankSelected: false
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: _ }
-# ALL-NEXT:   - { id: 1, class: _ }
-# ALL-NEXT:   - { id: 2, class: _ }
+# ALL-NEXT:   - { id: 0, class: _, preferred-register: '' }
+# ALL-NEXT:   - { id: 1, class: _, preferred-register: '' }
+# ALL-NEXT:   - { id: 2, class: _, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 # ALL:          %0(<8 x s64>) = COPY %zmm0
 # ALL-NEXT:     %1(<8 x s64>) = COPY %zmm1
 # ALL-NEXT:     %2(<8 x s64>) = G_MUL %0, %1
 # ALL-NEXT:     %zmm0 = COPY %2(<8 x s64>)

test/CodeGen/X86/GlobalISel/regbankselect-AVX2.mir

 name:            test_mul_vec256
 alignment:       4
 legalized:       true
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 # CHECK-LABEL: name:            test_mul_vec256
 # CHECK: registers:
-# CHECK:  - { id: 0, class: vecr }
-# CHECK:  - { id: 1, class: vecr }
+# CHECK:  - { id: 0, class: vecr, preferred-register: '' }
+# CHECK:  - { id: 1, class: vecr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body:             |
   bb.1 (%ir-block.0):
 
     %0(<8 x s32>) = IMPLICIT_DEF
     %1(<8 x s32>) = G_MUL %0, %0
     RET 0
 
 ...
 ---
 name:            test_add_vec256
 alignment:       4
 legalized:       true
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 # CHECK-LABEL: name:            test_add_vec256
 # CHECK: registers:
-# CHECK:  - { id: 0, class: vecr }
-# CHECK:  - { id: 1, class: vecr }
+# CHECK:  - { id: 0, class: vecr, preferred-register: '' }
+# CHECK:  - { id: 1, class: vecr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body:             |
   bb.1 (%ir-block.0):
 
     %0(<8 x s32>) = IMPLICIT_DEF
     %1(<8 x s32>) = G_ADD %0, %0
     RET 0
 
 ...
 ---
 name:            test_sub_vec256
 alignment:       4
 legalized:       true
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 # CHECK-LABEL: name:            test_sub_vec256
 # CHECK: registers:
-# CHECK:  - { id: 0, class: vecr }
-# CHECK:  - { id: 1, class: vecr }
+# CHECK:  - { id: 0, class: vecr, preferred-register: '' }
+# CHECK:  - { id: 1, class: vecr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body:             |
   bb.1 (%ir-block.0):
 
     %0(<8 x s32>) = IMPLICIT_DEF
     %1(<8 x s32>) = G_SUB %0, %0
     RET 0
 
 ...
 ---
 name:            test_load_v8i32_noalign
 # CHECK-LABEL: name:  test_load_v8i32_noalign
 alignment:       4
 legalized:       true
 regBankSelected: false
 # CHECK:       registers:
-# CHECK-NEXT:    - { id: 0, class: gpr }
-# CHECK-NEXT:    - { id: 1, class: vecr }
+# CHECK-NEXT:    - { id: 0, class: gpr, preferred-register: '' }
+# CHECK-NEXT:    - { id: 1, class: vecr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi
 
     %0(p0) = COPY %rdi
     %1(<8 x s32>) = G_LOAD %0(p0) :: (load 32 from %ir.p1, align 1)
     %ymm0 = COPY %1(<8 x s32>)
     RET 0, implicit %ymm0
 
 ...
 ---
 name:            test_store_v8i32_noalign
 # CHECK-LABEL: name:  test_store_v8i32_noalign
 alignment:       4
 legalized:       true
 regBankSelected: false
 # CHECK:       registers:
-# CHECK-NEXT:    - { id: 0, class: vecr }
-# CHECK-NEXT:    - { id: 1, class: gpr }
+# CHECK-NEXT:    - { id: 0, class: vecr, preferred-register: '' }
+# CHECK-NEXT:    - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi, %ymm0
 
     %0(<8 x s32>) = COPY %ymm0
     %1(p0) = COPY %rdi
     G_STORE %0(<8 x s32>), %1(p0) :: (store 32 into %ir.p1, align 1)
     RET 0
 
 ...

test/CodeGen/X86/GlobalISel/regbankselect-AVX512.mir

 ...
 ---
 name:            test_mul_vec512
 # CHECK-LABEL: name:  test_mul_vec512
 alignment:       4
 legalized:       true
 regBankSelected: false
 # CHECK:       registers:
-# CHECK-NEXT:    - { id: 0, class: vecr }
-# CHECK-NEXT:    - { id: 1, class: vecr }
+# CHECK-NEXT:    - { id: 0, class: vecr, preferred-register: '' }
+# CHECK-NEXT:    - { id: 1, class: vecr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body:             |
   bb.1 (%ir-block.0):
 
     %0(<16 x s32>) = IMPLICIT_DEF
     %1(<16 x s32>) = G_MUL %0, %0
     RET 0
 
 ...
 ---
 name:            test_add_vec512
 # CHECK-LABEL: name:  test_add_vec512
 alignment:       4
 legalized:       true
 regBankSelected: false
 # CHECK:       registers:
-# CHECK-NEXT:    - { id: 0, class: vecr }
-# CHECK-NEXT:    - { id: 1, class: vecr }
+# CHECK-NEXT:    - { id: 0, class: vecr, preferred-register: '' }
+# CHECK-NEXT:    - { id: 1, class: vecr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body:             |
   bb.1 (%ir-block.0):
 
     %0(<16 x s32>) = IMPLICIT_DEF
     %1(<16 x s32>) = G_ADD %0, %0
     RET 0
 
 ...
 ---
 name:            test_sub_vec512
 # CHECK-LABEL: name:  test_sub_vec512
 alignment:       4
 legalized:       true
 regBankSelected: false
 # CHECK:       registers:
-# CHECK-NEXT:    - { id: 0, class: vecr }
-# CHECK-NEXT:    - { id: 1, class: vecr }
+# CHECK-NEXT:    - { id: 0, class: vecr, preferred-register: '' }
+# CHECK-NEXT:    - { id: 1, class: vecr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body:             |
   bb.1 (%ir-block.0):
 
     %0(<16 x s32>) = IMPLICIT_DEF
     %1(<16 x s32>) = G_SUB %0, %0
     RET 0
 ...
 ---
 
 name:            test_load_v16i32_noalign
 # CHECK-LABEL: name:  test_load_v16i32_noalign
 alignment:       4
 legalized:       true
 regBankSelected: false
 # CHECK:       registers:
-# CHECK-NEXT:    - { id: 0, class: gpr }
-# CHECK-NEXT:    - { id: 1, class: vecr }
+# CHECK-NEXT:    - { id: 0, class: gpr, preferred-register: '' }
+# CHECK-NEXT:    - { id: 1, class: vecr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi
 
     %0(p0) = COPY %rdi
     %1(<16 x s32>) = G_LOAD %0(p0) :: (load 64 from %ir.p1, align 1)
     %zmm0 = COPY %1(<16 x s32>)
     RET 0, implicit %zmm0
 
 ...
 ---
 name:            test_store_v16i32_noalign
 # CHECK-LABEL: name:  test_store_v16i32_noalign
 alignment:       4
 legalized:       true
 regBankSelected: false
 # CHECK:       registers:
-# CHECK-NEXT:    - { id: 0, class: vecr }
-# CHECK-NEXT:    - { id: 1, class: gpr }
+# CHECK-NEXT:    - { id: 0, class: vecr, preferred-register: '' }
+# CHECK-NEXT:    - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi, %zmm0
 
     %0(<16 x s32>) = COPY %zmm0
     %1(p0) = COPY %rdi
     G_STORE %0(<16 x s32>), %1(p0) :: (store 64 into %ir.p1, align 1)
     RET 0
 
 ...

test/CodeGen/X86/GlobalISel/regbankselect-X32.mir

 # RUN: llc -mtriple=i386-linux-gnu -global-isel                       -run-pass=regbankselect %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=FAST
 # RUN: llc -mtriple=i386-linux-gnu -global-isel -regbankselect-greedy -run-pass=regbankselect %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=GREEDY
 
 --- |
   define void @test_uadde_i32() {
     ret void
   }
 
 ...
 ---
 name:            test_uadde_i32
 # CHECK-LABEL: name:  test_uadde_i32
 alignment:       4
 legalized:       true
 regBankSelected: false
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gpr }
-# CHECK-NEXT:   - { id: 1, class: gpr }
-# CHECK-NEXT:   - { id: 2, class: gpr }
-# CHECK-NEXT:   - { id: 3, class: gpr }
-# CHECK-NEXT:   - { id: 4, class: gpr }
+# CHECK-NEXT:   - { id: 0, class: gpr, preferred-register: '' }
+# CHECK-NEXT:   - { id: 1, class: gpr, preferred-register: '' }
+# CHECK-NEXT:   - { id: 2, class: gpr, preferred-register: '' }
+# CHECK-NEXT:   - { id: 3, class: gpr, preferred-register: '' }
+# CHECK-NEXT:   - { id: 4, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
   - { id: 3, class: _ }
   - { id: 4, class: _ }
 body:             |
   bb.0 (%ir-block.0):
     %0(s32) = IMPLICIT_DEF
     %1(s32) = IMPLICIT_DEF
     %2(s1) = IMPLICIT_DEF
     %3(s32), %4(s1) = G_UADDE %0, %1, %2
     RET 0
 
 ...

test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir

 name:            test_add_i8
 alignment:       4
 legalized:       true
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 # CHECK-LABEL: name:            test_add_i8
 # CHECK: registers:
-# CHECK:  - { id: 0, class: gpr }
-# CHECK:  - { id: 1, class: gpr }
-# CHECK:  - { id: 2, class: gpr }
+# CHECK:  - { id: 0, class: gpr, preferred-register: '' }
+# CHECK:  - { id: 1, class: gpr, preferred-register: '' }
+# CHECK:  - { id: 2, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %edi, %esi
 
     %0(s8) = COPY %edi
     %1(s8) = COPY %esi
     %2(s8) = G_ADD %0, %1
     %al = COPY %2(s8)
     RET 0, implicit %al
 
 ...
 ---
 name:            test_add_i16
 alignment:       4
 legalized:       true
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 # CHECK-LABEL: name:            test_add_i16
 # CHECK: registers:
-# CHECK:  - { id: 0, class: gpr }
-# CHECK:  - { id: 1, class: gpr }
-# CHECK:  - { id: 2, class: gpr }
+# CHECK:  - { id: 0, class: gpr, preferred-register: '' }
+# CHECK:  - { id: 1, class: gpr, preferred-register: '' }
+# CHECK:  - { id: 2, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %edi, %esi
 
     %0(s16) = COPY %edi
     %1(s16) = COPY %esi
     %2(s16) = G_ADD %0, %1
     %ax = COPY %2(s16)
     RET 0, implicit %ax
 
 ...
 ---
 name:            test_add_i32
 alignment:       4
 legalized:       true
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 # CHECK-LABEL: name:            test_add_i32
 # CHECK: registers:
-# CHECK:  - { id: 0, class: gpr }
-# CHECK:  - { id: 1, class: gpr }
-# CHECK:  - { id: 2, class: gpr }
+# CHECK:  - { id: 0, class: gpr, preferred-register: '' }
+# CHECK:  - { id: 1, class: gpr, preferred-register: '' }
+# CHECK:  - { id: 2, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %edi, %esi
 
     %0(s32) = COPY %edi
     %1(s32) = COPY %esi
     %2(s32) = G_ADD %0, %1
     %eax = COPY %2(s32)
     RET 0, implicit %eax
 
 ...
 ---
 name:            test_add_i64
 alignment:       4
 legalized:       true
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 # CHECK-LABEL: name:            test_add_i64
 # CHECK: registers:
-# CHECK:  - { id: 0, class: gpr }
-# CHECK:  - { id: 1, class: gpr }
-# CHECK:  - { id: 2, class: gpr }
+# CHECK:  - { id: 0, class: gpr, preferred-register: '' }
+# CHECK:  - { id: 1, class: gpr, preferred-register: '' }
+# CHECK:  - { id: 2, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi, %rsi
 
     %0(s64) = COPY %rdi
     %1(s64) = COPY %rsi
     %2(s64) = G_ADD %0, %1
     %rax = COPY %2(s64)
     RET 0, implicit %rax
 
 ...
 ---
 name:            test_mul_gpr
 alignment:       4
 legalized:       true
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 # CHECK-LABEL: name:            test_mul_gpr
 # CHECK: registers:
-# CHECK:  - { id: 0, class: gpr }
-# CHECK:  - { id: 1, class: gpr }
-# CHECK:  - { id: 2, class: gpr }
-# CHECK:  - { id: 3, class: gpr }
-# CHECK:  - { id: 4, class: gpr }
-# CHECK:  - { id: 5, class: gpr }
-# CHECK:  - { id: 6, class: gpr }
-# CHECK:  - { id: 7, class: gpr }
+# CHECK:  - { id: 0, class: gpr, preferred-register: '' }
+# CHECK:  - { id: 1, class: gpr, preferred-register: '' }
+# CHECK:  - { id: 2, class: gpr, preferred-register: '' }
+# CHECK:  - { id: 3, class: gpr, preferred-register: '' }
+# CHECK:  - { id: 4, class: gpr, preferred-register: '' }
+# CHECK:  - { id: 5, class: gpr, preferred-register: '' }
+# CHECK:  - { id: 6, class: gpr, preferred-register: '' }
+# CHECK:  - { id: 7, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
   - { id: 3, class: _ }
   - { id: 4, class: _ }
   - { id: 5, class: _ }
   - { id: 6, class: _ }

 name:            test_add_float
 alignment:       4
 legalized:       true
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 # CHECK-LABEL: name:            test_add_float
 # CHECK: registers:
-# CHECK:  - { id: 0, class: vecr }
-# CHECK:  - { id: 1, class: vecr }
-# CHECK:  - { id: 2, class: vecr }
+# CHECK:  - { id: 0, class: vecr, preferred-register: '' }
+# CHECK:  - { id: 1, class: vecr, preferred-register: '' }
+# CHECK:  - { id: 2, class: vecr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %xmm0, %xmm1
 
     %0(s32) = COPY %xmm0
     %1(s32) = COPY %xmm1
     %2(s32) = G_FADD %0, %1
     %xmm0 = COPY %2(s32)
     RET 0, implicit %xmm0
 
 ...
 ---
 name:            test_add_double
 alignment:       4
 legalized:       true
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 # CHECK-LABEL: name:            test_add_double
 # CHECK: registers:
-# CHECK:  - { id: 0, class: vecr }
-# CHECK:  - { id: 1, class: vecr }
-# CHECK:  - { id: 2, class: vecr }
+# CHECK:  - { id: 0, class: vecr, preferred-register: '' }
+# CHECK:  - { id: 1, class: vecr, preferred-register: '' }
+# CHECK:  - { id: 2, class: vecr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %xmm0, %xmm1
 
     %0(s64) = COPY %xmm0
     %1(s64) = COPY %xmm1
     %2(s64) = G_FADD %0, %1
     %xmm0 = COPY %2(s64)
     RET 0, implicit %xmm0
 
 ...
 ---
 name:            test_add_v4i32
 alignment:       4
 legalized:       true
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 # CHECK-LABEL: name:            test_add_v4i32
 # CHECK: registers:
-# CHECK:  - { id: 0, class: vecr }
-# CHECK:  - { id: 1, class: vecr }
-# CHECK:  - { id: 2, class: vecr }
+# CHECK:  - { id: 0, class: vecr, preferred-register: '' }
+# CHECK:  - { id: 1, class: vecr, preferred-register: '' }
+# CHECK:  - { id: 2, class: vecr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %xmm0, %xmm1
 
     %0(<4 x s32>) = COPY %xmm0
     %1(<4 x s32>) = COPY %xmm1
     %2(<4 x s32>) = G_ADD %0, %1
     %xmm0 = COPY %2(<4 x s32>)
     RET 0, implicit %xmm0
 
 ...
 ---
 name:            test_add_v4f32
 alignment:       4
 legalized:       true
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 # CHECK-LABEL: name:            test_add_v4f32
 # CHECK: registers:
-# CHECK:  - { id: 0, class: vecr }
-# CHECK:  - { id: 1, class: vecr }
-# CHECK:  - { id: 2, class: vecr }
+# CHECK:  - { id: 0, class: vecr, preferred-register: '' }
+# CHECK:  - { id: 1, class: vecr, preferred-register: '' }
+# CHECK:  - { id: 2, class: vecr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %xmm0, %xmm1
 
     %0(<4 x s32>) = COPY %xmm0
     %1(<4 x s32>) = COPY %xmm1
     %2(<4 x s32>) = G_FADD %0, %1
     %xmm0 = COPY %2(<4 x s32>)
     RET 0, implicit %xmm0
 
 ...
 ---
 name:            test_load_i8
 alignment:       4
 legalized:       true
 regBankSelected: false
 selected:        false
 # CHECK-LABEL: name:            test_load_i8
 # CHECK: registers:
-# CHECK:   - { id: 0, class: gpr }
-# CHECK:   - { id: 1, class: gpr }
+# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
+# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi
 
     %0(p0) = COPY %rdi
     %1(s8) = G_LOAD %0(p0) :: (load 1 from %ir.p1)
     %al = COPY %1(s8)
     RET 0, implicit %al
 
 ...
 ---
 name:            test_load_i16
 alignment:       4
 legalized:       true
 regBankSelected: false
 selected:        false
 # CHECK-LABEL: name:            test_load_i16
 # CHECK: registers:
-# CHECK:   - { id: 0, class: gpr }
-# CHECK:   - { id: 1, class: gpr }
+# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
+# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi
 
     %0(p0) = COPY %rdi
     %1(s16) = G_LOAD %0(p0) :: (load 2 from %ir.p1)
     %ax = COPY %1(s16)
     RET 0, implicit %ax
 
 ...
 ---
 name:            test_load_i32
 alignment:       4
 legalized:       true
 regBankSelected: false
 selected:        false
 # CHECK-LABEL: name:            test_load_i32
 # CHECK: registers:
-# CHECK:   - { id: 0, class: gpr }
-# CHECK:   - { id: 1, class: gpr }
+# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
+# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi
 
     %0(p0) = COPY %rdi
     %1(s32) = G_LOAD %0(p0) :: (load 4 from %ir.p1)
     %eax = COPY %1(s32)
     RET 0, implicit %eax
 
 ...
 ---
 name:            test_load_i64
 alignment:       4
 exposesReturnsTwice: false
 legalized:       true
 regBankSelected: false
 selected:        false
 # CHECK-LABEL: name:            test_load_i64
 # CHECK: registers:
-# CHECK:   - { id: 0, class: gpr }
-# CHECK:   - { id: 1, class: gpr }
+# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
+# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi
 
     %0(p0) = COPY %rdi
     %1(s64) = G_LOAD %0(p0) :: (load 8 from %ir.p1)
     %rax = COPY %1(s64)
     RET 0, implicit %rax
 
 ...
 ---
 name:            test_load_float
 alignment:       4
 legalized:       true
 regBankSelected: false
 selected:        false
 # CHECK-LABEL: name:            test_load_float
 # CHECK: registers:
-# CHECK:   - { id: 0, class: gpr }
-# CHECK:   - { id: 1, class: gpr }
+# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
+# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi
 
     %0(p0) = COPY %rdi
     %1(s32) = G_LOAD %0(p0) :: (load 4 from %ir.p1)
     %xmm0 = COPY %1(s32)
     RET 0, implicit %xmm0
 
 ...
 ---
 name:            test_load_double
 alignment:       4
 legalized:       true
 regBankSelected: false
 selected:        false
 # CHECK-LABEL: name:            test_load_double
 # CHECK: registers:
-# CHECK:   - { id: 0, class: gpr }
-# CHECK:   - { id: 1, class: gpr }
+# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
+# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi
 
     %0(p0) = COPY %rdi
     %1(s64) = G_LOAD %0(p0) :: (load 8 from %ir.p1)
     %xmm0 = COPY %1(s64)
     RET 0, implicit %xmm0
 
 ...
 ---
 name:            test_load_v4i32
 alignment:       4
 legalized:       true
 regBankSelected: false
 selected:        false
 # CHECK-LABEL: name:            test_load_v4i32
 # CHECK: registers:
-# CHECK:   - { id: 0, class: gpr }
-# CHECK:   - { id: 1, class: vecr }
+# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
+# CHECK:   - { id: 1, class: vecr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi
 
     %0(p0) = COPY %rdi
     %1(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.p1, align 1)
     %xmm0 = COPY %1(<4 x s32>)
     RET 0, implicit %xmm0
 
 ...
 ---
 name:            test_store_i32
 alignment:       4
 legalized:       true
 regBankSelected: false
 selected:        false
 # CHECK-LABEL: name:            test_store_i32
 # CHECK: registers:
-# CHECK:   - { id: 0, class: gpr }
-# CHECK:   - { id: 1, class: gpr }
+# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
+# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %edi, %rsi
 
     %0(s32) = COPY %edi
     %1(p0) = COPY %rsi
     G_STORE %0(s32), %1(p0) :: (store 4 into %ir.p1)
     %rax = COPY %1(p0)
     RET 0, implicit %rax
 
 ...
 ---
 name:            test_store_i64
 alignment:       4
 legalized:       true
 regBankSelected: false
 selected:        false
 # CHECK-LABEL: name:            test_store_i64
 # CHECK: registers:
-# CHECK:   - { id: 0, class: gpr }
-# CHECK:   - { id: 1, class: gpr }
+# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
+# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi, %rsi
 
     %0(s64) = COPY %rdi
     %1(p0) = COPY %rsi
     G_STORE %0(s64), %1(p0) :: (store 8 into %ir.p1)
     %rax = COPY %1(p0)
     RET 0, implicit %rax
 
 ...
 ---
 name:            test_store_float
 alignment:       4
 legalized:       true
 regBankSelected: false
 selected:        false
 # CHECK-LABEL: name:            test_store_float
 # CHECK: registers:
 
-# FAST-NEXT:    - { id: 0, class: vecr }
-# FAST-NEXT:    - { id: 1, class: gpr }
-# FAST-NEXT:    - { id: 2, class: gpr }
+# FAST-NEXT:    - { id: 0, class: vecr, preferred-register: '' }
+# FAST-NEXT:    - { id: 1, class: gpr, preferred-register: '' }
+# FAST-NEXT:    - { id: 2, class: gpr, preferred-register: '' }
 
-# GREEDY-NEXT:    - { id: 0, class: vecr }
-# GREEDY-NEXT:    - { id: 1, class: gpr }
+# GREEDY-NEXT:    - { id: 0, class: vecr, preferred-register: '' }
+# GREEDY-NEXT:    - { id: 1, class: gpr, preferred-register: '' }
 
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi, %xmm0
 

 name:            test_store_double
 alignment:       4
 legalized:       true
 regBankSelected: false
 selected:        false
 # CHECK-LABEL: name:            test_store_double
 # CHECK: registers:
 
-# FAST-NEXT:    - { id: 0, class: vecr }
-# FAST-NEXT:    - { id: 1, class: gpr }
-# FAST-NEXT:    - { id: 2, class: gpr }
+# FAST-NEXT:    - { id: 0, class: vecr, preferred-register: '' }
+# FAST-NEXT:    - { id: 1, class: gpr, preferred-register: '' }
+# FAST-NEXT:    - { id: 2, class: gpr, preferred-register: '' }
 
-# GREEDY-NEXT:    - { id: 0, class: vecr }
-# GREEDY-NEXT:    - { id: 1, class: gpr }
+# GREEDY-NEXT:    - { id: 0, class: vecr, preferred-register: '' }
+# GREEDY-NEXT:    - { id: 1, class: gpr, preferred-register: '' }
 
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi, %xmm0
 

 
 ...
 ---
 name:            constInt_check
 alignment:       4
 legalized:       true
 # CHECK-LABEL: name:            constInt_check
 # CHECK: registers:
-# CHECK-NEXT:  - { id: 0, class: gpr }
-# CHECK-NEXT:  - { id: 1, class: gpr }
-# CHECK-NEXT:  - { id: 2, class: gpr }
-# CHECK-NEXT:  - { id: 3, class: gpr }
+# CHECK-NEXT:  - { id: 0, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 3, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
   - { id: 3, class: _ }
 body:             |
   bb.0 (%ir-block.0):
     %0(s8) = G_CONSTANT i8 8
     %1(s16) = G_CONSTANT i16 16
     %2(s32) = G_CONSTANT i32 32
     %3(s64) = G_CONSTANT i64 64
     RET 0
 
 ...
 ---
 name:            trunc_check
 alignment:       4
 legalized:       true
 # CHECK-LABEL: name:            trunc_check
 # CHECK: registers:
-# CHECK-NEXT:  - { id: 0, class: gpr }
-# CHECK-NEXT:  - { id: 1, class: gpr }
-# CHECK-NEXT:  - { id: 2, class: gpr }
-# CHECK-NEXT:  - { id: 3, class: gpr }
+# CHECK-NEXT:  - { id: 0, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 3, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
   - { id: 3, class: _ }
 body:             |
   bb.0 (%ir-block.0):
     %0(s32) = IMPLICIT_DEF
     %1(s1) = G_TRUNC %0(s32)
     %2(s8) = G_TRUNC %0(s32)
     %3(s16) = G_TRUNC %0(s32)
     RET 0
 
 ...
 ---
 name:            test_gep
 legalized:       true
 # CHECK-LABEL: name:            test_gep
 # CHECK: registers:
-# CHECK-NEXT:  - { id: 0, class: gpr }
-# CHECK-NEXT:  - { id: 1, class: gpr }
-# CHECK-NEXT:  - { id: 2, class: gpr }
-# CHECK-NEXT:  - { id: 3, class: gpr }
-# CHECK-NEXT:  - { id: 4, class: gpr }
+# CHECK-NEXT:  - { id: 0, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 2, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 3, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 4, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
   - { id: 3, class: _ }
   - { id: 4, class: _ }
 body:             |
   bb.0 (%ir-block.0):
     %0(p0) = IMPLICIT_DEF
     %1(s32) = G_CONSTANT i32 20
     %2(p0) = G_GEP %0, %1(s32)
     %3(s64) = G_CONSTANT i64 20
     %4(p0) = G_GEP %0, %3(s64)
     RET 0
 
 ...
 ---
 name:            test_icmp_eq_i8
 # CHECK-LABEL: name:  test_icmp_eq_i8
 alignment:       4
 legalized:       true
 regBankSelected: false
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gpr }
-# CHECK-NEXT:   - { id: 1, class: gpr }
-# CHECK-NEXT:   - { id: 2, class: gpr }
+# CHECK-NEXT:   - { id: 0, class: gpr, preferred-register: '' }
+# CHECK-NEXT:   - { id: 1, class: gpr, preferred-register: '' }
+# CHECK-NEXT:   - { id: 2, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %edi, %esi
 
     %0(s8) = COPY %edi
     %1(s8) = COPY %esi
     %2(s1) = G_ICMP intpred(eq), %0(s8), %1
     %al = COPY %2(s1)
     RET 0, implicit %al
 
 ...
 ---
 name:            test_icmp_eq_i16
 # CHECK-LABEL: name:  test_icmp_eq_i16
 alignment:       4
 legalized:       true
 regBankSelected: false
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gpr }
-# CHECK-NEXT:   - { id: 1, class: gpr }
-# CHECK-NEXT:   - { id: 2, class: gpr }
+# CHECK-NEXT:   - { id: 0, class: gpr, preferred-register: '' }
+# CHECK-NEXT:   - { id: 1, class: gpr, preferred-register: '' }
+# CHECK-NEXT:   - { id: 2, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %edi, %esi
 
     %0(s16) = COPY %edi
     %1(s16) = COPY %esi
     %2(s1) = G_ICMP intpred(eq), %0(s16), %1
     %al = COPY %2(s1)
     RET 0, implicit %al
 
 ...
 ---
 name:            test_icmp_eq_i32
 # CHECK-LABEL: name:  test_icmp_eq_i32
 alignment:       4
 legalized:       true
 regBankSelected: false
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gpr }
-# CHECK-NEXT:   - { id: 1, class: gpr }
-# CHECK-NEXT:   - { id: 2, class: gpr }
+# CHECK-NEXT:   - { id: 0, class: gpr, preferred-register: '' }
+# CHECK-NEXT:   - { id: 1, class: gpr, preferred-register: '' }
+# CHECK-NEXT:   - { id: 2, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %edi, %esi
 
     %0(s32) = COPY %edi
     %1(s32) = COPY %esi
     %2(s1) = G_ICMP intpred(eq), %0(s32), %1
     %al = COPY %2(s1)
     RET 0, implicit %al
 
 ...
 ---
 name:            test_icmp_eq_i64
 # CHECK-LABEL: name:  test_icmp_eq_i64
 alignment:       4
 legalized:       true
 regBankSelected: false
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gpr }
-# CHECK-NEXT:   - { id: 1, class: gpr }
-# CHECK-NEXT:   - { id: 2, class: gpr }
+# CHECK-NEXT:   - { id: 0, class: gpr, preferred-register: '' }
+# CHECK-NEXT:   - { id: 1, class: gpr, preferred-register: '' }
+# CHECK-NEXT:   - { id: 2, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi, %rsi
 
     %0(s64) = COPY %rdi
     %1(s64) = COPY %rsi
     %2(s1) = G_ICMP intpred(eq), %0(s64), %1
     %al = COPY %2(s1)
     RET 0, implicit %al
 
 ...

test/CodeGen/X86/GlobalISel/select-add-v128.mir

 ...
 ---
 name:            test_add_v16i8
 # ALL-LABEL: name:  test_add_v16i8
 alignment:       4
 legalized:       true
 regBankSelected: true
 # NOVL:            registers:
-# NOVL-NEXT:         - { id: 0, class: vr128 }
-# NOVL-NEXT:         - { id: 1, class: vr128 }
-# NOVL-NEXT:         - { id: 2, class: vr128 }
+# NOVL-NEXT:         - { id: 0, class: vr128, preferred-register: '' }
+# NOVL-NEXT:         - { id: 1, class: vr128, preferred-register: '' }
+# NOVL-NEXT:         - { id: 2, class: vr128, preferred-register: '' }
 #
 # AVX512VL:        registers:
-# AVX512VL-NEXT:     - { id: 0, class: vr128 }
-# AVX512VL-NEXT:     - { id: 1, class: vr128 }
-# AVX512VL-NEXT:     - { id: 2, class: vr128 }
+# AVX512VL-NEXT:     - { id: 0, class: vr128, preferred-register: '' }
+# AVX512VL-NEXT:     - { id: 1, class: vr128, preferred-register: '' }
+# AVX512VL-NEXT:     - { id: 2, class: vr128, preferred-register: '' }
 #
 # AVX512BWVL:      registers:
-# AVX512BWVL-NEXT:   - { id: 0, class: vr128x }
-# AVX512BWVL-NEXT:   - { id: 1, class: vr128x }
-# AVX512BWVL-NEXT:   - { id: 2, class: vr128x }
+# AVX512BWVL-NEXT:   - { id: 0, class: vr128x, preferred-register: '' }
+# AVX512BWVL-NEXT:   - { id: 1, class: vr128x, preferred-register: '' }
+# AVX512BWVL-NEXT:   - { id: 2, class: vr128x, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # SSE2:                %2 = PADDBrr %0, %1
 #
 # AVX1:                %2 = VPADDBrr %0, %1
 #

 ...
 ---
 name:            test_add_v8i16
 # ALL-LABEL: name:  test_add_v8i16
 alignment:       4
 legalized:       true
 regBankSelected: true
 # NOVL:            registers:
-# NOVL-NEXT:         - { id: 0, class: vr128 }
-# NOVL-NEXT:         - { id: 1, class: vr128 }
-# NOVL-NEXT:         - { id: 2, class: vr128 }
+# NOVL-NEXT:         - { id: 0, class: vr128, preferred-register: '' }
+# NOVL-NEXT:         - { id: 1, class: vr128, preferred-register: '' }
+# NOVL-NEXT:         - { id: 2, class: vr128, preferred-register: '' }
 #
 # AVX512VL:        registers:
-# AVX512VL-NEXT:     - { id: 0, class: vr128 }
-# AVX512VL-NEXT:     - { id: 1, class: vr128 }
-# AVX512VL-NEXT:     - { id: 2, class: vr128 }
+# AVX512VL-NEXT:     - { id: 0, class: vr128, preferred-register: '' }
+# AVX512VL-NEXT:     - { id: 1, class: vr128, preferred-register: '' }
+# AVX512VL-NEXT:     - { id: 2, class: vr128, preferred-register: '' }
 #
 # AVX512BWVL:      registers:
-# AVX512BWVL-NEXT:   - { id: 0, class: vr128x }
-# AVX512BWVL-NEXT:   - { id: 1, class: vr128x }
-# AVX512BWVL-NEXT:   - { id: 2, class: vr128x }
+# AVX512BWVL-NEXT:   - { id: 0, class: vr128x, preferred-register: '' }
+# AVX512BWVL-NEXT:   - { id: 1, class: vr128x, preferred-register: '' }
+# AVX512BWVL-NEXT:   - { id: 2, class: vr128x, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # SSE2:                %2 = PADDWrr %0, %1
 #
 # AVX1:                %2 = VPADDWrr %0, %1
 #

 ...
 ---
 name:            test_add_v4i32
 # ALL-LABEL: name:  test_add_v4i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 # NOVL:            registers:
-# NOVL-NEXT:         - { id: 0, class: vr128 }
-# NOVL-NEXT:         - { id: 1, class: vr128 }
-# NOVL-NEXT:         - { id: 2, class: vr128 }
+# NOVL-NEXT:         - { id: 0, class: vr128, preferred-register: '' }
+# NOVL-NEXT:         - { id: 1, class: vr128, preferred-register: '' }
+# NOVL-NEXT:         - { id: 2, class: vr128, preferred-register: '' }
 #
 # AVX512VL:        registers:
-# AVX512VL-NEXT:     - { id: 0, class: vr128x }
-# AVX512VL-NEXT:     - { id: 1, class: vr128x }
-# AVX512VL-NEXT:     - { id: 2, class: vr128x }
+# AVX512VL-NEXT:     - { id: 0, class: vr128x, preferred-register: '' }
+# AVX512VL-NEXT:     - { id: 1, class: vr128x, preferred-register: '' }
+# AVX512VL-NEXT:     - { id: 2, class: vr128x, preferred-register: '' }
 #
 # AVX512BWVL:      registers:
-# AVX512BWVL-NEXT:   - { id: 0, class: vr128x }
-# AVX512BWVL-NEXT:   - { id: 1, class: vr128x }
-# AVX512BWVL-NEXT:   - { id: 2, class: vr128x }
+# AVX512BWVL-NEXT:   - { id: 0, class: vr128x, preferred-register: '' }
+# AVX512BWVL-NEXT:   - { id: 1, class: vr128x, preferred-register: '' }
+# AVX512BWVL-NEXT:   - { id: 2, class: vr128x, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # SSE2:                %2 = PADDDrr %0, %1
 #
 # AVX1:                %2 = VPADDDrr %0, %1
 #

 ...
 ---
 name:            test_add_v2i64
 # ALL-LABEL: name:  test_add_v2i64
 alignment:       4
 legalized:       true
 regBankSelected: true
 # NOVL:            registers:
-# NOVL-NEXT:         - { id: 0, class: vr128 }
-# NOVL-NEXT:         - { id: 1, class: vr128 }
-# NOVL-NEXT:         - { id: 2, class: vr128 }
+# NOVL-NEXT:         - { id: 0, class: vr128, preferred-register: '' }
+# NOVL-NEXT:         - { id: 1, class: vr128, preferred-register: '' }
+# NOVL-NEXT:         - { id: 2, class: vr128, preferred-register: '' }
 #
 # AVX512VL:        registers:
-# AVX512VL-NEXT:     - { id: 0, class: vr128x }
-# AVX512VL-NEXT:     - { id: 1, class: vr128x }
-# AVX512VL-NEXT:     - { id: 2, class: vr128x }
+# AVX512VL-NEXT:     - { id: 0, class: vr128x, preferred-register: '' }
+# AVX512VL-NEXT:     - { id: 1, class: vr128x, preferred-register: '' }
+# AVX512VL-NEXT:     - { id: 2, class: vr128x, preferred-register: '' }
 #
 # AVX512BWVL:      registers:
-# AVX512BWVL-NEXT:   - { id: 0, class: vr128x }
-# AVX512BWVL-NEXT:   - { id: 1, class: vr128x }
-# AVX512BWVL-NEXT:   - { id: 2, class: vr128x }
+# AVX512BWVL-NEXT:   - { id: 0, class: vr128x, preferred-register: '' }
+# AVX512BWVL-NEXT:   - { id: 1, class: vr128x, preferred-register: '' }
+# AVX512BWVL-NEXT:   - { id: 2, class: vr128x, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # SSE2:                %2 = PADDQrr %0, %1
 #
 # AVX1:                %2 = VPADDQrr %0, %1
 #

test/CodeGen/X86/GlobalISel/select-add-v256.mir

 ...
 ---
 name:            test_add_v32i8
 # ALL-LABEL: name:  test_add_v32i8
 alignment:       4
 legalized:       true
 regBankSelected: true
 # AVX2:            registers:
-# AVX2-NEXT:         - { id: 0, class: vr256 }
-# AVX2-NEXT:         - { id: 1, class: vr256 }
-# AVX2-NEXT:         - { id: 2, class: vr256 }
+# AVX2-NEXT:         - { id: 0, class: vr256, preferred-register: '' }
+# AVX2-NEXT:         - { id: 1, class: vr256, preferred-register: '' }
+# AVX2-NEXT:         - { id: 2, class: vr256, preferred-register: '' }
 #
 # AVX512VL:        registers:
-# AVX512VL-NEXT:     - { id: 0, class: vr256 }
-# AVX512VL-NEXT:     - { id: 1, class: vr256 }
-# AVX512VL-NEXT:     - { id: 2, class: vr256 }
+# AVX512VL-NEXT:     - { id: 0, class: vr256, preferred-register: '' }
+# AVX512VL-NEXT:     - { id: 1, class: vr256, preferred-register: '' }
+# AVX512VL-NEXT:     - { id: 2, class: vr256, preferred-register: '' }
 #
 # AVX512BWVL:      registers:
-# AVX512BWVL-NEXT:   - { id: 0, class: vr256x }
-# AVX512BWVL-NEXT:   - { id: 1, class: vr256x }
-# AVX512BWVL-NEXT:   - { id: 2, class: vr256x }
+# AVX512BWVL-NEXT:   - { id: 0, class: vr256x, preferred-register: '' }
+# AVX512BWVL-NEXT:   - { id: 1, class: vr256x, preferred-register: '' }
+# AVX512BWVL-NEXT:   - { id: 2, class: vr256x, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # AVX2:                %2 = VPADDBYrr %0, %1
 #
 # AVX512VL:            %2 = VPADDBYrr %0, %1
 #

 ...
 ---
 name:            test_add_v16i16
 # ALL-LABEL: name:  test_add_v16i16
 alignment:       4
 legalized:       true
 regBankSelected: true
 # AVX2:            registers:
-# AVX2-NEXT:         - { id: 0, class: vr256 }
-# AVX2-NEXT:         - { id: 1, class: vr256 }
-# AVX2-NEXT:         - { id: 2, class: vr256 }
+# AVX2-NEXT:         - { id: 0, class: vr256, preferred-register: '' }
+# AVX2-NEXT:         - { id: 1, class: vr256, preferred-register: '' }
+# AVX2-NEXT:         - { id: 2, class: vr256, preferred-register: '' }
 #
 # AVX512VL:        registers:
-# AVX512VL-NEXT:     - { id: 0, class: vr256 }
-# AVX512VL-NEXT:     - { id: 1, class: vr256 }
-# AVX512VL-NEXT:     - { id: 2, class: vr256 }
+# AVX512VL-NEXT:     - { id: 0, class: vr256, preferred-register: '' }
+# AVX512VL-NEXT:     - { id: 1, class: vr256, preferred-register: '' }
+# AVX512VL-NEXT:     - { id: 2, class: vr256, preferred-register: '' }
 #
 # AVX512BWVL:      registers:
-# AVX512BWVL-NEXT:   - { id: 0, class: vr256x }
-# AVX512BWVL-NEXT:   - { id: 1, class: vr256x }
-# AVX512BWVL-NEXT:   - { id: 2, class: vr256x }
+# AVX512BWVL-NEXT:   - { id: 0, class: vr256x, preferred-register: '' }
+# AVX512BWVL-NEXT:   - { id: 1, class: vr256x, preferred-register: '' }
+# AVX512BWVL-NEXT:   - { id: 2, class: vr256x, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # AVX2:                %2 = VPADDWYrr %0, %1
 #
 # AVX512VL:            %2 = VPADDWYrr %0, %1
 #

 ...
 ---
 name:            test_add_v8i32
 # ALL-LABEL: name:  test_add_v8i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 # AVX2:            registers:
-# AVX2-NEXT:         - { id: 0, class: vr256 }
-# AVX2-NEXT:         - { id: 1, class: vr256 }
-# AVX2-NEXT:         - { id: 2, class: vr256 }
+# AVX2-NEXT:         - { id: 0, class: vr256, preferred-register: '' }
+# AVX2-NEXT:         - { id: 1, class: vr256, preferred-register: '' }
+# AVX2-NEXT:         - { id: 2, class: vr256, preferred-register: '' }
 #
 # AVX512VL:        registers:
-# AVX512VL-NEXT:     - { id: 0, class: vr256x }
-# AVX512VL-NEXT:     - { id: 1, class: vr256x }
-# AVX512VL-NEXT:     - { id: 2, class: vr256x }
+# AVX512VL-NEXT:     - { id: 0, class: vr256x, preferred-register: '' }
+# AVX512VL-NEXT:     - { id: 1, class: vr256x, preferred-register: '' }
+# AVX512VL-NEXT:     - { id: 2, class: vr256x, preferred-register: '' }
 #
 # AVX512BWVL:      registers:
-# AVX512BWVL-NEXT:   - { id: 0, class: vr256x }
-# AVX512BWVL-NEXT:   - { id: 1, class: vr256x }
-# AVX512BWVL-NEXT:   - { id: 2, class: vr256x }
+# AVX512BWVL-NEXT:   - { id: 0, class: vr256x, preferred-register: '' }
+# AVX512BWVL-NEXT:   - { id: 1, class: vr256x, preferred-register: '' }
+# AVX512BWVL-NEXT:   - { id: 2, class: vr256x, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # AVX2:                %2 = VPADDDYrr %0, %1
 #
 # AVX512VL:            %2 = VPADDDZ256rr %0, %1
 #

 ...
 ---
 name:            test_add_v4i64
 # ALL-LABEL: name:  test_add_v4i64
 alignment:       4
 legalized:       true
 regBankSelected: true
 # AVX2:            registers:
-# AVX2-NEXT:         - { id: 0, class: vr256 }
-# AVX2-NEXT:         - { id: 1, class: vr256 }
-# AVX2-NEXT:         - { id: 2, class: vr256 }
+# AVX2-NEXT:         - { id: 0, class: vr256, preferred-register: '' }
+# AVX2-NEXT:         - { id: 1, class: vr256, preferred-register: '' }
+# AVX2-NEXT:         - { id: 2, class: vr256, preferred-register: '' }
 #
 # AVX512VL:        registers:
-# AVX512VL-NEXT:     - { id: 0, class: vr256x }
-# AVX512VL-NEXT:     - { id: 1, class: vr256x }
-# AVX512VL-NEXT:     - { id: 2, class: vr256x }
+# AVX512VL-NEXT:     - { id: 0, class: vr256x, preferred-register: '' }
+# AVX512VL-NEXT:     - { id: 1, class: vr256x, preferred-register: '' }
+# AVX512VL-NEXT:     - { id: 2, class: vr256x, preferred-register: '' }
 #
 # AVX512BWVL:      registers:
-# AVX512BWVL-NEXT:   - { id: 0, class: vr256x }
-# AVX512BWVL-NEXT:   - { id: 1, class: vr256x }
-# AVX512BWVL-NEXT:   - { id: 2, class: vr256x }
+# AVX512BWVL-NEXT:   - { id: 0, class: vr256x, preferred-register: '' }
+# AVX512BWVL-NEXT:   - { id: 1, class: vr256x, preferred-register: '' }
+# AVX512BWVL-NEXT:   - { id: 2, class: vr256x, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # AVX2:                %2 = VPADDQYrr %0, %1
 #
 # AVX512VL:            %2 = VPADDQZ256rr %0, %1
 #

test/CodeGen/X86/GlobalISel/select-add-v512.mir

 ...
 ---
 name:            test_add_v64i8
 # ALL-LABEL: name:  test_add_v64i8
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: vr512 }
-# ALL-NEXT:   - { id: 1, class: vr512 }
-# ALL-NEXT:   - { id: 2, class: vr512 }
+# ALL-NEXT:   - { id: 0, class: vr512, preferred-register: '' }
+# ALL-NEXT:   - { id: 1, class: vr512, preferred-register: '' }
+# ALL-NEXT:   - { id: 2, class: vr512, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # ALL:          %2 = VPADDBZrr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %zmm0, %zmm1
 
     %0(<64 x s8>) = COPY %zmm0
     %1(<64 x s8>) = COPY %zmm1
     %2(<64 x s8>) = G_ADD %0, %1
     %zmm0 = COPY %2(<64 x s8>)
     RET 0, implicit %zmm0
 
 ...
 ---
 name:            test_add_v32i16
 # ALL-LABEL: name:  test_add_v32i16
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: vr512 }
-# ALL-NEXT:   - { id: 1, class: vr512 }
-# ALL-NEXT:   - { id: 2, class: vr512 }
+# ALL-NEXT:   - { id: 0, class: vr512, preferred-register: '' }
+# ALL-NEXT:   - { id: 1, class: vr512, preferred-register: '' }
+# ALL-NEXT:   - { id: 2, class: vr512, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # ALL:          %2 = VPADDWZrr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %zmm0, %zmm1
 
     %0(<32 x s16>) = COPY %zmm0
     %1(<32 x s16>) = COPY %zmm1
     %2(<32 x s16>) = G_ADD %0, %1
     %zmm0 = COPY %2(<32 x s16>)
     RET 0, implicit %zmm0
 
 ...
 ---
 name:            test_add_v16i32
 # ALL-LABEL: name:  test_add_v16i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: vr512 }
-# ALL-NEXT:   - { id: 1, class: vr512 }
-# ALL-NEXT:   - { id: 2, class: vr512 }
+# ALL-NEXT:   - { id: 0, class: vr512, preferred-register: '' }
+# ALL-NEXT:   - { id: 1, class: vr512, preferred-register: '' }
+# ALL-NEXT:   - { id: 2, class: vr512, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # ALL:          %2 = VPADDDZrr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %zmm0, %zmm1
 
     %0(<16 x s32>) = COPY %zmm0
     %1(<16 x s32>) = COPY %zmm1
     %2(<16 x s32>) = G_ADD %0, %1
     %zmm0 = COPY %2(<16 x s32>)
     RET 0, implicit %zmm0
 
 ...
 ---
 name:            test_add_v8i64
 # ALL-LABEL: name:  test_add_v8i64
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: vr512 }
-# ALL-NEXT:   - { id: 1, class: vr512 }
-# ALL-NEXT:   - { id: 2, class: vr512 }
+# ALL-NEXT:   - { id: 0, class: vr512, preferred-register: '' }
+# ALL-NEXT:   - { id: 1, class: vr512, preferred-register: '' }
+# ALL-NEXT:   - { id: 2, class: vr512, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # ALL:          %2 = VPADDQZrr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %zmm0, %zmm1
 
     %0(<8 x s64>) = COPY %zmm0
     %1(<8 x s64>) = COPY %zmm1
     %2(<8 x s64>) = G_ADD %0, %1
     %zmm0 = COPY %2(<8 x s64>)
     RET 0, implicit %zmm0
 
 ...

test/CodeGen/X86/GlobalISel/select-add-x32.mir

 # RUN: llc -mtriple=i386-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=X32
 --- |
   define i64 @test_add_i64(i64 %a, i64 %b) {
     %r = add i64 %a, %b
     ret i64 %r
   }
 
 ...
 ---
 name:            test_add_i64
 # X32-LABEL: name:  test_add_i64
 alignment:       4
 legalized:       true
 regBankSelected: true
 # X32:      registers:
-# X32-NEXT:   - { id: 0, class: gr32 }
-# X32-NEXT:   - { id: 1, class: gr32 }
-# X32-NEXT:   - { id: 2, class: gr32 }
-# X32-NEXT:   - { id: 3, class: gr32 }
-# X32-NEXT:   - { id: 4, class: gpr }
-# X32-NEXT:   - { id: 5, class: gr32 }
-# X32-NEXT:   - { id: 6, class: gr32 }
-# X32-NEXT:   - { id: 7, class: gr32 }
-# X32-NEXT:   - { id: 8, class: gr32 }
-# X32-NEXT:   - { id: 9, class: gpr }
+# X32-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
+# X32-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
+# X32-NEXT:   - { id: 2, class: gr32, preferred-register: '' }
+# X32-NEXT:   - { id: 3, class: gr32, preferred-register: '' }
+# X32-NEXT:   - { id: 4, class: gpr, preferred-register: '' }
+# X32-NEXT:   - { id: 5, class: gr32, preferred-register: '' }
+# X32-NEXT:   - { id: 6, class: gr32, preferred-register: '' }
+# X32-NEXT:   - { id: 7, class: gr32, preferred-register: '' }
+# X32-NEXT:   - { id: 8, class: gr32, preferred-register: '' }
+# X32-NEXT:   - { id: 9, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
   - { id: 4, class: gpr }
   - { id: 5, class: gpr }
   - { id: 6, class: gpr }

test/CodeGen/X86/GlobalISel/select-add.mir

 ...
 
 ---
 name:            test_add_i64
 # ALL-LABEL: name:            test_add_i64
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:  - { id: 0, class: gr64 }
-# ALL-NEXT:  - { id: 1, class: gr64 }
-# ALL-NEXT:  - { id: 2, class: gr64 }
+# ALL-NEXT:  - { id: 0, class: gr64, preferred-register: '' }
+# ALL-NEXT:  - { id: 1, class: gr64, preferred-register: '' }
+# ALL-NEXT:  - { id: 2, class: gr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 # ALL:      %0 = COPY %rdi
 # ALL-NEXT: %1 = COPY %rsi
 # ALL-NEXT: %2 = ADD64rr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %edi, %esi
 
     %0(s64) = COPY %rdi
     %1(s64) = COPY %rsi
     %2(s64) = G_ADD %0, %1
     %rax = COPY %2(s64)
 
 ...
 
 ---
 name:            test_add_i32
 # ALL-LABEL: name:            test_add_i32
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:  - { id: 0, class: gr32 }
-# ALL-NEXT:  - { id: 1, class: gr32 }
-# ALL-NEXT:  - { id: 2, class: gr32 }
+# ALL-NEXT:  - { id: 0, class: gr32, preferred-register: '' }
+# ALL-NEXT:  - { id: 1, class: gr32, preferred-register: '' }
+# ALL-NEXT:  - { id: 2, class: gr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 # ALL:      %0 = COPY %edi
 # ALL-NEXT: %1 = COPY %esi
 # ALL-NEXT: %2 = ADD32rr %0, %1
 body:             |

 ---
 name:            test_add_i16
 # ALL-LABEL: name:            test_add_i16
 alignment:       4
 legalized:       true
 regBankSelected: true
 selected:        false
 # ALL:      registers:
-# ALL-NEXT:  - { id: 0, class: gr16 }
-# ALL-NEXT:  - { id: 1, class: gr16 }
-# ALL-NEXT:  - { id: 2, class: gr16 }
+# ALL-NEXT:  - { id: 0, class: gr16, preferred-register: '' }
+# ALL-NEXT:  - { id: 1, class: gr16, preferred-register: '' }
+# ALL-NEXT:  - { id: 2, class: gr16, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 # ALL: %0 = COPY %di
 # ALL: %1 = COPY %si
 # ALL: %2 = ADD16rr %0, %1, implicit-def %eflags
 body:             |

 ---
 name:            test_add_i8
 # ALL-LABEL: name:            test_add_i8
 alignment:       4
 legalized:       true
 regBankSelected: true
 selected:        false
 # ALL:      registers:
-# ALL-NEXT:  - { id: 0, class: gr8 }
-# ALL-NEXT:  - { id: 1, class: gr8 }
-# ALL-NEXT:  - { id: 2, class: gr8 }
+# ALL-NEXT:  - { id: 0, class: gr8, preferred-register: '' }
+# ALL-NEXT:  - { id: 1, class: gr8, preferred-register: '' }
+# ALL-NEXT:  - { id: 2, class: gr8, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 # ALL: %0 = COPY %dil
 # ALL: %1 = COPY %sil
 # ALL: %2 = ADD8rr %0, %1, implicit-def %eflags
 body:             |

 name:            test_add_float
 # ALL-LABEL: name:            test_add_float
 alignment:       4
 legalized:       true
 regBankSelected: true
 selected:        false
 tracksRegLiveness: true
 # ALL: registers:
-# NO_AVX512F-NEXT:  - { id: 0, class: fr32 }
-# NO_AVX512F-NEXT:  - { id: 1, class: fr32 }
-# NO_AVX512F-NEXT:  - { id: 2, class: fr32 }
-# AVX512ALL-NEXT:  - { id: 0, class: fr32x }
-# AVX512ALL-NEXT:  - { id: 1, class: fr32x }
-# AVX512ALL-NEXT:  - { id: 2, class: fr32x }
+# NO_AVX512F-NEXT:  - { id: 0, class: fr32, preferred-register: '' }
+# NO_AVX512F-NEXT:  - { id: 1, class: fr32, preferred-register: '' }
+# NO_AVX512F-NEXT:  - { id: 2, class: fr32, preferred-register: '' }
+# AVX512ALL-NEXT:  - { id: 0, class: fr32x, preferred-register: '' }
+# AVX512ALL-NEXT:  - { id: 1, class: fr32x, preferred-register: '' }
+# AVX512ALL-NEXT:  - { id: 2, class: fr32x, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # ALL:          %0 = COPY %xmm0
 # ALL-NEXT:     %1 = COPY %xmm1
 # SSE-NEXT:     %2 = ADDSSrr %0, %1
 # AVX-NEXT:     %2 = VADDSSrr %0, %1

 name:            test_add_double
 # ALL-LABEL: name:            test_add_double
 alignment:       4
 legalized:       true
 regBankSelected: true
 selected:        false
 tracksRegLiveness: true
 # ALL: registers:
-# NO_AVX512F-NEXT:  - { id: 0, class: fr64 }
-# NO_AVX512F-NEXT:  - { id: 1, class: fr64 }
-# NO_AVX512F-NEXT:  - { id: 2, class: fr64 }
-# AVX512ALL-NEXT:  - { id: 0, class: fr64x }
-# AVX512ALL-NEXT:  - { id: 1, class: fr64x }
-# AVX512ALL-NEXT:  - { id: 2, class: fr64x }
+# NO_AVX512F-NEXT:  - { id: 0, class: fr64, preferred-register: '' }
+# NO_AVX512F-NEXT:  - { id: 1, class: fr64, preferred-register: '' }
+# NO_AVX512F-NEXT:  - { id: 2, class: fr64, preferred-register: '' }
+# AVX512ALL-NEXT:  - { id: 0, class: fr64x, preferred-register: '' }
+# AVX512ALL-NEXT:  - { id: 1, class: fr64x, preferred-register: '' }
+# AVX512ALL-NEXT:  - { id: 2, class: fr64x, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # ALL:          %0 = COPY %xmm0
 # ALL-NEXT:     %1 = COPY %xmm1
 # SSE-NEXT:     %2 = ADDSDrr %0, %1
 # AVX-NEXT:     %2 = VADDSDrr %0, %1

 name:            test_add_v4i32
 # ALL-LABEL: name:            test_add_v4i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 selected:        false
 tracksRegLiveness: true
 # ALL: registers:
-# NO_AVX512VL-NEXT:  - { id: 0, class: vr128 }
-# NO_AVX512VL-NEXT:  - { id: 1, class: vr128 }
-# NO_AVX512VL-NEXT:  - { id: 2, class: vr128 }
-# AVX512VL-NEXT:  - { id: 0, class: vr128x }
-# AVX512VL-NEXT:  - { id: 1, class: vr128x }
-# AVX512VL-NEXT:  - { id: 2, class: vr128x }
+# NO_AVX512VL-NEXT:  - { id: 0, class: vr128, preferred-register: '' }
+# NO_AVX512VL-NEXT:  - { id: 1, class: vr128, preferred-register: '' }
+# NO_AVX512VL-NEXT:  - { id: 2, class: vr128, preferred-register: '' }
+# AVX512VL-NEXT:  - { id: 0, class: vr128x, preferred-register: '' }
+# AVX512VL-NEXT:  - { id: 1, class: vr128x, preferred-register: '' }
+# AVX512VL-NEXT:  - { id: 2, class: vr128x, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # ALL:           %0 = COPY %xmm0
 # ALL-NEXT:      %1 = COPY %xmm1
 # SSE-NEXT:      %2 = PADDDrr %0, %1
 # AVX-NEXT:      %2 = VPADDDrr %0, %1

 name:            test_add_v4f32
 # ALL-LABEL: name:            test_add_v4f32
 alignment:       4
 legalized:       true
 regBankSelected: true
 selected:        false
 tracksRegLiveness: true
 # ALL: registers:
-# NO_AVX512VL-NEXT:  - { id: 0, class: vr128 }
-# NO_AVX512VL-NEXT:  - { id: 1, class: vr128 }
-# NO_AVX512VL-NEXT:  - { id: 2, class: vr128 }
-# AVX512VL-NEXT:  - { id: 0, class: vr128x }
-# AVX512VL-NEXT:  - { id: 1, class: vr128x }
-# AVX512VL-NEXT:  - { id: 2, class: vr128x }
+# NO_AVX512VL-NEXT:  - { id: 0, class: vr128, preferred-register: '' }
+# NO_AVX512VL-NEXT:  - { id: 1, class: vr128, preferred-register: '' }
+# NO_AVX512VL-NEXT:  - { id: 2, class: vr128, preferred-register: '' }
+# AVX512VL-NEXT:  - { id: 0, class: vr128x, preferred-register: '' }
+# AVX512VL-NEXT:  - { id: 1, class: vr128x, preferred-register: '' }
+# AVX512VL-NEXT:  - { id: 2, class: vr128x, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # ALL:           %0 = COPY %xmm0
 # ALL-NEXT:      %1 = COPY %xmm1
 # SSE-NEXT:      %2 = ADDPSrr %0, %1
 # AVX-NEXT:      %2 = VADDPSrr %0, %1

test/CodeGen/X86/GlobalISel/select-cmp.mir

 ...
 ---
 name:            test_icmp_eq_i8
 # CHECK-LABEL: name:  test_icmp_eq_i8
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gr8 }
-# CHECK-NEXT:   - { id: 1, class: gr8 }
-# CHECK-NEXT:   - { id: 2, class: gr8 }
-# CHECK-NEXT:   - { id: 3, class: gr32 }
-# CHECK-NEXT:   - { id: 4, class: gr32 }
+# CHECK-NEXT:   - { id: 0, class: gr8, preferred-register: '' }
+# CHECK-NEXT:   - { id: 1, class: gr8, preferred-register: '' }
+# CHECK-NEXT:   - { id: 2, class: gr8, preferred-register: '' }
+# CHECK-NEXT:   - { id: 3, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 4, class: gr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 # CHECK:          %0 = COPY %dil
 # CHECK-NEXT:     %1 = COPY %sil
 # CHECK-NEXT:     CMP8rr %0, %1, implicit-def %eflags

 ...
 ---
 name:            test_icmp_eq_i16
 # CHECK-LABEL: name:  test_icmp_eq_i16
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gr16 }
-# CHECK-NEXT:   - { id: 1, class: gr16 }
-# CHECK-NEXT:   - { id: 2, class: gr8 }
-# CHECK-NEXT:   - { id: 3, class: gr32 }
-# CHECK-NEXT:   - { id: 4, class: gr32 }
+# CHECK-NEXT:   - { id: 0, class: gr16, preferred-register: '' }
+# CHECK-NEXT:   - { id: 1, class: gr16, preferred-register: '' }
+# CHECK-NEXT:   - { id: 2, class: gr8, preferred-register: '' }
+# CHECK-NEXT:   - { id: 3, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 4, class: gr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 # CHECK:          %0 = COPY %di
 # CHECK-NEXT:     %1 = COPY %si
 # CHECK-NEXT:     CMP16rr %0, %1, implicit-def %eflags

 ...
 ---
 name:            test_icmp_eq_i64
 # CHECK-LABEL: name:  test_icmp_eq_i64
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gr64 }
-# CHECK-NEXT:   - { id: 1, class: gr64 }
-# CHECK-NEXT:   - { id: 2, class: gr8 }
-# CHECK-NEXT:   - { id: 3, class: gr32 }
-# CHECK-NEXT:   - { id: 4, class: gr32 }
+# CHECK-NEXT:   - { id: 0, class: gr64, preferred-register: '' }
+# CHECK-NEXT:   - { id: 1, class: gr64, preferred-register: '' }
+# CHECK-NEXT:   - { id: 2, class: gr8, preferred-register: '' }
+# CHECK-NEXT:   - { id: 3, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 4, class: gr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 # CHECK:          %0 = COPY %rdi
 # CHECK-NEXT:     %1 = COPY %rsi
 # CHECK-NEXT:     CMP64rr %0, %1, implicit-def %eflags

 ...
 ---
 name:            test_icmp_eq_i32
 # CHECK-LABEL: name:  test_icmp_eq_i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gr32 }
-# CHECK-NEXT:   - { id: 1, class: gr32 }
-# CHECK-NEXT:   - { id: 2, class: gr8 }
-# CHECK-NEXT:   - { id: 3, class: gr32 }
-# CHECK-NEXT:   - { id: 4, class: gr32 }
+# CHECK-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 2, class: gr8, preferred-register: '' }
+# CHECK-NEXT:   - { id: 3, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 4, class: gr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 # CHECK:          %0 = COPY %edi
 # CHECK-NEXT:     %1 = COPY %esi
 # CHECK-NEXT:     CMP32rr %0, %1, implicit-def %eflags

 ...
 ---
 name:            test_icmp_ne_i32
 # CHECK-LABEL: name:  test_icmp_ne_i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gr32 }
-# CHECK-NEXT:   - { id: 1, class: gr32 }
-# CHECK-NEXT:   - { id: 2, class: gr8 }
-# CHECK-NEXT:   - { id: 3, class: gr32 }
-# CHECK-NEXT:   - { id: 4, class: gr32 }
+# CHECK-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 2, class: gr8, preferred-register: '' }
+# CHECK-NEXT:   - { id: 3, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 4, class: gr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 # CHECK:          %0 = COPY %edi
 # CHECK-NEXT:     %1 = COPY %esi
 # CHECK-NEXT:     CMP32rr %0, %1, implicit-def %eflags

 ...
 ---
 name:            test_icmp_ugt_i32
 # CHECK-LABEL: name:  test_icmp_ugt_i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gr32 }
-# CHECK-NEXT:   - { id: 1, class: gr32 }
-# CHECK-NEXT:   - { id: 2, class: gr8 }
-# CHECK-NEXT:   - { id: 3, class: gr32 }
-# CHECK-NEXT:   - { id: 4, class: gr32 }
+# CHECK-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 2, class: gr8, preferred-register: '' }
+# CHECK-NEXT:   - { id: 3, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 4, class: gr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 # CHECK:          %0 = COPY %edi
 # CHECK-NEXT:     %1 = COPY %esi
 # CHECK-NEXT:     CMP32rr %0, %1, implicit-def %eflags

 ...
 ---
 name:            test_icmp_uge_i32
 # CHECK-LABEL: name:  test_icmp_uge_i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gr32 }
-# CHECK-NEXT:   - { id: 1, class: gr32 }
-# CHECK-NEXT:   - { id: 2, class: gr8 }
-# CHECK-NEXT:   - { id: 3, class: gr32 }
-# CHECK-NEXT:   - { id: 4, class: gr32 }
+# CHECK-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 2, class: gr8, preferred-register: '' }
+# CHECK-NEXT:   - { id: 3, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 4, class: gr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 # CHECK:          %0 = COPY %edi
 # CHECK-NEXT:     %1 = COPY %esi
 # CHECK-NEXT:     CMP32rr %0, %1, implicit-def %eflags

 ...
 ---
 name:            test_icmp_ult_i32
 # CHECK-LABEL: name:  test_icmp_ult_i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gr32 }
-# CHECK-NEXT:   - { id: 1, class: gr32 }
-# CHECK-NEXT:   - { id: 2, class: gr8 }
-# CHECK-NEXT:   - { id: 3, class: gr32 }
-# CHECK-NEXT:   - { id: 4, class: gr32 }
+# CHECK-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 2, class: gr8, preferred-register: '' }
+# CHECK-NEXT:   - { id: 3, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 4, class: gr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 # CHECK:          %0 = COPY %edi
 # CHECK-NEXT:     %1 = COPY %esi
 # CHECK-NEXT:     CMP32rr %0, %1, implicit-def %eflags

 ...
 ---
 name:            test_icmp_ule_i32
 # CHECK-LABEL: name:  test_icmp_ule_i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gr32 }
-# CHECK-NEXT:   - { id: 1, class: gr32 }
-# CHECK-NEXT:   - { id: 2, class: gr8 }
-# CHECK-NEXT:   - { id: 3, class: gr32 }
-# CHECK-NEXT:   - { id: 4, class: gr32 }
+# CHECK-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 2, class: gr8, preferred-register: '' }
+# CHECK-NEXT:   - { id: 3, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 4, class: gr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 # CHECK:          %0 = COPY %edi
 # CHECK-NEXT:     %1 = COPY %esi
 # CHECK-NEXT:     CMP32rr %0, %1, implicit-def %eflags

 ...
 ---
 name:            test_icmp_sgt_i32
 # CHECK-LABEL: name:  test_icmp_sgt_i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gr32 }
-# CHECK-NEXT:   - { id: 1, class: gr32 }
-# CHECK-NEXT:   - { id: 2, class: gr8 }
-# CHECK-NEXT:   - { id: 3, class: gr32 }
-# CHECK-NEXT:   - { id: 4, class: gr32 }
+# CHECK-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 2, class: gr8, preferred-register: '' }
+# CHECK-NEXT:   - { id: 3, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 4, class: gr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 # CHECK:          %0 = COPY %edi
 # CHECK-NEXT:     %1 = COPY %esi
 # CHECK-NEXT:     CMP32rr %0, %1, implicit-def %eflags

 ...
 ---
 name:            test_icmp_sge_i32
 # CHECK-LABEL: name:  test_icmp_sge_i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gr32 }
-# CHECK-NEXT:   - { id: 1, class: gr32 }
-# CHECK-NEXT:   - { id: 2, class: gr8 }
-# CHECK-NEXT:   - { id: 3, class: gr32 }
-# CHECK-NEXT:   - { id: 4, class: gr32 }
+# CHECK-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 2, class: gr8, preferred-register: '' }
+# CHECK-NEXT:   - { id: 3, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 4, class: gr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 # CHECK:          %0 = COPY %edi
 # CHECK-NEXT:     %1 = COPY %esi
 # CHECK-NEXT:     CMP32rr %0, %1, implicit-def %eflags

 ...
 ---
 name:            test_icmp_slt_i32
 # CHECK-LABEL: name:  test_icmp_slt_i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gr32 }
-# CHECK-NEXT:   - { id: 1, class: gr32 }
-# CHECK-NEXT:   - { id: 2, class: gr8 }
-# CHECK-NEXT:   - { id: 3, class: gr32 }
-# CHECK-NEXT:   - { id: 4, class: gr32 }
+# CHECK-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 2, class: gr8, preferred-register: '' }
+# CHECK-NEXT:   - { id: 3, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 4, class: gr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 # CHECK:          %0 = COPY %edi
 # CHECK-NEXT:     %1 = COPY %esi
 # CHECK-NEXT:     CMP32rr %0, %1, implicit-def %eflags

 ...
 ---
 name:            test_icmp_sle_i32
 # CHECK-LABEL: name:  test_icmp_sle_i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gr32 }
-# CHECK-NEXT:   - { id: 1, class: gr32 }
-# CHECK-NEXT:   - { id: 2, class: gr8 }
-# CHECK-NEXT:   - { id: 3, class: gr32 }
-# CHECK-NEXT:   - { id: 4, class: gr32 }
+# CHECK-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 2, class: gr8, preferred-register: '' }
+# CHECK-NEXT:   - { id: 3, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 4, class: gr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 # CHECK:          %0 = COPY %edi
 # CHECK-NEXT:     %1 = COPY %esi
 # CHECK-NEXT:     CMP32rr %0, %1, implicit-def %eflags

test/CodeGen/X86/GlobalISel/select-constant.mir

 ...
 ---
 name:            const_i8
 legalized:       true
 regBankSelected: true
 selected:        false
 # CHECK-LABEL: name:            const_i8
 # CHECK: registers:
-# CHECK-NEXT:  - { id: 0, class: gr8 }
+# CHECK-NEXT:  - { id: 0, class: gr8, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
 # CHECK:  body:
 # CHECK:    %0 = MOV8ri 2
 body:             |
   bb.1 (%ir-block.0):
     %0(s8) = G_CONSTANT i8 2
     %al = COPY %0(s8)
     RET 0, implicit %al
 
 ...
 ---
 name:            const_i16
 legalized:       true
 regBankSelected: true
 selected:        false
 # CHECK-LABEL: name:            const_i16
 # CHECK: registers:
-# CHECK-NEXT:  - { id: 0, class: gr16 }
+# CHECK-NEXT:  - { id: 0, class: gr16, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
 # CHECK:  body:
 # CHECK:    %0 = MOV16ri 3
 body:             |
   bb.1 (%ir-block.0):
     %0(s16) = G_CONSTANT i16 3
     %ax = COPY %0(s16)
     RET 0, implicit %ax
 
 ...
 ---
 name:            const_i32
 legalized:       true
 regBankSelected: true
 selected:        false
 # CHECK-LABEL: name:            const_i32
 # CHECK: registers:
-# CHECK-NEXT:  - { id: 0, class: gr32 }
+# CHECK-NEXT:  - { id: 0, class: gr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
 # CHECK:  body:
 # CHECK:    %0 = MOV32ri 4
 body:             |
   bb.1 (%ir-block.0):
     %0(s32) = G_CONSTANT i32 4
     %eax = COPY %0(s32)
     RET 0, implicit %eax
 
 ...
 ---
 name:            const_i64
 legalized:       true
 regBankSelected: true
 selected:        false
 # CHECK-LABEL: name:            const_i64
 # CHECK: registers:
-# CHECK-NEXT:  - { id: 0, class: gr64 }
+# CHECK-NEXT:  - { id: 0, class: gr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
 # CHECK:  body:
 # CHECK:    %0 = MOV64ri 68719476720
 body:             |
   bb.1 (%ir-block.0):
     %0(s64) = G_CONSTANT i64 68719476720
     %rax = COPY %0(s64)
     RET 0, implicit %rax
 
 ...
 ---
 name:            const_i64_u32
 alignment:       4
 legalized:       true
 regBankSelected: true
 selected:        false
 # CHECK-LABEL: name:            const_i64_u32
 # CHECK: registers:
-# CHECK-NEXT:  - { id: 0, class: gr64 }
+# CHECK-NEXT:  - { id: 0, class: gr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
 # CHECK:  body:
 # CHECK:    %0 = MOV64ri32 1879048192
 body:             |
   bb.1 (%ir-block.0):
     %0(s64) = G_CONSTANT i64 1879048192
     %rax = COPY %0(s64)
     RET 0, implicit %rax
 
 ...
 ---
 name:            const_i64_i32
 legalized:       true
 regBankSelected: true
 selected:        false
 # CHECK-LABEL: name:            const_i64_i32
 # CHECK: registers:
-# CHECK-NEXT:  - { id: 0, class: gr64 }
+# CHECK-NEXT:  - { id: 0, class: gr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
 # CHECK:  body:
 # CHECK:    %0 = MOV64ri32 -1
 body:             |
   bb.1 (%ir-block.0):
     %0(s64) = G_CONSTANT i64 -1
     %rax = COPY %0(s64)
     RET 0, implicit %rax
 
 ...

test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir

 ...
 ---
 name:            test_zext_i1
 # ALL-LABEL: name:  test_zext_i1
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: gr8 }
-# ALL-NEXT:   - { id: 1, class: gr8 }
-# ALL-NEXT:   - { id: 2, class: gr64 }
-# ALL-NEXT:   - { id: 3, class: gr64 }
+# ALL-NEXT:   - { id: 0, class: gr8, preferred-register: '' }
+# ALL-NEXT:   - { id: 1, class: gr8, preferred-register: '' }
+# ALL-NEXT:   - { id: 2, class: gr64, preferred-register: '' }
+# ALL-NEXT:   - { id: 3, class: gr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 # ALL:          %0 = COPY %dil
 # ALL-NEXT:     %1 = COPY %0
 # ALL-NEXT:     %3 = SUBREG_TO_REG 0, %1, 1
 # ALL-NEXT:     %2 = AND64ri8 %3, 1, implicit-def %eflags

 ...
 ---
 name:            test_sext_i8
 # ALL-LABEL: name:  test_sext_i8
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: gr8 }
-# ALL-NEXT:   - { id: 1, class: gr64 }
+# ALL-NEXT:   - { id: 0, class: gr8, preferred-register: '' }
+# ALL-NEXT:   - { id: 1, class: gr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 # ALL:          %0 = COPY %dil
 # ALL-NEXT:     %1 = MOVSX64rr8 %0
 # ALL-NEXT:     %rax = COPY %1
 # ALL-NEXT:     RET 0, implicit %rax
 body:             |
   bb.1 (%ir-block.0):
     liveins: %edi
 
     %0(s8) = COPY %edi
     %1(s64) = G_SEXT %0(s8)
     %rax = COPY %1(s64)
     RET 0, implicit %rax
 
 ...
 ---
 name:            test_sext_i16
 # ALL-LABEL: name:  test_sext_i16
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: gr16 }
-# ALL-NEXT:   - { id: 1, class: gr64 }
+# ALL-NEXT:   - { id: 0, class: gr16, preferred-register: '' }
+# ALL-NEXT:   - { id: 1, class: gr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 # ALL:          %0 = COPY %di
 # ALL-NEXT:     %1 = MOVSX64rr16 %0
 # ALL-NEXT:     %rax = COPY %1
 # ALL-NEXT:     RET 0, implicit %rax
 body:             |

test/CodeGen/X86/GlobalISel/select-ext.mir

 ...
 ---
 name:            test_zext_i1
 # ALL-LABEL: name:  test_zext_i1
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: gr8 }
-# ALL-NEXT:   - { id: 1, class: gr32 }
-# ALL-NEXT:   - { id: 2, class: gr32 }
+# ALL-NEXT:   - { id: 0, class: gr8, preferred-register: '' }
+# ALL-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
+# ALL-NEXT:   - { id: 2, class: gr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 # ALL:          %0 = COPY %dil
 # ALL-NEXT:     %2 = SUBREG_TO_REG 0, %0, 1
 # ALL-NEXT:     %1 = AND32ri8 %2, 1, implicit-def %eflags
 # ALL-NEXT:     %eax = COPY %1
 # ALL-NEXT:     RET 0, implicit %eax

 ...
 ---
 name:            test_zext_i8
 # ALL-LABEL: name:  test_zext_i8
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: gr8 }
-# ALL-NEXT:   - { id: 1, class: gr32 }
+# ALL-NEXT:   - { id: 0, class: gr8, preferred-register: '' }
+# ALL-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 # ALL:          %0 = COPY %dil
 # ALL-NEXT:     %1 = MOVZX32rr8 %0
 # ALL-NEXT:     %eax = COPY %1
 # ALL-NEXT:     RET 0, implicit %eax
 body:             |
   bb.1 (%ir-block.0):
     liveins: %edi
 
     %0(s8) = COPY %edi
     %1(s32) = G_ZEXT %0(s8)
     %eax = COPY %1(s32)
     RET 0, implicit %eax
 
 ...
 ---
 name:            test_zext_i16
 # ALL-LABEL: name:  test_zext_i16
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: gr16 }
-# ALL-NEXT:   - { id: 1, class: gr32 }
+# ALL-NEXT:   - { id: 0, class: gr16, preferred-register: '' }
+# ALL-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 # ALL:          %0 = COPY %di
 # ALL-NEXT:     %1 = MOVZX32rr16 %0
 # ALL-NEXT:     %eax = COPY %1
 # ALL-NEXT:     RET 0, implicit %eax
 body:             |
   bb.1 (%ir-block.0):
     liveins: %edi
 
     %0(s16) = COPY %edi
     %1(s32) = G_ZEXT %0(s16)
     %eax = COPY %1(s32)
     RET 0, implicit %eax
 
 ...
 ---
 name:            test_sext_i8
 # ALL-LABEL: name:  test_sext_i8
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: gr8 }
-# ALL-NEXT:   - { id: 1, class: gr32 }
+# ALL-NEXT:   - { id: 0, class: gr8, preferred-register: '' }
+# ALL-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 # ALL:          %0 = COPY %dil
 # ALL-NEXT:     %1 = MOVSX32rr8 %0
 # ALL-NEXT:     %eax = COPY %1
 # ALL-NEXT:     RET 0, implicit %eax
 body:             |
   bb.1 (%ir-block.0):
     liveins: %edi
 
     %0(s8) = COPY %edi
     %1(s32) = G_SEXT %0(s8)
     %eax = COPY %1(s32)
     RET 0, implicit %eax
 
 ...
 ---
 name:            test_sext_i16
 # ALL-LABEL: name:  test_sext_i16
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: gr16 }
-# ALL-NEXT:   - { id: 1, class: gr32 }
+# ALL-NEXT:   - { id: 0, class: gr16, preferred-register: '' }
+# ALL-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 # ALL:          %0 = COPY %di
 # ALL-NEXT:     %1 = MOVSX32rr16 %0
 # ALL-NEXT:     %eax = COPY %1
 # ALL-NEXT:     RET 0, implicit %eax
 body:             |

test/CodeGen/X86/GlobalISel/select-gep.mir

 # RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK
 
 --- |
   define i32* @test_gep_i32(i32* %arr) {
     %arrayidx = getelementptr i32, i32* %arr, i32 5
     ret i32* %arrayidx
   }
 ...
 ---
 name:            test_gep_i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 selected:        false
 # CHECK-LABEL: name:            test_gep_i32
 # CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gr64 }
-# CHECK-NEXT: - { id: 1, class: gr64_nosp }
-# CHECK-NEXT: - { id: 2, class: gr64 }
+# CHECK-NEXT: - { id: 0, class: gr64, preferred-register: '' }
+# CHECK-NEXT: - { id: 1, class: gr64_nosp, preferred-register: '' }
+# CHECK-NEXT: - { id: 2, class: gr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 # CHECK:  body:
 # CHECK:       %1 = MOV64ri32 20
 # CHECK-NEXT:  %2 = LEA64r %0, 1, %1, 0, _
 body:             |

test/CodeGen/X86/GlobalISel/select-inc.mir

 # RUN: llc -mtriple=x86_64-linux-gnu                     -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=ALL,INC
 # RUN: llc -mtriple=x86_64-linux-gnu -mattr=+slow-incdec -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=ALL,ADD
 
 --- |
   define i8 @test_add_i8(i8 %arg1) {
     %ret = add i8 %arg1, 1
     ret i8 %ret
   }
 ...
 
 ---
 name:            test_add_i8
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:  - { id: 0, class: gr8 }
-# INC-NEXT:  - { id: 1, class: gpr }
-# ADD-NEXT:  - { id: 1, class: gr8 }
-# ALL-NEXT:  - { id: 2, class: gr8 }
+# ALL-NEXT:  - { id: 0, class: gr8, preferred-register: '' }
+# INC-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
+# ADD-NEXT:  - { id: 1, class: gr8, preferred-register: '' }
+# ALL-NEXT:  - { id: 2, class: gr8, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 # ALL:      %0 = COPY %al
 # INC-NEXT: %2 = INC8r %0
 # ADD-NEXT: %1 = MOV8ri 1
 # ADD-NEXT: %2 = ADD8rr %0, %1

test/CodeGen/X86/GlobalISel/select-leaf-constant.mir

 ...
 ---
 name:            const_i32_1
 legalized:       true
 regBankSelected: true
 selected:        false
 # CHECK-LABEL: name: const_i32_1
 # CHECK:       registers:
-# CHECK-NEXT:  - { id: 0, class: gr32 }
+# CHECK-NEXT:  - { id: 0, class: gr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
 # CHECK:  body:
 # CHECK:    %0 = MOV32ri 1
 body:             |
   bb.1 (%ir-block.0):
     %0(s32) = G_CONSTANT i32 1
     %eax = COPY %0(s32)
     RET 0, implicit %eax
 ...
 ---
 name:            const_i32_1_optsize
 legalized:       true
 regBankSelected: true
 selected:        false
 # CHECK-LABEL: name: const_i32_1_optsize
 # CHECK:       registers:
-# CHECK-NEXT:  - { id: 0, class: gr32 }
+# CHECK-NEXT:  - { id: 0, class: gr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
 # CHECK:  body:
 # CHECK:    %0 = MOV32r1
 body:             |
   bb.1 (%ir-block.0):
     %0(s32) = G_CONSTANT i32 1
     %eax = COPY %0(s32)
     RET 0, implicit %eax
 ...
 ---
 name:            const_i32_1b
 legalized:       true
 regBankSelected: true
 selected:        false
 # CHECK-LABEL: name: const_i32_1b
 # CHECK:       registers:
-# CHECK-NEXT:  - { id: 0, class: gr32 }
+# CHECK-NEXT:  - { id: 0, class: gr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
 # CHECK:  body:
 # CHECK:    %0 = MOV32ri 1
 body:             |
   bb.1 (%ir-block.0):
     %0(s32) = G_CONSTANT i32 1
     %eax = COPY %0(s32)
     RET 0, implicit %eax
 ...
 ---
 name:            const_i32_1_optsizeb
 legalized:       true
 regBankSelected: true
 selected:        false
 # CHECK-LABEL: name: const_i32_1_optsizeb
 # CHECK:       registers:
-# CHECK-NEXT:  - { id: 0, class: gr32 }
+# CHECK-NEXT:  - { id: 0, class: gr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
 # CHECK:  body:
 # CHECK:    %0 = MOV32r1
 body:             |
   bb.1 (%ir-block.0):
     %0(s32) = G_CONSTANT i32 1
     %eax = COPY %0(s32)
     RET 0, implicit %eax
 ...

test/CodeGen/X86/GlobalISel/select-memop-scalar-x32.mir

 ...
 ---
 name:            test_load_i8
 # ALL-LABEL: name:  test_load_i8
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: gr32 }
-# ALL-NEXT:   - { id: 1, class: gr32 }
-# ALL-NEXT:   - { id: 2, class: gr8 }
+# ALL-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
+# ALL-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
+# ALL-NEXT:   - { id: 2, class: gr8, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 fixedStack:
   - { id: 0, offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false }
 # ALL:          %1 = LEA32r %fixed-stack.0, 1, _, 0, _
 # ALL-NEXT:     %0 = MOV32rm %1, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0)

 ...
 ---
 name:            test_load_i16
 # ALL-LABEL: name:  test_load_i16
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: gr32 }
-# ALL-NEXT:   - { id: 1, class: gr32 }
-# ALL-NEXT:   - { id: 2, class: gr16 }
+# ALL-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
+# ALL-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
+# ALL-NEXT:   - { id: 2, class: gr16, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 fixedStack:
   - { id: 0, offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false }
 # ALL:          %1 = LEA32r %fixed-stack.0, 1, _, 0, _
 # ALL-NEXT:     %0 = MOV32rm %1, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0)

 ...
 ---
 name:            test_load_i32
 # ALL-LABEL: name:  test_load_i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: gr32 }
-# ALL-NEXT:   - { id: 1, class: gr32 }
-# ALL-NEXT:   - { id: 2, class: gr32 }
+# ALL-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
+# ALL-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
+# ALL-NEXT:   - { id: 2, class: gr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 fixedStack:
   - { id: 0, offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false }
 # ALL:          %1 = LEA32r %fixed-stack.0, 1, _, 0, _
 # ALL-NEXT:     %0 = MOV32rm %1, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0)

 ...
 ---
 name:            test_store_i8
 # ALL-LABEL: name:  test_store_i8
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: gr8 }
-# ALL-NEXT:   - { id: 1, class: gr32 }
-# ALL-NEXT:   - { id: 2, class: gr32 }
-# ALL-NEXT:   - { id: 3, class: gr32 }
+# ALL-NEXT:   - { id: 0, class: gr8, preferred-register: '' }
+# ALL-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
+# ALL-NEXT:   - { id: 2, class: gr32, preferred-register: '' }
+# ALL-NEXT:   - { id: 3, class: gr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 fixedStack:
   - { id: 0, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false }
   - { id: 1, offset: 0, size: 1, alignment: 16, isImmutable: true, isAliased: false }

 ...
 ---
 name:            test_store_i16
 # ALL-LABEL: name:  test_store_i16
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: gr16 }
-# ALL-NEXT:   - { id: 1, class: gr32 }
-# ALL-NEXT:   - { id: 2, class: gr32 }
-# ALL-NEXT:   - { id: 3, class: gr32 }
+# ALL-NEXT:   - { id: 0, class: gr16, preferred-register: '' }
+# ALL-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
+# ALL-NEXT:   - { id: 2, class: gr32, preferred-register: '' }
+# ALL-NEXT:   - { id: 3, class: gr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 fixedStack:
   - { id: 0, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false }
   - { id: 1, offset: 0, size: 2, alignment: 16, isImmutable: true, isAliased: false }

 ...
 ---
 name:            test_store_i32
 # ALL-LABEL: name:  test_store_i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: gr32 }
-# ALL-NEXT:   - { id: 1, class: gr32 }
-# ALL-NEXT:   - { id: 2, class: gr32 }
-# ALL-NEXT:   - { id: 3, class: gr32 }
+# ALL-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
+# ALL-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
+# ALL-NEXT:   - { id: 2, class: gr32, preferred-register: '' }
+# ALL-NEXT:   - { id: 3, class: gr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 fixedStack:
   - { id: 0, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false }
   - { id: 1, offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false }

 ...
 ---
 name:            test_load_ptr
 # ALL-LABEL: name:  test_load_ptr
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: gr32 }
-# ALL-NEXT:   - { id: 1, class: gr32 }
-# ALL-NEXT:   - { id: 2, class: gr32 }
+# ALL-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
+# ALL-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
+# ALL-NEXT:   - { id: 2, class: gr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 fixedStack:
   - { id: 0, offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false }
 # ALL:          %1 = LEA32r %fixed-stack.0, 1, _, 0, _
 # ALL-NEXT:     %0 = MOV32rm %1, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0)

 ...
 ---
 name:            test_store_ptr
 # ALL-LABEL: name:  test_store_ptr
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: gr32 }
-# ALL-NEXT:   - { id: 1, class: gr32 }
-# ALL-NEXT:   - { id: 2, class: gr32 }
-# ALL-NEXT:   - { id: 3, class: gr32 }
+# ALL-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
+# ALL-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
+# ALL-NEXT:   - { id: 2, class: gr32, preferred-register: '' }
+# ALL-NEXT:   - { id: 3, class: gr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 fixedStack:
   - { id: 0, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false }
   - { id: 1, offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false }

test/CodeGen/X86/GlobalISel/select-memop-scalar.mir

 ...
 ---
 # ALL-LABEL: name:            test_load_i8
 name:            test_load_i8
 alignment:       4
 legalized:       true
 regBankSelected: true
 registers:
-# ALL:   - { id: 0, class: gr64 }
-# ALL:   - { id: 1, class: gr8 }
+# ALL:   - { id: 0, class: gr64, preferred-register: '' }
+# ALL:   - { id: 1, class: gr8, preferred-register: '' }
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 # ALL:     %0 = COPY %rdi
 # ALL:     %1 = MOV8rm %0, 1, _, 0, _ :: (load 1 from %ir.p1)
 # ALL:     %al = COPY %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi
 
     %0(p0) = COPY %rdi
     %1(s8) = G_LOAD %0(p0) :: (load 1 from %ir.p1)
     %al = COPY %1(s8)
     RET 0, implicit %al
 
 ...
 ---
 # ALL-LABEL: name:            test_load_i16
 name:            test_load_i16
 alignment:       4
 legalized:       true
 regBankSelected: true
 registers:
-# ALL:   - { id: 0, class: gr64 }
-# ALL:   - { id: 1, class: gr16 }
+# ALL:   - { id: 0, class: gr64, preferred-register: '' }
+# ALL:   - { id: 1, class: gr16, preferred-register: '' }
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 # ALL:     %0 = COPY %rdi
 # ALL:     %1 = MOV16rm %0, 1, _, 0, _ :: (load 2 from %ir.p1)
 # ALL:     %ax = COPY %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi
 
     %0(p0) = COPY %rdi
     %1(s16) = G_LOAD %0(p0) :: (load 2 from %ir.p1)
     %ax = COPY %1(s16)
     RET 0, implicit %ax
 
 ...
 ---
 # ALL-LABEL: name:            test_load_i32
 name:            test_load_i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 registers:
-# ALL:   - { id: 0, class: gr64 }
-# ALL:   - { id: 1, class: gr32 }
+# ALL:   - { id: 0, class: gr64, preferred-register: '' }
+# ALL:   - { id: 1, class: gr32, preferred-register: '' }
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 # ALL:     %0 = COPY %rdi
 # ALL:     %1 = MOV32rm %0, 1, _, 0, _ :: (load 4 from %ir.p1)
 # ALL:     %eax = COPY %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi
 
     %0(p0) = COPY %rdi
     %1(s32) = G_LOAD %0(p0) :: (load 4 from %ir.p1)
     %eax = COPY %1(s32)
     RET 0, implicit %eax
 
 ...
 ---
 # ALL-LABEL: name:            test_load_i64
 name:            test_load_i64
 alignment:       4
 legalized:       true
 regBankSelected: true
 registers:
-# ALL:   - { id: 0, class: gr64 }
-# ALL:   - { id: 1, class: gr64 }
+# ALL:   - { id: 0, class: gr64, preferred-register: '' }
+# ALL:   - { id: 1, class: gr64, preferred-register: '' }
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 # ALL:     %0 = COPY %rdi
 # ALL:     %1 = MOV64rm %0, 1, _, 0, _ :: (load 8 from %ir.p1)
 # ALL:     %rax = COPY %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi
 
     %0(p0) = COPY %rdi
     %1(s64) = G_LOAD %0(p0) :: (load 8 from %ir.p1)
     %rax = COPY %1(s64)
     RET 0, implicit %rax
 
 ...
 ---
 # ALL-LABEL: name:            test_load_float
 name:            test_load_float
 alignment:       4
 legalized:       true
 regBankSelected: true
 registers:
-# ALL:   - { id: 0, class: gr64 }
-# ALL:   - { id: 1, class: gr32 }
+# ALL:   - { id: 0, class: gr64, preferred-register: '' }
+# ALL:   - { id: 1, class: gr32, preferred-register: '' }
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 # ALL:     %0 = COPY %rdi
 # ALL:     %1 = MOV32rm %0, 1, _, 0, _ :: (load 4 from %ir.p1)
 # ALL:     %xmm0 = COPY %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi
 
     %0(p0) = COPY %rdi
     %1(s32) = G_LOAD %0(p0) :: (load 4 from %ir.p1)
     %xmm0 = COPY %1(s32)
     RET 0, implicit %xmm0
 
 ...
 ---
 # ALL-LABEL: name:            test_load_float_vecreg
 name:            test_load_float_vecreg
 alignment:       4
 legalized:       true
 regBankSelected: true
 registers:
-# ALL:          - { id: 0, class: gr64 }
-# NO_AVX512F:   - { id: 1, class: fr32 }
-# AVX512ALL:    - { id: 1, class: fr32x }
+# ALL:          - { id: 0, class: gr64, preferred-register: '' }
+# NO_AVX512F:   - { id: 1, class: fr32, preferred-register: '' }
+# AVX512ALL:    - { id: 1, class: fr32x, preferred-register: '' }
   - { id: 0, class: gpr }
   - { id: 1, class: vecr }
 # ALL:       %0 = COPY %rdi
 # SSE:       %1 = MOVSSrm %0, 1, _, 0, _ :: (load 4 from %ir.p1)
 # AVX:       %1 = VMOVSSrm %0, 1, _, 0, _ :: (load 4 from %ir.p1)
 # AVX512ALL: %1 = VMOVSSZrm %0, 1, _, 0, _ :: (load 4 from %ir.p1)
 # ALL: %xmm0 = COPY %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi
 
     %0(p0) = COPY %rdi
     %1(s32) = G_LOAD %0(p0) :: (load 4 from %ir.p1)
     %xmm0 = COPY %1(s32)
     RET 0, implicit %xmm0
 
 ...
 ---
 # ALL-LABEL: name:            test_load_double
 name:            test_load_double
 alignment:       4
 legalized:       true
 regBankSelected: true
 registers:
-# ALL:   - { id: 0, class: gr64 }
-# ALL:   - { id: 1, class: gr64 }
+# ALL:   - { id: 0, class: gr64, preferred-register: '' }
+# ALL:   - { id: 1, class: gr64, preferred-register: '' }
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 # ALL:     %0 = COPY %rdi
 # ALL:     %1 = MOV64rm %0, 1, _, 0, _ :: (load 8 from %ir.p1)
 # ALL:     %xmm0 = COPY %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi
 
     %0(p0) = COPY %rdi
     %1(s64) = G_LOAD %0(p0) :: (load 8 from %ir.p1)
     %xmm0 = COPY %1(s64)
     RET 0, implicit %xmm0
 
 ...
 ---
 # ALL-LABEL: name:            test_load_double_vecreg
 name:            test_load_double_vecreg
 alignment:       4
 legalized:       true
 regBankSelected: true
 registers:
-# ALL:          - { id: 0, class: gr64 }
-# NO_AVX512F:   - { id: 1, class: fr64 }
-# AVX512ALL:    - { id: 1, class: fr64x }
+# ALL:          - { id: 0, class: gr64, preferred-register: '' }
+# NO_AVX512F:   - { id: 1, class: fr64, preferred-register: '' }
+# AVX512ALL:    - { id: 1, class: fr64x, preferred-register: '' }
   - { id: 0, class: gpr }
   - { id: 1, class: vecr }
 # ALL:       %0 = COPY %rdi
 # SSE:       %1 = MOVSDrm %0, 1, _, 0, _ :: (load 8 from %ir.p1)
 # AVX:       %1 = VMOVSDrm %0, 1, _, 0, _ :: (load 8 from %ir.p1)
 # AVX512ALL: %1 = VMOVSDZrm %0, 1, _, 0, _ :: (load 8 from %ir.p1)
 # ALL: %xmm0 = COPY %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi
 
     %0(p0) = COPY %rdi
     %1(s64) = G_LOAD %0(p0) :: (load 8 from %ir.p1)
     %xmm0 = COPY %1(s64)
     RET 0, implicit %xmm0
 
 ...
 ---
 # ALL-LABEL: name:            test_store_i32
 name:            test_store_i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 registers:
-# ALL:   - { id: 0, class: gr32 }
-# ALL:   - { id: 1, class: gr64 }
+# ALL:   - { id: 0, class: gr32, preferred-register: '' }
+# ALL:   - { id: 1, class: gr64, preferred-register: '' }
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 # ALL:     %0 = COPY %edi
 # ALL:     %1 = COPY %rsi
 # ALL:     MOV32mr %1, 1, _, 0, _, %0 :: (store 4 into %ir.p1)
 # ALL:     %rax = COPY %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %edi, %rsi
 
     %0(s32) = COPY %edi
     %1(p0) = COPY %rsi
     G_STORE %0(s32), %1(p0) :: (store 4 into %ir.p1)
     %rax = COPY %1(p0)
     RET 0, implicit %rax
 
 ...
 ---
 # ALL-LABEL: name:            test_store_i64
 name:            test_store_i64
 alignment:       4
 legalized:       true
 regBankSelected: true
 registers:
-# ALL:   - { id: 0, class: gr64 }
-# ALL:   - { id: 1, class: gr64 }
+# ALL:   - { id: 0, class: gr64, preferred-register: '' }
+# ALL:   - { id: 1, class: gr64, preferred-register: '' }
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 # ALL:     %0 = COPY %rdi
 # ALL:     %1 = COPY %rsi
 # ALL:     MOV64mr %1, 1, _, 0, _, %0 :: (store 8 into %ir.p1)
 # ALL:     %rax = COPY %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi, %rsi
 
     %0(s64) = COPY %rdi
     %1(p0) = COPY %rsi
     G_STORE %0(s64), %1(p0) :: (store 8 into %ir.p1)
     %rax = COPY %1(p0)
     RET 0, implicit %rax
 
 ...
 ---
 # ALL-LABEL: name:            test_store_float
 name:            test_store_float
 alignment:       4
 legalized:       true
 regBankSelected: true
 registers:
-# ALL:   - { id: 0, class: fr32x }
-# ALL:   - { id: 1, class: gr64 }
-# ALL:   - { id: 2, class: gr32 }
+# ALL:   - { id: 0, class: fr32x, preferred-register: '' }
+# ALL:   - { id: 1, class: gr64, preferred-register: '' }
+# ALL:   - { id: 2, class: gr32, preferred-register: '' }
   - { id: 0, class: vecr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 # ALL:     %0 = COPY %xmm0
 # ALL:     %1 = COPY %rdi
 # ALL:     %2 = COPY %0
 # ALL:     MOV32mr %1, 1, _, 0, _, %2 :: (store 4 into %ir.p1)
 # ALL:     %rax = COPY %1

 ...
 ---
 # ALL-LABEL: name:            test_store_float_vec
 name:            test_store_float_vec
 alignment:       4
 legalized:       true
 regBankSelected: true
 registers:
-# NO_AVX512F:   - { id: 0, class: fr32 }
-# AVX512ALL:    - { id: 0, class: fr32x }
-# ALL:   - { id: 1, class: gr64 }
+# NO_AVX512F:   - { id: 0, class: fr32, preferred-register: '' }
+# AVX512ALL:    - { id: 0, class: fr32x, preferred-register: '' }
+# ALL:   - { id: 1, class: gr64, preferred-register: '' }
   - { id: 0, class: vecr }
   - { id: 1, class: gpr }
 # ALL:       %0 = COPY %xmm0
 # ALL:       %1 = COPY %rdi
 # SSE:       MOVSSmr %1, 1, _, 0, _, %0 :: (store 4 into %ir.p1)
 # AVX:       VMOVSSmr %1, 1, _, 0, _, %0 :: (store 4 into %ir.p1)
 # AVX512ALL: VMOVSSZmr %1, 1, _, 0, _, %0 :: (store 4 into %ir.p1)
 # ALL:       %rax = COPY %1

 ...
 ---
 # ALL-LABEL: name:            test_store_double
 name:            test_store_double
 alignment:       4
 legalized:       true
 regBankSelected: true
 registers:
-# ALL:   - { id: 0, class: fr64x }
-# ALL:   - { id: 1, class: gr64 }
-# ALL:   - { id: 2, class: gr64 }
+# ALL:   - { id: 0, class: fr64x, preferred-register: '' }
+# ALL:   - { id: 1, class: gr64, preferred-register: '' }
+# ALL:   - { id: 2, class: gr64, preferred-register: '' }
   - { id: 0, class: vecr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 # ALL:     %0 = COPY %xmm0
 # ALL:     %1 = COPY %rdi
 # ALL:     %2 = COPY %0
 # ALL:     MOV64mr %1, 1, _, 0, _, %2 :: (store 8 into %ir.p1)
 # ALL:     %rax = COPY %1

 ...
 ---
 # ALL-LABEL: name:            test_store_double_vec
 name:            test_store_double_vec
 alignment:       4
 legalized:       true
 regBankSelected: true
 registers:
-# NO_AVX512F:   - { id: 0, class: fr64 }
-# AVX512ALL:    - { id: 0, class: fr64x }
-# ALL:   - { id: 1, class: gr64 }
+# NO_AVX512F:   - { id: 0, class: fr64, preferred-register: '' }
+# AVX512ALL:    - { id: 0, class: fr64x, preferred-register: '' }
+# ALL:   - { id: 1, class: gr64, preferred-register: '' }
   - { id: 0, class: vecr }
   - { id: 1, class: gpr }
 # ALL:       %0 = COPY %xmm0
 # ALL:       %1 = COPY %rdi
 # SSE:       MOVSDmr %1, 1, _, 0, _, %0 :: (store 8 into %ir.p1)
 # AVX:       VMOVSDmr %1, 1, _, 0, _, %0 :: (store 8 into %ir.p1)
 # AVX512ALL: VMOVSDZmr %1, 1, _, 0, _, %0 :: (store 8 into %ir.p1)
 # ALL:       %rax = COPY %1

 ---
 # ALL-LABEL: name:            test_load_ptr
 name:            test_load_ptr
 alignment:       4
 legalized:       true
 regBankSelected: true
 selected:        false
 registers:
-# ALL:   - { id: 0, class: gr64 }
-# ALL:   - { id: 1, class: gr64 }
+# ALL:   - { id: 0, class: gr64, preferred-register: '' }
+# ALL:   - { id: 1, class: gr64, preferred-register: '' }
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 # ALL: %1 = MOV64rm %0, 1, _, 0, _ :: (load 8 from %ir.ptr1)
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi
 
     %0(p0) = COPY %rdi
     %1(p0) = G_LOAD %0(p0) :: (load 8 from %ir.ptr1)
     %rax = COPY %1(p0)
     RET 0, implicit %rax
 
 ...
 ---
 # ALL-LABEL: name:            test_store_ptr
 name:            test_store_ptr
 alignment:       4
 legalized:       true
 regBankSelected: true
 selected:        false
 registers:
-# ALL:   - { id: 0, class: gr64 }
-# ALL:   - { id: 1, class: gr64 }
+# ALL:   - { id: 0, class: gr64, preferred-register: '' }
+# ALL:   - { id: 1, class: gr64, preferred-register: '' }
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 # ALL: MOV64mr %0, 1, _, 0, _, %1 :: (store 8 into %ir.ptr1)
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi, %rsi
 
     %0(p0) = COPY %rdi
     %1(p0) = COPY %rsi
     G_STORE %1(p0), %0(p0) :: (store 8 into %ir.ptr1)
     RET 0
 
 ...

test/CodeGen/X86/GlobalISel/select-memop-v128.mir

 ...
 ---
 # ALL-LABEL: name:            test_load_v4i32_noalign
 name:            test_load_v4i32_noalign
 alignment:       4
 legalized:       true
 regBankSelected: true
 registers:
-# ALL:          - { id: 0, class: gr64 }
-# NO_AVX512F:   - { id: 1, class: vr128 }
-# AVX512ALL:    - { id: 1, class: vr128x }
+# ALL:          - { id: 0, class: gr64, preferred-register: '' }
+# NO_AVX512F:   - { id: 1, class: vr128, preferred-register: '' }
+# AVX512ALL:    - { id: 1, class: vr128x, preferred-register: '' }
   - { id: 0, class: gpr }
   - { id: 1, class: vecr }
 # ALL:      %0 = COPY %rdi
 # SSE:      %1 = MOVUPSrm %0, 1, _, 0, _ :: (load 16 from %ir.p1, align 1)
 # AVX:      %1 = VMOVUPSrm %0, 1, _, 0, _ :: (load 16 from %ir.p1, align 1)
 # AVX512F:  %1 = VMOVUPSZ128rm_NOVLX %0, 1, _, 0, _ :: (load 16 from %ir.p1, align 1)
 # AVX512VL: %1 = VMOVUPSZ128rm %0, 1, _, 0, _ :: (load 16 from %ir.p1, align 1)
 # ALL: %xmm0 = COPY %1

 ...
 ---
 # ALL-LABEL: name:            test_load_v4i32_align
 name:            test_load_v4i32_align
 alignment:       4
 legalized:       true
 regBankSelected: true
 registers:
-# ALL:   - { id: 0, class: gr64 }
-# NO_AVX512F:   - { id: 1, class: vr128 }
-# AVX512ALL:    - { id: 1, class: vr128x }
+# ALL:   - { id: 0, class: gr64, preferred-register: '' }
+# NO_AVX512F:   - { id: 1, class: vr128, preferred-register: '' }
+# AVX512ALL:    - { id: 1, class: vr128x, preferred-register: '' }
   - { id: 0, class: gpr }
   - { id: 1, class: vecr }
 # ALL:      %0 = COPY %rdi
 # SSE:      %1 = MOVAPSrm %0, 1, _, 0, _ :: (load 16 from %ir.p1)
 # AVX:      %1 = VMOVAPSrm %0, 1, _, 0, _ :: (load 16 from %ir.p1)
 # AVX512F:  %1 = VMOVAPSZ128rm_NOVLX %0, 1, _, 0, _ :: (load 16 from %ir.p1)
 # AVX512VL: %1 = VMOVAPSZ128rm %0, 1, _, 0, _ :: (load 16 from %ir.p1)
 # ALL: %xmm0 = COPY %1

 ...
 ---
 # ALL-LABEL: name:            test_store_v4i32_align
 name:            test_store_v4i32_align
 alignment:       4
 legalized:       true
 regBankSelected: true
 registers:
-# NO_AVX512F:   - { id: 0, class: vr128 }
-# AVX512ALL:    - { id: 0, class: vr128x }
-# ALL:   - { id: 1, class: gr64 }
+# NO_AVX512F:   - { id: 0, class: vr128, preferred-register: '' }
+# AVX512ALL:    - { id: 0, class: vr128x, preferred-register: '' }
+# ALL:   - { id: 1, class: gr64, preferred-register: '' }
   - { id: 0, class: vecr }
   - { id: 1, class: gpr }
 # ALL:       %0 = COPY %xmm0
 # ALL:       %1 = COPY %rdi
 # SSE:       MOVAPSmr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1)
 # AVX:       VMOVAPSmr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1)
 # AVX512F:   VMOVAPSZ128mr_NOVLX %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1)
 # AVX512VL:  VMOVAPSZ128mr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1)

 ...
 ---
 # ALL-LABEL: name:            test_store_v4i32_noalign
 name:            test_store_v4i32_noalign
 alignment:       4
 legalized:       true
 regBankSelected: true
 registers:
-# NO_AVX512F:   - { id: 0, class: vr128 }
-# AVX512ALL:    - { id: 0, class: vr128x }
-# ALL:   - { id: 1, class: gr64 }
+# NO_AVX512F:   - { id: 0, class: vr128, preferred-register: '' }
+# AVX512ALL:    - { id: 0, class: vr128x, preferred-register: '' }
+# ALL:   - { id: 1, class: gr64, preferred-register: '' }
   - { id: 0, class: vecr }
   - { id: 1, class: gpr }
 # ALL:       %0 = COPY %xmm0
 # ALL:       %1 = COPY %rdi
 # SSE:       MOVUPSmr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1, align 1)
 # AVX:       VMOVUPSmr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1, align 1)
 # AVX512F:   VMOVUPSZ128mr_NOVLX %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1, align 1)
 # AVX512VL:  VMOVUPSZ128mr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1, align 1)

test/CodeGen/X86/GlobalISel/select-memop-v256.mir

 ...
 ---
 name:            test_load_v8i32_noalign
 # ALL-LABEL: name:  test_load_v8i32_noalign
 alignment:       4
 legalized:       true
 regBankSelected: true
 # NO_AVX512F:       registers:
-# NO_AVX512F-NEXT:    - { id: 0, class: gr64 }
-# NO_AVX512F-NEXT:    - { id: 1, class: vr256 }
+# NO_AVX512F-NEXT:    - { id: 0, class: gr64, preferred-register: '' }
+# NO_AVX512F-NEXT:    - { id: 1, class: vr256, preferred-register: '' }
 #
 # AVX512ALL:        registers:
-# AVX512ALL-NEXT:     - { id: 0, class: gr64 }
-# AVX512ALL-NEXT:     - { id: 1, class: vr256x }
+# AVX512ALL-NEXT:     - { id: 0, class: gr64, preferred-register: '' }
+# AVX512ALL-NEXT:     - { id: 1, class: vr256x, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: vecr }
 # NO_AVX512F:           %0 = COPY %rdi
 # NO_AVX512F-NEXT:      %1 = VMOVUPSYrm %0, 1, _, 0, _ :: (load 32 from %ir.p1, align 1)
 # NO_AVX512F-NEXT:      %ymm0 = COPY %1
 # NO_AVX512F-NEXT:      RET 0, implicit %ymm0
 #

 ...
 ---
 name:            test_load_v8i32_align
 # ALL-LABEL: name:  test_load_v8i32_align
 alignment:       4
 legalized:       true
 regBankSelected: true
 # NO_AVX512F:       registers:
-# NO_AVX512F-NEXT:    - { id: 0, class: gr64 }
-# NO_AVX512F-NEXT:    - { id: 1, class: vr256 }
+# NO_AVX512F-NEXT:    - { id: 0, class: gr64, preferred-register: '' }
+# NO_AVX512F-NEXT:    - { id: 1, class: vr256, preferred-register: '' }
 #
 # AVX512ALL:        registers:
-# AVX512ALL-NEXT:     - { id: 0, class: gr64 }
-# AVX512ALL-NEXT:     - { id: 1, class: vr256x }
+# AVX512ALL-NEXT:     - { id: 0, class: gr64, preferred-register: '' }
+# AVX512ALL-NEXT:     - { id: 1, class: vr256x, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: vecr }
 # NO_AVX512F:           %0 = COPY %rdi
 # NO_AVX512F-NEXT:      %1 = VMOVAPSYrm %0, 1, _, 0, _ :: (load 32 from %ir.p1)
 # NO_AVX512F-NEXT:      %ymm0 = COPY %1
 # NO_AVX512F-NEXT:      RET 0, implicit %ymm0
 #

 ...
 ---
 name:            test_store_v8i32_noalign
 # ALL-LABEL: name:  test_store_v8i32_noalign
 alignment:       4
 legalized:       true
 regBankSelected: true
 # NO_AVX512F:       registers:
-# NO_AVX512F-NEXT:    - { id: 0, class: vr256 }
-# NO_AVX512F-NEXT:    - { id: 1, class: gr64 }
+# NO_AVX512F-NEXT:    - { id: 0, class: vr256, preferred-register: '' }
+# NO_AVX512F-NEXT:    - { id: 1, class: gr64, preferred-register: '' }
 #
 # AVX512ALL:        registers:
-# AVX512ALL-NEXT:     - { id: 0, class: vr256x }
-# AVX512ALL-NEXT:     - { id: 1, class: gr64 }
+# AVX512ALL-NEXT:     - { id: 0, class: vr256x, preferred-register: '' }
+# AVX512ALL-NEXT:     - { id: 1, class: gr64, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: gpr }
 # NO_AVX512F:           %0 = COPY %ymm0
 # NO_AVX512F-NEXT:      %1 = COPY %rdi
 # NO_AVX512F-NEXT:      VMOVUPSYmr %1, 1, _, 0, _, %0 :: (store 32 into %ir.p1, align 1)
 # NO_AVX512F-NEXT:      RET 0
 #

 ...
 ---
 name:            test_store_v8i32_align
 # ALL-LABEL: name:  test_store_v8i32_align
 alignment:       4
 legalized:       true
 regBankSelected: true
 # NO_AVX512F:       registers:
-# NO_AVX512F-NEXT:    - { id: 0, class: vr256 }
-# NO_AVX512F-NEXT:    - { id: 1, class: gr64 }
+# NO_AVX512F-NEXT:    - { id: 0, class: vr256, preferred-register: '' }
+# NO_AVX512F-NEXT:    - { id: 1, class: gr64, preferred-register: '' }
 #
 # AVX512ALL:        registers:
-# AVX512ALL-NEXT:     - { id: 0, class: vr256x }
-# AVX512ALL-NEXT:     - { id: 1, class: gr64 }
+# AVX512ALL-NEXT:     - { id: 0, class: vr256x, preferred-register: '' }
+# AVX512ALL-NEXT:     - { id: 1, class: gr64, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: gpr }
 # NO_AVX512F:           %0 = COPY %ymm0
 # NO_AVX512F-NEXT:      %1 = COPY %rdi
 # NO_AVX512F-NEXT:      VMOVAPSYmr %1, 1, _, 0, _, %0 :: (store 32 into %ir.p1)
 # NO_AVX512F-NEXT:      RET 0
 #

test/CodeGen/X86/GlobalISel/select-memop-v512.mir

 ...
 ---
 name:            test_load_v16i32_noalign
 # AVX512F-LABEL: name:  test_load_v16i32_noalign
 alignment:       4
 legalized:       true
 regBankSelected: true
 # AVX512F:      registers:
-# AVX512F-NEXT:   - { id: 0, class: gr64 }
-# AVX512F-NEXT:   - { id: 1, class: vr512 }
+# AVX512F-NEXT:   - { id: 0, class: gr64, preferred-register: '' }
+# AVX512F-NEXT:   - { id: 1, class: vr512, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: vecr }
 # AVX512F:          %0 = COPY %rdi
 # AVX512F-NEXT:     %1 = VMOVUPSZrm %0, 1, _, 0, _ :: (load 64 from %ir.p1, align 1)
 # AVX512F-NEXT:     %zmm0 = COPY %1
 # AVX512F-NEXT:     RET 0, implicit %zmm0
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi
 
     %0(p0) = COPY %rdi
     %1(<16 x s32>) = G_LOAD %0(p0) :: (load 64 from %ir.p1, align 1)
     %zmm0 = COPY %1(<16 x s32>)
     RET 0, implicit %zmm0
 
 ...
 ---
 name:            test_load_v16i32_align
 # AVX512F-LABEL: name:  test_load_v16i32_align
 alignment:       4
 legalized:       true
 regBankSelected: true
 # AVX512F:      registers:
-# AVX512F-NEXT:   - { id: 0, class: gr64 }
-# AVX512F-NEXT:   - { id: 1, class: vr512 }
+# AVX512F-NEXT:   - { id: 0, class: gr64, preferred-register: '' }
+# AVX512F-NEXT:   - { id: 1, class: vr512, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: vecr }
 # AVX512F:          %0 = COPY %rdi
 # AVX512F-NEXT:     %1 = VMOVUPSZrm %0, 1, _, 0, _ :: (load 64 from %ir.p1, align 32)
 # AVX512F-NEXT:     %zmm0 = COPY %1
 # AVX512F-NEXT:     RET 0, implicit %zmm0
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi
 
     %0(p0) = COPY %rdi
     %1(<16 x s32>) = G_LOAD %0(p0) :: (load 64 from %ir.p1, align 32)
     %zmm0 = COPY %1(<16 x s32>)
     RET 0, implicit %zmm0
 
 ...
 ---
 name:            test_store_v16i32_noalign
 # AVX512F-LABEL: name:  test_store_v16i32_noalign
 alignment:       4
 legalized:       true
 regBankSelected: true
 # AVX512F:      registers:
-# AVX512F-NEXT:   - { id: 0, class: vr512 }
-# AVX512F-NEXT:   - { id: 1, class: gr64 }
+# AVX512F-NEXT:   - { id: 0, class: vr512, preferred-register: '' }
+# AVX512F-NEXT:   - { id: 1, class: gr64, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: gpr }
 # AVX512F:          %0 = COPY %zmm0
 # AVX512F-NEXT:     %1 = COPY %rdi
 # AVX512F-NEXT:     VMOVUPSZmr %1, 1, _, 0, _, %0 :: (store 64 into %ir.p1, align 1)
 # AVX512F-NEXT:     RET 0
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi, %zmm0
 
     %0(<16 x s32>) = COPY %zmm0
     %1(p0) = COPY %rdi
     G_STORE %0(<16 x s32>), %1(p0) :: (store 64 into %ir.p1, align 1)
     RET 0
 
 ...
 ---
 name:            test_store_v16i32_align
 # AVX512F-LABEL: name:  test_store_v16i32_align
 alignment:       4
 legalized:       true
 regBankSelected: true
 # AVX512F:      registers:
-# AVX512F-NEXT:   - { id: 0, class: vr512 }
-# AVX512F-NEXT:   - { id: 1, class: gr64 }
+# AVX512F-NEXT:   - { id: 0, class: vr512, preferred-register: '' }
+# AVX512F-NEXT:   - { id: 1, class: gr64, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: gpr }
 # AVX512F:          %0 = COPY %zmm0
 # AVX512F-NEXT:     %1 = COPY %rdi
 # AVX512F-NEXT:     VMOVUPSZmr %1, 1, _, 0, _, %0 :: (store 64 into %ir.p1, align 32)
 # AVX512F-NEXT:     RET 0
 body:             |

test/CodeGen/X86/GlobalISel/select-mul-scalar.mir

 ...
 ---
 name:            test_mul_i16
 # ALL-LABEL: name:  test_mul_i16
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: gr16 }
-# ALL-NEXT:   - { id: 1, class: gr16 }
-# ALL-NEXT:   - { id: 2, class: gr16 }
+# ALL-NEXT:   - { id: 0, class: gr16, preferred-register: '' }
+# ALL-NEXT:   - { id: 1, class: gr16, preferred-register: '' }
+# ALL-NEXT:   - { id: 2, class: gr16, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 # ALL:      body:             |
 # ALL:          %0 = COPY %di
 # ALL-NEXT:     %1 = COPY %si
 # ALL-NEXT:     %2 = IMUL16rr %0, %1, implicit-def %eflags

 ...
 ---
 name:            test_mul_i32
 # ALL-LABEL: name:  test_mul_i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: gr32 }
-# ALL-NEXT:   - { id: 1, class: gr32 }
-# ALL-NEXT:   - { id: 2, class: gr32 }
+# ALL-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
+# ALL-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
+# ALL-NEXT:   - { id: 2, class: gr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 # ALL:      body:             |
 # ALL:          %0 = COPY %edi
 # ALL-NEXT:     %1 = COPY %esi
 # ALL-NEXT:     %2 = IMUL32rr %0, %1, implicit-def %eflags

 ...
 ---
 name:            test_mul_i64
 # ALL-LABEL: name:  test_mul_i64
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: gr64 }
-# ALL-NEXT:   - { id: 1, class: gr64 }
-# ALL-NEXT:   - { id: 2, class: gr64 }
+# ALL-NEXT:   - { id: 0, class: gr64, preferred-register: '' }
+# ALL-NEXT:   - { id: 1, class: gr64, preferred-register: '' }
+# ALL-NEXT:   - { id: 2, class: gr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 # ALL:      body:             |
 # ALL:          %0 = COPY %rdi
 # ALL-NEXT:     %1 = COPY %rsi
 # ALL-NEXT:     %2 = IMUL64rr %0, %1, implicit-def %eflags

test/CodeGen/X86/GlobalISel/select-mul-vec.mir

 ...
 ---
 name:            test_mul_v8i16
 # CHECK-LABEL: name:  test_mul_v8i16
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: vr128 }
-# CHECK-NEXT:   - { id: 1, class: vr128 }
-# CHECK-NEXT:   - { id: 2, class: vr128 }
+# CHECK-NEXT:   - { id: 0, class: vr128, preferred-register: '' }
+# CHECK-NEXT:   - { id: 1, class: vr128, preferred-register: '' }
+# CHECK-NEXT:   - { id: 2, class: vr128, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # CHECK:          %2 = PMULLWrr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %xmm0, %xmm1
 
     %0(<8 x s16>) = COPY %xmm0
     %1(<8 x s16>) = COPY %xmm1
     %2(<8 x s16>) = G_MUL %0, %1
     %xmm0 = COPY %2(<8 x s16>)
     RET 0, implicit %xmm0
 
 ...
 ---
 name:            test_mul_v8i16_avx
 # CHECK-LABEL: name:  test_mul_v8i16_avx
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: vr128 }
-# CHECK-NEXT:   - { id: 1, class: vr128 }
-# CHECK-NEXT:   - { id: 2, class: vr128 }
+# CHECK-NEXT:   - { id: 0, class: vr128, preferred-register: '' }
+# CHECK-NEXT:   - { id: 1, class: vr128, preferred-register: '' }
+# CHECK-NEXT:   - { id: 2, class: vr128, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # CHECK:          %2 = VPMULLWrr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %xmm0, %xmm1
 
     %0(<8 x s16>) = COPY %xmm0
     %1(<8 x s16>) = COPY %xmm1
     %2(<8 x s16>) = G_MUL %0, %1
     %xmm0 = COPY %2(<8 x s16>)
     RET 0, implicit %xmm0
 
 ...
 ---
 name:            test_mul_v8i16_avx512bwvl
 # CHECK-LABEL: name:  test_mul_v8i16_avx512bwvl
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: vr128x }
-# CHECK-NEXT:   - { id: 1, class: vr128x }
-# CHECK-NEXT:   - { id: 2, class: vr128x }
+# CHECK-NEXT:   - { id: 0, class: vr128x, preferred-register: '' }
+# CHECK-NEXT:   - { id: 1, class: vr128x, preferred-register: '' }
+# CHECK-NEXT:   - { id: 2, class: vr128x, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # CHECK:          %2 = VPMULLWZ128rr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %xmm0, %xmm1
 
     %0(<8 x s16>) = COPY %xmm0
     %1(<8 x s16>) = COPY %xmm1
     %2(<8 x s16>) = G_MUL %0, %1
     %xmm0 = COPY %2(<8 x s16>)
     RET 0, implicit %xmm0
 
 ...
 ---
 name:            test_mul_v4i32
 # CHECK-LABEL: name:  test_mul_v4i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: vr128 }
-# CHECK-NEXT:   - { id: 1, class: vr128 }
-# CHECK-NEXT:   - { id: 2, class: vr128 }
+# CHECK-NEXT:   - { id: 0, class: vr128, preferred-register: '' }
+# CHECK-NEXT:   - { id: 1, class: vr128, preferred-register: '' }
+# CHECK-NEXT:   - { id: 2, class: vr128, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # CHECK:          %2 = PMULLDrr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %xmm0, %xmm1
 
     %0(<4 x s32>) = COPY %xmm0
     %1(<4 x s32>) = COPY %xmm1
     %2(<4 x s32>) = G_MUL %0, %1
     %xmm0 = COPY %2(<4 x s32>)
     RET 0, implicit %xmm0
 
 ...
 ---
 name:            test_mul_v4i32_avx
 # CHECK-LABEL: name:  test_mul_v4i32_avx
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: vr128 }
-# CHECK-NEXT:   - { id: 1, class: vr128 }
-# CHECK-NEXT:   - { id: 2, class: vr128 }
+# CHECK-NEXT:   - { id: 0, class: vr128, preferred-register: '' }
+# CHECK-NEXT:   - { id: 1, class: vr128, preferred-register: '' }
+# CHECK-NEXT:   - { id: 2, class: vr128, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # CHECK:          %2 = VPMULLDrr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %xmm0, %xmm1
 
     %0(<4 x s32>) = COPY %xmm0
     %1(<4 x s32>) = COPY %xmm1
     %2(<4 x s32>) = G_MUL %0, %1
     %xmm0 = COPY %2(<4 x s32>)
     RET 0, implicit %xmm0
 
 ...
 ---
 name:            test_mul_v4i32_avx512vl
 # CHECK-LABEL: name:  test_mul_v4i32_avx512vl
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: vr128x }
-# CHECK-NEXT:   - { id: 1, class: vr128x }
-# CHECK-NEXT:   - { id: 2, class: vr128x }
+# CHECK-NEXT:   - { id: 0, class: vr128x, preferred-register: '' }
+# CHECK-NEXT:   - { id: 1, class: vr128x, preferred-register: '' }
+# CHECK-NEXT:   - { id: 2, class: vr128x, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # CHECK:          %2 = VPMULLDZ128rr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %xmm0, %xmm1
 
     %0(<4 x s32>) = COPY %xmm0
     %1(<4 x s32>) = COPY %xmm1
     %2(<4 x s32>) = G_MUL %0, %1
     %xmm0 = COPY %2(<4 x s32>)
     RET 0, implicit %xmm0
 
 ...
 ---
 name:            test_mul_v2i64
 # CHECK-LABEL: name:  test_mul_v2i64
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: vr128x }
-# CHECK-NEXT:   - { id: 1, class: vr128x }
-# CHECK-NEXT:   - { id: 2, class: vr128x }
+# CHECK-NEXT:   - { id: 0, class: vr128x, preferred-register: '' }
+# CHECK-NEXT:   - { id: 1, class: vr128x, preferred-register: '' }
+# CHECK-NEXT:   - { id: 2, class: vr128x, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # CHECK:          %2 = VPMULLQZ128rr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %xmm0, %xmm1
 
     %0(<2 x s64>) = COPY %xmm0
     %1(<2 x s64>) = COPY %xmm1
     %2(<2 x s64>) = G_MUL %0, %1
     %xmm0 = COPY %2(<2 x s64>)
     RET 0, implicit %xmm0
 
 ...
 ---
 name:            test_mul_v16i16
 # CHECK-LABEL: name:  test_mul_v16i16
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: vr256 }
-# CHECK-NEXT:   - { id: 1, class: vr256 }
-# CHECK-NEXT:   - { id: 2, class: vr256 }
+# CHECK-NEXT:   - { id: 0, class: vr256, preferred-register: '' }
+# CHECK-NEXT:   - { id: 1, class: vr256, preferred-register: '' }
+# CHECK-NEXT:   - { id: 2, class: vr256, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # CHECK:          %2 = VPMULLWYrr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %ymm0, %ymm1
 
     %0(<16 x s16>) = COPY %ymm0
     %1(<16 x s16>) = COPY %ymm1
     %2(<16 x s16>) = G_MUL %0, %1
     %ymm0 = COPY %2(<16 x s16>)
     RET 0, implicit %ymm0
 
 ...
 ---
 name:            test_mul_v16i16_avx512bwvl
 # CHECK-LABEL: name:  test_mul_v16i16_avx512bwvl
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: vr256x }
-# CHECK-NEXT:   - { id: 1, class: vr256x }
-# CHECK-NEXT:   - { id: 2, class: vr256x }
+# CHECK-NEXT:   - { id: 0, class: vr256x, preferred-register: '' }
+# CHECK-NEXT:   - { id: 1, class: vr256x, preferred-register: '' }
+# CHECK-NEXT:   - { id: 2, class: vr256x, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # CHECK:          %2 = VPMULLWZ256rr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %ymm0, %ymm1
 
     %0(<16 x s16>) = COPY %ymm0
     %1(<16 x s16>) = COPY %ymm1
     %2(<16 x s16>) = G_MUL %0, %1
     %ymm0 = COPY %2(<16 x s16>)
     RET 0, implicit %ymm0
 
 ...
 ---
 name:            test_mul_v8i32
 # CHECK-LABEL: name:  test_mul_v8i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: vr256 }
-# CHECK-NEXT:   - { id: 1, class: vr256 }
-# CHECK-NEXT:   - { id: 2, class: vr256 }
+# CHECK-NEXT:   - { id: 0, class: vr256, preferred-register: '' }
+# CHECK-NEXT:   - { id: 1, class: vr256, preferred-register: '' }
+# CHECK-NEXT:   - { id: 2, class: vr256, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # CHECK:          %2 = VPMULLDYrr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %ymm0, %ymm1
 
     %0(<8 x s32>) = COPY %ymm0
     %1(<8 x s32>) = COPY %ymm1
     %2(<8 x s32>) = G_MUL %0, %1
     %ymm0 = COPY %2(<8 x s32>)
     RET 0, implicit %ymm0
 
 ...
 ---
 name:            test_mul_v8i32_avx512vl
 # CHECK-LABEL: name:  test_mul_v8i32_avx512vl
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: vr256x }
-# CHECK-NEXT:   - { id: 1, class: vr256x }
-# CHECK-NEXT:   - { id: 2, class: vr256x }
+# CHECK-NEXT:   - { id: 0, class: vr256x, preferred-register: '' }
+# CHECK-NEXT:   - { id: 1, class: vr256x, preferred-register: '' }
+# CHECK-NEXT:   - { id: 2, class: vr256x, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # CHECK:          %2 = VPMULLDZ256rr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %ymm0, %ymm1
 
     %0(<8 x s32>) = COPY %ymm0
     %1(<8 x s32>) = COPY %ymm1
     %2(<8 x s32>) = G_MUL %0, %1
     %ymm0 = COPY %2(<8 x s32>)
     RET 0, implicit %ymm0
 
 ...
 ---
 name:            test_mul_v4i64
 # CHECK-LABEL: name:  test_mul_v4i64
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: vr256x }
-# CHECK-NEXT:   - { id: 1, class: vr256x }
-# CHECK-NEXT:   - { id: 2, class: vr256x }
+# CHECK-NEXT:   - { id: 0, class: vr256x, preferred-register: '' }
+# CHECK-NEXT:   - { id: 1, class: vr256x, preferred-register: '' }
+# CHECK-NEXT:   - { id: 2, class: vr256x, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # CHECK:          %2 = VPMULLQZ256rr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %ymm0, %ymm1
 
     %0(<4 x s64>) = COPY %ymm0
     %1(<4 x s64>) = COPY %ymm1
     %2(<4 x s64>) = G_MUL %0, %1
     %ymm0 = COPY %2(<4 x s64>)
     RET 0, implicit %ymm0
 
 ...
 ---
 name:            test_mul_v32i16
 # CHECK-LABEL: name:  test_mul_v32i16
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: vr512 }
-# CHECK-NEXT:   - { id: 1, class: vr512 }
-# CHECK-NEXT:   - { id: 2, class: vr512 }
+# CHECK-NEXT:   - { id: 0, class: vr512, preferred-register: '' }
+# CHECK-NEXT:   - { id: 1, class: vr512, preferred-register: '' }
+# CHECK-NEXT:   - { id: 2, class: vr512, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # CHECK:          %2 = VPMULLWZrr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %zmm0, %zmm1
 
     %0(<32 x s16>) = COPY %zmm0
     %1(<32 x s16>) = COPY %zmm1
     %2(<32 x s16>) = G_MUL %0, %1
     %zmm0 = COPY %2(<32 x s16>)
     RET 0, implicit %zmm0
 
 ...
 ---
 name:            test_mul_v16i32
 # CHECK-LABEL: name:  test_mul_v16i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: vr512 }
-# CHECK-NEXT:   - { id: 1, class: vr512 }
-# CHECK-NEXT:   - { id: 2, class: vr512 }
+# CHECK-NEXT:   - { id: 0, class: vr512, preferred-register: '' }
+# CHECK-NEXT:   - { id: 1, class: vr512, preferred-register: '' }
+# CHECK-NEXT:   - { id: 2, class: vr512, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # CHECK:          %2 = VPMULLDZrr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %zmm0, %zmm1
 
     %0(<16 x s32>) = COPY %zmm0
     %1(<16 x s32>) = COPY %zmm1
     %2(<16 x s32>) = G_MUL %0, %1
     %zmm0 = COPY %2(<16 x s32>)
     RET 0, implicit %zmm0
 
 ...
 ---
 name:            test_mul_v8i64
 # CHECK-LABEL: name:  test_mul_v8i64
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: vr512 }
-# CHECK-NEXT:   - { id: 1, class: vr512 }
-# CHECK-NEXT:   - { id: 2, class: vr512 }
+# CHECK-NEXT:   - { id: 0, class: vr512, preferred-register: '' }
+# CHECK-NEXT:   - { id: 1, class: vr512, preferred-register: '' }
+# CHECK-NEXT:   - { id: 2, class: vr512, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # CHECK:          %2 = VPMULLQZrr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %zmm0, %zmm1
 
     %0(<8 x s64>) = COPY %zmm0
     %1(<8 x s64>) = COPY %zmm1
     %2(<8 x s64>) = G_MUL %0, %1
     %zmm0 = COPY %2(<8 x s64>)
     RET 0, implicit %zmm0
 
 ...

test/CodeGen/X86/GlobalISel/select-sub-v128.mir

 ...
 ---
 name:            test_sub_v16i8
 # ALL-LABEL: name:  test_sub_v16i8
 alignment:       4
 legalized:       true
 regBankSelected: true
 # NOVL:            registers:
-# NOVL-NEXT:         - { id: 0, class: vr128 }
-# NOVL-NEXT:         - { id: 1, class: vr128 }
-# NOVL-NEXT:         - { id: 2, class: vr128 }
+# NOVL-NEXT:         - { id: 0, class: vr128, preferred-register: '' }
+# NOVL-NEXT:         - { id: 1, class: vr128, preferred-register: '' }
+# NOVL-NEXT:         - { id: 2, class: vr128, preferred-register: '' }
 #
 # AVX512VL:        registers:
-# AVX512VL-NEXT:     - { id: 0, class: vr128 }
-# AVX512VL-NEXT:     - { id: 1, class: vr128 }
-# AVX512VL-NEXT:     - { id: 2, class: vr128 }
+# AVX512VL-NEXT:     - { id: 0, class: vr128, preferred-register: '' }
+# AVX512VL-NEXT:     - { id: 1, class: vr128, preferred-register: '' }
+# AVX512VL-NEXT:     - { id: 2, class: vr128, preferred-register: '' }
 #
 # AVX512BWVL:      registers:
-# AVX512BWVL-NEXT:   - { id: 0, class: vr128x }
-# AVX512BWVL-NEXT:   - { id: 1, class: vr128x }
-# AVX512BWVL-NEXT:   - { id: 2, class: vr128x }
+# AVX512BWVL-NEXT:   - { id: 0, class: vr128x, preferred-register: '' }
+# AVX512BWVL-NEXT:   - { id: 1, class: vr128x, preferred-register: '' }
+# AVX512BWVL-NEXT:   - { id: 2, class: vr128x, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # SSE2:                %2 = PSUBBrr %0, %1
 #
 # AVX1:                %2 = VPSUBBrr %0, %1
 #

 ...
 ---
 name:            test_sub_v8i16
 # ALL-LABEL: name:  test_sub_v8i16
 alignment:       4
 legalized:       true
 regBankSelected: true
 # NOVL:            registers:
-# NOVL-NEXT:         - { id: 0, class: vr128 }
-# NOVL-NEXT:         - { id: 1, class: vr128 }
-# NOVL-NEXT:         - { id: 2, class: vr128 }
+# NOVL-NEXT:         - { id: 0, class: vr128, preferred-register: '' }
+# NOVL-NEXT:         - { id: 1, class: vr128, preferred-register: '' }
+# NOVL-NEXT:         - { id: 2, class: vr128, preferred-register: '' }
 #
 # AVX512VL:        registers:
-# AVX512VL-NEXT:     - { id: 0, class: vr128 }
-# AVX512VL-NEXT:     - { id: 1, class: vr128 }
-# AVX512VL-NEXT:     - { id: 2, class: vr128 }
+# AVX512VL-NEXT:     - { id: 0, class: vr128, preferred-register: '' }
+# AVX512VL-NEXT:     - { id: 1, class: vr128, preferred-register: '' }
+# AVX512VL-NEXT:     - { id: 2, class: vr128, preferred-register: '' }
 #
 # AVX512BWVL:      registers:
-# AVX512BWVL-NEXT:   - { id: 0, class: vr128x }
-# AVX512BWVL-NEXT:   - { id: 1, class: vr128x }
-# AVX512BWVL-NEXT:   - { id: 2, class: vr128x }
+# AVX512BWVL-NEXT:   - { id: 0, class: vr128x, preferred-register: '' }
+# AVX512BWVL-NEXT:   - { id: 1, class: vr128x, preferred-register: '' }
+# AVX512BWVL-NEXT:   - { id: 2, class: vr128x, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # SSE2:                %2 = PSUBWrr %0, %1
 #
 # AVX1:                %2 = VPSUBWrr %0, %1
 #

 ...
 ---
 name:            test_sub_v4i32
 # ALL-LABEL: name:  test_sub_v4i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 # NOVL:            registers:
-# NOVL-NEXT:         - { id: 0, class: vr128 }
-# NOVL-NEXT:         - { id: 1, class: vr128 }
-# NOVL-NEXT:         - { id: 2, class: vr128 }
+# NOVL-NEXT:         - { id: 0, class: vr128, preferred-register: '' }
+# NOVL-NEXT:         - { id: 1, class: vr128, preferred-register: '' }
+# NOVL-NEXT:         - { id: 2, class: vr128, preferred-register: '' }
 #
 # AVX512VL:        registers:
-# AVX512VL-NEXT:     - { id: 0, class: vr128x }
-# AVX512VL-NEXT:     - { id: 1, class: vr128x }
-# AVX512VL-NEXT:     - { id: 2, class: vr128x }
+# AVX512VL-NEXT:     - { id: 0, class: vr128x, preferred-register: '' }
+# AVX512VL-NEXT:     - { id: 1, class: vr128x, preferred-register: '' }
+# AVX512VL-NEXT:     - { id: 2, class: vr128x, preferred-register: '' }
 #
 # AVX512BWVL:      registers:
-# AVX512BWVL-NEXT:   - { id: 0, class: vr128x }
-# AVX512BWVL-NEXT:   - { id: 1, class: vr128x }
-# AVX512BWVL-NEXT:   - { id: 2, class: vr128x }
+# AVX512BWVL-NEXT:   - { id: 0, class: vr128x, preferred-register: '' }
+# AVX512BWVL-NEXT:   - { id: 1, class: vr128x, preferred-register: '' }
+# AVX512BWVL-NEXT:   - { id: 2, class: vr128x, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # SSE2:                %2 = PSUBDrr %0, %1
 #
 # AVX1:                %2 = VPSUBDrr %0, %1
 #

 ...
 ---
 name:            test_sub_v2i64
 # ALL-LABEL: name:  test_sub_v2i64
 alignment:       4
 legalized:       true
 regBankSelected: true
 # NOVL:            registers:
-# NOVL-NEXT:         - { id: 0, class: vr128 }
-# NOVL-NEXT:         - { id: 1, class: vr128 }
-# NOVL-NEXT:         - { id: 2, class: vr128 }
+# NOVL-NEXT:         - { id: 0, class: vr128, preferred-register: '' }
+# NOVL-NEXT:         - { id: 1, class: vr128, preferred-register: '' }
+# NOVL-NEXT:         - { id: 2, class: vr128, preferred-register: '' }
 #
 # AVX512VL:        registers:
-# AVX512VL-NEXT:     - { id: 0, class: vr128x }
-# AVX512VL-NEXT:     - { id: 1, class: vr128x }
-# AVX512VL-NEXT:     - { id: 2, class: vr128x }
+# AVX512VL-NEXT:     - { id: 0, class: vr128x, preferred-register: '' }
+# AVX512VL-NEXT:     - { id: 1, class: vr128x, preferred-register: '' }
+# AVX512VL-NEXT:     - { id: 2, class: vr128x, preferred-register: '' }
 #
 # AVX512BWVL:      registers:
-# AVX512BWVL-NEXT:   - { id: 0, class: vr128x }
-# AVX512BWVL-NEXT:   - { id: 1, class: vr128x }
-# AVX512BWVL-NEXT:   - { id: 2, class: vr128x }
+# AVX512BWVL-NEXT:   - { id: 0, class: vr128x, preferred-register: '' }
+# AVX512BWVL-NEXT:   - { id: 1, class: vr128x, preferred-register: '' }
+# AVX512BWVL-NEXT:   - { id: 2, class: vr128x, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # SSE2:                %2 = PSUBQrr %0, %1
 #
 # AVX1:                %2 = VPSUBQrr %0, %1
 #

test/CodeGen/X86/GlobalISel/select-sub-v256.mir

 ...
 ---
 name:            test_sub_v32i8
 # ALL-LABEL: name:  test_sub_v32i8
 alignment:       4
 legalized:       true
 regBankSelected: true
 # AVX2:            registers:
-# AVX2-NEXT:         - { id: 0, class: vr256 }
-# AVX2-NEXT:         - { id: 1, class: vr256 }
-# AVX2-NEXT:         - { id: 2, class: vr256 }
+# AVX2-NEXT:         - { id: 0, class: vr256, preferred-register: '' }
+# AVX2-NEXT:         - { id: 1, class: vr256, preferred-register: '' }
+# AVX2-NEXT:         - { id: 2, class: vr256, preferred-register: '' }
 #
 # AVX512VL:        registers:
-# AVX512VL-NEXT:     - { id: 0, class: vr256 }
-# AVX512VL-NEXT:     - { id: 1, class: vr256 }
-# AVX512VL-NEXT:     - { id: 2, class: vr256 }
+# AVX512VL-NEXT:     - { id: 0, class: vr256, preferred-register: '' }
+# AVX512VL-NEXT:     - { id: 1, class: vr256, preferred-register: '' }
+# AVX512VL-NEXT:     - { id: 2, class: vr256, preferred-register: '' }
 #
 # AVX512BWVL:      registers:
-# AVX512BWVL-NEXT:   - { id: 0, class: vr256x }
-# AVX512BWVL-NEXT:   - { id: 1, class: vr256x }
-# AVX512BWVL-NEXT:   - { id: 2, class: vr256x }
+# AVX512BWVL-NEXT:   - { id: 0, class: vr256x, preferred-register: '' }
+# AVX512BWVL-NEXT:   - { id: 1, class: vr256x, preferred-register: '' }
+# AVX512BWVL-NEXT:   - { id: 2, class: vr256x, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # AVX2:                %2 = VPSUBBYrr %0, %1
 #
 # AVX512VL:            %2 = VPSUBBYrr %0, %1
 #

 ...
 ---
 name:            test_sub_v16i16
 # ALL-LABEL: name:  test_sub_v16i16
 alignment:       4
 legalized:       true
 regBankSelected: true
 # AVX2:            registers:
-# AVX2-NEXT:         - { id: 0, class: vr256 }
-# AVX2-NEXT:         - { id: 1, class: vr256 }
-# AVX2-NEXT:         - { id: 2, class: vr256 }
+# AVX2-NEXT:         - { id: 0, class: vr256, preferred-register: '' }
+# AVX2-NEXT:         - { id: 1, class: vr256, preferred-register: '' }
+# AVX2-NEXT:         - { id: 2, class: vr256, preferred-register: '' }
 #
 # AVX512VL:        registers:
-# AVX512VL-NEXT:     - { id: 0, class: vr256 }
-# AVX512VL-NEXT:     - { id: 1, class: vr256 }
-# AVX512VL-NEXT:     - { id: 2, class: vr256 }
+# AVX512VL-NEXT:     - { id: 0, class: vr256, preferred-register: '' }
+# AVX512VL-NEXT:     - { id: 1, class: vr256, preferred-register: '' }
+# AVX512VL-NEXT:     - { id: 2, class: vr256, preferred-register: '' }
 #
 # AVX512BWVL:      registers:
-# AVX512BWVL-NEXT:   - { id: 0, class: vr256x }
-# AVX512BWVL-NEXT:   - { id: 1, class: vr256x }
-# AVX512BWVL-NEXT:   - { id: 2, class: vr256x }
+# AVX512BWVL-NEXT:   - { id: 0, class: vr256x, preferred-register: '' }
+# AVX512BWVL-NEXT:   - { id: 1, class: vr256x, preferred-register: '' }
+# AVX512BWVL-NEXT:   - { id: 2, class: vr256x, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # AVX2:                %2 = VPSUBWYrr %0, %1
 #
 # AVX512VL:            %2 = VPSUBWYrr %0, %1
 #

 ...
 ---
 name:            test_sub_v8i32
 # ALL-LABEL: name:  test_sub_v8i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 # AVX2:            registers:
-# AVX2-NEXT:         - { id: 0, class: vr256 }
-# AVX2-NEXT:         - { id: 1, class: vr256 }
-# AVX2-NEXT:         - { id: 2, class: vr256 }
+# AVX2-NEXT:         - { id: 0, class: vr256, preferred-register: '' }
+# AVX2-NEXT:         - { id: 1, class: vr256, preferred-register: '' }
+# AVX2-NEXT:         - { id: 2, class: vr256, preferred-register: '' }
 #
 # AVX512VL:        registers:
-# AVX512VL-NEXT:     - { id: 0, class: vr256x }
-# AVX512VL-NEXT:     - { id: 1, class: vr256x }
-# AVX512VL-NEXT:     - { id: 2, class: vr256x }
+# AVX512VL-NEXT:     - { id: 0, class: vr256x, preferred-register: '' }
+# AVX512VL-NEXT:     - { id: 1, class: vr256x, preferred-register: '' }
+# AVX512VL-NEXT:     - { id: 2, class: vr256x, preferred-register: '' }
 #
 # AVX512BWVL:      registers:
-# AVX512BWVL-NEXT:   - { id: 0, class: vr256x }
-# AVX512BWVL-NEXT:   - { id: 1, class: vr256x }
-# AVX512BWVL-NEXT:   - { id: 2, class: vr256x }
+# AVX512BWVL-NEXT:   - { id: 0, class: vr256x, preferred-register: '' }
+# AVX512BWVL-NEXT:   - { id: 1, class: vr256x, preferred-register: '' }
+# AVX512BWVL-NEXT:   - { id: 2, class: vr256x, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # AVX2:                %2 = VPSUBDYrr %0, %1
 #
 # AVX512VL:            %2 = VPSUBDZ256rr %0, %1
 #

 ...
 ---
 name:            test_sub_v4i64
 # ALL-LABEL: name:  test_sub_v4i64
 alignment:       4
 legalized:       true
 regBankSelected: true
 # AVX2:            registers:
-# AVX2-NEXT:         - { id: 0, class: vr256 }
-# AVX2-NEXT:         - { id: 1, class: vr256 }
-# AVX2-NEXT:         - { id: 2, class: vr256 }
+# AVX2-NEXT:         - { id: 0, class: vr256, preferred-register: '' }
+# AVX2-NEXT:         - { id: 1, class: vr256, preferred-register: '' }
+# AVX2-NEXT:         - { id: 2, class: vr256, preferred-register: '' }
 #
 # AVX512VL:        registers:
-# AVX512VL-NEXT:     - { id: 0, class: vr256x }
-# AVX512VL-NEXT:     - { id: 1, class: vr256x }
-# AVX512VL-NEXT:     - { id: 2, class: vr256x }
+# AVX512VL-NEXT:     - { id: 0, class: vr256x, preferred-register: '' }
+# AVX512VL-NEXT:     - { id: 1, class: vr256x, preferred-register: '' }
+# AVX512VL-NEXT:     - { id: 2, class: vr256x, preferred-register: '' }
 #
 # AVX512BWVL:      registers:
-# AVX512BWVL-NEXT:   - { id: 0, class: vr256x }
-# AVX512BWVL-NEXT:   - { id: 1, class: vr256x }
-# AVX512BWVL-NEXT:   - { id: 2, class: vr256x }
+# AVX512BWVL-NEXT:   - { id: 0, class: vr256x, preferred-register: '' }
+# AVX512BWVL-NEXT:   - { id: 1, class: vr256x, preferred-register: '' }
+# AVX512BWVL-NEXT:   - { id: 2, class: vr256x, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # AVX2:                %2 = VPSUBQYrr %0, %1
 #
 # AVX512VL:            %2 = VPSUBQZ256rr %0, %1
 #

test/CodeGen/X86/GlobalISel/select-sub-v512.mir

 ...
 ---
 name:            test_sub_v64i8
 # ALL-LABEL: name:  test_sub_v64i8
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: vr512 }
-# ALL-NEXT:   - { id: 1, class: vr512 }
-# ALL-NEXT:   - { id: 2, class: vr512 }
+# ALL-NEXT:   - { id: 0, class: vr512, preferred-register: '' }
+# ALL-NEXT:   - { id: 1, class: vr512, preferred-register: '' }
+# ALL-NEXT:   - { id: 2, class: vr512, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # ALL:          %2 = VPSUBBZrr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %zmm0, %zmm1
 
     %0(<64 x s8>) = COPY %zmm0
     %1(<64 x s8>) = COPY %zmm1
     %2(<64 x s8>) = G_SUB %0, %1
     %zmm0 = COPY %2(<64 x s8>)
     RET 0, implicit %zmm0
 
 ...
 ---
 name:            test_sub_v32i16
 # ALL-LABEL: name:  test_sub_v32i16
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: vr512 }
-# ALL-NEXT:   - { id: 1, class: vr512 }
-# ALL-NEXT:   - { id: 2, class: vr512 }
+# ALL-NEXT:   - { id: 0, class: vr512, preferred-register: '' }
+# ALL-NEXT:   - { id: 1, class: vr512, preferred-register: '' }
+# ALL-NEXT:   - { id: 2, class: vr512, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # ALL:          %2 = VPSUBWZrr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %zmm0, %zmm1
 
     %0(<32 x s16>) = COPY %zmm0
     %1(<32 x s16>) = COPY %zmm1
     %2(<32 x s16>) = G_SUB %0, %1
     %zmm0 = COPY %2(<32 x s16>)
     RET 0, implicit %zmm0
 
 ...
 ---
 name:            test_sub_v16i32
 # ALL-LABEL: name:  test_sub_v16i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: vr512 }
-# ALL-NEXT:   - { id: 1, class: vr512 }
-# ALL-NEXT:   - { id: 2, class: vr512 }
+# ALL-NEXT:   - { id: 0, class: vr512, preferred-register: '' }
+# ALL-NEXT:   - { id: 1, class: vr512, preferred-register: '' }
+# ALL-NEXT:   - { id: 2, class: vr512, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # ALL:          %2 = VPSUBDZrr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %zmm0, %zmm1
 
     %0(<16 x s32>) = COPY %zmm0
     %1(<16 x s32>) = COPY %zmm1
     %2(<16 x s32>) = G_SUB %0, %1
     %zmm0 = COPY %2(<16 x s32>)
     RET 0, implicit %zmm0
 
 ...
 ---
 name:            test_sub_v8i64
 # ALL-LABEL: name:  test_sub_v8i64
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: vr512 }
-# ALL-NEXT:   - { id: 1, class: vr512 }
-# ALL-NEXT:   - { id: 2, class: vr512 }
+# ALL-NEXT:   - { id: 0, class: vr512, preferred-register: '' }
+# ALL-NEXT:   - { id: 1, class: vr512, preferred-register: '' }
+# ALL-NEXT:   - { id: 2, class: vr512, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # ALL:          %2 = VPSUBQZrr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %zmm0, %zmm1
 
     %0(<8 x s64>) = COPY %zmm0
     %1(<8 x s64>) = COPY %zmm1
     %2(<8 x s64>) = G_SUB %0, %1
     %zmm0 = COPY %2(<8 x s64>)
     RET 0, implicit %zmm0
 
 ...

test/CodeGen/X86/GlobalISel/select-sub.mir

--- |
   }
 
 ...
 ---
 name:            test_sub_i64
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:  - { id: 0, class: gr64 }
-# ALL-NEXT:  - { id: 1, class: gr64 }
-# ALL-NEXT:  - { id: 2, class: gr64 }
+# ALL-NEXT:  - { id: 0, class: gr64, preferred-register: '' }
+# ALL-NEXT:  - { id: 1, class: gr64, preferred-register: '' }
+# ALL-NEXT:  - { id: 2, class: gr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 # ALL:      %0 = COPY %rdi
 # ALL-NEXT: %1 = COPY %rsi
 # ALL-NEXT: %2 = SUB64rr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %edi, %esi
 
     %0(s64) = COPY %rdi
     %1(s64) = COPY %rsi
     %2(s64) = G_SUB %0, %1
     %rax = COPY %2(s64)
 
 ...
 
 ---
 name:            test_sub_i32
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:  - { id: 0, class: gr32 }
-# ALL-NEXT:  - { id: 1, class: gr32 }
-# ALL-NEXT:  - { id: 2, class: gr32 }
+# ALL-NEXT:  - { id: 0, class: gr32, preferred-register: '' }
+# ALL-NEXT:  - { id: 1, class: gr32, preferred-register: '' }
+# ALL-NEXT:  - { id: 2, class: gr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 # ALL:      %0 = COPY %edi
 # ALL-NEXT: %1 = COPY %esi
 # ALL-NEXT: %2 = SUB32rr %0, %1
 body:             |

 ---
 name:            test_sub_float
 alignment:       4
 legalized:       true
 regBankSelected: true
 selected:        false
 tracksRegLiveness: true
 # ALL: registers:
-# NO_AVX512F-NEXT:  - { id: 0, class: fr32 }
-# NO_AVX512F-NEXT:  - { id: 1, class: fr32 }
-# NO_AVX512F-NEXT:  - { id: 2, class: fr32 }
-# AVX512ALL-NEXT:  - { id: 0, class: fr32x }
-# AVX512ALL-NEXT:  - { id: 1, class: fr32x }
-# AVX512ALL-NEXT:  - { id: 2, class: fr32x }
+# NO_AVX512F-NEXT:  - { id: 0, class: fr32, preferred-register: '' }
+# NO_AVX512F-NEXT:  - { id: 1, class: fr32, preferred-register: '' }
+# NO_AVX512F-NEXT:  - { id: 2, class: fr32, preferred-register: '' }
+# AVX512ALL-NEXT:  - { id: 0, class: fr32x, preferred-register: '' }
+# AVX512ALL-NEXT:  - { id: 1, class: fr32x, preferred-register: '' }
+# AVX512ALL-NEXT:  - { id: 2, class: fr32x, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # ALL:          %0 = COPY %xmm0
 # ALL-NEXT:     %1 = COPY %xmm1
 # SSE-NEXT:     %2 = SUBSSrr %0, %1
 # AVX-NEXT:     %2 = VSUBSSrr %0, %1

 ---
 name:            test_sub_double
 alignment:       4
 legalized:       true
 regBankSelected: true
 selected:        false
 tracksRegLiveness: true
 # ALL: registers:
-# NO_AVX512F-NEXT:  - { id: 0, class: fr64 }
-# NO_AVX512F-NEXT:  - { id: 1, class: fr64 }
-# NO_AVX512F-NEXT:  - { id: 2, class: fr64 }
-# AVX512ALL-NEXT:  - { id: 0, class: fr64x }
-# AVX512ALL-NEXT:  - { id: 1, class: fr64x }
-# AVX512ALL-NEXT:  - { id: 2, class: fr64x }
+# NO_AVX512F-NEXT:  - { id: 0, class: fr64, preferred-register: '' }
+# NO_AVX512F-NEXT:  - { id: 1, class: fr64, preferred-register: '' }
+# NO_AVX512F-NEXT:  - { id: 2, class: fr64, preferred-register: '' }
+# AVX512ALL-NEXT:  - { id: 0, class: fr64x, preferred-register: '' }
+# AVX512ALL-NEXT:  - { id: 1, class: fr64x, preferred-register: '' }
+# AVX512ALL-NEXT:  - { id: 2, class: fr64x, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # ALL:          %0 = COPY %xmm0
 # ALL-NEXT:     %1 = COPY %xmm1
 # SSE-NEXT:     %2 = SUBSDrr %0, %1
 # AVX-NEXT:     %2 = VSUBSDrr %0, %1

 ---
 name:            test_sub_v4i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 selected:        false
 tracksRegLiveness: true
 # ALL: registers:
-# NO_AVX512VL-NEXT:  - { id: 0, class: vr128 }
-# NO_AVX512VL-NEXT:  - { id: 1, class: vr128 }
-# NO_AVX512VL-NEXT:  - { id: 2, class: vr128 }
-# AVX512VL-NEXT:  - { id: 0, class: vr128x }
-# AVX512VL-NEXT:  - { id: 1, class: vr128x }
-# AVX512VL-NEXT:  - { id: 2, class: vr128x }
+# NO_AVX512VL-NEXT:  - { id: 0, class: vr128, preferred-register: '' }
+# NO_AVX512VL-NEXT:  - { id: 1, class: vr128, preferred-register: '' }
+# NO_AVX512VL-NEXT:  - { id: 2, class: vr128, preferred-register: '' }
+# AVX512VL-NEXT:  - { id: 0, class: vr128x, preferred-register: '' }
+# AVX512VL-NEXT:  - { id: 1, class: vr128x, preferred-register: '' }
+# AVX512VL-NEXT:  - { id: 2, class: vr128x, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # ALL:           %0 = COPY %xmm0
 # ALL-NEXT:      %1 = COPY %xmm1
 # SSE-NEXT:      %2 = PSUBDrr %0, %1
 # AVX-NEXT:      %2 = VPSUBDrr %0, %1

 ---
 name:            test_sub_v4f32
 alignment:       4
 legalized:       true
 regBankSelected: true
 selected:        false
 tracksRegLiveness: true
 # ALL: registers:
-# NO_AVX512VL-NEXT:  - { id: 0, class: vr128 }
-# NO_AVX512VL-NEXT:  - { id: 1, class: vr128 }
-# NO_AVX512VL-NEXT:  - { id: 2, class: vr128 }
-# AVX512VL-NEXT:  - { id: 0, class: vr128x }
-# AVX512VL-NEXT:  - { id: 1, class: vr128x }
-# AVX512VL-NEXT:  - { id: 2, class: vr128x }
+# NO_AVX512VL-NEXT:  - { id: 0, class: vr128, preferred-register: '' }
+# NO_AVX512VL-NEXT:  - { id: 1, class: vr128, preferred-register: '' }
+# NO_AVX512VL-NEXT:  - { id: 2, class: vr128, preferred-register: '' }
+# AVX512VL-NEXT:  - { id: 0, class: vr128x, preferred-register: '' }
+# AVX512VL-NEXT:  - { id: 1, class: vr128x, preferred-register: '' }
+# AVX512VL-NEXT:  - { id: 2, class: vr128x, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # ALL:           %0 = COPY %xmm0
 # ALL-NEXT:      %1 = COPY %xmm1
 # SSE-NEXT:      %2 = SUBPSrr %0, %1
 # AVX-NEXT:      %2 = VSUBPSrr %0, %1

test/CodeGen/X86/GlobalISel/select-trunc.mir

 ...
 ---
 name:            trunc_i32toi1
 # CHECK-LABEL: name:  trunc_i32toi1
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gr32 }
-# CHECK-NEXT:   - { id: 1, class: gr8 }
+# CHECK-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 1, class: gr8, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 # CHECK:          %0 = COPY %edi
 # CHECK-NEXT:     %1 = COPY %0.sub_8bit
 # CHECK-NEXT:     %al = COPY %1
 # CHECK-NEXT:     RET 0, implicit %al
 body:             |
   bb.1 (%ir-block.0):
     liveins: %edi
 
     %0(s32) = COPY %edi
     %1(s1) = G_TRUNC %0(s32)
     %al = COPY %1(s1)
     RET 0, implicit %al
 
 ...
 ---
 name:            trunc_i32toi8
 # CHECK-LABEL: name:  trunc_i32toi8
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gr32 }
-# CHECK-NEXT:   - { id: 1, class: gr8 }
+# CHECK-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 1, class: gr8, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 # CHECK:          %0 = COPY %edi
 # CHECK-NEXT:     %1 = COPY %0.sub_8bit
 # CHECK-NEXT:     %al = COPY %1
 # CHECK-NEXT:     RET 0, implicit %al
 body:             |
   bb.1 (%ir-block.0):
     liveins: %edi
 
     %0(s32) = COPY %edi
     %1(s8) = G_TRUNC %0(s32)
     %al = COPY %1(s8)
     RET 0, implicit %al
 
 ...
 ---
 name:            trunc_i32toi16
 # CHECK-LABEL: name:  trunc_i32toi16
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gr32 }
-# CHECK-NEXT:   - { id: 1, class: gr16 }
+# CHECK-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 1, class: gr16, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 # CHECK:          %0 = COPY %edi
 # CHECK-NEXT:     %1 = COPY %0.sub_16bit
 # CHECK-NEXT:     %ax = COPY %1
 # CHECK-NEXT:     RET 0, implicit %ax
 body:             |
   bb.1 (%ir-block.0):
     liveins: %edi
 
     %0(s32) = COPY %edi
     %1(s16) = G_TRUNC %0(s32)
     %ax = COPY %1(s16)
     RET 0, implicit %ax
 
 ...
 ---
 name:            trunc_i64toi8
 # CHECK-LABEL: name:  trunc_i64toi8
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gr64_with_sub_8bit }
-# CHECK-NEXT:   - { id: 1, class: gr8 }
+# CHECK-NEXT:   - { id: 0, class: gr64_with_sub_8bit, preferred-register: '' }
+# CHECK-NEXT:   - { id: 1, class: gr8, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 # CHECK:          %0 = COPY %rdi
 # CHECK-NEXT:     %1 = COPY %0.sub_8bit
 # CHECK-NEXT:     %al = COPY %1
 # CHECK-NEXT:     RET 0, implicit %al
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi
 
     %0(s64) = COPY %rdi
     %1(s8) = G_TRUNC %0(s64)
     %al = COPY %1(s8)
     RET 0, implicit %al
 
 ...
 ---
 name:            trunc_i64toi16
 # CHECK-LABEL: name:  trunc_i64toi16
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gr64 }
-# CHECK-NEXT:   - { id: 1, class: gr16 }
+# CHECK-NEXT:   - { id: 0, class: gr64, preferred-register: '' }
+# CHECK-NEXT:   - { id: 1, class: gr16, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 # CHECK:          %0 = COPY %rdi
 # CHECK-NEXT:     %1 = COPY %0.sub_16bit
 # CHECK-NEXT:     %ax = COPY %1
 # CHECK-NEXT:     RET 0, implicit %ax
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi
 
     %0(s64) = COPY %rdi
     %1(s16) = G_TRUNC %0(s64)
     %ax = COPY %1(s16)
     RET 0, implicit %ax
 
 ...
 ---
 name:            trunc_i64toi32
 # CHECK-LABEL: name:  trunc_i64toi32
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gr64 }
-# CHECK-NEXT:   - { id: 1, class: gr32 }
+# CHECK-NEXT:   - { id: 0, class: gr64, preferred-register: '' }
+# CHECK-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 # CHECK:          %0 = COPY %rdi
 # CHECK-NEXT:     %1 = COPY %0.sub_32bit
 # CHECK-NEXT:     %eax = COPY %1
 # CHECK-NEXT:     RET 0, implicit %eax
 body:             |

test/CodeGen/X86/virtual-registers-cleared-in-machine-functions-liveins.ll

body:
   ret i32 %c
 }
 
 ; PRE-RA: liveins:
 ; PRE-RA-NEXT: - { reg: '%edi', virtual-reg: '%0' }
 ; PRE-RA-NEXT: - { reg: '%esi', virtual-reg: '%1' }
 
 ; POST-RA: liveins:
-; POST-RA-NEXT: - { reg: '%edi' }
-; POST-RA-NEXT: - { reg: '%esi' }
+; POST-RA-NEXT: - { reg: '%edi', virtual-reg: '' }
+; POST-RA-NEXT: - { reg: '%esi', virtual-reg: '' }