Diff 95897

include/llvm/CodeGen/MachineValueType.h

Show First 20 Lines • Show All 49 Lines • ▼ Show 20 Lines	enum SimpleValueType : int8_t {
f64 = 9, // This is a 64 bit floating point value		f64 = 9, // This is a 64 bit floating point value
f80 = 10, // This is a 80 bit floating point value		f80 = 10, // This is a 80 bit floating point value
f128 = 11, // This is a 128 bit floating point value		f128 = 11, // This is a 128 bit floating point value
ppcf128 = 12, // This is a PPC 128-bit floating point value		ppcf128 = 12, // This is a PPC 128-bit floating point value

FIRST_FP_VALUETYPE = f16,		FIRST_FP_VALUETYPE = f16,
LAST_FP_VALUETYPE = ppcf128,		LAST_FP_VALUETYPE = ppcf128,

v2i1 = 13, // 2 x i1		v1i1 = 13, // 2 x i1
		craig.topperUnsubmitted Not Done Reply Inline Actions This needs to be rebased on top of a commit that went in today that changed this for ScalableVector MVTs. craig.topper: This needs to be rebased on top of a commit that went in today that changed this for…
v4i1 = 14, // 4 x i1		v2i1 = 14, // 2 x i1
v8i1 = 15, // 8 x i1		v4i1 = 15, // 4 x i1
v16i1 = 16, // 16 x i1		v8i1 = 16, // 8 x i1
v32i1 = 17, // 32 x i1		v16i1 = 17, // 16 x i1
v64i1 = 18, // 64 x i1		v32i1 = 18, // 32 x i1
v512i1 = 19, // 512 x i1		v64i1 = 19, // 64 x i1
v1024i1 = 20, // 1024 x i1		v512i1 = 20, // 512 x i1
		v1024i1 = 21, // 1024 x i1
v1i8 = 21, // 1 x i8
v2i8 = 22, // 2 x i8		v1i8 = 22, // 1 x i8
v4i8 = 23, // 4 x i8		v2i8 = 23, // 2 x i8
v8i8 = 24, // 8 x i8		v4i8 = 24, // 4 x i8
v16i8 = 25, // 16 x i8		v8i8 = 25, // 8 x i8
v32i8 = 26, // 32 x i8		v16i8 = 26, // 16 x i8
v64i8 = 27, // 64 x i8		v32i8 = 27, // 32 x i8
v128i8 = 28, //128 x i8		v64i8 = 28, // 64 x i8
v256i8 = 29, //256 x i8		v128i8 = 29, //128 x i8
		v256i8 = 30, //256 x i8
v1i16 = 30, // 1 x i16
v2i16 = 31, // 2 x i16		v1i16 = 31, // 1 x i16
v4i16 = 32, // 4 x i16		v2i16 = 32, // 2 x i16
v8i16 = 33, // 8 x i16		v4i16 = 33, // 4 x i16
v16i16 = 34, // 16 x i16		v8i16 = 34, // 8 x i16
v32i16 = 35, // 32 x i16		v16i16 = 35, // 16 x i16
v64i16 = 36, // 64 x i16		v32i16 = 36, // 32 x i16
v128i16 = 37, //128 x i16		v64i16 = 37, // 64 x i16
		v128i16 = 38, //128 x i16
v1i32 = 38, // 1 x i32
v2i32 = 39, // 2 x i32		v1i32 = 39, // 1 x i32
v4i32 = 40, // 4 x i32		v2i32 = 40, // 2 x i32
v8i32 = 41, // 8 x i32		v4i32 = 41, // 4 x i32
v16i32 = 42, // 16 x i32		v8i32 = 42, // 8 x i32
v32i32 = 43, // 32 x i32		v16i32 = 43, // 16 x i32
v64i32 = 44, // 64 x i32		v32i32 = 44, // 32 x i32
		v64i32 = 45, // 64 x i32
v1i64 = 45, // 1 x i64
v2i64 = 46, // 2 x i64		v1i64 = 46, // 1 x i64
v4i64 = 47, // 4 x i64		v2i64 = 47, // 2 x i64
v8i64 = 48, // 8 x i64		v4i64 = 48, // 4 x i64
v16i64 = 49, // 16 x i64		v8i64 = 49, // 8 x i64
v32i64 = 50, // 32 x i64		v16i64 = 50, // 16 x i64
		v32i64 = 51, // 32 x i64

v1i128 = 51, // 1 x i128		v1i128 = 52, // 1 x i128

FIRST_INTEGER_VECTOR_VALUETYPE = v2i1,		FIRST_INTEGER_VECTOR_VALUETYPE = v1i1,
LAST_INTEGER_VECTOR_VALUETYPE = v1i128,		LAST_INTEGER_VECTOR_VALUETYPE = v1i128,

v2f16 = 52, // 2 x f16		v2f16 = 53, // 2 x f16
v4f16 = 53, // 4 x f16		v4f16 = 54, // 4 x f16
v8f16 = 54, // 8 x f16		v8f16 = 55, // 8 x f16
v1f32 = 55, // 1 x f32		v1f32 = 56, // 1 x f32
v2f32 = 56, // 2 x f32		v2f32 = 57, // 2 x f32
v4f32 = 57, // 4 x f32		v4f32 = 58, // 4 x f32
v8f32 = 58, // 8 x f32		v8f32 = 59, // 8 x f32
v16f32 = 59, // 16 x f32		v16f32 = 60, // 16 x f32
v1f64 = 60, // 1 x f64		v1f64 = 61, // 1 x f64
v2f64 = 61, // 2 x f64		v2f64 = 62, // 2 x f64
v4f64 = 62, // 4 x f64		v4f64 = 63, // 4 x f64
v8f64 = 63, // 8 x f64		v8f64 = 64, // 8 x f64

FIRST_FP_VECTOR_VALUETYPE = v2f16,		FIRST_FP_VECTOR_VALUETYPE = v2f16,
LAST_FP_VECTOR_VALUETYPE = v8f64,		LAST_FP_VECTOR_VALUETYPE = v8f64,

FIRST_VECTOR_VALUETYPE = v2i1,		FIRST_VECTOR_VALUETYPE = v1i1,
LAST_VECTOR_VALUETYPE = v8f64,		LAST_VECTOR_VALUETYPE = v8f64,

x86mmx = 64, // This is an X86 MMX value		x86mmx = 65, // This is an X86 MMX value

Glue = 65, // This glues nodes together during pre-RA sched		Glue = 66, // This glues nodes together during pre-RA sched

isVoid = 66, // This has no value		isVoid = 67, // This has no value

Untyped = 67, // This value takes a register, but has		Untyped = 68, // This value takes a register, but has
// unspecified type. The register class		// unspecified type. The register class
// will be determined by the opcode.		// will be determined by the opcode.

FIRST_VALUETYPE = 0, // This is always the beginning of the list.		FIRST_VALUETYPE = 0, // This is always the beginning of the list.
LAST_VALUETYPE = 68, // This always remains at the end of the list.		LAST_VALUETYPE = 69, // This always remains at the end of the list.

// This is the current maximum for LAST_VALUETYPE.		// This is the current maximum for LAST_VALUETYPE.
// MVT::MAX_ALLOWED_VALUETYPE is used for asserts and to size bit vectors		// MVT::MAX_ALLOWED_VALUETYPE is used for asserts and to size bit vectors
// This value must be a multiple of 32.		// This value must be a multiple of 32.
MAX_ALLOWED_VALUETYPE = 96,		MAX_ALLOWED_VALUETYPE = 96,

// A value of type llvm::TokenTy		// A value of type llvm::TokenTy
token = 120,		token = 120,
▲ Show 20 Lines • Show All 161 Lines • ▼ Show 20 Lines	public:
MVT getScalarType() const {		MVT getScalarType() const {
return isVector() ? getVectorElementType() : *this;		return isVector() ? getVectorElementType() : *this;
}		}

MVT getVectorElementType() const {		MVT getVectorElementType() const {
switch (SimpleTy) {		switch (SimpleTy) {
default:		default:
llvm_unreachable("Not a vector MVT!");		llvm_unreachable("Not a vector MVT!");
		case v1i1:
case v2i1:		case v2i1:
case v4i1:		case v4i1:
case v8i1:		case v8i1:
case v16i1:		case v16i1:
case v32i1:		case v32i1:
case v64i1:		case v64i1:
case v512i1:		case v512i1:
case v1024i1: return i1;		case v1024i1: return i1;
▲ Show 20 Lines • Show All 86 Lines • ▼ Show 20 Lines	unsigned getVectorNumElements() const {
case v2i1:		case v2i1:
case v2i8:		case v2i8:
case v2i16:		case v2i16:
case v2i32:		case v2i32:
case v2i64:		case v2i64:
case v2f16:		case v2f16:
case v2f32:		case v2f32:
case v2f64: return 2;		case v2f64: return 2;
		case v1i1:
case v1i8:		case v1i8:
case v1i16:		case v1i16:
case v1i32:		case v1i32:
case v1i64:		case v1i64:
case v1i128:		case v1i128:
case v1f32:		case v1f32:
case v1f64: return 1;		case v1f64: return 1;
}		}
Show All 13 Lines	unsigned getSizeInBits() const {
case vAny:		case vAny:
case Any:		case Any:
llvm_unreachable("Value type is overloaded.");		llvm_unreachable("Value type is overloaded.");
case token:		case token:
llvm_unreachable("Token type is a sentinel that cannot be used "		llvm_unreachable("Token type is a sentinel that cannot be used "
"in codegen and has no size");		"in codegen and has no size");
case Metadata:		case Metadata:
llvm_unreachable("Value type is metadata.");		llvm_unreachable("Value type is metadata.");
		case v1i1:
		craig.topperUnsubmitted Not Done Reply Inline Actions Can you put the scalar type before the vector type? That would be more consistent with the other code. craig.topper: Can you put the scalar type before the vector type? That would be more consistent with the…
case i1 : return 1;		case i1 : return 1;
case v2i1: return 2;		case v2i1: return 2;
case v4i1: return 4;		case v4i1: return 4;
case i8 :		case i8 :
case v1i8:		case v1i8:
case v8i1: return 8;		case v8i1: return 8;
case i16 :		case i16 :
case f16:		case f16:
▲ Show 20 Lines • Show All 129 Lines • ▼ Show 20 Lines	static MVT getIntegerVT(unsigned BitWidth) {
}		}
}		}

static MVT getVectorVT(MVT VT, unsigned NumElements) {		static MVT getVectorVT(MVT VT, unsigned NumElements) {
switch (VT.SimpleTy) {		switch (VT.SimpleTy) {
default:		default:
break;		break;
case MVT::i1:		case MVT::i1:
		if (NumElements == 1) return MVT::v1i1;
if (NumElements == 2) return MVT::v2i1;		if (NumElements == 2) return MVT::v2i1;
if (NumElements == 4) return MVT::v4i1;		if (NumElements == 4) return MVT::v4i1;
if (NumElements == 8) return MVT::v8i1;		if (NumElements == 8) return MVT::v8i1;
if (NumElements == 16) return MVT::v16i1;		if (NumElements == 16) return MVT::v16i1;
if (NumElements == 32) return MVT::v32i1;		if (NumElements == 32) return MVT::v32i1;
if (NumElements == 64) return MVT::v64i1;		if (NumElements == 64) return MVT::v64i1;
if (NumElements == 512) return MVT::v512i1;		if (NumElements == 512) return MVT::v512i1;
if (NumElements == 1024) return MVT::v1024i1;		if (NumElements == 1024) return MVT::v1024i1;
▲ Show 20 Lines • Show All 120 Lines • Show Last 20 Lines

include/llvm/CodeGen/ValueTypes.td

	Show All 27 Lines
	def i128 : ValueType<128, 6>; // 128-bit integer value			def i128 : ValueType<128, 6>; // 128-bit integer value
	def f16 : ValueType<16 , 7>; // 16-bit floating point value			def f16 : ValueType<16 , 7>; // 16-bit floating point value
	def f32 : ValueType<32 , 8>; // 32-bit floating point value			def f32 : ValueType<32 , 8>; // 32-bit floating point value
	def f64 : ValueType<64 , 9>; // 64-bit floating point value			def f64 : ValueType<64 , 9>; // 64-bit floating point value
	def f80 : ValueType<80 , 10>; // 80-bit floating point value			def f80 : ValueType<80 , 10>; // 80-bit floating point value
	def f128 : ValueType<128, 11>; // 128-bit floating point value			def f128 : ValueType<128, 11>; // 128-bit floating point value
	def ppcf128: ValueType<128, 12>; // PPC 128-bit floating point value			def ppcf128: ValueType<128, 12>; // PPC 128-bit floating point value

	def v2i1 : ValueType<2 , 13>; // 2 x i1 vector value			def v1i1 : ValueType<1 , 13>; // 1 x i1 vector value
	def v4i1 : ValueType<4 , 14>; // 4 x i1 vector value			def v2i1 : ValueType<2 , 14>; // 2 x i1 vector value
	def v8i1 : ValueType<8 , 15>; // 8 x i1 vector value			def v4i1 : ValueType<4 , 15>; // 4 x i1 vector value
	def v16i1 : ValueType<16, 16>; // 16 x i1 vector value			def v8i1 : ValueType<8 , 16>; // 8 x i1 vector value
	def v32i1 : ValueType<32 , 17>; // 32 x i1 vector value			def v16i1 : ValueType<16, 17>; // 16 x i1 vector value
	def v64i1 : ValueType<64 , 18>; // 64 x i1 vector value			def v32i1 : ValueType<32 , 18>; // 32 x i1 vector value
	def v512i1 : ValueType<512, 19>; // 512 x i1 vector value			def v64i1 : ValueType<64 , 19>; // 64 x i1 vector value
	def v1024i1: ValueType<1024,20>; //1024 x i1 vector value			def v512i1 : ValueType<512, 20>; // 512 x i1 vector value
				def v1024i1: ValueType<1024,21>; //1024 x i1 vector value
	def v1i8 : ValueType<16, 21>; // 1 x i8 vector value
	def v2i8 : ValueType<16 , 22>; // 2 x i8 vector value			def v1i8 : ValueType<16, 22>; // 1 x i8 vector value
	def v4i8 : ValueType<32 , 23>; // 4 x i8 vector value			def v2i8 : ValueType<16 , 23>; // 2 x i8 vector value
	def v8i8 : ValueType<64 , 24>; // 8 x i8 vector value			def v4i8 : ValueType<32 , 24>; // 4 x i8 vector value
	def v16i8 : ValueType<128, 25>; // 16 x i8 vector value			def v8i8 : ValueType<64 , 25>; // 8 x i8 vector value
	def v32i8 : ValueType<256, 26>; // 32 x i8 vector value			def v16i8 : ValueType<128, 26>; // 16 x i8 vector value
	def v64i8 : ValueType<512, 27>; // 64 x i8 vector value			def v32i8 : ValueType<256, 27>; // 32 x i8 vector value
	def v128i8 : ValueType<1024,28>; //128 x i8 vector value			def v64i8 : ValueType<512, 28>; // 64 x i8 vector value
	def v256i8 : ValueType<2048,29>; //256 x i8 vector value			def v128i8 : ValueType<1024,29>; //128 x i8 vector value
				def v256i8 : ValueType<2048,30>; //256 x i8 vector value
	def v1i16 : ValueType<16 , 30>; // 1 x i16 vector value
	def v2i16 : ValueType<32 , 31>; // 2 x i16 vector value			def v1i16 : ValueType<16 , 31>; // 1 x i16 vector value
	def v4i16 : ValueType<64 , 32>; // 4 x i16 vector value			def v2i16 : ValueType<32 , 32>; // 2 x i16 vector value
	def v8i16 : ValueType<128, 33>; // 8 x i16 vector value			def v4i16 : ValueType<64 , 33>; // 4 x i16 vector value
	def v16i16 : ValueType<256, 34>; // 16 x i16 vector value			def v8i16 : ValueType<128, 34>; // 8 x i16 vector value
	def v32i16 : ValueType<512, 35>; // 32 x i16 vector value			def v16i16 : ValueType<256, 35>; // 16 x i16 vector value
	def v64i16 : ValueType<1024,36>; // 64 x i16 vector value			def v32i16 : ValueType<512, 36>; // 32 x i16 vector value
	def v128i16: ValueType<2048,37>; //128 x i16 vector value			def v64i16 : ValueType<1024,37>; // 64 x i16 vector value
				def v128i16: ValueType<2048,38>; //128 x i16 vector value
	def v1i32 : ValueType<32 , 38>; // 1 x i32 vector value
	def v2i32 : ValueType<64 , 39>; // 2 x i32 vector value			def v1i32 : ValueType<32 , 39>; // 1 x i32 vector value
	def v4i32 : ValueType<128, 40>; // 4 x i32 vector value			def v2i32 : ValueType<64 , 40>; // 2 x i32 vector value
	def v8i32 : ValueType<256, 41>; // 8 x i32 vector value			def v4i32 : ValueType<128, 41>; // 4 x i32 vector value
	def v16i32 : ValueType<512, 42>; // 16 x i32 vector value			def v8i32 : ValueType<256, 42>; // 8 x i32 vector value
	def v32i32 : ValueType<1024,43>; // 32 x i32 vector value			def v16i32 : ValueType<512, 43>; // 16 x i32 vector value
	def v64i32 : ValueType<2048,44>; // 32 x i32 vector value			def v32i32 : ValueType<1024,44>; // 32 x i32 vector value
				def v64i32 : ValueType<2048,45>; // 32 x i32 vector value
	def v1i64 : ValueType<64 , 45>; // 1 x i64 vector value
	def v2i64 : ValueType<128, 46>; // 2 x i64 vector value			def v1i64 : ValueType<64 , 46>; // 1 x i64 vector value
	def v4i64 : ValueType<256, 47>; // 4 x i64 vector value			def v2i64 : ValueType<128, 47>; // 2 x i64 vector value
	def v8i64 : ValueType<512, 48>; // 8 x i64 vector value			def v4i64 : ValueType<256, 48>; // 4 x i64 vector value
	def v16i64 : ValueType<1024,49>; // 16 x i64 vector value			def v8i64 : ValueType<512, 49>; // 8 x i64 vector value
	def v32i64 : ValueType<2048,50>; // 32 x i64 vector value			def v16i64 : ValueType<1024,50>; // 16 x i64 vector value
				def v32i64 : ValueType<2048,51>; // 32 x i64 vector value
	def v1i128 : ValueType<128, 51>; // 1 x i128 vector value
				def v1i128 : ValueType<128, 52>; // 1 x i128 vector value
	def v2f16 : ValueType<32 , 52>; // 2 x f16 vector value
	def v4f16 : ValueType<64 , 53>; // 4 x f16 vector value			def v2f16 : ValueType<32 , 53>; // 2 x f16 vector value
	def v8f16 : ValueType<128, 54>; // 8 x f16 vector value			def v4f16 : ValueType<64 , 54>; // 4 x f16 vector value
	def v1f32 : ValueType<32 , 55>; // 1 x f32 vector value			def v8f16 : ValueType<128, 55>; // 8 x f16 vector value
	def v2f32 : ValueType<64 , 56>; // 2 x f32 vector value			def v1f32 : ValueType<32 , 56>; // 1 x f32 vector value
	def v4f32 : ValueType<128, 57>; // 4 x f32 vector value			def v2f32 : ValueType<64 , 57>; // 2 x f32 vector value
	def v8f32 : ValueType<256, 58>; // 8 x f32 vector value			def v4f32 : ValueType<128, 58>; // 4 x f32 vector value
	def v16f32 : ValueType<512, 59>; // 16 x f32 vector value			def v8f32 : ValueType<256, 59>; // 8 x f32 vector value
	def v1f64 : ValueType<64, 60>; // 1 x f64 vector value			def v16f32 : ValueType<512, 60>; // 16 x f32 vector value
	def v2f64 : ValueType<128, 61>; // 2 x f64 vector value			def v1f64 : ValueType<64, 61>; // 1 x f64 vector value
	def v4f64 : ValueType<256, 62>; // 4 x f64 vector value			def v2f64 : ValueType<128, 62>; // 2 x f64 vector value
	def v8f64 : ValueType<512, 63>; // 8 x f64 vector value			def v4f64 : ValueType<256, 63>; // 4 x f64 vector value
				def v8f64 : ValueType<512, 64>; // 8 x f64 vector value

	def x86mmx : ValueType<64 , 64>; // X86 MMX value
	def FlagVT : ValueType<0 , 65>; // Pre-RA sched glue			def x86mmx : ValueType<64 , 65>; // X86 MMX value
	def isVoid : ValueType<0 , 66>; // Produces no value			def FlagVT : ValueType<0 , 66>; // Pre-RA sched glue
	def untyped: ValueType<8 , 67>; // Produces an untyped value			def isVoid : ValueType<0 , 67>; // Produces no value
				def untyped: ValueType<8 , 68>; // Produces an untyped value
	def token : ValueType<0 , 120>; // TokenTy			def token : ValueType<0 , 120>; // TokenTy
	def MetadataVT: ValueType<0, 121>; // Metadata			def MetadataVT: ValueType<0, 121>; // Metadata

	// Pseudo valuetype mapped to the current pointer size to any address space.			// Pseudo valuetype mapped to the current pointer size to any address space.
	// Should only be used in TableGen.			// Should only be used in TableGen.
	def iPTRAny : ValueType<0, 122>;			def iPTRAny : ValueType<0, 122>;

	// Pseudo valuetype to represent "vector of any size"			// Pseudo valuetype to represent "vector of any size"
	Show All 13 Lines

lib/IR/ValueTypes.cpp

Show First 20 Lines • Show All 136 Lines • ▼ Show 20 Lines	std::string EVT::getEVTString() const {
case MVT::f64: return "f64";		case MVT::f64: return "f64";
case MVT::f80: return "f80";		case MVT::f80: return "f80";
case MVT::f128: return "f128";		case MVT::f128: return "f128";
case MVT::ppcf128: return "ppcf128";		case MVT::ppcf128: return "ppcf128";
case MVT::isVoid: return "isVoid";		case MVT::isVoid: return "isVoid";
case MVT::Other: return "ch";		case MVT::Other: return "ch";
case MVT::Glue: return "glue";		case MVT::Glue: return "glue";
case MVT::x86mmx: return "x86mmx";		case MVT::x86mmx: return "x86mmx";
		case MVT::v1i1: return "v1i1";
case MVT::v2i1: return "v2i1";		case MVT::v2i1: return "v2i1";
case MVT::v4i1: return "v4i1";		case MVT::v4i1: return "v4i1";
case MVT::v8i1: return "v8i1";		case MVT::v8i1: return "v8i1";
case MVT::v16i1: return "v16i1";		case MVT::v16i1: return "v16i1";
case MVT::v32i1: return "v32i1";		case MVT::v32i1: return "v32i1";
case MVT::v64i1: return "v64i1";		case MVT::v64i1: return "v64i1";
case MVT::v512i1: return "v512i1";		case MVT::v512i1: return "v512i1";
case MVT::v1024i1: return "v1024i1";		case MVT::v1024i1: return "v1024i1";
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines	Type *EVT::getTypeForEVT(LLVMContext &Context) const {
case MVT::i128: return IntegerType::get(Context, 128);		case MVT::i128: return IntegerType::get(Context, 128);
case MVT::f16: return Type::getHalfTy(Context);		case MVT::f16: return Type::getHalfTy(Context);
case MVT::f32: return Type::getFloatTy(Context);		case MVT::f32: return Type::getFloatTy(Context);
case MVT::f64: return Type::getDoubleTy(Context);		case MVT::f64: return Type::getDoubleTy(Context);
case MVT::f80: return Type::getX86_FP80Ty(Context);		case MVT::f80: return Type::getX86_FP80Ty(Context);
case MVT::f128: return Type::getFP128Ty(Context);		case MVT::f128: return Type::getFP128Ty(Context);
case MVT::ppcf128: return Type::getPPC_FP128Ty(Context);		case MVT::ppcf128: return Type::getPPC_FP128Ty(Context);
case MVT::x86mmx: return Type::getX86_MMXTy(Context);		case MVT::x86mmx: return Type::getX86_MMXTy(Context);
		case MVT::v1i1: return VectorType::get(Type::getInt1Ty(Context), 1);
case MVT::v2i1: return VectorType::get(Type::getInt1Ty(Context), 2);		case MVT::v2i1: return VectorType::get(Type::getInt1Ty(Context), 2);
case MVT::v4i1: return VectorType::get(Type::getInt1Ty(Context), 4);		case MVT::v4i1: return VectorType::get(Type::getInt1Ty(Context), 4);
case MVT::v8i1: return VectorType::get(Type::getInt1Ty(Context), 8);		case MVT::v8i1: return VectorType::get(Type::getInt1Ty(Context), 8);
case MVT::v16i1: return VectorType::get(Type::getInt1Ty(Context), 16);		case MVT::v16i1: return VectorType::get(Type::getInt1Ty(Context), 16);
case MVT::v32i1: return VectorType::get(Type::getInt1Ty(Context), 32);		case MVT::v32i1: return VectorType::get(Type::getInt1Ty(Context), 32);
case MVT::v64i1: return VectorType::get(Type::getInt1Ty(Context), 64);		case MVT::v64i1: return VectorType::get(Type::getInt1Ty(Context), 64);
case MVT::v512i1: return VectorType::get(Type::getInt1Ty(Context), 512);		case MVT::v512i1: return VectorType::get(Type::getInt1Ty(Context), 512);
case MVT::v1024i1: return VectorType::get(Type::getInt1Ty(Context), 1024);		case MVT::v1024i1: return VectorType::get(Type::getInt1Ty(Context), 1024);
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lib/Target/X86/X86CallingConv.td

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// X86-64 Intel regcall calling convention.		// X86-64 Intel regcall calling convention.
multiclass X86_RegCall_base<RC_X86_RegCall RC> {		multiclass X86_RegCall_base<RC_X86_RegCall RC> {
def CC_#NAME : CallingConv<[		def CC_#NAME : CallingConv<[
// Handles byval parameters.		// Handles byval parameters.
CCIfSubtarget<"is64Bit()", CCIfByVal<CCPassByVal<8, 8>>>,		CCIfSubtarget<"is64Bit()", CCIfByVal<CCPassByVal<8, 8>>>,
CCIfByVal<CCPassByVal<4, 4>>,		CCIfByVal<CCPassByVal<4, 4>>,

// Promote i1/i8/i16 arguments to i32.		// Promote i1/i8/i16 arguments to i32.
		craig.topperUnsubmitted Done Reply Inline Actions Update comment craig.topper: Update comment
CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,		CCIfType<[v1i1, i8, i16], CCPromoteToType<i32>>,
		craig.topperUnsubmitted Done Reply Inline Actions Merge with the line below and have 4 types? craig.topper: Merge with the line below and have 4 types?

// Promote v8i1/v16i1/v32i1 arguments to i32.		// Promote v8i1/v16i1/v32i1 arguments to i32.
CCIfType<[v8i1, v16i1, v32i1], CCPromoteToType<i32>>,		CCIfType<[v8i1, v16i1, v32i1], CCPromoteToType<i32>>,

// bool, char, int, enum, long, pointer --> GPR		// bool, char, int, enum, long, pointer --> GPR
CCIfType<[i32], CCAssignToReg<RC.GPR_32>>,		CCIfType<[i32], CCAssignToReg<RC.GPR_32>>,

// long long, __int64 --> GPR		// long long, __int64 --> GPR
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines	// Handles byval parameters.
CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],		CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
CCAssignToStack<32, 32>>,		CCAssignToStack<32, 32>>,

// 512-bit vectors get 64-byte stack slots that are 64-byte aligned.		// 512-bit vectors get 64-byte stack slots that are 64-byte aligned.
CCIfType<[v16i32, v8i64, v16f32, v8f64], CCAssignToStack<64, 64>>		CCIfType<[v16i32, v8i64, v16f32, v8f64], CCAssignToStack<64, 64>>
]>;		]>;

def RetCC_#NAME : CallingConv<[		def RetCC_#NAME : CallingConv<[
// Promote i1, v8i1 arguments to i8.		// Promote i1, v8i1 arguments to i8.
		craig.topperUnsubmitted Done Reply Inline Actions Update comment craig.topper: Update comment
CCIfType<[i1, v8i1], CCPromoteToType<i8>>,		CCIfType<[v1i1, v8i1], CCPromoteToType<i8>>,
		craig.topperUnsubmitted Done Reply Inline Actions Shouldn't this be merge with the line below to list 3 types? craig.topper: Shouldn't this be merge with the line below to list 3 types?

// Promote v16i1 arguments to i16.		// Promote v16i1 arguments to i16.
CCIfType<[v16i1], CCPromoteToType<i16>>,		CCIfType<[v16i1], CCPromoteToType<i16>>,

// Promote v32i1 arguments to i32.		// Promote v32i1 arguments to i32.
CCIfType<[v32i1], CCPromoteToType<i32>>,		CCIfType<[v32i1], CCPromoteToType<i32>>,

// bool, char, int, enum, long, pointer --> GPR		// bool, char, int, enum, long, pointer --> GPR
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines	def RetCC_X86Common : CallingConv<[
// instead. This is because using AH for the second register conflicts with		// instead. This is because using AH for the second register conflicts with
// the way LLVM does multiple return values -- a return of {i16,i8} would end		// the way LLVM does multiple return values -- a return of {i16,i8} would end
// up in AX and AH, which overlap. Front-ends wishing to conform to the ABI		// up in AX and AH, which overlap. Front-ends wishing to conform to the ABI
// for functions that return two i8 values are currently expected to pack the		// for functions that return two i8 values are currently expected to pack the
// values into an i16 (which uses AX, and thus AL:AH).		// values into an i16 (which uses AX, and thus AL:AH).
//		//
// For code that doesn't care about the ABI, we allow returning more than two		// For code that doesn't care about the ABI, we allow returning more than two
// integer values in registers.		// integer values in registers.
CCIfType<[i1], CCPromoteToType<i8>>,		CCIfType<[v1i1], CCPromoteToType<i8>>,
CCIfType<[i8] , CCAssignToReg<[AL, DL, CL]>>,		CCIfType<[i8] , CCAssignToReg<[AL, DL, CL]>>,
CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>,		CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>,
CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>,		CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>,
CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX]>>,		CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX]>>,

// Boolean vectors of AVX-512 are returned in SIMD registers.		// Boolean vectors of AVX-512 are returned in SIMD registers.
// The call from AVX to AVX-512 function should work,		// The call from AVX to AVX-512 function should work,
// since the boolean types in AVX/AVX2 are promoted by default.		// since the boolean types in AVX/AVX2 are promoted by default.
▲ Show 20 Lines • Show All 151 Lines • ▼ Show 20 Lines	def RetCC_X86_64_WebKit_JS : CallingConv<[
CCIfType<[i64], CCAssignToReg<[RAX]>>		CCIfType<[i64], CCAssignToReg<[RAX]>>
]>;		]>;

def RetCC_X86_64_Swift : CallingConv<[		def RetCC_X86_64_Swift : CallingConv<[

CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>,		CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>,

// For integers, ECX, R8D can be used as extra return registers.		// For integers, ECX, R8D can be used as extra return registers.
CCIfType<[i1], CCPromoteToType<i8>>,		CCIfType<[v1i1], CCPromoteToType<i8>>,
CCIfType<[i8] , CCAssignToReg<[AL, DL, CL, R8B]>>,		CCIfType<[i8] , CCAssignToReg<[AL, DL, CL, R8B]>>,
CCIfType<[i16], CCAssignToReg<[AX, DX, CX, R8W]>>,		CCIfType<[i16], CCAssignToReg<[AX, DX, CX, R8W]>>,
CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX, R8D]>>,		CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX, R8D]>>,
CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX, R8]>>,		CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX, R8]>>,

// XMM0, XMM1, XMM2 and XMM3 can be used to return FP values.		// XMM0, XMM1, XMM2 and XMM3 can be used to return FP values.
CCIfType<[f32], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>,		CCIfType<[f32], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>,
CCIfType<[f64], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>,		CCIfType<[f64], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>,
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//===----------------------------------------------------------------------===//		//===----------------------------------------------------------------------===//
// X86-64 Argument Calling Conventions		// X86-64 Argument Calling Conventions
//===----------------------------------------------------------------------===//		//===----------------------------------------------------------------------===//

def CC_X86_64_C : CallingConv<[		def CC_X86_64_C : CallingConv<[
// Handles byval parameters.		// Handles byval parameters.
CCIfByVal<CCPassByVal<8, 8>>,		CCIfByVal<CCPassByVal<8, 8>>,

// Promote i1/i8/i16 arguments to i32.		// Promote i1/i8/i16 arguments to i32.
		craig.topperUnsubmitted Done Reply Inline Actions Update comment. craig.topper: Update comment.
CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,		CCIfType<[v1i1, i8, i16], CCPromoteToType<i32>>,
		craig.topperUnsubmitted Done Reply Inline Actions Isn't the original line redundant? craig.topper: Isn't the original line redundant?

// The 'nest' parameter, if any, is passed in R10.		// The 'nest' parameter, if any, is passed in R10.
CCIfNest<CCIfSubtarget<"isTarget64BitILP32()", CCAssignToReg<[R10D]>>>,		CCIfNest<CCIfSubtarget<"isTarget64BitILP32()", CCAssignToReg<[R10D]>>>,
CCIfNest<CCAssignToReg<[R10]>>,		CCIfNest<CCAssignToReg<[R10]>>,

// Pass SwiftSelf in a callee saved register.		// Pass SwiftSelf in a callee saved register.
CCIfSwiftSelf<CCIfType<[i64], CCAssignToReg<[R13]>>>,		CCIfSwiftSelf<CCIfType<[i64], CCAssignToReg<[R13]>>>,

▲ Show 20 Lines • Show All 81 Lines • ▼ Show 20 Lines	def CC_X86_64_HHVM_C : CallingConv<[
CCDelegateTo<CC_X86_64_C>		CCDelegateTo<CC_X86_64_C>
]>;		]>;

// Calling convention used on Win64		// Calling convention used on Win64
def CC_X86_Win64_C : CallingConv<[		def CC_X86_Win64_C : CallingConv<[
// FIXME: Handle byval stuff.		// FIXME: Handle byval stuff.
// FIXME: Handle varargs.		// FIXME: Handle varargs.

// Promote i1/i8/i16 arguments to i32.		// Promote i1/i8/i16 arguments to i32.
		craig.topperUnsubmitted Done Reply Inline Actions Update comment craig.topper: Update comment
CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,		CCIfType<[v1i1, i8, i16], CCPromoteToType<i32>>,
		craig.topperUnsubmitted Done Reply Inline Actions Isn't the old line here redundant? craig.topper: Isn't the old line here redundant?

// The 'nest' parameter, if any, is passed in R10.		// The 'nest' parameter, if any, is passed in R10.
CCIfNest<CCAssignToReg<[R10]>>,		CCIfNest<CCAssignToReg<[R10]>>,

// 128 bit vectors are passed by pointer		// 128 bit vectors are passed by pointer
CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCPassIndirect<i64>>,		CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCPassIndirect<i64>>,


▲ Show 20 Lines • Show All 194 Lines • ▼ Show 20 Lines	def CC_X86_32_Common : CallingConv<[
// Darwin passes vectors in a form that differs from the i386 psABI		// Darwin passes vectors in a form that differs from the i386 psABI
CCIfSubtarget<"isTargetDarwin()", CCDelegateTo<CC_X86_32_Vector_Darwin>>,		CCIfSubtarget<"isTargetDarwin()", CCDelegateTo<CC_X86_32_Vector_Darwin>>,

// Otherwise, drop to 'normal' X86-32 CC		// Otherwise, drop to 'normal' X86-32 CC
CCDelegateTo<CC_X86_32_Vector_Standard>		CCDelegateTo<CC_X86_32_Vector_Standard>
]>;		]>;

def CC_X86_32_C : CallingConv<[		def CC_X86_32_C : CallingConv<[
// Promote i1/i8/i16 arguments to i32.		// Promote i1/i8/i16 arguments to i32.
		craig.topperUnsubmitted Done Reply Inline Actions Fix the comment craig.topper: Fix the comment
CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,		CCIfType<[v1i1, i8, i16], CCPromoteToType<i32>>,
		craig.topperUnsubmitted Done Reply Inline Actions Isn't the second line here redundant? craig.topper: Isn't the second line here redundant?

// The 'nest' parameter, if any, is passed in ECX.		// The 'nest' parameter, if any, is passed in ECX.
CCIfNest<CCAssignToReg<[ECX]>>,		CCIfNest<CCAssignToReg<[ECX]>>,

// The first 3 integer arguments, if marked 'inreg' and if the call is not		// The first 3 integer arguments, if marked 'inreg' and if the call is not
// a vararg call, are passed in integer registers.		// a vararg call, are passed in integer registers.
CCIfNotVarArg<CCIfInReg<CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>>>,		CCIfNotVarArg<CCIfInReg<CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>>>,

// Otherwise, same as everything else.		// Otherwise, same as everything else.
CCDelegateTo<CC_X86_32_Common>		CCDelegateTo<CC_X86_32_Common>
]>;		]>;

def CC_X86_32_MCU : CallingConv<[		def CC_X86_32_MCU : CallingConv<[
// Handles byval parameters. Note that, like FastCC, we can't rely on		// Handles byval parameters. Note that, like FastCC, we can't rely on
// the delegation to CC_X86_32_Common because that happens after code that		// the delegation to CC_X86_32_Common because that happens after code that
// puts arguments in registers.		// puts arguments in registers.
CCIfByVal<CCPassByVal<4, 4>>,		CCIfByVal<CCPassByVal<4, 4>>,

// Promote i1/i8/i16 arguments to i32.		// Promote i1/i8/i16 arguments to i32.
CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,		CCIfType<[v1i1, i8, i16], CCPromoteToType<i32>>,
		craig.topperUnsubmitted Done Reply Inline Actions Merge with the line below and fix comment craig.topper: Merge with the line below and fix comment

// If the call is not a vararg call, some arguments may be passed		// If the call is not a vararg call, some arguments may be passed
// in integer registers.		// in integer registers.
CCIfNotVarArg<CCIfType<[i32], CCCustom<"CC_X86_32_MCUInReg">>>,		CCIfNotVarArg<CCIfType<[i32], CCCustom<"CC_X86_32_MCUInReg">>>,

// Otherwise, same as everything else.		// Otherwise, same as everything else.
CCDelegateTo<CC_X86_32_Common>		CCDelegateTo<CC_X86_32_Common>
]>;		]>;

def CC_X86_32_FastCall : CallingConv<[		def CC_X86_32_FastCall : CallingConv<[
// Promote i1/i8/i16 arguments to i32.		// Promote i1/i8/i16 arguments to i32.
CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,		CCIfType<[v1i1, i8, i16], CCPromoteToType<i32>>,
		craig.topperUnsubmitted Done Reply Inline Actions Merge with the line below and fix comment craig.topper: Merge with the line below and fix comment

// The 'nest' parameter, if any, is passed in EAX.		// The 'nest' parameter, if any, is passed in EAX.
CCIfNest<CCAssignToReg<[EAX]>>,		CCIfNest<CCAssignToReg<[EAX]>>,

// The first 2 integer arguments are passed in ECX/EDX		// The first 2 integer arguments are passed in ECX/EDX
CCIfInReg<CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>>,		CCIfInReg<CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>>,

// Otherwise, same as everything else.		// Otherwise, same as everything else.
Show All 13 Lines	def CC_X86_32_ThisCall_Common : CallingConv<[
CCIfType<[i32], CCAssignToReg<[ECX]>>,		CCIfType<[i32], CCAssignToReg<[ECX]>>,

// Otherwise, same as everything else.		// Otherwise, same as everything else.
CCDelegateTo<CC_X86_32_Common>		CCDelegateTo<CC_X86_32_Common>
]>;		]>;

def CC_X86_32_ThisCall_Mingw : CallingConv<[		def CC_X86_32_ThisCall_Mingw : CallingConv<[
// Promote i1/i8/i16 arguments to i32.		// Promote i1/i8/i16 arguments to i32.
CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,		CCIfType<[v1i1, i8, i16], CCPromoteToType<i32>>,
		craig.topperUnsubmitted Done Reply Inline Actions Merge with the line below and fix comment craig.topper: Merge with the line below and fix comment

CCDelegateTo<CC_X86_32_ThisCall_Common>		CCDelegateTo<CC_X86_32_ThisCall_Common>
]>;		]>;

def CC_X86_32_ThisCall_Win : CallingConv<[		def CC_X86_32_ThisCall_Win : CallingConv<[
// Promote i1/i8/i16 arguments to i32.		// Promote i1/i8/i16 arguments to i32.
CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,		CCIfType<[v1i1, i8, i16], CCPromoteToType<i32>>,
		craig.topperUnsubmitted Done Reply Inline Actions Merge with the line below and fix comment. craig.topper: Merge with the line below and fix comment.

// Pass sret arguments indirectly through stack.		// Pass sret arguments indirectly through stack.
CCIfSRet<CCAssignToStack<4, 4>>,		CCIfSRet<CCAssignToStack<4, 4>>,

CCDelegateTo<CC_X86_32_ThisCall_Common>		CCDelegateTo<CC_X86_32_ThisCall_Common>
]>;		]>;

def CC_X86_32_ThisCall : CallingConv<[		def CC_X86_32_ThisCall : CallingConv<[
CCIfSubtarget<"isTargetCygMing()", CCDelegateTo<CC_X86_32_ThisCall_Mingw>>,		CCIfSubtarget<"isTargetCygMing()", CCDelegateTo<CC_X86_32_ThisCall_Mingw>>,
CCDelegateTo<CC_X86_32_ThisCall_Win>		CCDelegateTo<CC_X86_32_ThisCall_Win>
]>;		]>;

def CC_X86_32_FastCC : CallingConv<[		def CC_X86_32_FastCC : CallingConv<[
// Handles byval parameters. Note that we can't rely on the delegation		// Handles byval parameters. Note that we can't rely on the delegation
// to CC_X86_32_Common for this because that happens after code that		// to CC_X86_32_Common for this because that happens after code that
// puts arguments in registers.		// puts arguments in registers.
CCIfByVal<CCPassByVal<4, 4>>,		CCIfByVal<CCPassByVal<4, 4>>,

// Promote i1/i8/i16 arguments to i32.		// Promote i1/i8/i16 arguments to i32.
CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,		CCIfType<[v1i1, i8, i16], CCPromoteToType<i32>>,
		craig.topperUnsubmitted Done Reply Inline Actions Merge with the line below and fix comment craig.topper: Merge with the line below and fix comment

// The 'nest' parameter, if any, is passed in EAX.		// The 'nest' parameter, if any, is passed in EAX.
CCIfNest<CCAssignToReg<[EAX]>>,		CCIfNest<CCAssignToReg<[EAX]>>,

// The first 2 integer arguments are passed in ECX/EDX		// The first 2 integer arguments are passed in ECX/EDX
CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>,		CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>,

// The first 3 float or double arguments, if the call is not a vararg		// The first 3 float or double arguments, if the call is not a vararg
▲ Show 20 Lines • Show All 226 Lines • Show Last 20 Lines

lib/Target/X86/X86ISelLowering.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

Show First 20 Lines • Show All 1,165 Lines • ▼ Show 20 Lines
}		}

if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512()) {		if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512()) {
addRegisterClass(MVT::v16i32, &X86::VR512RegClass);		addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
addRegisterClass(MVT::v16f32, &X86::VR512RegClass);		addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
addRegisterClass(MVT::v8i64, &X86::VR512RegClass);		addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
addRegisterClass(MVT::v8f64, &X86::VR512RegClass);		addRegisterClass(MVT::v8f64, &X86::VR512RegClass);

addRegisterClass(MVT::i1, &X86::VK1RegClass);		addRegisterClass(MVT::v1i1, &X86::VK1RegClass);
addRegisterClass(MVT::v8i1, &X86::VK8RegClass);		addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
addRegisterClass(MVT::v16i1, &X86::VK16RegClass);		addRegisterClass(MVT::v16i1, &X86::VK16RegClass);

for (MVT VT : MVT::fp_vector_valuetypes())		for (MVT VT : MVT::fp_vector_valuetypes())
setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);		setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);

for (auto ExtType : {ISD::ZEXTLOAD, ISD::SEXTLOAD, ISD::EXTLOAD}) {		for (auto ExtType : {ISD::ZEXTLOAD, ISD::SEXTLOAD, ISD::EXTLOAD}) {
setLoadExtAction(ExtType, MVT::v16i32, MVT::v16i8, Legal);		setLoadExtAction(ExtType, MVT::v16i32, MVT::v16i8, Legal);
setLoadExtAction(ExtType, MVT::v16i32, MVT::v16i16, Legal);		setLoadExtAction(ExtType, MVT::v16i32, MVT::v16i16, Legal);
setLoadExtAction(ExtType, MVT::v32i16, MVT::v32i8, Legal);		setLoadExtAction(ExtType, MVT::v32i16, MVT::v32i8, Legal);
setLoadExtAction(ExtType, MVT::v8i64, MVT::v8i8, Legal);		setLoadExtAction(ExtType, MVT::v8i64, MVT::v8i8, Legal);
setLoadExtAction(ExtType, MVT::v8i64, MVT::v8i16, Legal);		setLoadExtAction(ExtType, MVT::v8i64, MVT::v8i16, Legal);
setLoadExtAction(ExtType, MVT::v8i64, MVT::v8i32, Legal);		setLoadExtAction(ExtType, MVT::v8i64, MVT::v8i32, Legal);
}		}
setOperationAction(ISD::BR_CC, MVT::i1, Expand);
setOperationAction(ISD::SETCC, MVT::i1, Custom);
setOperationAction(ISD::SETCCE, MVT::i1, Custom);
setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
setOperationAction(ISD::XOR, MVT::i1, Legal);
setOperationAction(ISD::OR, MVT::i1, Legal);
setOperationAction(ISD::AND, MVT::i1, Legal);
setOperationAction(ISD::SUB, MVT::i1, Custom);
setOperationAction(ISD::ADD, MVT::i1, Custom);
setOperationAction(ISD::MUL, MVT::i1, Custom);

for (MVT VT : {MVT::v2i64, MVT::v4i32, MVT::v8i32, MVT::v4i64, MVT::v8i16,		for (MVT VT : {MVT::v2i64, MVT::v4i32, MVT::v8i32, MVT::v4i64, MVT::v8i16,
MVT::v16i8, MVT::v16i16, MVT::v32i8, MVT::v16i32,		MVT::v16i8, MVT::v16i16, MVT::v32i8, MVT::v16i32,
MVT::v8i64, MVT::v32i16, MVT::v64i8}) {		MVT::v8i64, MVT::v32i16, MVT::v64i8}) {
MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());		MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
setLoadExtAction(ISD::SEXTLOAD, VT, MaskVT, Custom);		setLoadExtAction(ISD::SEXTLOAD, VT, MaskVT, Custom);
setLoadExtAction(ISD::ZEXTLOAD, VT, MaskVT, Custom);		setLoadExtAction(ISD::ZEXTLOAD, VT, MaskVT, Custom);
setLoadExtAction(ISD::EXTLOAD, VT, MaskVT, Custom);		setLoadExtAction(ISD::EXTLOAD, VT, MaskVT, Custom);
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines	if (Subtarget.hasVLX()){
setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);		setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
} else {		} else {
for (auto VT : {MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,		for (auto VT : {MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
MVT::v4f32, MVT::v8f32, MVT::v2f64, MVT::v4f64}) {		MVT::v4f32, MVT::v8f32, MVT::v2f64, MVT::v4f64}) {
setOperationAction(ISD::MLOAD, VT, Custom);		setOperationAction(ISD::MLOAD, VT, Custom);
setOperationAction(ISD::MSTORE, VT, Custom);		setOperationAction(ISD::MSTORE, VT, Custom);
}		}
}		}
setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);		setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);		setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i1, Custom);		setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i1, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i1, Custom);		setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i1, Custom);
setOperationAction(ISD::VSELECT, MVT::v8i1, Expand);		setOperationAction(ISD::VSELECT, MVT::v8i1, Expand);
setOperationAction(ISD::VSELECT, MVT::v16i1, Expand);		setOperationAction(ISD::VSELECT, MVT::v16i1, Expand);
if (Subtarget.hasDQI()) {		if (Subtarget.hasDQI()) {
setOperationAction(ISD::SINT_TO_FP, MVT::v8i64, Legal);		setOperationAction(ISD::SINT_TO_FP, MVT::v8i64, Legal);
▲ Show 20 Lines • Show All 78 Lines • ▼ Show 20 Lines	if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512()) {
setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);		setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Custom);		setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Custom);

setOperationAction(ISD::SETCC, MVT::v16i1, Custom);		setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
setOperationAction(ISD::SETCC, MVT::v8i1, Custom);		setOperationAction(ISD::SETCC, MVT::v8i1, Custom);

setOperationAction(ISD::MUL, MVT::v8i64, Custom);		setOperationAction(ISD::MUL, MVT::v8i64, Custom);

		setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v1i1, Custom);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);		setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);		setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v16i1, Custom);		setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v16i1, Custom);
setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);		setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);		setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
		setOperationAction(ISD::BUILD_VECTOR, MVT::v1i1, Custom);
setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);		setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);		setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
setOperationAction(ISD::SELECT, MVT::v8f64, Custom);		setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
setOperationAction(ISD::SELECT, MVT::v8i64, Custom);		setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
setOperationAction(ISD::SELECT, MVT::v16f32, Custom);		setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
setOperationAction(ISD::SELECT, MVT::v16i1, Custom);		setOperationAction(ISD::SELECT, MVT::v16i1, Custom);
setOperationAction(ISD::SELECT, MVT::v8i1, Custom);		setOperationAction(ISD::SELECT, MVT::v8i1, Custom);

▲ Show 20 Lines • Show All 392 Lines • ▼ Show 20 Lines	X86TargetLowering::getPreferredVectorAction(EVT VT) const {

return TargetLoweringBase::getPreferredVectorAction(VT);		return TargetLoweringBase::getPreferredVectorAction(VT);
}		}

EVT X86TargetLowering::getSetCCResultType(const DataLayout &DL,		EVT X86TargetLowering::getSetCCResultType(const DataLayout &DL,
LLVMContext& Context,		LLVMContext& Context,
EVT VT) const {		EVT VT) const {
if (!VT.isVector())		if (!VT.isVector())
return Subtarget.hasAVX512() ? MVT::i1: MVT::i8;		return MVT::i8;

if (VT.isSimple()) {		if (VT.isSimple()) {
MVT VVT = VT.getSimpleVT();		MVT VVT = VT.getSimpleVT();
const unsigned NumElts = VVT.getVectorNumElements();		const unsigned NumElts = VVT.getVectorNumElements();
MVT EltVT = VVT.getVectorElementType();		MVT EltVT = VVT.getVectorElementType();
if (VVT.is512BitVector()) {		if (VVT.is512BitVector()) {
if (Subtarget.hasAVX512())		if (Subtarget.hasAVX512())
if (EltVT == MVT::i32 \|\| EltVT == MVT::i64 \|\|		if (EltVT == MVT::i32 \|\| EltVT == MVT::i64 \|\|
▲ Show 20 Lines • Show All 756 Lines • ▼ Show 20 Lines
/// The function will lower a register of various sizes (8/16/32/64)		/// The function will lower a register of various sizes (8/16/32/64)
/// to a mask value of the expected size (v8i1/v16i1/v32i1/v64i1)		/// to a mask value of the expected size (v8i1/v16i1/v32i1/v64i1)
/// \returns a DAG node contains the operand after lowering to mask type.		/// \returns a DAG node contains the operand after lowering to mask type.
static SDValue lowerRegToMasks(const SDValue &ValArg, const EVT &ValVT,		static SDValue lowerRegToMasks(const SDValue &ValArg, const EVT &ValVT,
const EVT &ValLoc, const SDLoc &Dl,		const EVT &ValLoc, const SDLoc &Dl,
SelectionDAG &DAG) {		SelectionDAG &DAG) {
SDValue ValReturned = ValArg;		SDValue ValReturned = ValArg;

		if (ValVT == MVT::v1i1)
		return DAG.getNode(ISD::SCALAR_TO_VECTOR, Dl, MVT::v1i1, ValReturned);

if (ValVT == MVT::v64i1) {		if (ValVT == MVT::v64i1) {
// In 32 bit machine, this case is handled by getv64i1Argument		// In 32 bit machine, this case is handled by getv64i1Argument
assert(ValLoc == MVT::i64 && "Expecting only i64 locations");		assert(ValLoc == MVT::i64 && "Expecting only i64 locations");
// In 64 bit machine, There is no need to truncate the value only bitcast		// In 64 bit machine, There is no need to truncate the value only bitcast
} else {		} else {
MVT maskLen;		MVT maskLen;
switch (ValVT.getSimpleVT().SimpleTy) {		switch (ValVT.getSimpleVT().SimpleTy) {
case MVT::v8i1:		case MVT::v8i1:
maskLen = MVT::i8;		maskLen = MVT::i8;
break;		break;
case MVT::v16i1:		case MVT::v16i1:
maskLen = MVT::i16;		maskLen = MVT::i16;
break;		break;
case MVT::v32i1:		case MVT::v32i1:
maskLen = MVT::i32;		maskLen = MVT::i32;
break;		break;
default:		default:
llvm_unreachable("Expecting a vector of i1 types");		llvm_unreachable("Expecting a vector of i1 types");
}		}

ValReturned = DAG.getNode(ISD::TRUNCATE, Dl, maskLen, ValReturned);		ValReturned = DAG.getNode(ISD::TRUNCATE, Dl, maskLen, ValReturned);
}		}

return DAG.getBitcast(ValVT, ValReturned);		return DAG.getBitcast(ValVT, ValReturned);
}		}

/// Lower the result values of a call into the		/// Lower the result values of a call into the
/// appropriate copies out of appropriate physical registers.		/// appropriate copies out of appropriate physical registers.
///		///
SDValue X86TargetLowering::LowerCallResult(		SDValue X86TargetLowering::LowerCallResult(
SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,		SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
▲ Show 20 Lines • Show All 289 Lines • ▼ Show 20 Lines	X86TargetLowering::LowerMemArgument(SDValue Chain, CallingConv::ID CallConv,
if (CallConv == CallingConv::X86_INTR) {		if (CallConv == CallingConv::X86_INTR) {
MFI.setObjectOffset(FI, Offset);		MFI.setObjectOffset(FI, Offset);
}		}

SDValue FIN = DAG.getFrameIndex(FI, PtrVT);		SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
SDValue Val = DAG.getLoad(		SDValue Val = DAG.getLoad(
ValVT, dl, Chain, FIN,		ValVT, dl, Chain, FIN,
MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));		MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
return ExtendedInMem ? DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val)		return ExtendedInMem
		? (VA.getValVT().isVector()
		? DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VA.getValVT(), Val)
		: DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val))
: Val;		: Val;
}		}

// FIXME: Get this from tablegen.		// FIXME: Get this from tablegen.
static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,		static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
const X86Subtarget &Subtarget) {		const X86Subtarget &Subtarget) {
assert(Subtarget.is64Bit());		assert(Subtarget.is64Bit());

if (Subtarget.isCallingConvWin64(CallConv)) {		if (Subtarget.isCallingConvWin64(CallConv)) {
▲ Show 20 Lines • Show All 133 Lines • ▼ Show 20 Lines	if (VA.isRegLoc()) {
else if (RegVT.is512BitVector())		else if (RegVT.is512BitVector())
RC = &X86::VR512RegClass;		RC = &X86::VR512RegClass;
else if (RegVT.is256BitVector())		else if (RegVT.is256BitVector())
RC = Subtarget.hasVLX() ? &X86::VR256XRegClass : &X86::VR256RegClass;		RC = Subtarget.hasVLX() ? &X86::VR256XRegClass : &X86::VR256RegClass;
else if (RegVT.is128BitVector())		else if (RegVT.is128BitVector())
RC = Subtarget.hasVLX() ? &X86::VR128XRegClass : &X86::VR128RegClass;		RC = Subtarget.hasVLX() ? &X86::VR128XRegClass : &X86::VR128RegClass;
else if (RegVT == MVT::x86mmx)		else if (RegVT == MVT::x86mmx)
RC = &X86::VR64RegClass;		RC = &X86::VR64RegClass;
else if (RegVT == MVT::i1)		else if (RegVT == MVT::v1i1)
RC = &X86::VK1RegClass;		RC = &X86::VK1RegClass;
else if (RegVT == MVT::v8i1)		else if (RegVT == MVT::v8i1)
RC = &X86::VK8RegClass;		RC = &X86::VK8RegClass;
else if (RegVT == MVT::v16i1)		else if (RegVT == MVT::v16i1)
RC = &X86::VK16RegClass;		RC = &X86::VK16RegClass;
else if (RegVT == MVT::v32i1)		else if (RegVT == MVT::v32i1)
RC = &X86::VK32RegClass;		RC = &X86::VK32RegClass;
else if (RegVT == MVT::v64i1)		else if (RegVT == MVT::v64i1)
▲ Show 20 Lines • Show All 3,902 Lines • ▼ Show 20 Lines
static SDValue ConvertI1VectorToInteger(SDValue Op, SelectionDAG &DAG) {		static SDValue ConvertI1VectorToInteger(SDValue Op, SelectionDAG &DAG) {
assert(ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) &&		assert(ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) &&
Op.getScalarValueSizeInBits() == 1 &&		Op.getScalarValueSizeInBits() == 1 &&
"Can not convert non-constant vector");		"Can not convert non-constant vector");
uint64_t Immediate = 0;		uint64_t Immediate = 0;
for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {		for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
SDValue In = Op.getOperand(idx);		SDValue In = Op.getOperand(idx);
if (!In.isUndef())		if (!In.isUndef())
Immediate \|= cast<ConstantSDNode>(In)->getZExtValue() << idx;		Immediate \|= (cast<ConstantSDNode>(In)->getZExtValue() & 0x1) << idx;
}		}
SDLoc dl(Op);		SDLoc dl(Op);
MVT VT = MVT::getIntegerVT(std::max((int)Op.getValueSizeInBits(), 8));		MVT VT = MVT::getIntegerVT(std::max((int)Op.getValueSizeInBits(), 8));
return DAG.getConstant(Immediate, dl, VT);		return DAG.getConstant(Immediate, dl, VT);
}		}
// Lower BUILD_VECTOR operation for v8i1 and v16i1 types.		// Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
SDValue		SDValue
X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {		X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
Show All 26 Lines	X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
int SplatIdx = -1;		int SplatIdx = -1;
for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {		for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
SDValue In = Op.getOperand(idx);		SDValue In = Op.getOperand(idx);
if (In.isUndef())		if (In.isUndef())
continue;		continue;
if (!isa<ConstantSDNode>(In))		if (!isa<ConstantSDNode>(In))
NonConstIdx.push_back(idx);		NonConstIdx.push_back(idx);
else {		else {
Immediate \|= cast<ConstantSDNode>(In)->getZExtValue() << idx;		Immediate \|= (cast<ConstantSDNode>(In)->getZExtValue() & 0x1) << idx;
HasConstElts = true;		HasConstElts = true;
}		}
if (SplatIdx < 0)		if (SplatIdx < 0)
SplatIdx = idx;		SplatIdx = idx;
else if (In != Op.getOperand(SplatIdx))		else if (IsSplat && In != Op.getOperand(SplatIdx))
		craig.topperUnsubmitted Done Reply Inline Actions Why did this if statement need to change? craig.topper: Why did this if statement need to change?
		guyblankAuthorUnsubmitted Not Done Reply Inline Actions just leftovers from other changes i had here which weren't needed. guyblank: just leftovers from other changes i had here which weren't needed.
IsSplat = false;		IsSplat = false;
}		}

// for splat use " (select i1 splat_elt, all-ones, all-zeroes)"		// for splat use " (select i1 splat_elt, all-ones, all-zeroes)"
if (IsSplat)		if (IsSplat)
return DAG.getNode(ISD::SELECT, dl, VT, Op.getOperand(SplatIdx),		return DAG.getNode(ISD::SELECT, dl, VT, Op.getOperand(SplatIdx),
DAG.getConstant(1, dl, VT),		DAG.getConstant(1, dl, VT),
DAG.getConstant(0, dl, VT));		DAG.getConstant(0, dl, VT));
▲ Show 20 Lines • Show All 6,985 Lines • ▼ Show 20 Lines
SDValue		SDValue
X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {		X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
SDValue Vec = Op.getOperand(0);		SDValue Vec = Op.getOperand(0);
SDLoc dl(Vec);		SDLoc dl(Vec);
MVT VecVT = Vec.getSimpleValueType();		MVT VecVT = Vec.getSimpleValueType();
SDValue Idx = Op.getOperand(1);		SDValue Idx = Op.getOperand(1);
MVT EltVT = Op.getSimpleValueType();		MVT EltVT = Op.getSimpleValueType();

assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
assert((VecVT.getVectorNumElements() <= 16 \|\| Subtarget.hasBWI()) &&		assert((VecVT.getVectorNumElements() <= 16 \|\| Subtarget.hasBWI()) &&
"Unexpected vector type in ExtractBitFromMaskVector");		"Unexpected vector type in ExtractBitFromMaskVector");

// variable index can't be handled in mask registers,		// variable index can't be handled in mask registers,
// extend vector to VR512/128		// extend vector to VR512/128
if (!isa<ConstantSDNode>(Idx)) {		if (!isa<ConstantSDNode>(Idx)) {
unsigned NumElts = VecVT.getVectorNumElements();		unsigned NumElts = VecVT.getVectorNumElements();
// Extending v8i1/v16i1 to 512-bit get better performance on KNL		// Extending v8i1/v16i1 to 512-bit get better performance on KNL
Show All 17 Lines	Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, VecVT,
DAG.getIntPtrConstant(0, dl));		DAG.getIntPtrConstant(0, dl));
}		}
unsigned MaxSift = VecVT.getVectorNumElements() - 1;		unsigned MaxSift = VecVT.getVectorNumElements() - 1;
if (MaxSift - IdxVal)		if (MaxSift - IdxVal)
Vec = DAG.getNode(X86ISD::KSHIFTL, dl, VecVT, Vec,		Vec = DAG.getNode(X86ISD::KSHIFTL, dl, VecVT, Vec,
DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));		DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
Vec = DAG.getNode(X86ISD::KSHIFTR, dl, VecVT, Vec,		Vec = DAG.getNode(X86ISD::KSHIFTR, dl, VecVT, Vec,
DAG.getConstant(MaxSift, dl, MVT::i8));		DAG.getConstant(MaxSift, dl, MVT::i8));
return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,		return DAG.getNode(X86ISD::VEXTRACT, dl, Op.getSimpleValueType(), Vec,
DAG.getIntPtrConstant(0, dl));		DAG.getIntPtrConstant(0, dl));
}		}

SDValue		SDValue
X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,		X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
SelectionDAG &DAG) const {		SelectionDAG &DAG) const {
SDLoc dl(Op);		SDLoc dl(Op);
SDValue Vec = Op.getOperand(0);		SDValue Vec = Op.getOperand(0);
MVT VecVT = Vec.getSimpleValueType();		MVT VecVT = Vec.getSimpleValueType();
SDValue Idx = Op.getOperand(1);		SDValue Idx = Op.getOperand(1);

if (Op.getSimpleValueType() == MVT::i1)		if (VecVT.getVectorElementType() == MVT::i1)
		craig.topperUnsubmitted Not Done Reply Inline Actions What's the different between this and the original line? Doesn't Op's VT have to match the elements of the vector? craig.topper: What's the different between this and the original line? Doesn't Op's VT have to match the…
		guyblankAuthorUnsubmitted Not Done Reply Inline Actions since i1 is illegal, Op VT would be i8 when extracting from i1 vectors. it is ok for the return type of extract vector element to be wider than the vector elements. guyblank: since i1 is illegal, Op VT would be i8 when extracting from i1 vectors. it is ok for the…
return ExtractBitFromMaskVector(Op, DAG);		return ExtractBitFromMaskVector(Op, DAG);

if (!isa<ConstantSDNode>(Idx)) {		if (!isa<ConstantSDNode>(Idx)) {
// Its more profitable to go through memory (1 cycles throughput)		// Its more profitable to go through memory (1 cycles throughput)
// than using VMOVD + VPERMV/PSHUFB sequence ( 2/3 cycles throughput)		// than using VMOVD + VPERMV/PSHUFB sequence ( 2/3 cycles throughput)
// IACA tool was used to get performance estimation		// IACA tool was used to get performance estimation
// (https://software.intel.com/en-us/articles/intel-architecture-code-analyzer)		// (https://software.intel.com/en-us/articles/intel-architecture-code-analyzer)
//		//
▲ Show 20 Lines • Show All 154 Lines • ▼ Show 20 Lines	X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {

if(Vec.isUndef()) {		if(Vec.isUndef()) {
if (IdxVal)		if (IdxVal)
EltInVec = DAG.getNode(X86ISD::KSHIFTL, dl, VecVT, EltInVec,		EltInVec = DAG.getNode(X86ISD::KSHIFTL, dl, VecVT, EltInVec,
DAG.getConstant(IdxVal, dl, MVT::i8));		DAG.getConstant(IdxVal, dl, MVT::i8));
return EltInVec;		return EltInVec;
}		}

// Insertion of one bit into first or last position		// Insertion of one bit into first position
// can be done with two SHIFTs + OR.
if (IdxVal == 0 ) {		if (IdxVal == 0 ) {
// EltInVec already at correct index and other bits are 0.		// Clean top bits of vector.
		EltInVec = DAG.getNode(X86ISD::KSHIFTL, dl, VecVT, EltInVec,
		DAG.getConstant(NumElems - 1, dl, MVT::i8));
		EltInVec = DAG.getNode(X86ISD::KSHIFTR, dl, VecVT, EltInVec,
		DAG.getConstant(NumElems - 1, dl, MVT::i8));
// Clean the first bit in source vector.		// Clean the first bit in source vector.
Vec = DAG.getNode(X86ISD::KSHIFTR, dl, VecVT, Vec,		Vec = DAG.getNode(X86ISD::KSHIFTR, dl, VecVT, Vec,
DAG.getConstant(1 , dl, MVT::i8));		DAG.getConstant(1 , dl, MVT::i8));
Vec = DAG.getNode(X86ISD::KSHIFTL, dl, VecVT, Vec,		Vec = DAG.getNode(X86ISD::KSHIFTL, dl, VecVT, Vec,
DAG.getConstant(1, dl, MVT::i8));		DAG.getConstant(1, dl, MVT::i8));

return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);		return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
}		}
		// Insertion of one bit into last position
if (IdxVal == NumElems -1) {		if (IdxVal == NumElems -1) {
// Move the bit to the last position inside the vector.		// Move the bit to the last position inside the vector.
EltInVec = DAG.getNode(X86ISD::KSHIFTL, dl, VecVT, EltInVec,		EltInVec = DAG.getNode(X86ISD::KSHIFTL, dl, VecVT, EltInVec,
DAG.getConstant(IdxVal, dl, MVT::i8));		DAG.getConstant(IdxVal, dl, MVT::i8));
// Clean the last bit in the source vector.		// Clean the last bit in the source vector.
Vec = DAG.getNode(X86ISD::KSHIFTL, dl, VecVT, Vec,		Vec = DAG.getNode(X86ISD::KSHIFTL, dl, VecVT, Vec,
DAG.getConstant(1, dl, MVT::i8));		DAG.getConstant(1, dl, MVT::i8));
Vec = DAG.getNode(X86ISD::KSHIFTR, dl, VecVT, Vec,		Vec = DAG.getNode(X86ISD::KSHIFTR, dl, VecVT, Vec,
▲ Show 20 Lines • Show All 3,134 Lines • ▼ Show 20 Lines
}		}

SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {		SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {

MVT VT = Op.getSimpleValueType();		MVT VT = Op.getSimpleValueType();

if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);		if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);

assert(((!Subtarget.hasAVX512() && VT == MVT::i8) \|\| (VT == MVT::i1))		assert(VT == MVT::i8 && "SetCC type must be 8-bit integer");
&& "SetCC type must be 8-bit or 1-bit integer");
SDValue Op0 = Op.getOperand(0);		SDValue Op0 = Op.getOperand(0);
SDValue Op1 = Op.getOperand(1);		SDValue Op1 = Op.getOperand(1);
SDLoc dl(Op);		SDLoc dl(Op);
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();		ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();

// Optimize to BT if possible.		// Optimize to BT if possible.
// Lower (X & (1 << N)) == 0 to BT(X, N).		// Lower (X & (1 << N)) == 0 to BT(X, N).
// Lower ((X >>u N) & 1) != 0 to BT(X, N).		// Lower ((X >>u N) & 1) != 0 to BT(X, N).
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines	if (Cond.getOpcode() == ISD::SETCC &&
(Subtarget.hasSSE1() && VT == MVT::f32)) &&		(Subtarget.hasSSE1() && VT == MVT::f32)) &&
VT == Cond.getOperand(0).getSimpleValueType() && Cond->hasOneUse()) {		VT == Cond.getOperand(0).getSimpleValueType() && Cond->hasOneUse()) {
SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);		SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
int SSECC = translateX86FSETCC(		int SSECC = translateX86FSETCC(
cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);		cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);

if (SSECC != 8) {		if (SSECC != 8) {
if (Subtarget.hasAVX512()) {		if (Subtarget.hasAVX512()) {
SDValue Cmp = DAG.getNode(X86ISD::FSETCCM, DL, MVT::i1, CondOp0,		SDValue Cmp = DAG.getNode(X86ISD::FSETCCM, DL, MVT::v1i1, CondOp0,
CondOp1, DAG.getConstant(SSECC, DL, MVT::i8));		CondOp1, DAG.getConstant(SSECC, DL, MVT::i8));
return DAG.getNode(VT.isVector() ? X86ISD::SELECT : X86ISD::SELECTS,		return DAG.getNode(VT.isVector() ? X86ISD::SELECT : X86ISD::SELECTS,
DL, VT, Cmp, Op1, Op2);		DL, VT, Cmp, Op1, Op2);
}		}

SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,		SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
DAG.getConstant(SSECC, DL, MVT::i8));		DAG.getConstant(SSECC, DL, MVT::i8));

Show All 31 Lines	if (SSECC != 8) {
}		}
SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);		SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);		SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);		return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
}		}
}		}

// AVX512 fallback is to lower selects of scalar floats to masked moves.		// AVX512 fallback is to lower selects of scalar floats to masked moves.
if (Cond.getValueType() == MVT::i1 && (VT == MVT::f64 \|\| VT == MVT::f32) &&		if ((VT == MVT::f64 \|\| VT == MVT::f32) && Subtarget.hasAVX512()) {
Subtarget.hasAVX512())		SDValue Cmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v1i1, Cond);
return DAG.getNode(X86ISD::SELECTS, DL, VT, Cond, Op1, Op2);		return DAG.getNode(X86ISD::SELECTS, DL, VT, Cmp, Op1, Op2);
		}

if (VT.isVector() && VT.getVectorElementType() == MVT::i1) {		if (VT.isVector() && VT.getVectorElementType() == MVT::i1) {
SDValue Op1Scalar;		SDValue Op1Scalar;
if (ISD::isBuildVectorOfConstantSDNodes(Op1.getNode()))		if (ISD::isBuildVectorOfConstantSDNodes(Op1.getNode()))
Op1Scalar = ConvertI1VectorToInteger(Op1, DAG);		Op1Scalar = ConvertI1VectorToInteger(Op1, DAG);
else if (Op1.getOpcode() == ISD::BITCAST && Op1.getOperand(0))		else if (Op1.getOpcode() == ISD::BITCAST && Op1.getOperand(0))
Op1Scalar = Op1.getOperand(0);		Op1Scalar = Op1.getOperand(0);
SDValue Op2Scalar;		SDValue Op2Scalar;
▲ Show 20 Lines • Show All 1,526 Lines • ▼ Show 20 Lines	static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
}		}
if (PreservedSrc.isUndef())		if (PreservedSrc.isUndef())
PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);		PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
return DAG.getNode(OpcodeSelect, dl, VT, VMask, Op, PreservedSrc);		return DAG.getNode(OpcodeSelect, dl, VT, VMask, Op, PreservedSrc);
}		}

/// \brief Creates an SDNode for a predicated scalar operation.		/// \brief Creates an SDNode for a predicated scalar operation.
/// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).		/// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
/// The mask is coming as MVT::i8 and it should be truncated		/// The mask is coming as MVT::i8 and it should be transformed
/// to MVT::i1 while lowering masking intrinsics.		/// to MVT::v1i1 while lowering masking intrinsics.
/// The main difference between ScalarMaskingNode and VectorMaskingNode is using		/// The main difference between ScalarMaskingNode and VectorMaskingNode is using
/// "X86select" instead of "vselect". We just can't create the "vselect" node		/// "X86select" instead of "vselect". We just can't create the "vselect" node
/// for a scalar instruction.		/// for a scalar instruction.
static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,		static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
SDValue PreservedSrc,		SDValue PreservedSrc,
const X86Subtarget &Subtarget,		const X86Subtarget &Subtarget,
SelectionDAG &DAG) {		SelectionDAG &DAG) {
if (isAllOnesConstant(Mask))
return Op;

MVT VT = Op.getSimpleValueType();		MVT VT = Op.getSimpleValueType();
SDLoc dl(Op);		SDLoc dl(Op);
// The mask should be of type MVT::i1
SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);		if (auto *MaskConst = dyn_cast<ConstantSDNode>(Mask)) {
		if (MaskConst->getZExtValue() & 0x1)
		return Op;
		return PreservedSrc.isUndef() ? getZeroVector(VT, Subtarget, DAG, dl)
		: PreservedSrc;
		}

if (Op.getOpcode() == X86ISD::FSETCCM \|\|		if (Op.getOpcode() == X86ISD::FSETCCM \|\|
Op.getOpcode() == X86ISD::FSETCCM_RND)		Op.getOpcode() == X86ISD::FSETCCM_RND) {
		SDValue IMask = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i1, Mask);
return DAG.getNode(ISD::AND, dl, VT, Op, IMask);		return DAG.getNode(ISD::AND, dl, VT, Op, IMask);
if (Op.getOpcode() == X86ISD::VFPCLASS \|\|		}
Op.getOpcode() == X86ISD::VFPCLASSS)		if (Op.getOpcode() == X86ISD::VFPCLASSS) {
		craig.topperUnsubmitted Done Reply Inline Actions This seems like an unrelated cleanup. Commit separately? Why are curly braces being added? craig.topper: This seems like an unrelated cleanup. Commit separately? Why are curly braces being added?
		SDValue IMask = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i1, Mask);
return DAG.getNode(ISD::OR, dl, VT, Op, IMask);		return DAG.getNode(ISD::OR, dl, VT, Op, IMask);
		}

if (PreservedSrc.isUndef())		if (PreservedSrc.isUndef())
PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);		PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
return DAG.getNode(X86ISD::SELECTS, dl, VT, IMask, Op, PreservedSrc);		return DAG.getNode(X86ISD::SELECTS, dl, VT, Mask, Op, PreservedSrc);
}		}

static int getSEHRegistrationNodeSize(const Function *Fn) {		static int getSEHRegistrationNodeSize(const Function *Fn) {
if (!Fn->hasPersonalityFn())		if (!Fn->hasPersonalityFn())
report_fatal_error(		report_fatal_error(
"querying registration node size for function without personality");		"querying registration node size for function without personality");
// The RegNodeSize is 6 32-bit words for SEH and 4 for C++ EH. See		// The RegNodeSize is 6 32-bit words for SEH and 4 for C++ EH. See
// WinEHStatePass for the full struct definition.		// WinEHStatePass for the full struct definition.
▲ Show 20 Lines • Show All 415 Lines • ▼ Show 20 Lines	case FPCLASS: {
DAG.getUNDEF(BitcastVT), FPclassMask,		DAG.getUNDEF(BitcastVT), FPclassMask,
DAG.getIntPtrConstant(0, dl));		DAG.getIntPtrConstant(0, dl));
return DAG.getBitcast(Op.getValueType(), Res);		return DAG.getBitcast(Op.getValueType(), Res);
}		}
case FPCLASSS: {		case FPCLASSS: {
SDValue Src1 = Op.getOperand(1);		SDValue Src1 = Op.getOperand(1);
SDValue Imm = Op.getOperand(2);		SDValue Imm = Op.getOperand(2);
SDValue Mask = Op.getOperand(3);		SDValue Mask = Op.getOperand(3);
SDValue FPclass = DAG.getNode(IntrData->Opc0, dl, MVT::i1, Src1, Imm);		SDValue FPclass = DAG.getNode(IntrData->Opc0, dl, MVT::v1i1, Src1, Imm);
SDValue FPclassMask = getScalarMaskingNode(FPclass, Mask,		SDValue FPclassMask = getScalarMaskingNode(FPclass, Mask,
DAG.getTargetConstant(0, dl, MVT::i1), Subtarget, DAG);		DAG.getTargetConstant(0, dl, MVT::i1), Subtarget, DAG);
return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, FPclassMask);		return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i8, FPclassMask,
		DAG.getIntPtrConstant(0, dl));
}		}
case CMP_MASK:		case CMP_MASK:
case CMP_MASK_CC: {		case CMP_MASK_CC: {
// Comparison intrinsics with masks.		// Comparison intrinsics with masks.
// Example of transformation:		// Example of transformation:
// (i8 (int_x86_avx512_mask_pcmpeq_q_128		// (i8 (int_x86_avx512_mask_pcmpeq_q_128
// (v2i64 %a), (v2i64 %b), (i8 %mask))) ->		// (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
// (i8 (bitcast		// (i8 (bitcast
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines	case CMP_MASK_SCALAR_CC: {
SDValue Src2 = Op.getOperand(2);		SDValue Src2 = Op.getOperand(2);
SDValue CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(3));		SDValue CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(3));
SDValue Mask = Op.getOperand(4);		SDValue Mask = Op.getOperand(4);

SDValue Cmp;		SDValue Cmp;
if (IntrData->Opc1 != 0) {		if (IntrData->Opc1 != 0) {
SDValue Rnd = Op.getOperand(5);		SDValue Rnd = Op.getOperand(5);
if (!isRoundModeCurDirection(Rnd))		if (!isRoundModeCurDirection(Rnd))
Cmp = DAG.getNode(IntrData->Opc1, dl, MVT::i1, Src1, Src2, CC, Rnd);		Cmp = DAG.getNode(IntrData->Opc1, dl, MVT::v1i1, Src1, Src2, CC, Rnd);
}		}
//default rounding mode		//default rounding mode
if(!Cmp.getNode())		if(!Cmp.getNode())
Cmp = DAG.getNode(IntrData->Opc0, dl, MVT::i1, Src1, Src2, CC);		Cmp = DAG.getNode(IntrData->Opc0, dl, MVT::v1i1, Src1, Src2, CC);

SDValue CmpMask = getScalarMaskingNode(Cmp, Mask,		SDValue CmpMask = getScalarMaskingNode(Cmp, Mask,
DAG.getTargetConstant(0, dl,		DAG.getTargetConstant(0, dl,
MVT::i1),		MVT::i1),
Subtarget, DAG);		Subtarget, DAG);
		return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i8, CmpMask,
return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, CmpMask);		DAG.getIntPtrConstant(0, dl));
}		}
case COMI: { // Comparison intrinsics		case COMI: { // Comparison intrinsics
ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;		ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
SDValue LHS = Op.getOperand(1);		SDValue LHS = Op.getOperand(1);
SDValue RHS = Op.getOperand(2);		SDValue RHS = Op.getOperand(2);
SDValue Comi = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);		SDValue Comi = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
SDValue InvComi = DAG.getNode(IntrData->Opc0, dl, MVT::i32, RHS, LHS);		SDValue InvComi = DAG.getNode(IntrData->Opc0, dl, MVT::i32, RHS, LHS);
SDValue SetCC;		SDValue SetCC;
Show All 31 Lines	if (IntrData) {
case COMI_RM: { // Comparison intrinsics with Sae		case COMI_RM: { // Comparison intrinsics with Sae
SDValue LHS = Op.getOperand(1);		SDValue LHS = Op.getOperand(1);
SDValue RHS = Op.getOperand(2);		SDValue RHS = Op.getOperand(2);
unsigned CondVal = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();		unsigned CondVal = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
SDValue Sae = Op.getOperand(4);		SDValue Sae = Op.getOperand(4);

SDValue FCmp;		SDValue FCmp;
if (isRoundModeCurDirection(Sae))		if (isRoundModeCurDirection(Sae))
FCmp = DAG.getNode(X86ISD::FSETCCM, dl, MVT::i1, LHS, RHS,		FCmp = DAG.getNode(X86ISD::FSETCCM, dl, MVT::v1i1, LHS, RHS,
DAG.getConstant(CondVal, dl, MVT::i8));		DAG.getConstant(CondVal, dl, MVT::i8));
else		else
FCmp = DAG.getNode(X86ISD::FSETCCM_RND, dl, MVT::i1, LHS, RHS,		FCmp = DAG.getNode(X86ISD::FSETCCM_RND, dl, MVT::v1i1, LHS, RHS,
DAG.getConstant(CondVal, dl, MVT::i8), Sae);		DAG.getConstant(CondVal, dl, MVT::i8), Sae);
// AnyExt just uses KMOVW %kreg, %r32; ZeroExt emits "and $1, %reg"		return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i32, FCmp,
return DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, FCmp);		DAG.getIntPtrConstant(0, dl));
}		}
case VSHIFT:		case VSHIFT:
return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),		return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
Op.getOperand(1), Op.getOperand(2), Subtarget,		Op.getOperand(1), Op.getOperand(2), Subtarget,
DAG);		DAG);
case COMPRESS_EXPAND_IN_REG: {		case COMPRESS_EXPAND_IN_REG: {
SDValue Mask = Op.getOperand(3);		SDValue Mask = Op.getOperand(3);
SDValue DataToCompress = Op.getOperand(1);		SDValue DataToCompress = Op.getOperand(1);
▲ Show 20 Lines • Show All 3,722 Lines • ▼ Show 20 Lines	static SDValue ExtendToType(SDValue InOp, MVT NVT, SelectionDAG &DAG,
assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&		assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&
"input and widen element type must match");		"input and widen element type must match");

unsigned InNumElts = InVT.getVectorNumElements();		unsigned InNumElts = InVT.getVectorNumElements();
unsigned WidenNumElts = NVT.getVectorNumElements();		unsigned WidenNumElts = NVT.getVectorNumElements();
assert(WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0 &&		assert(WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0 &&
"Unexpected request for vector widening");		"Unexpected request for vector widening");

EVT EltVT = NVT.getVectorElementType();

SDLoc dl(InOp);		SDLoc dl(InOp);
if (InOp.getOpcode() == ISD::CONCAT_VECTORS &&		if (InOp.getOpcode() == ISD::CONCAT_VECTORS &&
InOp.getNumOperands() == 2) {		InOp.getNumOperands() == 2) {
SDValue N1 = InOp.getOperand(1);		SDValue N1 = InOp.getOperand(1);
if ((ISD::isBuildVectorAllZeros(N1.getNode()) && FillWithZeroes) \|\|		if ((ISD::isBuildVectorAllZeros(N1.getNode()) && FillWithZeroes) \|\|
N1.isUndef()) {		N1.isUndef()) {
InOp = InOp.getOperand(0);		InOp = InOp.getOperand(0);
InVT = InOp.getSimpleValueType();		InVT = InOp.getSimpleValueType();
InNumElts = InVT.getVectorNumElements();		InNumElts = InVT.getVectorNumElements();
}		}
}		}
if (ISD::isBuildVectorOfConstantSDNodes(InOp.getNode()) \|\|		if (ISD::isBuildVectorOfConstantSDNodes(InOp.getNode()) \|\|
ISD::isBuildVectorOfConstantFPSDNodes(InOp.getNode())) {		ISD::isBuildVectorOfConstantFPSDNodes(InOp.getNode())) {
SmallVector<SDValue, 16> Ops;		SmallVector<SDValue, 16> Ops;
for (unsigned i = 0; i < InNumElts; ++i)		for (unsigned i = 0; i < InNumElts; ++i)
Ops.push_back(InOp.getOperand(i));		Ops.push_back(InOp.getOperand(i));

		EVT EltVT = InOp.getOperand(0).getValueType();

SDValue FillVal = FillWithZeroes ? DAG.getConstant(0, dl, EltVT) :		SDValue FillVal = FillWithZeroes ? DAG.getConstant(0, dl, EltVT) :
DAG.getUNDEF(EltVT);		DAG.getUNDEF(EltVT);
for (unsigned i = 0; i < WidenNumElts - InNumElts; ++i)		for (unsigned i = 0; i < WidenNumElts - InNumElts; ++i)
Ops.push_back(FillVal);		Ops.push_back(FillVal);
return DAG.getBuildVector(NVT, dl, Ops);		return DAG.getBuildVector(NVT, dl, Ops);
}		}
SDValue FillVal = FillWithZeroes ? DAG.getConstant(0, dl, NVT) :		SDValue FillVal = FillWithZeroes ? DAG.getConstant(0, dl, NVT) :
DAG.getUNDEF(NVT);		DAG.getUNDEF(NVT);
▲ Show 20 Lines • Show All 6,147 Lines • ▼ Show 20 Lines	combineVSelectWithAllOnesOrZeros(SDNode *N, SelectionDAG &DAG,
assert(CondVT.isVector() && "Vector select expects a vector selector!");		assert(CondVT.isVector() && "Vector select expects a vector selector!");

bool FValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());		bool FValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
// Check if the first operand is all zeros and Cond type is vXi1.		// Check if the first operand is all zeros and Cond type is vXi1.
// This situation only applies to avx512.		// This situation only applies to avx512.
if (FValIsAllZeros && Subtarget.hasAVX512() && Cond.hasOneUse() &&		if (FValIsAllZeros && Subtarget.hasAVX512() && Cond.hasOneUse() &&
CondVT.getVectorElementType() == MVT::i1) {		CondVT.getVectorElementType() == MVT::i1) {
// Invert the cond to not(cond) : xor(op,allones)=not(op)		// Invert the cond to not(cond) : xor(op,allones)=not(op)
SDValue CondNew = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,		SDValue CondNew =
DAG.getAllOnesConstant(DL, CondVT));		DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
		craig.topperUnsubmitted Done Reply Inline Actions Can we reuse CondVT here instead of calling Cond.getValueType() again? Why cant' we use DAG.getAllOnesConstant anymore? Does the constant have different with than CondVT's element type now? What does that do? craig.topper: Can we reuse CondVT here instead of calling Cond.getValueType() again? Why cant' we use DAG.
		guyblankAuthorUnsubmitted Not Done Reply Inline Actions getAllOnesConstant probably just got lost in a merge. there is no issue with it guyblank: getAllOnesConstant probably just got lost in a merge. there is no issue with it
		DAG.getConstant(APInt::getAllOnesValue(8), DL, CondVT));
// Vselect cond, op1, op2 = Vselect not(cond), op2, op1		// Vselect cond, op1, op2 = Vselect not(cond), op2, op1
return DAG.getNode(ISD::VSELECT, DL, VT, CondNew, RHS, LHS);		return DAG.getNode(ISD::VSELECT, DL, VT, CondNew, RHS, LHS);
}		}

// To use the condition operand as a bitwise mask, it must have elements that		// To use the condition operand as a bitwise mask, it must have elements that
// are the same size as the select elements. Ie, the condition operand must		// are the same size as the select elements. Ie, the condition operand must
// have already been promoted from the IR select condition type <N x i1>.		// have already been promoted from the IR select condition type <N x i1>.
// Don't check if the types themselves are equal because that excludes		// Don't check if the types themselves are equal because that excludes
▲ Show 20 Lines • Show All 1,731 Lines • ▼ Show 20 Lines	if (VT == MVT::f32 \|\| VT == MVT::f64) {
}		}

if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) \|\|		if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) \|\|
(cc0 == X86::COND_NE && cc1 == X86::COND_P)) {		(cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
// FIXME: need symbolic constants for these magic numbers.		// FIXME: need symbolic constants for these magic numbers.
// See X86ATTInstPrinter.cpp:printSSECC().		// See X86ATTInstPrinter.cpp:printSSECC().
unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;		unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
if (Subtarget.hasAVX512()) {		if (Subtarget.hasAVX512()) {
SDValue FSetCC = DAG.getNode(X86ISD::FSETCCM, DL, MVT::i1, CMP00,		SDValue FSetCC =
CMP01,		DAG.getNode(X86ISD::FSETCCM, DL, MVT::v1i1, CMP00, CMP01,
DAG.getConstant(x86cc, DL, MVT::i8));		DAG.getConstant(x86cc, DL, MVT::i8));
if (N->getValueType(0) != MVT::i1)		return DAG.getNode(X86ISD::VEXTRACT, DL, N->getSimpleValueType(0),
return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),		FSetCC, DAG.getIntPtrConstant(0, DL));
FSetCC);
return FSetCC;
}		}
SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,		SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
CMP00.getValueType(), CMP00, CMP01,		CMP00.getValueType(), CMP00, CMP01,
DAG.getConstant(x86cc, DL,		DAG.getConstant(x86cc, DL,
MVT::i8));		MVT::i8));

bool is64BitFP = (CMP00.getValueType() == MVT::f64);		bool is64BitFP = (CMP00.getValueType() == MVT::f64);
MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;		MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
▲ Show 20 Lines • Show All 4,713 Lines • Show Last 20 Lines

lib/Target/X86/X86InstrAVX512.td

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Show All 25 Lines	class X86VectorVTInfo<int numelts, ValueType eltvt, RegisterClass rc,

// Corresponding mask register class.		// Corresponding mask register class.
RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);		RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);

// Corresponding write-mask register class.		// Corresponding write-mask register class.
RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");		RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");

// The mask VT.		// The mask VT.
ValueType KVT = !cast<ValueType>(!if (!eq (NumElts, 1), "i1",		ValueType KVT = !cast<ValueType>("v" # NumElts # "i1");
"v" # NumElts # "i1"));

// Suffix used in the instruction mnemonic.		// Suffix used in the instruction mnemonic.
string Suffix = suffix;		string Suffix = suffix;

// VTName is a string name for vector VT. For vector types it will be		// VTName is a string name for vector VT. For vector types it will be
// v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32		// v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32
// It is a little bit complex for scalar types, where NumElts = 1.		// It is a little bit complex for scalar types, where NumElts = 1.
// In this case we build v4f32 or v2f64		// In this case we build v4f32 or v2f64
▲ Show 20 Lines • Show All 2,214 Lines • ▼ Show 20 Lines	def : Pat<(v2i1 (load addr:$src)),
(COPY_TO_REGCLASS (MOVZX32rm8 addr:$src), VK2)>;		(COPY_TO_REGCLASS (MOVZX32rm8 addr:$src), VK2)>;
def : Pat<(v4i1 (load addr:$src)),		def : Pat<(v4i1 (load addr:$src)),
(COPY_TO_REGCLASS (MOVZX32rm8 addr:$src), VK4)>;		(COPY_TO_REGCLASS (MOVZX32rm8 addr:$src), VK4)>;
}		}

let Predicates = [HasAVX512] in {		let Predicates = [HasAVX512] in {
def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),		def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
(KMOVWmk addr:$dst, VK16:$src)>;		(KMOVWmk addr:$dst, VK16:$src)>;
def : Pat<(i1 (load addr:$src)),		def : Pat<(v1i1 (load addr:$src)),
(COPY_TO_REGCLASS (AND32ri8 (MOVZX32rm8 addr:$src), (i32 1)), VK1)>;		(COPY_TO_REGCLASS (AND32ri8 (MOVZX32rm8 addr:$src), (i32 1)), VK1)>;
def : Pat<(v16i1 (bitconvert (i16 (load addr:$src)))),		def : Pat<(v16i1 (bitconvert (i16 (load addr:$src)))),
(KMOVWkm addr:$src)>;		(KMOVWkm addr:$src)>;
}		}
let Predicates = [HasBWI] in {		let Predicates = [HasBWI] in {
def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),		def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
(KMOVDmk addr:$dst, VK32:$src)>;		(KMOVDmk addr:$dst, VK32:$src)>;
def : Pat<(v32i1 (bitconvert (i32 (load addr:$src)))),		def : Pat<(v32i1 (bitconvert (i32 (load addr:$src)))),
(KMOVDkm addr:$src)>;		(KMOVDkm addr:$src)>;
def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),		def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
(KMOVQmk addr:$dst, VK64:$src)>;		(KMOVQmk addr:$dst, VK64:$src)>;
def : Pat<(v64i1 (bitconvert (i64 (load addr:$src)))),		def : Pat<(v64i1 (bitconvert (i64 (load addr:$src)))),
(KMOVQkm addr:$src)>;		(KMOVQkm addr:$src)>;
}		}

let Predicates = [HasAVX512] in {		let Predicates = [HasAVX512] in {
def : Pat<(i1 (trunc (i64 GR64:$src))),		multiclass operation_gpr_mask_copy_lowering<RegisterClass maskRC, ValueType maskVT,
(COPY_TO_REGCLASS (AND32ri8 (EXTRACT_SUBREG $src, sub_32bit),		RegisterClass gprRC, ValueType gprVT> {
(i32 1)), VK1)>;		def : Pat<(maskVT (scalar_to_vector gprRC:$src)),
		(COPY_TO_REGCLASS gprRC:$src, maskRC)>;
		craig.topperUnsubmitted Done Reply Inline Actions Align v16i1 to same column as v8i1 above. craig.topper: Align v16i1 to same column as v8i1 above.

		def : Pat<(gprVT (X86Vextract maskRC:$src, (iPTR 0))),
		(COPY_TO_REGCLASS maskRC:$src, gprRC)>;

		}
		defm : operation_gpr_mask_copy_lowering<VK1, v1i1, GR8, i8>;
		craig.topperUnsubmitted Done Reply Inline Actions The identation on the VK16 seems off. Same with VK8 on the pattern below. craig.topper: The identation on the VK16 seems off. Same with VK8 on the pattern below.
		defm : operation_gpr_mask_copy_lowering<VK2, v2i1, GR8, i8>;
		defm : operation_gpr_mask_copy_lowering<VK4, v4i1, GR8, i8>;
		defm : operation_gpr_mask_copy_lowering<VK8, v8i1, GR8, i8>;
		defm : operation_gpr_mask_copy_lowering<VK16, v16i1, GR8, i8>;
		defm : operation_gpr_mask_copy_lowering<VK32, v32i1, GR8, i8>;
		defm : operation_gpr_mask_copy_lowering<VK64, v64i1, GR8, i8>;

		defm : operation_gpr_mask_copy_lowering<VK1, v1i1, GR32, i32>;
		defm : operation_gpr_mask_copy_lowering<VK2, v2i1, GR32, i32>;
		defm : operation_gpr_mask_copy_lowering<VK4, v4i1, GR32, i32>;
		defm : operation_gpr_mask_copy_lowering<VK8, v8i1, GR32, i32>;
		defm : operation_gpr_mask_copy_lowering<VK16, v16i1, GR32, i32>;
		defm : operation_gpr_mask_copy_lowering<VK32, v32i1, GR32, i32>;
		defm : operation_gpr_mask_copy_lowering<VK64, v64i1, GR32, i32>;

		def : Pat<(i32 (anyext (i8 (X86Vextract VK64:$src, (iPTR 0))))), (COPY_TO_REGCLASS VK64:$src, GR32)>;
		def : Pat<(i32 (anyext (i8 (X86Vextract VK32:$src, (iPTR 0))))), (COPY_TO_REGCLASS VK32:$src, GR32)>;
		def : Pat<(i32 (anyext (i8 (X86Vextract VK16:$src, (iPTR 0))))), (COPY_TO_REGCLASS VK16:$src, GR32)>;
		def : Pat<(i32 (anyext (i8 (X86Vextract VK8:$src, (iPTR 0))))), (COPY_TO_REGCLASS VK8:$src, GR32)>;
		def : Pat<(i32 (anyext (i8 (X86Vextract VK4:$src, (iPTR 0))))), (COPY_TO_REGCLASS VK4:$src, GR32)>;
		def : Pat<(i32 (anyext (i8 (X86Vextract VK2:$src, (iPTR 0))))), (COPY_TO_REGCLASS VK2:$src, GR32)>;

def : Pat<(i1 (trunc (i32 GR32:$src))),		def : Pat<(X86kshiftr (X86kshiftl (v1i1 (scalar_to_vector GR8:$src)), (i8 15)), (i8 15)) ,
(COPY_TO_REGCLASS (AND32ri8 $src, (i32 1)), VK1)>;

def : Pat<(i1 (trunc (i32 (assertzext_i1 GR32:$src)))),
(COPY_TO_REGCLASS GR32:$src, VK1)>;

def : Pat<(i1 (trunc (i8 GR8:$src))),
(COPY_TO_REGCLASS		(COPY_TO_REGCLASS
(AND32ri8 (INSERT_SUBREG (i32 (IMPLICIT_DEF)),		(KMOVWkr (AND32ri8 (INSERT_SUBREG (i32 (IMPLICIT_DEF)),
GR8:$src, sub_8bit), (i32 1)), VK1)>;		GR8:$src, sub_8bit), (i32 1))),
		VK1)>;
def : Pat<(i1 (trunc (i16 GR16:$src))),		def : Pat<(X86kshiftr (X86kshiftl (v16i1 (scalar_to_vector GR8:$src)), (i8 15)), (i8 15)) ,
(COPY_TO_REGCLASS		(COPY_TO_REGCLASS
(AND32ri8 (INSERT_SUBREG (i32 (IMPLICIT_DEF)),		(KMOVWkr (AND32ri8 (INSERT_SUBREG (i32 (IMPLICIT_DEF)),
GR16:$src, sub_16bit), (i32 1)), VK1)>;		GR8:$src, sub_8bit), (i32 1))),
		VK16)>;
def : Pat<(i32 (zext VK1:$src)),		def : Pat<(X86kshiftr (X86kshiftl (v8i1 (scalar_to_vector GR8:$src)), (i8 15)), (i8 15)) ,
(AND32ri8 (COPY_TO_REGCLASS VK1:$src, GR32), (i32 1))>;		(COPY_TO_REGCLASS
		(KMOVWkr (AND32ri8 (INSERT_SUBREG (i32 (IMPLICIT_DEF)),
def : Pat<(i32 (anyext VK1:$src)),		GR8:$src, sub_8bit), (i32 1))),
(COPY_TO_REGCLASS VK1:$src, GR32)>;		VK8)>;

def : Pat<(i8 (zext VK1:$src)),
(EXTRACT_SUBREG
(AND32ri8 (COPY_TO_REGCLASS VK1:$src, GR32), (i32 1)), sub_8bit)>;

def : Pat<(i8 (anyext VK1:$src)),
(EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS VK1:$src, GR32)), sub_8bit)>;

def : Pat<(i64 (zext VK1:$src)),
(SUBREG_TO_REG (i64 0),
(AND32ri8 (COPY_TO_REGCLASS VK1:$src, GR32), (i32 1)), sub_32bit)>;

def : Pat<(i64 (anyext VK1:$src)),
(INSERT_SUBREG (i64 (IMPLICIT_DEF)),
(i32 (COPY_TO_REGCLASS VK1:$src, GR32)), sub_32bit)>;

def : Pat<(i16 (zext VK1:$src)),
(EXTRACT_SUBREG
(AND32ri8 (COPY_TO_REGCLASS VK1:$src, GR32), (i32 1)), sub_16bit)>;

def : Pat<(i16 (anyext VK1:$src)),
(EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS VK1:$src, GR32)), sub_16bit)>;
}		}
def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
(COPY_TO_REGCLASS VK1:$src, VK16)>;
def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
(COPY_TO_REGCLASS VK1:$src, VK8)>;
def : Pat<(v4i1 (scalar_to_vector VK1:$src)),
(COPY_TO_REGCLASS VK1:$src, VK4)>;
def : Pat<(v2i1 (scalar_to_vector VK1:$src)),
(COPY_TO_REGCLASS VK1:$src, VK2)>;
def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
(COPY_TO_REGCLASS VK1:$src, VK32)>;
def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
(COPY_TO_REGCLASS VK1:$src, VK64)>;

def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;

def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))), (COPY_TO_REGCLASS VK64:$src, VK1)>;
def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))), (COPY_TO_REGCLASS VK32:$src, VK1)>;
def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))), (COPY_TO_REGCLASS VK16:$src, VK1)>;
def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))), (COPY_TO_REGCLASS VK8:$src, VK1)>;
def : Pat<(i1 (X86Vextract VK4:$src, (iPTR 0))), (COPY_TO_REGCLASS VK4:$src, VK1)>;
def : Pat<(i1 (X86Vextract VK2:$src, (iPTR 0))), (COPY_TO_REGCLASS VK2:$src, VK1)>;

// Mask unary operation		// Mask unary operation
// - KNOT		// - KNOT
multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,		multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
RegisterClass KRC, SDPatternOperator OpNode,		RegisterClass KRC, SDPatternOperator OpNode,
Predicate prd> {		Predicate prd> {
let Predicates = [prd] in		let Predicates = [prd] in
def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),		def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
▲ Show 20 Lines • Show All 184 Lines • ▼ Show 20 Lines
defm KSET0 : avx512_mask_setop_w<immAllZerosV>;		defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
defm KSET1 : avx512_mask_setop_w<immAllOnesV>;		defm KSET1 : avx512_mask_setop_w<immAllOnesV>;

// With AVX-512 only, 8-bit mask is promoted to 16-bit mask.		// With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
let Predicates = [HasAVX512] in {		let Predicates = [HasAVX512] in {
def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;		def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
def : Pat<(v4i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK4)>;		def : Pat<(v4i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK4)>;
def : Pat<(v2i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK2)>;		def : Pat<(v2i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK2)>;
		def : Pat<(v1i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK1)>;
def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;		def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
def : Pat<(v4i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK4)>;		def : Pat<(v4i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK4)>;
def : Pat<(v2i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK2)>;		def : Pat<(v2i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK2)>;
let AddedComplexity = 10 in { // To optimize isel table.		def : Pat<(v1i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK1)>;
def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
def : Pat<(i1 1), (COPY_TO_REGCLASS (KSHIFTRWri (KSET1W), (i8 15)), VK1)>;
def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSHIFTRWri (KSET1W), (i8 15)), VK1)>;
}
}		}

// Patterns for kmask insert_subvector/extract_subvector to/from index=0		// Patterns for kmask insert_subvector/extract_subvector to/from index=0
multiclass operation_subvector_mask_lowering<RegisterClass subRC, ValueType subVT,		multiclass operation_subvector_mask_lowering<RegisterClass subRC, ValueType subVT,
RegisterClass RC, ValueType VT> {		RegisterClass RC, ValueType VT> {
def : Pat<(subVT (extract_subvector (VT RC:$src), (iPTR 0))),		def : Pat<(subVT (extract_subvector (VT RC:$src), (iPTR 0))),
(subVT (COPY_TO_REGCLASS RC:$src, subRC))>;		(subVT (COPY_TO_REGCLASS RC:$src, subRC))>;

def : Pat<(VT (insert_subvector undef, subRC:$src, (iPTR 0))),		def : Pat<(VT (insert_subvector undef, subRC:$src, (iPTR 0))),
(VT (COPY_TO_REGCLASS subRC:$src, RC))>;		(VT (COPY_TO_REGCLASS subRC:$src, RC))>;
}		}
		defm : operation_subvector_mask_lowering<VK1, v1i1, VK2, v2i1>;
		defm : operation_subvector_mask_lowering<VK1, v1i1, VK4, v4i1>;
		defm : operation_subvector_mask_lowering<VK1, v1i1, VK8, v8i1>;
		defm : operation_subvector_mask_lowering<VK1, v1i1, VK16, v16i1>;
		defm : operation_subvector_mask_lowering<VK1, v1i1, VK32, v32i1>;
		defm : operation_subvector_mask_lowering<VK1, v1i1, VK64, v64i1>;

defm : operation_subvector_mask_lowering<VK2, v2i1, VK4, v4i1>;		defm : operation_subvector_mask_lowering<VK2, v2i1, VK4, v4i1>;
defm : operation_subvector_mask_lowering<VK2, v2i1, VK8, v8i1>;		defm : operation_subvector_mask_lowering<VK2, v2i1, VK8, v8i1>;
defm : operation_subvector_mask_lowering<VK2, v2i1, VK16, v16i1>;		defm : operation_subvector_mask_lowering<VK2, v2i1, VK16, v16i1>;
defm : operation_subvector_mask_lowering<VK2, v2i1, VK32, v32i1>;		defm : operation_subvector_mask_lowering<VK2, v2i1, VK32, v32i1>;
defm : operation_subvector_mask_lowering<VK2, v2i1, VK64, v64i1>;		defm : operation_subvector_mask_lowering<VK2, v2i1, VK64, v64i1>;

defm : operation_subvector_mask_lowering<VK4, v4i1, VK8, v8i1>;		defm : operation_subvector_mask_lowering<VK4, v4i1, VK8, v8i1>;
▲ Show 20 Lines • Show All 663 Lines • ▼ Show 20 Lines	defm VMOVSDZ : avx512_move_scalar<"vmovsd", X86Movsd, f64x_info>,
VEX_LIG, XD, VEX_W, EVEX_CD8<64, CD8VT1>;		VEX_LIG, XD, VEX_W, EVEX_CD8<64, CD8VT1>;


multiclass avx512_move_scalar_lowering<string InstrStr, SDNode OpNode,		multiclass avx512_move_scalar_lowering<string InstrStr, SDNode OpNode,
PatLeaf ZeroFP, X86VectorVTInfo _> {		PatLeaf ZeroFP, X86VectorVTInfo _> {

def : Pat<(_.VT (OpNode _.RC:$src0,		def : Pat<(_.VT (OpNode _.RC:$src0,
(_.VT (scalar_to_vector		(_.VT (scalar_to_vector
(_.EltVT (X86selects (i1 (trunc GR32:$mask)),		(_.EltVT (X86selects (scalar_to_vector (and (i8 (trunc GR32:$mask)), (i8 1))),
(_.EltVT _.FRC:$src1),		(_.EltVT _.FRC:$src1),
(_.EltVT _.FRC:$src2))))))),		(_.EltVT _.FRC:$src2))))))),
(COPY_TO_REGCLASS (!cast<Instruction>(InstrStr#rrk)		(COPY_TO_REGCLASS (!cast<Instruction>(InstrStr#rrk)
(COPY_TO_REGCLASS _.FRC:$src2, _.RC),		(COPY_TO_REGCLASS _.FRC:$src2, _.RC),
(COPY_TO_REGCLASS GR32:$mask, VK1WM),		(COPY_TO_REGCLASS GR32:$mask, VK1WM),
(_.VT _.RC:$src0), _.FRC:$src1),		(_.VT _.RC:$src0), _.FRC:$src1),
_.RC)>;		_.RC)>;

def : Pat<(_.VT (OpNode _.RC:$src0,		def : Pat<(_.VT (OpNode _.RC:$src0,
(_.VT (scalar_to_vector		(_.VT (scalar_to_vector
(_.EltVT (X86selects (i1 (trunc GR32:$mask)),		(_.EltVT (X86selects (scalar_to_vector (and (i8 (trunc GR32:$mask)), (i8 1))),
(_.EltVT _.FRC:$src1),		(_.EltVT _.FRC:$src1),
(_.EltVT ZeroFP))))))),		(_.EltVT ZeroFP))))))),
(COPY_TO_REGCLASS (!cast<Instruction>(InstrStr#rrkz)		(COPY_TO_REGCLASS (!cast<Instruction>(InstrStr#rrkz)
(COPY_TO_REGCLASS GR32:$mask, VK1WM),		(COPY_TO_REGCLASS GR32:$mask, VK1WM),
(_.VT _.RC:$src0), _.FRC:$src1),		(_.VT _.RC:$src0), _.FRC:$src1),
_.RC)>;		_.RC)>;
}		}

multiclass avx512_store_scalar_lowering<string InstrStr, AVX512VLVectorVTInfo _,		multiclass avx512_store_scalar_lowering<string InstrStr, AVX512VLVectorVTInfo _,
dag Mask, RegisterClass MaskRC> {		dag Mask, RegisterClass MaskRC> {

def : Pat<(masked_store addr:$dst, Mask,		def : Pat<(masked_store addr:$dst, Mask,
(_.info512.VT (insert_subvector undef,		(_.info512.VT (insert_subvector undef,
(_.info256.VT (insert_subvector undef,		(_.info256.VT (insert_subvector undef,
(_.info128.VT _.info128.RC:$src),		(_.info128.VT _.info128.RC:$src),
(iPTR 0))),		(iPTR 0))),
(iPTR 0)))),		(iPTR 0)))),
(!cast<Instruction>(InstrStr#mrk) addr:$dst,		(!cast<Instruction>(InstrStr#mrk) addr:$dst,
(i1 (COPY_TO_REGCLASS MaskRC:$mask, VK1WM)),		(COPY_TO_REGCLASS MaskRC:$mask, VK1WM),
(COPY_TO_REGCLASS _.info128.RC:$src, _.info128.FRC))>;		(COPY_TO_REGCLASS _.info128.RC:$src, _.info128.FRC))>;

}		}

multiclass avx512_store_scalar_lowering_subreg<string InstrStr,		multiclass avx512_store_scalar_lowering_subreg<string InstrStr,
AVX512VLVectorVTInfo _,		AVX512VLVectorVTInfo _,
dag Mask, RegisterClass MaskRC,		dag Mask, RegisterClass MaskRC,
SubRegIndex subreg> {		SubRegIndex subreg> {

def : Pat<(masked_store addr:$dst, Mask,		def : Pat<(masked_store addr:$dst, Mask,
(_.info512.VT (insert_subvector undef,		(_.info512.VT (insert_subvector undef,
(_.info256.VT (insert_subvector undef,		(_.info256.VT (insert_subvector undef,
(_.info128.VT _.info128.RC:$src),		(_.info128.VT _.info128.RC:$src),
(iPTR 0))),		(iPTR 0))),
(iPTR 0)))),		(iPTR 0)))),
(!cast<Instruction>(InstrStr#mrk) addr:$dst,		(!cast<Instruction>(InstrStr#mrk) addr:$dst,
(i1 (COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), MaskRC:$mask, subreg)), VK1WM)),		(COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), MaskRC:$mask, subreg)), VK1WM),
(COPY_TO_REGCLASS _.info128.RC:$src, _.info128.FRC))>;		(COPY_TO_REGCLASS _.info128.RC:$src, _.info128.FRC))>;

}		}

multiclass avx512_load_scalar_lowering<string InstrStr, AVX512VLVectorVTInfo _,		multiclass avx512_load_scalar_lowering<string InstrStr, AVX512VLVectorVTInfo _,
dag Mask, RegisterClass MaskRC> {		dag Mask, RegisterClass MaskRC> {

def : Pat<(_.info128.VT (extract_subvector		def : Pat<(_.info128.VT (extract_subvector
(_.info512.VT (masked_load addr:$srcAddr, Mask,		(_.info512.VT (masked_load addr:$srcAddr, Mask,
(_.info512.VT (bitconvert		(_.info512.VT (bitconvert
(v16i32 immAllZerosV))))),		(v16i32 immAllZerosV))))),
(iPTR 0))),		(iPTR 0))),
(!cast<Instruction>(InstrStr#rmkz)		(!cast<Instruction>(InstrStr#rmkz)
(i1 (COPY_TO_REGCLASS MaskRC:$mask, VK1WM)),		(COPY_TO_REGCLASS MaskRC:$mask, VK1WM),
addr:$srcAddr)>;		addr:$srcAddr)>;

def : Pat<(_.info128.VT (extract_subvector		def : Pat<(_.info128.VT (extract_subvector
(_.info512.VT (masked_load addr:$srcAddr, Mask,		(_.info512.VT (masked_load addr:$srcAddr, Mask,
(_.info512.VT (insert_subvector undef,		(_.info512.VT (insert_subvector undef,
(_.info256.VT (insert_subvector undef,		(_.info256.VT (insert_subvector undef,
(_.info128.VT (X86vzmovl _.info128.RC:$src)),		(_.info128.VT (X86vzmovl _.info128.RC:$src)),
(iPTR 0))),		(iPTR 0))),
(iPTR 0))))),		(iPTR 0))))),
(iPTR 0))),		(iPTR 0))),
(!cast<Instruction>(InstrStr#rmk) _.info128.RC:$src,		(!cast<Instruction>(InstrStr#rmk) _.info128.RC:$src,
(i1 (COPY_TO_REGCLASS MaskRC:$mask, VK1WM)),		(COPY_TO_REGCLASS MaskRC:$mask, VK1WM),
addr:$srcAddr)>;		addr:$srcAddr)>;

}		}

multiclass avx512_load_scalar_lowering_subreg<string InstrStr,		multiclass avx512_load_scalar_lowering_subreg<string InstrStr,
AVX512VLVectorVTInfo _,		AVX512VLVectorVTInfo _,
dag Mask, RegisterClass MaskRC,		dag Mask, RegisterClass MaskRC,
SubRegIndex subreg> {		SubRegIndex subreg> {

def : Pat<(_.info128.VT (extract_subvector		def : Pat<(_.info128.VT (extract_subvector
(_.info512.VT (masked_load addr:$srcAddr, Mask,		(_.info512.VT (masked_load addr:$srcAddr, Mask,
(_.info512.VT (bitconvert		(_.info512.VT (bitconvert
(v16i32 immAllZerosV))))),		(v16i32 immAllZerosV))))),
(iPTR 0))),		(iPTR 0))),
(!cast<Instruction>(InstrStr#rmkz)		(!cast<Instruction>(InstrStr#rmkz)
(i1 (COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), MaskRC:$mask, subreg)), VK1WM)),		(COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), MaskRC:$mask, subreg)), VK1WM),
addr:$srcAddr)>;		addr:$srcAddr)>;

def : Pat<(_.info128.VT (extract_subvector		def : Pat<(_.info128.VT (extract_subvector
(_.info512.VT (masked_load addr:$srcAddr, Mask,		(_.info512.VT (masked_load addr:$srcAddr, Mask,
(_.info512.VT (insert_subvector undef,		(_.info512.VT (insert_subvector undef,
(_.info256.VT (insert_subvector undef,		(_.info256.VT (insert_subvector undef,
(_.info128.VT (X86vzmovl _.info128.RC:$src)),		(_.info128.VT (X86vzmovl _.info128.RC:$src)),
(iPTR 0))),		(iPTR 0))),
(iPTR 0))))),		(iPTR 0))))),
(iPTR 0))),		(iPTR 0))),
(!cast<Instruction>(InstrStr#rmk) _.info128.RC:$src,		(!cast<Instruction>(InstrStr#rmk) _.info128.RC:$src,
(i1 (COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), MaskRC:$mask, subreg)), VK1WM)),		(COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), MaskRC:$mask, subreg)), VK1WM),
addr:$srcAddr)>;		addr:$srcAddr)>;

}		}

defm : avx512_move_scalar_lowering<"VMOVSSZ", X86Movss, fp32imm0, v4f32x_info>;		defm : avx512_move_scalar_lowering<"VMOVSSZ", X86Movss, fp32imm0, v4f32x_info>;
defm : avx512_move_scalar_lowering<"VMOVSDZ", X86Movsd, fp64imm0, v2f64x_info>;		defm : avx512_move_scalar_lowering<"VMOVSDZ", X86Movsd, fp64imm0, v2f64x_info>;

defm : avx512_store_scalar_lowering<"VMOVSSZ", avx512vl_f32_info,		defm : avx512_store_scalar_lowering<"VMOVSSZ", avx512vl_f32_info,
Show All 14 Lines	def : Pat<(f32 (X86selects VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
(COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),		(COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
VK1WM:$mask, (v4f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;		VK1WM:$mask, (v4f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;

def : Pat<(f64 (X86selects VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),		def : Pat<(f64 (X86selects VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
(COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),		(COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
VK1WM:$mask, (v2f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;		VK1WM:$mask, (v2f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;

def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),		def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
(VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), GR8:$mask, sub_8bit)), VK1WM)),		(VMOVSSZmrk addr:$dst, (COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), GR8:$mask, sub_8bit)), VK1WM),
(COPY_TO_REGCLASS VR128X:$src, FR32X))>;		(COPY_TO_REGCLASS VR128X:$src, FR32X))>;

let hasSideEffects = 0 in		let hasSideEffects = 0 in
defm VMOVSSZrr_REV : AVX512_maskable_in_asm<0x11, MRMDestReg, f32x_info,		defm VMOVSSZrr_REV : AVX512_maskable_in_asm<0x11, MRMDestReg, f32x_info,
(outs VR128X:$dst), (ins VR128X:$src1, FR32X:$src2),		(outs VR128X:$dst), (ins VR128X:$src1, FR32X:$src2),
"vmovss.s", "$src2, $src1", "$src1, $src2", []>,		"vmovss.s", "$src2, $src1", "$src1, $src2", []>,
XS, EVEX_4V, VEX_LIG;		XS, EVEX_4V, VEX_LIG;

▲ Show 20 Lines • Show All 6,030 Lines • Show Last 20 Lines

lib/Target/X86/X86InstrFragmentsSIMD.td

	Show First 20 Lines • Show All 268 Lines • ▼ Show 20 Lines

	def X86select : SDNode<"X86ISD::SELECT",			def X86select : SDNode<"X86ISD::SELECT",
	SDTypeProfile<1, 3, [SDTCVecEltisVT<1, i1>,			SDTypeProfile<1, 3, [SDTCVecEltisVT<1, i1>,
	SDTCisSameAs<0, 2>,			SDTCisSameAs<0, 2>,
	SDTCisSameAs<2, 3>,			SDTCisSameAs<2, 3>,
	SDTCisSameNumEltsAs<0, 1>]>>;			SDTCisSameNumEltsAs<0, 1>]>>;

	def X86selects : SDNode<"X86ISD::SELECTS",			def X86selects : SDNode<"X86ISD::SELECTS",
	SDTypeProfile<1, 3, [SDTCisVT<1, i1>,			SDTypeProfile<1, 3, [SDTCisVT<1, v1i1>,
	SDTCisSameAs<0, 2>,			SDTCisSameAs<0, 2>,
	SDTCisSameAs<2, 3>]>>;			SDTCisSameAs<2, 3>]>>;

	def X86pmuludq : SDNode<"X86ISD::PMULUDQ",			def X86pmuludq : SDNode<"X86ISD::PMULUDQ",
	SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>,			SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>,
	SDTCVecEltisVT<1, i32>,			SDTCVecEltisVT<1, i32>,
	SDTCisSameSizeAs<0,1>,			SDTCisSameSizeAs<0,1>,
	SDTCisSameAs<1,2>]>,			SDTCisSameAs<1,2>]>,
	▲ Show 20 Lines • Show All 150 Lines • ▼ Show 20 Lines
	def X86VRndScale : SDNode<"X86ISD::VRNDSCALE", SDTFPUnaryOpImmRound>;			def X86VRndScale : SDNode<"X86ISD::VRNDSCALE", SDTFPUnaryOpImmRound>;
	def X86VGetMant : SDNode<"X86ISD::VGETMANT", SDTFPUnaryOpImmRound>;			def X86VGetMant : SDNode<"X86ISD::VGETMANT", SDTFPUnaryOpImmRound>;
	def X86Vfpclass : SDNode<"X86ISD::VFPCLASS",			def X86Vfpclass : SDNode<"X86ISD::VFPCLASS",
	SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i1>,			SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i1>,
	SDTCisFP<1>,			SDTCisFP<1>,
	SDTCisSameNumEltsAs<0,1>,			SDTCisSameNumEltsAs<0,1>,
	SDTCisVT<2, i32>]>, []>;			SDTCisVT<2, i32>]>, []>;
	def X86Vfpclasss : SDNode<"X86ISD::VFPCLASSS",			def X86Vfpclasss : SDNode<"X86ISD::VFPCLASSS",
	SDTypeProfile<1, 2, [SDTCisVT<0, i1>,			SDTypeProfile<1, 2, [SDTCisVT<0, v1i1>,
	SDTCisFP<1>, SDTCisVT<2, i32>]>,[]>;			SDTCisFP<1>, SDTCisVT<2, i32>]>,[]>;

	def X86SubVBroadcast : SDNode<"X86ISD::SUBV_BROADCAST",			def X86SubVBroadcast : SDNode<"X86ISD::SUBV_BROADCAST",
	SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,			SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
	SDTCisSubVecOfVec<1, 0>]>, []>;			SDTCisSubVecOfVec<1, 0>]>, []>;

	def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;			def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
	def X86VBroadcastm : SDNode<"X86ISD::VBROADCASTM", SDTVBroadcastm>;			def X86VBroadcastm : SDNode<"X86ISD::VBROADCASTM", SDTVBroadcastm>;
	def X86Vextract : SDNode<"X86ISD::VEXTRACT", SDTypeProfile<1, 2,			def X86Vextract : SDNode<"X86ISD::VEXTRACT", SDTypeProfile<1, 2,
	[SDTCisEltOfVec<0, 1>, SDTCisVec<1>,			[SDTCisVec<1>,
	SDTCisPtrTy<2>]>, []>;			SDTCisPtrTy<2>]>, []>;

	def X86Blendi : SDNode<"X86ISD::BLENDI", SDTBlend>;			def X86Blendi : SDNode<"X86ISD::BLENDI", SDTBlend>;

	def X86Addsub : SDNode<"X86ISD::ADDSUB", SDTFPBinOp>;			def X86Addsub : SDNode<"X86ISD::ADDSUB", SDTFPBinOp>;

	def X86faddRnd : SDNode<"X86ISD::FADD_RND", SDTFPBinOpRound>;			def X86faddRnd : SDNode<"X86ISD::FADD_RND", SDTFPBinOpRound>;
	def X86faddRnds : SDNode<"X86ISD::FADDS_RND", SDTFPBinOpRound>;			def X86faddRnds : SDNode<"X86ISD::FADDS_RND", SDTFPBinOpRound>;
	▲ Show 20 Lines • Show All 664 Lines • Show Last 20 Lines

lib/Target/X86/X86InstrInfo.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 6,298 Lines • ▼ Show 20 Lines
	// Try and copy between VR128/VR64 and GR64 registers.			// Try and copy between VR128/VR64 and GR64 registers.
	static unsigned CopyToFromAsymmetricReg(unsigned &DestReg, unsigned &SrcReg,			static unsigned CopyToFromAsymmetricReg(unsigned &DestReg, unsigned &SrcReg,
	const X86Subtarget &Subtarget) {			const X86Subtarget &Subtarget) {
	bool HasAVX = Subtarget.hasAVX();			bool HasAVX = Subtarget.hasAVX();
	bool HasAVX512 = Subtarget.hasAVX512();			bool HasAVX512 = Subtarget.hasAVX512();

	// SrcReg(MaskReg) -> DestReg(GR64)			// SrcReg(MaskReg) -> DestReg(GR64)
	// SrcReg(MaskReg) -> DestReg(GR32)			// SrcReg(MaskReg) -> DestReg(GR32)
				// SrcReg(MaskReg) -> DestReg(GR16)
				// SrcReg(MaskReg) -> DestReg(GR8)

	// All KMASK RegClasses hold the same k registers, can be tested against anyone.			// All KMASK RegClasses hold the same k registers, can be tested against anyone.
	if (X86::VK16RegClass.contains(SrcReg)) {			if (X86::VK16RegClass.contains(SrcReg)) {
	if (X86::GR64RegClass.contains(DestReg)) {			if (X86::GR64RegClass.contains(DestReg)) {
	assert(Subtarget.hasBWI());			assert(Subtarget.hasBWI());
	return X86::KMOVQrk;			return X86::KMOVQrk;
	}			}
	if (X86::GR32RegClass.contains(DestReg))			if (X86::GR32RegClass.contains(DestReg))
	return Subtarget.hasBWI() ? X86::KMOVDrk : X86::KMOVWrk;			return Subtarget.hasBWI() ? X86::KMOVDrk : X86::KMOVWrk;
				if (X86::GR16RegClass.contains(DestReg)) {
				craig.topperUnsubmitted Not Done Reply Inline Actions Why is this code coming back? We should use the right SUBREG operations in the output patterns so that we only do GR32/GR64 copies. craig.topper: Why is this code coming back? We should use the right SUBREG operations in the output patterns…
				DestReg = getX86SubSuperRegister(DestReg, 32);
				return X86::KMOVWrk;
				}
				if (X86::GR8RegClass.contains(DestReg)) {
				assert(!isHReg(DestReg) && "Cannot move between mask and h-reg");
				DestReg = getX86SubSuperRegister(DestReg, 32);
				return Subtarget.hasDQI() ? X86::KMOVBrk : X86::KMOVWrk;
				}
	}			}

	// SrcReg(GR64) -> DestReg(MaskReg)			// SrcReg(GR64) -> DestReg(MaskReg)
	// SrcReg(GR32) -> DestReg(MaskReg)			// SrcReg(GR32) -> DestReg(MaskReg)
				// SrcReg(GR16) -> DestReg(MaskReg)
				// SrcReg(GR8) -> DestReg(MaskReg)

	// All KMASK RegClasses hold the same k registers, can be tested against anyone.			// All KMASK RegClasses hold the same k registers, can be tested against anyone.
	if (X86::VK16RegClass.contains(DestReg)) {			if (X86::VK16RegClass.contains(DestReg)) {
	if (X86::GR64RegClass.contains(SrcReg)) {			if (X86::GR64RegClass.contains(SrcReg)) {
	assert(Subtarget.hasBWI());			assert(Subtarget.hasBWI());
	return X86::KMOVQkr;			return X86::KMOVQkr;
	}			}
	if (X86::GR32RegClass.contains(SrcReg))			if (X86::GR32RegClass.contains(SrcReg))
	return Subtarget.hasBWI() ? X86::KMOVDkr : X86::KMOVWkr;			return Subtarget.hasBWI() ? X86::KMOVDkr : X86::KMOVWkr;
				if (X86::GR16RegClass.contains(SrcReg)) {
				SrcReg = getX86SubSuperRegister(SrcReg, 32);
				return X86::KMOVWkr;
				}
				if (X86::GR8RegClass.contains(SrcReg)) {
				assert(!isHReg(SrcReg) && "Cannot move between mask and h-reg");
				SrcReg = getX86SubSuperRegister(SrcReg, 32);
				return Subtarget.hasDQI() ? X86::KMOVBkr : X86::KMOVWkr;
				}
	}			}


	// SrcReg(VR128) -> DestReg(GR64)			// SrcReg(VR128) -> DestReg(GR64)
				craig.topperUnsubmitted Done Reply Inline Actions Not sure why there are two blanks lines in the current code, but don't delete the extra one in this patch. craig.topper: Not sure why there are two blanks lines in the current code, but don't delete the extra one in…
	// SrcReg(VR64) -> DestReg(GR64)			// SrcReg(VR64) -> DestReg(GR64)
	// SrcReg(GR64) -> DestReg(VR128)			// SrcReg(GR64) -> DestReg(VR128)
	// SrcReg(GR64) -> DestReg(VR64)			// SrcReg(GR64) -> DestReg(VR64)

	if (X86::GR64RegClass.contains(DestReg)) {			if (X86::GR64RegClass.contains(DestReg)) {
	if (X86::VR128XRegClass.contains(SrcReg))			if (X86::VR128XRegClass.contains(SrcReg))
	// Copy from a VR128 register to a GR64 register.			// Copy from a VR128 register to a GR64 register.
	return HasAVX512 ? X86::VMOVPQIto64Zrr :			return HasAVX512 ? X86::VMOVPQIto64Zrr :
	▲ Show 20 Lines • Show All 4,120 Lines • Show Last 20 Lines

lib/Target/X86/X86RegisterInfo.td

	Show First 20 Lines • Show All 505 Lines • ▼ Show 20 Lines

	// Extended VR128 and VR256 for AVX-512 instructions			// Extended VR128 and VR256 for AVX-512 instructions
	def VR128X : RegisterClass<"X86", [v4f32, v2f64, v16i8, v8i16, v4i32, v2i64],			def VR128X : RegisterClass<"X86", [v4f32, v2f64, v16i8, v8i16, v4i32, v2i64],
	128, (add FR32X)>;			128, (add FR32X)>;
	def VR256X : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64],			def VR256X : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64],
	256, (sequence "YMM%u", 0, 31)>;			256, (sequence "YMM%u", 0, 31)>;

	// Mask registers			// Mask registers
	def VK1 : RegisterClass<"X86", [i1], 16, (sequence "K%u", 0, 7)> {let Size = 16;}			def VK1 : RegisterClass<"X86", [v1i1], 16, (sequence "K%u", 0, 7)> {let Size = 16;}
	def VK2 : RegisterClass<"X86", [v2i1], 16, (add VK1)> {let Size = 16;}			def VK2 : RegisterClass<"X86", [v2i1], 16, (add VK1)> {let Size = 16;}
	def VK4 : RegisterClass<"X86", [v4i1], 16, (add VK2)> {let Size = 16;}			def VK4 : RegisterClass<"X86", [v4i1], 16, (add VK2)> {let Size = 16;}
	def VK8 : RegisterClass<"X86", [v8i1], 16, (add VK4)> {let Size = 16;}			def VK8 : RegisterClass<"X86", [v8i1], 16, (add VK4)> {let Size = 16;}
	def VK16 : RegisterClass<"X86", [v16i1], 16, (add VK8)> {let Size = 16;}			def VK16 : RegisterClass<"X86", [v16i1], 16, (add VK8)> {let Size = 16;}
	def VK32 : RegisterClass<"X86", [v32i1], 32, (add VK16)> {let Size = 32;}			def VK32 : RegisterClass<"X86", [v32i1], 32, (add VK16)> {let Size = 32;}
	def VK64 : RegisterClass<"X86", [v64i1], 64, (add VK32)> {let Size = 64;}			def VK64 : RegisterClass<"X86", [v64i1], 64, (add VK32)> {let Size = 64;}

	def VK1WM : RegisterClass<"X86", [i1], 16, (sub VK1, K0)> {let Size = 16;}			def VK1WM : RegisterClass<"X86", [v1i1], 16, (sub VK1, K0)> {let Size = 16;}
	def VK2WM : RegisterClass<"X86", [v2i1], 16, (sub VK2, K0)> {let Size = 16;}			def VK2WM : RegisterClass<"X86", [v2i1], 16, (sub VK2, K0)> {let Size = 16;}
	def VK4WM : RegisterClass<"X86", [v4i1], 16, (sub VK4, K0)> {let Size = 16;}			def VK4WM : RegisterClass<"X86", [v4i1], 16, (sub VK4, K0)> {let Size = 16;}
	def VK8WM : RegisterClass<"X86", [v8i1], 16, (sub VK8, K0)> {let Size = 16;}			def VK8WM : RegisterClass<"X86", [v8i1], 16, (sub VK8, K0)> {let Size = 16;}
	def VK16WM : RegisterClass<"X86", [v16i1], 16, (add VK8WM)> {let Size = 16;}			def VK16WM : RegisterClass<"X86", [v16i1], 16, (add VK8WM)> {let Size = 16;}
	def VK32WM : RegisterClass<"X86", [v32i1], 32, (add VK16WM)> {let Size = 32;}			def VK32WM : RegisterClass<"X86", [v32i1], 32, (add VK16WM)> {let Size = 32;}
	def VK64WM : RegisterClass<"X86", [v64i1], 64, (add VK32WM)> {let Size = 64;}			def VK64WM : RegisterClass<"X86", [v64i1], 64, (add VK32WM)> {let Size = 64;}

	// Bound registers			// Bound registers
	def BNDR : RegisterClass<"X86", [v2i64], 128, (sequence "BND%u", 0, 3)>;			def BNDR : RegisterClass<"X86", [v2i64], 128, (sequence "BND%u", 0, 3)>;

test/CodeGen/X86/avx512-cmp.ll

	Show First 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
	l1:			l1:
	%c = fsub float %a, %b			%c = fsub float %a, %b
	ret float %c			ret float %c
	l2:			l2:
	%c1 = fadd float %a, %b			%c1 = fadd float %a, %b
	ret float %c1			ret float %c1
	}			}

	; FIXME: Can use vcmpeqss and extract from the mask here in AVX512.
	define i32 @test3(float %a, float %b) {			define i32 @test3(float %a, float %b) {
	; ALL-LABEL: test3:			; KNL-LABEL: test3:
	; ALL: ## BB#0:			; KNL: ## BB#0:
	; ALL-NEXT: vucomiss %xmm1, %xmm0			; KNL-NEXT: vcmpeqss %xmm1, %xmm0, %k0
	; ALL-NEXT: setnp %al			; KNL-NEXT: kmovw %k0, %eax
	; ALL-NEXT: sete %cl			; KNL-NEXT: movzbl %al, %eax
	; ALL-NEXT: andb %al, %cl			; KNL-NEXT: retq
	; ALL-NEXT: movzbl %cl, %eax			;
	; ALL-NEXT: retq			; SKX-LABEL: test3:
				; SKX: ## BB#0:
				; SKX-NEXT: vcmpeqss %xmm1, %xmm0, %k0
				; SKX-NEXT: kmovb %k0, %eax
				; SKX-NEXT: movzbl %al, %eax
				; SKX-NEXT: retq

	%cmp10.i = fcmp oeq float %a, %b			%cmp10.i = fcmp oeq float %a, %b
	%conv11.i = zext i1 %cmp10.i to i32			%conv11.i = zext i1 %cmp10.i to i32
	ret i32 %conv11.i			ret i32 %conv11.i
	}			}

	define float @test5(float %p) #0 {			define float @test5(float %p) #0 {
	; ALL-LABEL: test5:			; ALL-LABEL: test5:
	; ALL: ## BB#0: ## %entry			; ALL: ## BB#0: ## %entry
	; ALL-NEXT: vxorps %xmm1, %xmm1, %xmm1			; ALL-NEXT: vxorps %xmm1, %xmm1, %xmm1
	; ALL-NEXT: vucomiss %xmm1, %xmm0			; ALL-NEXT: vucomiss %xmm1, %xmm0
	; ALL-NEXT: jne LBB3_1			; ALL-NEXT: jne LBB3_1
	; ALL-NEXT: jp LBB3_1			; ALL-NEXT: jp LBB3_1
	; ALL-NEXT: ## BB#2: ## %return			; ALL-NEXT: ## BB#2: ## %return
	; ALL-NEXT: retq			; ALL-NEXT: retq
	; ALL-NEXT: LBB3_1: ## %if.end			; ALL-NEXT: LBB3_1: ## %if.end
	; ALL-NEXT: seta %al			; ALL-NEXT: seta %al
	; ALL-NEXT: movzbl %al, %eax			; ALL-NEXT: movzbl %al, %eax
	; ALL-NEXT: leaq {{.*}}(%rip), %rcx			; ALL-NEXT: leaq {{.*}}(%rip), %rcx
	; ALL-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero			; ALL-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
	; ALL-NEXT: retq			; ALL-NEXT: retq
	▲ Show 20 Lines • Show All 72 Lines • ▼ Show 20 Lines
	br i1 %cmp10.i, label %A, label %B			br i1 %cmp10.i, label %A, label %B
	A:			A:
	ret i32 6			ret i32 6
	B:			B:
	ret i32 7			ret i32 7
	}			}

	define i32 @test10(i64 %b, i64 %c, i1 %d) {			define i32 @test10(i64 %b, i64 %c, i1 %d) {
	; KNL-LABEL: test10:			; ALL-LABEL: test10:
	; KNL: ## BB#0:			; ALL: ## BB#0:
	; KNL-NEXT: andl $1, %edx			; ALL-NEXT: movl %edx, %eax
	; KNL-NEXT: kmovw %edx, %k0			; ALL-NEXT: andb $1, %al
	; KNL-NEXT: cmpq %rsi, %rdi			; ALL-NEXT: cmpq %rsi, %rdi
	; KNL-NEXT: sete %al			; ALL-NEXT: sete %cl
	; KNL-NEXT: andl $1, %eax			; ALL-NEXT: orb %dl, %cl
	; KNL-NEXT: kmovw %eax, %k1			; ALL-NEXT: andb $1, %cl
	; KNL-NEXT: korw %k1, %k0, %k1			; ALL-NEXT: cmpb %cl, %al
	; KNL-NEXT: kxorw %k1, %k0, %k0			; ALL-NEXT: je LBB8_1
	; KNL-NEXT: kmovw %k0, %eax			; ALL-NEXT: ## BB#2: ## %if.end.i
	; KNL-NEXT: andl $1, %eax			; ALL-NEXT: movl $6, %eax
	; KNL-NEXT: testb %al, %al			; ALL-NEXT: retq
	; KNL-NEXT: je LBB8_1			; ALL-NEXT: LBB8_1: ## %if.then.i
	; KNL-NEXT: ## BB#2: ## %if.end.i			; ALL-NEXT: movl $5, %eax
	; KNL-NEXT: movl $6, %eax			; ALL-NEXT: retq
	; KNL-NEXT: retq
	; KNL-NEXT: LBB8_1: ## %if.then.i
	; KNL-NEXT: movl $5, %eax
	; KNL-NEXT: retq
	;
	; SKX-LABEL: test10:
	; SKX: ## BB#0:
	; SKX-NEXT: andl $1, %edx
	; SKX-NEXT: kmovd %edx, %k0
	; SKX-NEXT: cmpq %rsi, %rdi
	; SKX-NEXT: sete %al
	; SKX-NEXT: andl $1, %eax
	; SKX-NEXT: kmovd %eax, %k1
	; SKX-NEXT: korw %k1, %k0, %k1
	; SKX-NEXT: kxorw %k1, %k0, %k0
	; SKX-NEXT: kmovd %k0, %eax
	; SKX-NEXT: andl $1, %eax
	; SKX-NEXT: testb %al, %al
	; SKX-NEXT: je LBB8_1
	; SKX-NEXT: ## BB#2: ## %if.end.i
	; SKX-NEXT: movl $6, %eax
	; SKX-NEXT: retq
	; SKX-NEXT: LBB8_1: ## %if.then.i
	; SKX-NEXT: movl $5, %eax
	; SKX-NEXT: retq

	%cmp8.i = icmp eq i64 %b, %c			%cmp8.i = icmp eq i64 %b, %c
	%or1 = or i1 %d, %cmp8.i			%or1 = or i1 %d, %cmp8.i
	%xor1 = xor i1 %d, %or1			%xor1 = xor i1 %d, %or1
	br i1 %xor1, label %if.end.i, label %if.then.i			br i1 %xor1, label %if.end.i, label %if.then.i

	if.then.i:			if.then.i:
	ret i32 5			ret i32 5

	if.end.i:			if.end.i:
	ret i32 6			ret i32 6
	}			}

test/CodeGen/X86/avx512-cvt.ll

	Show First 20 Lines • Show All 1,546 Lines • ▼ Show 20 Lines
	define <2 x float> @uitofp_2i1_float(<2 x i32> %a) {			define <2 x float> @uitofp_2i1_float(<2 x i32> %a) {
	; NOVL-LABEL: uitofp_2i1_float:			; NOVL-LABEL: uitofp_2i1_float:
	; NOVL: ## BB#0:			; NOVL: ## BB#0:
	; NOVL-NEXT: vpxor %xmm1, %xmm1, %xmm1			; NOVL-NEXT: vpxor %xmm1, %xmm1, %xmm1
	; NOVL-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]			; NOVL-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
	; NOVL-NEXT: vmovdqa {{.*#+}} xmm1 = [9223372036854775808,9223372036854775808]			; NOVL-NEXT: vmovdqa {{.*#+}} xmm1 = [9223372036854775808,9223372036854775808]
	; NOVL-NEXT: vpxor %xmm1, %xmm0, %xmm0			; NOVL-NEXT: vpxor %xmm1, %xmm0, %xmm0
	; NOVL-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0			; NOVL-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0
	; NOVL-NEXT: vpextrq $1, %xmm0, %rax			; NOVL-NEXT: vpextrb $8, %xmm0, %eax
	; NOVL-NEXT: andl $1, %eax			; NOVL-NEXT: andl $1, %eax
	; NOVL-NEXT: vcvtsi2ssl %eax, %xmm2, %xmm1			; NOVL-NEXT: vcvtsi2ssl %eax, %xmm2, %xmm1
	; NOVL-NEXT: vmovq %xmm0, %rax			; NOVL-NEXT: vpextrb $0, %xmm0, %eax
	; NOVL-NEXT: andl $1, %eax			; NOVL-NEXT: andl $1, %eax
	; NOVL-NEXT: vcvtsi2ssl %eax, %xmm2, %xmm0			; NOVL-NEXT: vcvtsi2ssl %eax, %xmm2, %xmm0
	; NOVL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]			; NOVL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
	; NOVL-NEXT: retq			; NOVL-NEXT: retq
	;			;
	; VL-LABEL: uitofp_2i1_float:			; VL-LABEL: uitofp_2i1_float:
	; VL: ## BB#0:			; VL: ## BB#0:
	; VL-NEXT: vpxor %xmm1, %xmm1, %xmm1			; VL-NEXT: vpxor %xmm1, %xmm1, %xmm1
	▲ Show 20 Lines • Show All 46 Lines • Show Last 20 Lines

test/CodeGen/X86/avx512-ext.ll

Show First 20 Lines • Show All 1,428 Lines • ▼ Show 20 Lines	; SKX-NEXT: retq
%y = sext <8 x i1> %x1 to <8 x i32>		%y = sext <8 x i1> %x1 to <8 x i32>
ret <8 x i32> %y		ret <8 x i32> %y
}		}


define i16 @trunc_i32_to_i1(i32 %a) {		define i16 @trunc_i32_to_i1(i32 %a) {
; KNL-LABEL: trunc_i32_to_i1:		; KNL-LABEL: trunc_i32_to_i1:
; KNL: ## BB#0:		; KNL: ## BB#0:
; KNL-NEXT: andl $1, %edi
; KNL-NEXT: kmovw %edi, %k0
; KNL-NEXT: movw $-4, %ax		; KNL-NEXT: movw $-4, %ax
; KNL-NEXT: kmovw %eax, %k1		; KNL-NEXT: kmovw %eax, %k0
; KNL-NEXT: kshiftrw $1, %k1, %k1		; KNL-NEXT: kshiftrw $1, %k0, %k0
; KNL-NEXT: kshiftlw $1, %k1, %k1		; KNL-NEXT: kshiftlw $1, %k0, %k0
; KNL-NEXT: korw %k0, %k1, %k0		; KNL-NEXT: andl $1, %edi
		; KNL-NEXT: kmovw %edi, %k1
		; KNL-NEXT: korw %k1, %k0, %k0
; KNL-NEXT: kmovw %k0, %eax		; KNL-NEXT: kmovw %k0, %eax
; KNL-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>		; KNL-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
; KNL-NEXT: retq		; KNL-NEXT: retq
;		;
; SKX-LABEL: trunc_i32_to_i1:		; SKX-LABEL: trunc_i32_to_i1:
; SKX: ## BB#0:		; SKX: ## BB#0:
; SKX-NEXT: andl $1, %edi
; SKX-NEXT: kmovd %edi, %k0
; SKX-NEXT: movw $-4, %ax		; SKX-NEXT: movw $-4, %ax
; SKX-NEXT: kmovd %eax, %k1		; SKX-NEXT: kmovd %eax, %k0
; SKX-NEXT: kshiftrw $1, %k1, %k1		; SKX-NEXT: kshiftrw $1, %k0, %k0
; SKX-NEXT: kshiftlw $1, %k1, %k1		; SKX-NEXT: kshiftlw $1, %k0, %k0
; SKX-NEXT: korw %k0, %k1, %k0		; SKX-NEXT: andl $1, %edi
		; SKX-NEXT: kmovw %edi, %k1
		; SKX-NEXT: korw %k1, %k0, %k0
; SKX-NEXT: kmovd %k0, %eax		; SKX-NEXT: kmovd %k0, %eax
; SKX-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>		; SKX-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
; SKX-NEXT: retq		; SKX-NEXT: retq
%a_i = trunc i32 %a to i1		%a_i = trunc i32 %a to i1
%maskv = insertelement <16 x i1> <i1 true, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, i1 %a_i, i32 0		%maskv = insertelement <16 x i1> <i1 true, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, i1 %a_i, i32 0
%res = bitcast <16 x i1> %maskv to i16		%res = bitcast <16 x i1> %maskv to i16
ret i16 %res		ret i16 %res
}		}
▲ Show 20 Lines • Show All 323 Lines • Show Last 20 Lines

test/CodeGen/X86/avx512-fsel.ll

	; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py			; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
	; RUN: llc -O0 -mattr=+avx512f < %s \| FileCheck %s			; RUN: llc -O0 -mattr=+avx512f < %s \| FileCheck %s

	target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"			target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
	target triple = "x86_64-apple-macosx10.11.0"			target triple = "x86_64-apple-macosx10.11.0"

	define i32 @test(float %a, float %b) {			define i32 @test(float %a, float %b) {
	; CHECK-LABEL: test:			; CHECK-LABEL: test:
	; CHECK: ## BB#0:			; CHECK: ## BB#0:
	; CHECK-NEXT: pushq %rax			; CHECK-NEXT: pushq %rax
	; CHECK-NEXT: Lcfi0:			; CHECK-NEXT: Lcfi0:
	; CHECK-NEXT: .cfi_def_cfa_offset 16			; CHECK-NEXT: .cfi_def_cfa_offset 16
	; CHECK-NEXT: vucomiss %xmm1, %xmm0			; CHECK-NEXT: vcmpeqss %xmm1, %xmm0, %k0
	; CHECK-NEXT: setp %al			; CHECK-NEXT: kmovw %k0, %eax
	; CHECK-NEXT: setne %cl			; CHECK-NEXT: xorb $-1, %al
	; CHECK-NEXT: setnp %dl
	; CHECK-NEXT: sete %sil
	; CHECK-NEXT: andb %dl, %sil
	; CHECK-NEXT: ## implicit-def: %EDI
	; CHECK-NEXT: movb %sil, %dil
	; CHECK-NEXT: andl $1, %edi
	; CHECK-NEXT: kmovw %edi, %k0
	; CHECK-NEXT: orb %al, %cl
	; CHECK-NEXT: ## implicit-def: %EDI
	; CHECK-NEXT: movb %cl, %dil
	; CHECK-NEXT: andl $1, %edi
	; CHECK-NEXT: kmovw %edi, %k1
	; CHECK-NEXT: kmovw %k1, %edi
	; CHECK-NEXT: movb %dil, %al
	; CHECK-NEXT: testb $1, %al			; CHECK-NEXT: testb $1, %al
	; CHECK-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ## 2-byte Spill
	; CHECK-NEXT: jne LBB0_1			; CHECK-NEXT: jne LBB0_1
	; CHECK-NEXT: jmp LBB0_2			; CHECK-NEXT: jmp LBB0_2
	; CHECK-NEXT: LBB0_1: ## %L_0			; CHECK-NEXT: LBB0_1: ## %L_0
	; CHECK-NEXT: callq ___assert_rtn			; CHECK-NEXT: callq ___assert_rtn
	; CHECK-NEXT: LBB0_2: ## %L_1			; CHECK-NEXT: LBB0_2: ## %L_1
	; CHECK-NEXT: xorl %eax, %eax			; CHECK-NEXT: xorl %eax, %eax
	; CHECK-NEXT: popq %rcx			; CHECK-NEXT: popq %rcx
	; CHECK-NEXT: retq			; CHECK-NEXT: retq
	Show All 15 Lines

test/CodeGen/X86/avx512-i1test.ll

Show First 20 Lines • Show All 60 Lines • ▼ Show 20 Lines	L_30: ; preds = %bb51, %L_10
ret void		ret void
}		}

; The following test generates suboptimal code on AVX-512		; The following test generates suboptimal code on AVX-512
; PR 28175		; PR 28175
define i64 @func2(i1 zeroext %i, i32 %j) {		define i64 @func2(i1 zeroext %i, i32 %j) {
; CHECK-LABEL: func2:		; CHECK-LABEL: func2:
; CHECK: # BB#0: # %entry		; CHECK: # BB#0: # %entry
; CHECK-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
; CHECK-NEXT: testl %esi, %esi		; CHECK-NEXT: testl %esi, %esi
; CHECK-NEXT: je .LBB1_1		; CHECK-NEXT: je .LBB1_1
; CHECK-NEXT: # BB#2: # %if.then		; CHECK-NEXT: # BB#2: # %if.then
; CHECK-NEXT: jmp bar # TAILCALL		; CHECK-NEXT: jmp bar # TAILCALL
; CHECK-NEXT: .LBB1_1: # %return		; CHECK-NEXT: .LBB1_1: # %return
; CHECK-NEXT: orq $-2, %rdi		; CHECK-NEXT: movzbl %dil, %eax
; CHECK-NEXT: movq %rdi, %rax		; CHECK-NEXT: orq $-2, %rax
; CHECK-NEXT: retq		; CHECK-NEXT: retq
entry:		entry:
%tobool = icmp eq i32 %j, 0		%tobool = icmp eq i32 %j, 0
br i1 %tobool, label %if.end, label %if.then		br i1 %tobool, label %if.end, label %if.then

if.then: ; preds = %entry		if.then: ; preds = %entry
%call = tail call i64 @bar()		%call = tail call i64 @bar()
br label %return		br label %return
Show All 12 Lines

test/CodeGen/X86/avx512-insert-extract.ll

Show First 20 Lines • Show All 254 Lines • ▼ Show 20 Lines

define <16 x i32> @test11(<16 x i32>%a, <16 x i32>%b) {		define <16 x i32> @test11(<16 x i32>%a, <16 x i32>%b) {
; KNL-LABEL: test11:		; KNL-LABEL: test11:
; KNL: ## BB#0:		; KNL: ## BB#0:
; KNL-NEXT: vpcmpltud %zmm1, %zmm0, %k0		; KNL-NEXT: vpcmpltud %zmm1, %zmm0, %k0
; KNL-NEXT: kshiftlw $11, %k0, %k0		; KNL-NEXT: kshiftlw $11, %k0, %k0
; KNL-NEXT: kshiftrw $15, %k0, %k0		; KNL-NEXT: kshiftrw $15, %k0, %k0
; KNL-NEXT: kmovw %k0, %eax		; KNL-NEXT: kmovw %k0, %eax
; KNL-NEXT: andl $1, %eax		; KNL-NEXT: testb $1, %al
; KNL-NEXT: testb %al, %al
; KNL-NEXT: je LBB10_2		; KNL-NEXT: je LBB10_2
; KNL-NEXT: ## BB#1: ## %A		; KNL-NEXT: ## BB#1: ## %A
; KNL-NEXT: vmovdqa64 %zmm1, %zmm0		; KNL-NEXT: vmovdqa64 %zmm1, %zmm0
; KNL-NEXT: retq		; KNL-NEXT: retq
; KNL-NEXT: LBB10_2: ## %B		; KNL-NEXT: LBB10_2: ## %B
; KNL-NEXT: vpaddd %zmm0, %zmm1, %zmm0		; KNL-NEXT: vpaddd %zmm0, %zmm1, %zmm0
; KNL-NEXT: retq		; KNL-NEXT: retq
;		;
; SKX-LABEL: test11:		; SKX-LABEL: test11:
; SKX: ## BB#0:		; SKX: ## BB#0:
; SKX-NEXT: vpcmpltud %zmm1, %zmm0, %k0		; SKX-NEXT: vpcmpltud %zmm1, %zmm0, %k0
; SKX-NEXT: kshiftlw $11, %k0, %k0		; SKX-NEXT: kshiftlw $11, %k0, %k0
; SKX-NEXT: kshiftrw $15, %k0, %k0		; SKX-NEXT: kshiftrw $15, %k0, %k0
; SKX-NEXT: kmovd %k0, %eax		; SKX-NEXT: kmovb %k0, %eax
; SKX-NEXT: andl $1, %eax		; SKX-NEXT: testb $1, %al
; SKX-NEXT: testb %al, %al
; SKX-NEXT: je LBB10_2		; SKX-NEXT: je LBB10_2
; SKX-NEXT: ## BB#1: ## %A		; SKX-NEXT: ## BB#1: ## %A
; SKX-NEXT: vmovdqa64 %zmm1, %zmm0		; SKX-NEXT: vmovdqa64 %zmm1, %zmm0
; SKX-NEXT: retq		; SKX-NEXT: retq
; SKX-NEXT: LBB10_2: ## %B		; SKX-NEXT: LBB10_2: ## %B
; SKX-NEXT: vpaddd %zmm0, %zmm1, %zmm0		; SKX-NEXT: vpaddd %zmm0, %zmm1, %zmm0
; SKX-NEXT: retq		; SKX-NEXT: retq
%cmp_res = icmp ult <16 x i32> %a, %b		%cmp_res = icmp ult <16 x i32> %a, %b
%ia = extractelement <16 x i1> %cmp_res, i32 4		%ia = extractelement <16 x i1> %cmp_res, i32 4
br i1 %ia, label %A, label %B		br i1 %ia, label %A, label %B
A:		A:
ret <16 x i32>%b		ret <16 x i32>%b
B:		B:
%c = add <16 x i32>%b, %a		%c = add <16 x i32>%b, %a
ret <16 x i32>%c		ret <16 x i32>%c
}		}

define i64 @test12(<16 x i64>%a, <16 x i64>%b, i64 %a1, i64 %b1) {		define i64 @test12(<16 x i64>%a, <16 x i64>%b, i64 %a1, i64 %b1) {
; KNL-LABEL: test12:		; KNL-LABEL: test12:
; KNL: ## BB#0:		; KNL: ## BB#0:
; KNL-NEXT: vpcmpgtq %zmm0, %zmm2, %k0		; KNL-NEXT: vpcmpgtq %zmm0, %zmm2, %k0
; KNL-NEXT: vpcmpgtq %zmm1, %zmm3, %k1
; KNL-NEXT: kunpckbw %k0, %k1, %k0
; KNL-NEXT: kshiftlw $15, %k0, %k0		; KNL-NEXT: kshiftlw $15, %k0, %k0
; KNL-NEXT: kshiftrw $15, %k0, %k0		; KNL-NEXT: kshiftrw $15, %k0, %k0
; KNL-NEXT: kmovw %k0, %eax		; KNL-NEXT: kmovw %k0, %eax
; KNL-NEXT: andl $1, %eax		; KNL-NEXT: testb $1, %al
; KNL-NEXT: testb %al, %al
; KNL-NEXT: cmoveq %rsi, %rdi		; KNL-NEXT: cmoveq %rsi, %rdi
; KNL-NEXT: movq %rdi, %rax		; KNL-NEXT: movq %rdi, %rax
; KNL-NEXT: retq		; KNL-NEXT: retq
;		;
; SKX-LABEL: test12:		; SKX-LABEL: test12:
; SKX: ## BB#0:		; SKX: ## BB#0:
; SKX-NEXT: vpcmpgtq %zmm0, %zmm2, %k0		; SKX-NEXT: vpcmpgtq %zmm0, %zmm2, %k0
; SKX-NEXT: vpcmpgtq %zmm1, %zmm3, %k1		; SKX-NEXT: kshiftlb $7, %k0, %k0
; SKX-NEXT: kunpckbw %k0, %k1, %k0		; SKX-NEXT: kshiftrb $7, %k0, %k0
; SKX-NEXT: kshiftlw $15, %k0, %k0		; SKX-NEXT: kmovb %k0, %eax
; SKX-NEXT: kshiftrw $15, %k0, %k0		; SKX-NEXT: testb $1, %al
; SKX-NEXT: kmovd %k0, %eax
; SKX-NEXT: andl $1, %eax
; SKX-NEXT: testb %al, %al
; SKX-NEXT: cmoveq %rsi, %rdi		; SKX-NEXT: cmoveq %rsi, %rdi
; SKX-NEXT: movq %rdi, %rax		; SKX-NEXT: movq %rdi, %rax
; SKX-NEXT: vzeroupper		; SKX-NEXT: vzeroupper
; SKX-NEXT: retq		; SKX-NEXT: retq
%cmpvector_func.i = icmp slt <16 x i64> %a, %b		%cmpvector_func.i = icmp slt <16 x i64> %a, %b
%extract24vector_func.i = extractelement <16 x i1> %cmpvector_func.i, i32 0		%extract24vector_func.i = extractelement <16 x i1> %cmpvector_func.i, i32 0
%res = select i1 %extract24vector_func.i, i64 %a1, i64 %b1		%res = select i1 %extract24vector_func.i, i64 %a1, i64 %b1
ret i64 %res		ret i64 %res
}		}

define i16 @test13(i32 %a, i32 %b) {		define i16 @test13(i32 %a, i32 %b) {
; KNL-LABEL: test13:		; KNL-LABEL: test13:
; KNL: ## BB#0:		; KNL: ## BB#0:
; KNL-NEXT: cmpl %esi, %edi		; KNL-NEXT: cmpl %esi, %edi
; KNL-NEXT: setb %al		; KNL-NEXT: setb %al
		; KNL-NEXT: movw $-4, %cx
		; KNL-NEXT: kmovw %ecx, %k0
		; KNL-NEXT: kshiftrw $1, %k0, %k0
		; KNL-NEXT: kshiftlw $1, %k0, %k0
; KNL-NEXT: andl $1, %eax		; KNL-NEXT: andl $1, %eax
; KNL-NEXT: kmovw %eax, %k0
; KNL-NEXT: movw $-4, %ax
; KNL-NEXT: kmovw %eax, %k1		; KNL-NEXT: kmovw %eax, %k1
; KNL-NEXT: kshiftrw $1, %k1, %k1		; KNL-NEXT: korw %k1, %k0, %k0
; KNL-NEXT: kshiftlw $1, %k1, %k1
; KNL-NEXT: korw %k0, %k1, %k0
; KNL-NEXT: kmovw %k0, %eax		; KNL-NEXT: kmovw %k0, %eax
; KNL-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>		; KNL-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
; KNL-NEXT: retq		; KNL-NEXT: retq
;		;
; SKX-LABEL: test13:		; SKX-LABEL: test13:
; SKX: ## BB#0:		; SKX: ## BB#0:
; SKX-NEXT: cmpl %esi, %edi		; SKX-NEXT: cmpl %esi, %edi
; SKX-NEXT: setb %al		; SKX-NEXT: setb %al
		; SKX-NEXT: movw $-4, %cx
		; SKX-NEXT: kmovd %ecx, %k0
		; SKX-NEXT: kshiftrw $1, %k0, %k0
		; SKX-NEXT: kshiftlw $1, %k0, %k0
; SKX-NEXT: andl $1, %eax		; SKX-NEXT: andl $1, %eax
; SKX-NEXT: kmovd %eax, %k0		; SKX-NEXT: kmovw %eax, %k1
; SKX-NEXT: movw $-4, %ax		; SKX-NEXT: korw %k1, %k0, %k0
; SKX-NEXT: kmovd %eax, %k1
; SKX-NEXT: kshiftrw $1, %k1, %k1
; SKX-NEXT: kshiftlw $1, %k1, %k1
; SKX-NEXT: korw %k0, %k1, %k0
; SKX-NEXT: kmovd %k0, %eax		; SKX-NEXT: kmovd %k0, %eax
; SKX-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>		; SKX-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
; SKX-NEXT: retq		; SKX-NEXT: retq
%cmp_res = icmp ult i32 %a, %b		%cmp_res = icmp ult i32 %a, %b
%maskv = insertelement <16 x i1> <i1 true, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, i1 %cmp_res, i32 0		%maskv = insertelement <16 x i1> <i1 true, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, i1 %cmp_res, i32 0
%res = bitcast <16 x i1> %maskv to i16		%res = bitcast <16 x i1> %maskv to i16
ret i16 %res		ret i16 %res
}		}

define i64 @test14(<8 x i64>%a, <8 x i64>%b, i64 %a1, i64 %b1) {		define i64 @test14(<8 x i64>%a, <8 x i64>%b, i64 %a1, i64 %b1) {
; KNL-LABEL: test14:		; KNL-LABEL: test14:
; KNL: ## BB#0:		; KNL: ## BB#0:
; KNL-NEXT: vpcmpgtq %zmm0, %zmm1, %k0		; KNL-NEXT: vpcmpgtq %zmm0, %zmm1, %k0
; KNL-NEXT: kshiftlw $11, %k0, %k0		; KNL-NEXT: kshiftlw $11, %k0, %k0
; KNL-NEXT: kshiftrw $15, %k0, %k0		; KNL-NEXT: kshiftrw $15, %k0, %k0
; KNL-NEXT: kmovw %k0, %eax		; KNL-NEXT: kmovw %k0, %eax
; KNL-NEXT: andl $1, %eax		; KNL-NEXT: testb $1, %al
; KNL-NEXT: testb %al, %al
; KNL-NEXT: cmoveq %rsi, %rdi		; KNL-NEXT: cmoveq %rsi, %rdi
; KNL-NEXT: movq %rdi, %rax		; KNL-NEXT: movq %rdi, %rax
; KNL-NEXT: retq		; KNL-NEXT: retq
;		;
; SKX-LABEL: test14:		; SKX-LABEL: test14:
; SKX: ## BB#0:		; SKX: ## BB#0:
; SKX-NEXT: vpcmpgtq %zmm0, %zmm1, %k0		; SKX-NEXT: vpcmpgtq %zmm0, %zmm1, %k0
; SKX-NEXT: kshiftlb $3, %k0, %k0		; SKX-NEXT: kshiftlb $3, %k0, %k0
; SKX-NEXT: kshiftrb $7, %k0, %k0		; SKX-NEXT: kshiftrb $7, %k0, %k0
; SKX-NEXT: kmovd %k0, %eax		; SKX-NEXT: kmovb %k0, %eax
; SKX-NEXT: andl $1, %eax		; SKX-NEXT: testb $1, %al
; SKX-NEXT: testb %al, %al
; SKX-NEXT: cmoveq %rsi, %rdi		; SKX-NEXT: cmoveq %rsi, %rdi
; SKX-NEXT: movq %rdi, %rax		; SKX-NEXT: movq %rdi, %rax
; SKX-NEXT: vzeroupper		; SKX-NEXT: vzeroupper
; SKX-NEXT: retq		; SKX-NEXT: retq
%cmpvector_func.i = icmp slt <8 x i64> %a, %b		%cmpvector_func.i = icmp slt <8 x i64> %a, %b
%extract24vector_func.i = extractelement <8 x i1> %cmpvector_func.i, i32 4		%extract24vector_func.i = extractelement <8 x i1> %cmpvector_func.i, i32 4
%res = select i1 %extract24vector_func.i, i64 %a1, i64 %b1		%res = select i1 %extract24vector_func.i, i64 %a1, i64 %b1
ret i64 %res		ret i64 %res
Show All 21 Lines	; SKX-NEXT: retq
%x1 = insertelement <16 x i1> undef, i1 %x, i32 10		%x1 = insertelement <16 x i1> undef, i1 %x, i32 10
%x2 = bitcast <16 x i1>%x1 to i16		%x2 = bitcast <16 x i1>%x1 to i16
ret i16 %x2		ret i16 %x2
}		}

define i16 @test16(i1 *%addr, i16 %a) {		define i16 @test16(i1 *%addr, i16 %a) {
; KNL-LABEL: test16:		; KNL-LABEL: test16:
; KNL: ## BB#0:		; KNL: ## BB#0:
; KNL-NEXT: movzbl (%rdi), %eax		; KNL-NEXT: movb (%rdi), %al
; KNL-NEXT: andl $1, %eax		; KNL-NEXT: kmovw %esi, %k1
		; KNL-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; KNL-NEXT: kmovw %eax, %k1		; KNL-NEXT: kmovw %eax, %k1
; KNL-NEXT: kmovw %esi, %k2
; KNL-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k2} {z}
; KNL-NEXT: vpternlogd $255, %zmm1, %zmm1, %zmm1 {%k1} {z}		; KNL-NEXT: vpternlogd $255, %zmm1, %zmm1, %zmm1 {%k1} {z}
; KNL-NEXT: vmovdqa32 {{.*#+}} zmm2 = [0,1,2,3,4,5,6,7,8,9,16,11,12,13,14,15]		; KNL-NEXT: vmovdqa32 {{.*#+}} zmm2 = [0,1,2,3,4,5,6,7,8,9,16,11,12,13,14,15]
; KNL-NEXT: vpermi2d %zmm1, %zmm0, %zmm2		; KNL-NEXT: vpermi2d %zmm1, %zmm0, %zmm2
; KNL-NEXT: vpslld $31, %zmm2, %zmm0		; KNL-NEXT: vpslld $31, %zmm2, %zmm0
; KNL-NEXT: vptestmd %zmm0, %zmm0, %k0		; KNL-NEXT: vptestmd %zmm0, %zmm0, %k0
; KNL-NEXT: kmovw %k0, %eax		; KNL-NEXT: kmovw %k0, %eax
; KNL-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>		; KNL-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
; KNL-NEXT: retq		; KNL-NEXT: retq
;		;
; SKX-LABEL: test16:		; SKX-LABEL: test16:
; SKX: ## BB#0:		; SKX: ## BB#0:
; SKX-NEXT: movzbl (%rdi), %eax		; SKX-NEXT: movb (%rdi), %al
; SKX-NEXT: andl $1, %eax		; SKX-NEXT: kmovd %esi, %k0
; SKX-NEXT: kmovd %eax, %k0		; SKX-NEXT: vpmovm2d %k0, %zmm0
; SKX-NEXT: kmovd %esi, %k1		; SKX-NEXT: kmovb %eax, %k0
; SKX-NEXT: vpmovm2d %k1, %zmm0
; SKX-NEXT: vpmovm2d %k0, %zmm1		; SKX-NEXT: vpmovm2d %k0, %zmm1
; SKX-NEXT: vmovdqa32 {{.*#+}} zmm2 = [0,1,2,3,4,5,6,7,8,9,16,11,12,13,14,15]		; SKX-NEXT: vmovdqa32 {{.*#+}} zmm2 = [0,1,2,3,4,5,6,7,8,9,16,11,12,13,14,15]
; SKX-NEXT: vpermi2d %zmm1, %zmm0, %zmm2		; SKX-NEXT: vpermi2d %zmm1, %zmm0, %zmm2
; SKX-NEXT: vpmovd2m %zmm2, %k0		; SKX-NEXT: vpmovd2m %zmm2, %k0
; SKX-NEXT: kmovd %k0, %eax		; SKX-NEXT: kmovd %k0, %eax
; SKX-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>		; SKX-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
; SKX-NEXT: vzeroupper		; SKX-NEXT: vzeroupper
; SKX-NEXT: retq		; SKX-NEXT: retq
%x = load i1 , i1 * %addr, align 128		%x = load i1 , i1 * %addr, align 128
%a1 = bitcast i16 %a to <16 x i1>		%a1 = bitcast i16 %a to <16 x i1>
%x1 = insertelement <16 x i1> %a1, i1 %x, i32 10		%x1 = insertelement <16 x i1> %a1, i1 %x, i32 10
%x2 = bitcast <16 x i1>%x1 to i16		%x2 = bitcast <16 x i1>%x1 to i16
ret i16 %x2		ret i16 %x2
}		}

define i8 @test17(i1 *%addr, i8 %a) {		define i8 @test17(i1 *%addr, i8 %a) {
; KNL-LABEL: test17:		; KNL-LABEL: test17:
; KNL: ## BB#0:		; KNL: ## BB#0:
; KNL-NEXT: movzbl (%rdi), %eax		; KNL-NEXT: movb (%rdi), %al
; KNL-NEXT: andl $1, %eax		; KNL-NEXT: kmovw %esi, %k1
		; KNL-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; KNL-NEXT: kmovw %eax, %k1		; KNL-NEXT: kmovw %eax, %k1
; KNL-NEXT: kmovw %esi, %k2
; KNL-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k2} {z}
; KNL-NEXT: vpternlogq $255, %zmm1, %zmm1, %zmm1 {%k1} {z}		; KNL-NEXT: vpternlogq $255, %zmm1, %zmm1, %zmm1 {%k1} {z}
; KNL-NEXT: vmovdqa64 {{.*#+}} zmm2 = [0,1,2,3,8,5,6,7]		; KNL-NEXT: vmovdqa64 {{.*#+}} zmm2 = [0,1,2,3,8,5,6,7]
; KNL-NEXT: vpermi2q %zmm1, %zmm0, %zmm2		; KNL-NEXT: vpermi2q %zmm1, %zmm0, %zmm2
; KNL-NEXT: vpsllq $63, %zmm2, %zmm0		; KNL-NEXT: vpsllq $63, %zmm2, %zmm0
; KNL-NEXT: vptestmq %zmm0, %zmm0, %k0		; KNL-NEXT: vptestmq %zmm0, %zmm0, %k0
; KNL-NEXT: kmovw %k0, %eax		; KNL-NEXT: kmovw %k0, %eax
; KNL-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>		; KNL-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
; KNL-NEXT: retq		; KNL-NEXT: retq
;		;
; SKX-LABEL: test17:		; SKX-LABEL: test17:
; SKX: ## BB#0:		; SKX: ## BB#0:
; SKX-NEXT: movzbl (%rdi), %eax		; SKX-NEXT: movb (%rdi), %al
; SKX-NEXT: andl $1, %eax		; SKX-NEXT: kmovd %esi, %k0
; SKX-NEXT: kmovd %eax, %k0		; SKX-NEXT: vpmovm2q %k0, %zmm0
; SKX-NEXT: kmovd %esi, %k1		; SKX-NEXT: kmovb %eax, %k0
; SKX-NEXT: vpmovm2q %k1, %zmm0
; SKX-NEXT: vpmovm2q %k0, %zmm1		; SKX-NEXT: vpmovm2q %k0, %zmm1
; SKX-NEXT: vmovdqa64 {{.*#+}} zmm2 = [0,1,2,3,8,5,6,7]		; SKX-NEXT: vmovdqa64 {{.*#+}} zmm2 = [0,1,2,3,8,5,6,7]
; SKX-NEXT: vpermi2q %zmm1, %zmm0, %zmm2		; SKX-NEXT: vpermi2q %zmm1, %zmm0, %zmm2
; SKX-NEXT: vpmovq2m %zmm2, %k0		; SKX-NEXT: vpmovq2m %zmm2, %k0
; SKX-NEXT: kmovd %k0, %eax		; SKX-NEXT: kmovd %k0, %eax
; SKX-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>		; SKX-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
; SKX-NEXT: vzeroupper		; SKX-NEXT: vzeroupper
; SKX-NEXT: retq		; SKX-NEXT: retq
▲ Show 20 Lines • Show All 783 Lines • ▼ Show 20 Lines
; KNL-NEXT: movq %rbp, %rsp		; KNL-NEXT: movq %rbp, %rsp
; KNL-NEXT: popq %rbp		; KNL-NEXT: popq %rbp
; KNL-NEXT: retq		; KNL-NEXT: retq
;		;
; SKX-LABEL: test_insertelement_v32i1:		; SKX-LABEL: test_insertelement_v32i1:
; SKX: ## BB#0:		; SKX: ## BB#0:
; SKX-NEXT: cmpl %esi, %edi		; SKX-NEXT: cmpl %esi, %edi
; SKX-NEXT: setb %al		; SKX-NEXT: setb %al
; SKX-NEXT: andl $1, %eax		; SKX-NEXT: vpcmpltud %zmm2, %zmm0, %k0
; SKX-NEXT: kmovd %eax, %k0		; SKX-NEXT: vpcmpltud %zmm3, %zmm1, %k1
; SKX-NEXT: vpcmpltud %zmm2, %zmm0, %k1		; SKX-NEXT: kunpckwd %k0, %k1, %k0
; SKX-NEXT: vpcmpltud %zmm3, %zmm1, %k2		; SKX-NEXT: vpmovm2w %k0, %zmm0
; SKX-NEXT: kunpckwd %k1, %k2, %k1		; SKX-NEXT: kmovb %eax, %k0
; SKX-NEXT: vpmovm2w %k1, %zmm0
; SKX-NEXT: vpmovm2w %k0, %zmm1		; SKX-NEXT: vpmovm2w %k0, %zmm1
; SKX-NEXT: vmovdqu16 {{.*#+}} zmm2 = [0,1,2,3,32,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31]		; SKX-NEXT: vmovdqu16 {{.*#+}} zmm2 = [0,1,2,3,32,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31]
; SKX-NEXT: vpermi2w %zmm1, %zmm0, %zmm2		; SKX-NEXT: vpermi2w %zmm1, %zmm0, %zmm2
; SKX-NEXT: vpmovw2m %zmm2, %k0		; SKX-NEXT: vpmovw2m %zmm2, %k0
; SKX-NEXT: kmovd %k0, %eax		; SKX-NEXT: kmovd %k0, %eax
; SKX-NEXT: vzeroupper		; SKX-NEXT: vzeroupper
; SKX-NEXT: retq		; SKX-NEXT: retq
%cmp_res_i1 = icmp ult i32 %a, %b		%cmp_res_i1 = icmp ult i32 %a, %b
%cmp_cmp_vec = icmp ult <32 x i32> %x, %y		%cmp_cmp_vec = icmp ult <32 x i32> %x, %y
%maskv = insertelement <32 x i1> %cmp_cmp_vec, i1 %cmp_res_i1, i32 4		%maskv = insertelement <32 x i1> %cmp_cmp_vec, i1 %cmp_res_i1, i32 4
%res = bitcast <32 x i1> %maskv to i32		%res = bitcast <32 x i1> %maskv to i32
ret i32 %res		ret i32 %res
}		}

define i8 @test_iinsertelement_v4i1(i32 %a, i32 %b, <4 x i32> %x , <4 x i32> %y) {		define i8 @test_iinsertelement_v4i1(i32 %a, i32 %b, <4 x i32> %x , <4 x i32> %y) {
; KNL-LABEL: test_iinsertelement_v4i1:		; KNL-LABEL: test_iinsertelement_v4i1:
; KNL: ## BB#0:		; KNL: ## BB#0:
; KNL-NEXT: cmpl %esi, %edi		; KNL-NEXT: cmpl %esi, %edi
; KNL-NEXT: setb %al		; KNL-NEXT: setb %al
; KNL-NEXT: andl $1, %eax
; KNL-NEXT: kmovw %eax, %k1
; KNL-NEXT: vpbroadcastd {{.*}}(%rip), %xmm2		; KNL-NEXT: vpbroadcastd {{.*}}(%rip), %xmm2
; KNL-NEXT: vpxor %xmm2, %xmm0, %xmm0		; KNL-NEXT: vpxor %xmm2, %xmm0, %xmm0
; KNL-NEXT: vpxor %xmm2, %xmm1, %xmm1		; KNL-NEXT: vpxor %xmm2, %xmm1, %xmm1
; KNL-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0		; KNL-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0
; KNL-NEXT: vpextrd $1, %xmm0, %eax		; KNL-NEXT: vpextrb $4, %xmm0, %ecx
; KNL-NEXT: andl $1, %eax		; KNL-NEXT: kmovw %ecx, %k1
; KNL-NEXT: kmovw %eax, %k2		; KNL-NEXT: vpternlogq $255, %zmm1, %zmm1, %zmm1 {%k1} {z}
; KNL-NEXT: vpternlogq $255, %zmm1, %zmm1, %zmm1 {%k2} {z}		; KNL-NEXT: vpextrb $0, %xmm0, %ecx
; KNL-NEXT: vmovd %xmm0, %eax		; KNL-NEXT: kmovw %ecx, %k1
; KNL-NEXT: andl $1, %eax		; KNL-NEXT: vpternlogq $255, %zmm2, %zmm2, %zmm2 {%k1} {z}
; KNL-NEXT: kmovw %eax, %k2
; KNL-NEXT: vpternlogq $255, %zmm2, %zmm2, %zmm2 {%k2} {z}
; KNL-NEXT: vmovdqa64 {{.*#+}} zmm3 = [0,8,2,3,4,5,6,7]		; KNL-NEXT: vmovdqa64 {{.*#+}} zmm3 = [0,8,2,3,4,5,6,7]
; KNL-NEXT: vpermi2q %zmm1, %zmm2, %zmm3		; KNL-NEXT: vpermi2q %zmm1, %zmm2, %zmm3
; KNL-NEXT: vpsllq $63, %zmm3, %zmm1		; KNL-NEXT: vpsllq $63, %zmm3, %zmm1
; KNL-NEXT: vptestmq %zmm1, %zmm1, %k2		; KNL-NEXT: vptestmq %zmm1, %zmm1, %k1
; KNL-NEXT: vpternlogq $255, %zmm1, %zmm1, %zmm1 {%k2} {z}		; KNL-NEXT: vpternlogq $255, %zmm1, %zmm1, %zmm1 {%k1} {z}
		; KNL-NEXT: kmovw %eax, %k1
; KNL-NEXT: vpternlogq $255, %zmm2, %zmm2, %zmm2 {%k1} {z}		; KNL-NEXT: vpternlogq $255, %zmm2, %zmm2, %zmm2 {%k1} {z}
; KNL-NEXT: vmovdqa64 {{.*#+}} zmm3 = [0,1,8,3,4,5,6,7]		; KNL-NEXT: vmovdqa64 {{.*#+}} zmm3 = [0,1,8,3,4,5,6,7]
; KNL-NEXT: vpermi2q %zmm2, %zmm1, %zmm3		; KNL-NEXT: vpermi2q %zmm2, %zmm1, %zmm3
; KNL-NEXT: vpsllq $63, %zmm3, %zmm1		; KNL-NEXT: vpsllq $63, %zmm3, %zmm1
; KNL-NEXT: vptestmq %zmm1, %zmm1, %k1		; KNL-NEXT: vptestmq %zmm1, %zmm1, %k1
; KNL-NEXT: vpternlogq $255, %zmm1, %zmm1, %zmm1 {%k1} {z}		; KNL-NEXT: vpternlogq $255, %zmm1, %zmm1, %zmm1 {%k1} {z}
; KNL-NEXT: vpextrd $3, %xmm0, %eax		; KNL-NEXT: vpextrb $12, %xmm0, %eax
; KNL-NEXT: andl $1, %eax
; KNL-NEXT: kmovw %eax, %k1		; KNL-NEXT: kmovw %eax, %k1
; KNL-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}		; KNL-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; KNL-NEXT: vmovdqa64 {{.*#+}} zmm2 = [0,1,2,8,4,5,6,7]		; KNL-NEXT: vmovdqa64 {{.*#+}} zmm2 = [0,1,2,8,4,5,6,7]
; KNL-NEXT: vpermi2q %zmm0, %zmm1, %zmm2		; KNL-NEXT: vpermi2q %zmm0, %zmm1, %zmm2
; KNL-NEXT: vpsllq $63, %zmm2, %zmm0		; KNL-NEXT: vpsllq $63, %zmm2, %zmm0
; KNL-NEXT: vptestmq %zmm0, %zmm0, %k0		; KNL-NEXT: vptestmq %zmm0, %zmm0, %k0
; KNL-NEXT: kmovw %k0, %eax		; KNL-NEXT: kmovw %k0, %eax
; KNL-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>		; KNL-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
; KNL-NEXT: retq		; KNL-NEXT: retq
;		;
; SKX-LABEL: test_iinsertelement_v4i1:		; SKX-LABEL: test_iinsertelement_v4i1:
; SKX: ## BB#0:		; SKX: ## BB#0:
; SKX-NEXT: cmpl %esi, %edi		; SKX-NEXT: cmpl %esi, %edi
; SKX-NEXT: setb %al		; SKX-NEXT: setb %al
; SKX-NEXT: andl $1, %eax		; SKX-NEXT: vpcmpltud %xmm1, %xmm0, %k0
; SKX-NEXT: kmovd %eax, %k0		; SKX-NEXT: vpmovm2d %k0, %xmm0
; SKX-NEXT: vpcmpltud %xmm1, %xmm0, %k1		; SKX-NEXT: kmovb %eax, %k0
; SKX-NEXT: vpmovm2d %k1, %xmm0
; SKX-NEXT: vpmovm2d %k0, %xmm1		; SKX-NEXT: vpmovm2d %k0, %xmm1
; SKX-NEXT: vpbroadcastq %xmm1, %xmm1		; SKX-NEXT: vpbroadcastq %xmm1, %xmm1
; SKX-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3]		; SKX-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3]
; SKX-NEXT: vpmovd2m %xmm0, %k0		; SKX-NEXT: vpmovd2m %xmm0, %k0
; SKX-NEXT: kmovd %k0, %eax		; SKX-NEXT: kmovd %k0, %eax
; SKX-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>		; SKX-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
; SKX-NEXT: retq		; SKX-NEXT: retq
%cmp_res_i1 = icmp ult i32 %a, %b		%cmp_res_i1 = icmp ult i32 %a, %b
%cmp_cmp_vec = icmp ult <4 x i32> %x, %y		%cmp_cmp_vec = icmp ult <4 x i32> %x, %y
%maskv = insertelement <4 x i1> %cmp_cmp_vec, i1 %cmp_res_i1, i32 2		%maskv = insertelement <4 x i1> %cmp_cmp_vec, i1 %cmp_res_i1, i32 2
%res0 = shufflevector <4 x i1> %maskv, <4 x i1> undef , <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 4, i32 4, i32 4>		%res0 = shufflevector <4 x i1> %maskv, <4 x i1> undef , <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 4, i32 4, i32 4>
%res = bitcast <8 x i1> %res0 to i8		%res = bitcast <8 x i1> %res0 to i8
ret i8 %res		ret i8 %res
}		}

define i8 @test_iinsertelement_v2i1(i32 %a, i32 %b, <2 x i64> %x , <2 x i64> %y) {		define i8 @test_iinsertelement_v2i1(i32 %a, i32 %b, <2 x i64> %x , <2 x i64> %y) {
; KNL-LABEL: test_iinsertelement_v2i1:		; KNL-LABEL: test_iinsertelement_v2i1:
; KNL: ## BB#0:		; KNL: ## BB#0:
; KNL-NEXT: cmpl %esi, %edi		; KNL-NEXT: cmpl %esi, %edi
; KNL-NEXT: setb %al		; KNL-NEXT: setb %al
; KNL-NEXT: andl $1, %eax
; KNL-NEXT: kmovw %eax, %k1
; KNL-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]		; KNL-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]
; KNL-NEXT: vpxor %xmm2, %xmm0, %xmm0		; KNL-NEXT: vpxor %xmm2, %xmm0, %xmm0
; KNL-NEXT: vpxor %xmm2, %xmm1, %xmm1		; KNL-NEXT: vpxor %xmm2, %xmm1, %xmm1
; KNL-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0		; KNL-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0
; KNL-NEXT: vmovq %xmm0, %rax		; KNL-NEXT: vpextrb $0, %xmm0, %ecx
; KNL-NEXT: andl $1, %eax		; KNL-NEXT: kmovw %ecx, %k1
; KNL-NEXT: kmovw %eax, %k2		; KNL-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; KNL-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k2} {z}		; KNL-NEXT: kmovw %eax, %k1
; KNL-NEXT: vpternlogq $255, %zmm1, %zmm1, %zmm1 {%k1} {z}		; KNL-NEXT: vpternlogq $255, %zmm1, %zmm1, %zmm1 {%k1} {z}
; KNL-NEXT: vmovdqa64 {{.*#+}} zmm2 = [0,8,2,3,4,5,6,7]		; KNL-NEXT: vmovdqa64 {{.*#+}} zmm2 = [0,8,2,3,4,5,6,7]
; KNL-NEXT: vpermi2q %zmm1, %zmm0, %zmm2		; KNL-NEXT: vpermi2q %zmm1, %zmm0, %zmm2
; KNL-NEXT: vpsllq $63, %zmm2, %zmm0		; KNL-NEXT: vpsllq $63, %zmm2, %zmm0
; KNL-NEXT: vptestmq %zmm0, %zmm0, %k0		; KNL-NEXT: vptestmq %zmm0, %zmm0, %k0
; KNL-NEXT: kmovw %k0, %eax		; KNL-NEXT: kmovw %k0, %eax
; KNL-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>		; KNL-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
; KNL-NEXT: retq		; KNL-NEXT: retq
;		;
; SKX-LABEL: test_iinsertelement_v2i1:		; SKX-LABEL: test_iinsertelement_v2i1:
; SKX: ## BB#0:		; SKX: ## BB#0:
; SKX-NEXT: cmpl %esi, %edi		; SKX-NEXT: cmpl %esi, %edi
; SKX-NEXT: setb %al		; SKX-NEXT: setb %al
; SKX-NEXT: andl $1, %eax		; SKX-NEXT: vpcmpltuq %xmm1, %xmm0, %k0
; SKX-NEXT: kmovd %eax, %k0		; SKX-NEXT: kmovb %eax, %k1
; SKX-NEXT: vpcmpltuq %xmm1, %xmm0, %k1
; SKX-NEXT: kshiftlw $1, %k1, %k1		; SKX-NEXT: kshiftlw $1, %k1, %k1
; SKX-NEXT: kshiftrw $1, %k1, %k1
; SKX-NEXT: kshiftlw $1, %k0, %k0		; SKX-NEXT: kshiftlw $1, %k0, %k0
; SKX-NEXT: korw %k0, %k1, %k0		; SKX-NEXT: kshiftrw $1, %k0, %k0
		; SKX-NEXT: korw %k1, %k0, %k0
; SKX-NEXT: kmovd %k0, %eax		; SKX-NEXT: kmovd %k0, %eax
; SKX-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>		; SKX-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
; SKX-NEXT: retq		; SKX-NEXT: retq
%cmp_res_i1 = icmp ult i32 %a, %b		%cmp_res_i1 = icmp ult i32 %a, %b
%cmp_cmp_vec = icmp ult <2 x i64> %x, %y		%cmp_cmp_vec = icmp ult <2 x i64> %x, %y
%maskv = insertelement <2 x i1> %cmp_cmp_vec, i1 %cmp_res_i1, i32 1		%maskv = insertelement <2 x i1> %cmp_cmp_vec, i1 %cmp_res_i1, i32 1
%res0 = shufflevector <2 x i1> %maskv, <2 x i1> undef , <8 x i32> <i32 0, i32 1, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>		%res0 = shufflevector <2 x i1> %maskv, <2 x i1> undef , <8 x i32> <i32 0, i32 1, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>
%res = bitcast <8 x i1> %res0 to i8		%res = bitcast <8 x i1> %res0 to i8
ret i8 %res		ret i8 %res
}		}

define zeroext i8 @test_extractelement_v2i1(<2 x i64> %a, <2 x i64> %b) {		define zeroext i8 @test_extractelement_v2i1(<2 x i64> %a, <2 x i64> %b) {
; KNL-LABEL: test_extractelement_v2i1:		; KNL-LABEL: test_extractelement_v2i1:
; KNL: ## BB#0:		; KNL: ## BB#0:
; KNL-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]		; KNL-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]
; KNL-NEXT: vpxor %xmm2, %xmm1, %xmm1		; KNL-NEXT: vpxor %xmm2, %xmm1, %xmm1
; KNL-NEXT: vpxor %xmm2, %xmm0, %xmm0		; KNL-NEXT: vpxor %xmm2, %xmm0, %xmm0
; KNL-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0		; KNL-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0
; KNL-NEXT: vpextrb $0, %xmm0, %eax		; KNL-NEXT: vpextrb $0, %xmm0, %eax
; KNL-NEXT: addb $4, %al		; KNL-NEXT: andb $1, %al
; KNL-NEXT: movzbl %al, %eax		; KNL-NEXT: movb $4, %cl
		; KNL-NEXT: subb %al, %cl
		; KNL-NEXT: movzbl %cl, %eax
; KNL-NEXT: retq		; KNL-NEXT: retq
;		;
; SKX-LABEL: test_extractelement_v2i1:		; SKX-LABEL: test_extractelement_v2i1:
; SKX: ## BB#0:		; SKX: ## BB#0:
; SKX-NEXT: vpcmpnleuq %xmm1, %xmm0, %k0		; SKX-NEXT: vpcmpnleuq %xmm1, %xmm0, %k0
; SKX-NEXT: kshiftlw $15, %k0, %k0		; SKX-NEXT: kshiftlw $15, %k0, %k0
; SKX-NEXT: kshiftrw $15, %k0, %k0		; SKX-NEXT: kshiftrw $15, %k0, %k0
; SKX-NEXT: kmovd %k0, %eax		; SKX-NEXT: kmovb %k0, %eax
; SKX-NEXT: andl $1, %eax		; SKX-NEXT: andb $1, %al
; SKX-NEXT: cmpb $1, %al		; SKX-NEXT: movb $4, %cl
; SKX-NEXT: movb $3, %al		; SKX-NEXT: subb %al, %cl
; SKX-NEXT: adcb $0, %al		; SKX-NEXT: movzbl %cl, %eax
; SKX-NEXT: movzbl %al, %eax
; SKX-NEXT: retq		; SKX-NEXT: retq
%t1 = icmp ugt <2 x i64> %a, %b		%t1 = icmp ugt <2 x i64> %a, %b
%t2 = extractelement <2 x i1> %t1, i32 0		%t2 = extractelement <2 x i1> %t1, i32 0
%res = select i1 %t2, i8 3, i8 4		%res = select i1 %t2, i8 3, i8 4
ret i8 %res		ret i8 %res
}		}

define zeroext i8 @extractelement_v2i1_alt(<2 x i64> %a, <2 x i64> %b) {		define zeroext i8 @extractelement_v2i1_alt(<2 x i64> %a, <2 x i64> %b) {
; KNL-LABEL: extractelement_v2i1_alt:		; KNL-LABEL: extractelement_v2i1_alt:
; KNL: ## BB#0:		; KNL: ## BB#0:
; KNL-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]		; KNL-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]
; KNL-NEXT: vpxor %xmm2, %xmm1, %xmm1		; KNL-NEXT: vpxor %xmm2, %xmm1, %xmm1
; KNL-NEXT: vpxor %xmm2, %xmm0, %xmm0		; KNL-NEXT: vpxor %xmm2, %xmm0, %xmm0
; KNL-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0		; KNL-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0
; KNL-NEXT: vpextrb $0, %xmm0, %eax		; KNL-NEXT: vpextrb $0, %xmm0, %eax
; KNL-NEXT: addb $4, %al		; KNL-NEXT: andb $1, %al
; KNL-NEXT: movzbl %al, %eax		; KNL-NEXT: movb $4, %cl
		; KNL-NEXT: subb %al, %cl
		; KNL-NEXT: movzbl %cl, %eax
; KNL-NEXT: retq		; KNL-NEXT: retq
;		;
; SKX-LABEL: extractelement_v2i1_alt:		; SKX-LABEL: extractelement_v2i1_alt:
; SKX: ## BB#0:		; SKX: ## BB#0:
; SKX-NEXT: vpcmpnleuq %xmm1, %xmm0, %k0		; SKX-NEXT: vpcmpnleuq %xmm1, %xmm0, %k0
; SKX-NEXT: kshiftlw $15, %k0, %k0		; SKX-NEXT: kshiftlw $15, %k0, %k0
; SKX-NEXT: kshiftrw $15, %k0, %k0		; SKX-NEXT: kshiftrw $15, %k0, %k0
; SKX-NEXT: kmovd %k0, %eax		; SKX-NEXT: kmovb %k0, %eax
; SKX-NEXT: andl $1, %eax		; SKX-NEXT: andb $1, %al
; SKX-NEXT: cmpb $1, %al		; SKX-NEXT: movb $4, %cl
; SKX-NEXT: movb $3, %al		; SKX-NEXT: subb %al, %cl
; SKX-NEXT: adcb $0, %al		; SKX-NEXT: movzbl %cl, %eax
; SKX-NEXT: movzbl %al, %eax
; SKX-NEXT: retq		; SKX-NEXT: retq
%t1 = icmp ugt <2 x i64> %a, %b		%t1 = icmp ugt <2 x i64> %a, %b
%t2 = extractelement <2 x i1> %t1, i32 0		%t2 = extractelement <2 x i1> %t1, i32 0
%sext = sext i1 %t2 to i8		%sext = sext i1 %t2 to i8
%res = add i8 %sext, 4		%res = add i8 %sext, 4
ret i8 %res		ret i8 %res
}		}

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; KNL-LABEL: test_extractelement_v64i1:		; KNL-LABEL: test_extractelement_v64i1:
; KNL: ## BB#0:		; KNL: ## BB#0:
; KNL-NEXT: vmovdqa {{.*#+}} ymm0 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128]		; KNL-NEXT: vmovdqa {{.*#+}} ymm0 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128]
; KNL-NEXT: vpxor %ymm0, %ymm3, %ymm2		; KNL-NEXT: vpxor %ymm0, %ymm3, %ymm2
; KNL-NEXT: vpxor %ymm0, %ymm1, %ymm0		; KNL-NEXT: vpxor %ymm0, %ymm1, %ymm0
; KNL-NEXT: vpcmpgtb %ymm2, %ymm0, %ymm0		; KNL-NEXT: vpcmpgtb %ymm2, %ymm0, %ymm0
; KNL-NEXT: vextracti128 $1, %ymm0, %xmm0		; KNL-NEXT: vextracti128 $1, %ymm0, %xmm0
; KNL-NEXT: vpextrb $15, %xmm0, %eax		; KNL-NEXT: vpextrb $15, %xmm0, %eax
; KNL-NEXT: addb $4, %al		; KNL-NEXT: andb $1, %al
; KNL-NEXT: movzbl %al, %eax		; KNL-NEXT: movb $4, %cl
		; KNL-NEXT: subb %al, %cl
		; KNL-NEXT: movzbl %cl, %eax
; KNL-NEXT: retq		; KNL-NEXT: retq
;		;
; SKX-LABEL: test_extractelement_v64i1:		; SKX-LABEL: test_extractelement_v64i1:
; SKX: ## BB#0:		; SKX: ## BB#0:
; SKX-NEXT: vpcmpnleub %zmm1, %zmm0, %k0		; SKX-NEXT: vpcmpnleub %zmm1, %zmm0, %k0
; SKX-NEXT: kshiftrq $63, %k0, %k0		; SKX-NEXT: kshiftrq $63, %k0, %k0
; SKX-NEXT: kmovd %k0, %eax		; SKX-NEXT: kmovb %k0, %eax
; SKX-NEXT: andl $1, %eax		; SKX-NEXT: andb $1, %al
; SKX-NEXT: cmpb $1, %al		; SKX-NEXT: movb $4, %cl
; SKX-NEXT: movb $3, %al		; SKX-NEXT: subb %al, %cl
; SKX-NEXT: adcb $0, %al		; SKX-NEXT: movzbl %cl, %eax
; SKX-NEXT: movzbl %al, %eax
; SKX-NEXT: vzeroupper		; SKX-NEXT: vzeroupper
; SKX-NEXT: retq		; SKX-NEXT: retq
%t1 = icmp ugt <64 x i8> %a, %b		%t1 = icmp ugt <64 x i8> %a, %b
%t2 = extractelement <64 x i1> %t1, i32 63		%t2 = extractelement <64 x i1> %t1, i32 63
%res = select i1 %t2, i8 3, i8 4		%res = select i1 %t2, i8 3, i8 4
ret i8 %res		ret i8 %res
}		}

define zeroext i8 @extractelement_v64i1_alt(<64 x i8> %a, <64 x i8> %b) {		define zeroext i8 @extractelement_v64i1_alt(<64 x i8> %a, <64 x i8> %b) {
; KNL-LABEL: extractelement_v64i1_alt:		; KNL-LABEL: extractelement_v64i1_alt:
; KNL: ## BB#0:		; KNL: ## BB#0:
; KNL-NEXT: vmovdqa {{.*#+}} ymm0 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128]		; KNL-NEXT: vmovdqa {{.*#+}} ymm0 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128]
; KNL-NEXT: vpxor %ymm0, %ymm3, %ymm2		; KNL-NEXT: vpxor %ymm0, %ymm3, %ymm2
; KNL-NEXT: vpxor %ymm0, %ymm1, %ymm0		; KNL-NEXT: vpxor %ymm0, %ymm1, %ymm0
; KNL-NEXT: vpcmpgtb %ymm2, %ymm0, %ymm0		; KNL-NEXT: vpcmpgtb %ymm2, %ymm0, %ymm0
; KNL-NEXT: vextracti128 $1, %ymm0, %xmm0		; KNL-NEXT: vextracti128 $1, %ymm0, %xmm0
; KNL-NEXT: vpextrb $15, %xmm0, %eax		; KNL-NEXT: vpextrb $15, %xmm0, %eax
; KNL-NEXT: addb $4, %al		; KNL-NEXT: andb $1, %al
; KNL-NEXT: movzbl %al, %eax		; KNL-NEXT: movb $4, %cl
		; KNL-NEXT: subb %al, %cl
		; KNL-NEXT: movzbl %cl, %eax
; KNL-NEXT: retq		; KNL-NEXT: retq
;		;
; SKX-LABEL: extractelement_v64i1_alt:		; SKX-LABEL: extractelement_v64i1_alt:
; SKX: ## BB#0:		; SKX: ## BB#0:
; SKX-NEXT: vpcmpnleub %zmm1, %zmm0, %k0		; SKX-NEXT: vpcmpnleub %zmm1, %zmm0, %k0
; SKX-NEXT: kshiftrq $63, %k0, %k0		; SKX-NEXT: kshiftrq $63, %k0, %k0
; SKX-NEXT: kmovd %k0, %eax		; SKX-NEXT: kmovb %k0, %eax
; SKX-NEXT: andl $1, %eax		; SKX-NEXT: andb $1, %al
; SKX-NEXT: cmpb $1, %al		; SKX-NEXT: movb $4, %cl
; SKX-NEXT: movb $3, %al		; SKX-NEXT: subb %al, %cl
; SKX-NEXT: adcb $0, %al		; SKX-NEXT: movzbl %cl, %eax
; SKX-NEXT: movzbl %al, %eax
; SKX-NEXT: vzeroupper		; SKX-NEXT: vzeroupper
; SKX-NEXT: retq		; SKX-NEXT: retq
%t1 = icmp ugt <64 x i8> %a, %b		%t1 = icmp ugt <64 x i8> %a, %b
%t2 = extractelement <64 x i1> %t1, i32 63		%t2 = extractelement <64 x i1> %t1, i32 63
%sext = sext i1 %t2 to i8		%sext = sext i1 %t2 to i8
%res = add i8 %sext, 4		%res = add i8 %sext, 4
ret i8 %res		ret i8 %res
}		}
▲ Show 20 Lines • Show All 736 Lines • ▼ Show 20 Lines
;		;
; SKX-LABEL: test_extractelement_varible_v2i1:		; SKX-LABEL: test_extractelement_varible_v2i1:
; SKX: ## BB#0:		; SKX: ## BB#0:
; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>		; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
; SKX-NEXT: vpcmpnleuq %xmm1, %xmm0, %k0		; SKX-NEXT: vpcmpnleuq %xmm1, %xmm0, %k0
; SKX-NEXT: vpmovm2q %k0, %xmm0		; SKX-NEXT: vpmovm2q %k0, %xmm0
; SKX-NEXT: vmovdqa %xmm0, -{{[0-9]+}}(%rsp)		; SKX-NEXT: vmovdqa %xmm0, -{{[0-9]+}}(%rsp)
; SKX-NEXT: andl $1, %edi		; SKX-NEXT: andl $1, %edi
; SKX-NEXT: movl -24(%rsp,%rdi,8), %eax		; SKX-NEXT: movzbl -24(%rsp,%rdi,8), %eax
; SKX-NEXT: andl $1, %eax		; SKX-NEXT: andl $1, %eax
; SKX-NEXT: retq		; SKX-NEXT: retq
%t1 = icmp ugt <2 x i64> %a, %b		%t1 = icmp ugt <2 x i64> %a, %b
%t2 = extractelement <2 x i1> %t1, i32 %index		%t2 = extractelement <2 x i1> %t1, i32 %index
%res = zext i1 %t2 to i8		%res = zext i1 %t2 to i8
ret i8 %res		ret i8 %res
}		}

Show All 13 Lines
;		;
; SKX-LABEL: test_extractelement_varible_v4i1:		; SKX-LABEL: test_extractelement_varible_v4i1:
; SKX: ## BB#0:		; SKX: ## BB#0:
; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>		; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
; SKX-NEXT: vpcmpnleud %xmm1, %xmm0, %k0		; SKX-NEXT: vpcmpnleud %xmm1, %xmm0, %k0
; SKX-NEXT: vpmovm2d %k0, %xmm0		; SKX-NEXT: vpmovm2d %k0, %xmm0
; SKX-NEXT: vmovdqa %xmm0, -{{[0-9]+}}(%rsp)		; SKX-NEXT: vmovdqa %xmm0, -{{[0-9]+}}(%rsp)
; SKX-NEXT: andl $3, %edi		; SKX-NEXT: andl $3, %edi
; SKX-NEXT: movl -24(%rsp,%rdi,4), %eax		; SKX-NEXT: movzbl -24(%rsp,%rdi,4), %eax
; SKX-NEXT: andl $1, %eax		; SKX-NEXT: andl $1, %eax
; SKX-NEXT: retq		; SKX-NEXT: retq
%t1 = icmp ugt <4 x i32> %a, %b		%t1 = icmp ugt <4 x i32> %a, %b
%t2 = extractelement <4 x i1> %t1, i32 %index		%t2 = extractelement <4 x i1> %t1, i32 %index
%res = zext i1 %t2 to i8		%res = zext i1 %t2 to i8
ret i8 %res		ret i8 %res
}		}

Show All 12 Lines
; KNL-NEXT: subq $128, %rsp		; KNL-NEXT: subq $128, %rsp
; KNL-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>		; KNL-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
; KNL-NEXT: ## kill: %YMM1<def> %YMM1<kill> %ZMM1<def>		; KNL-NEXT: ## kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
; KNL-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def>		; KNL-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; KNL-NEXT: vpcmpnleud %zmm1, %zmm0, %k1		; KNL-NEXT: vpcmpnleud %zmm1, %zmm0, %k1
; KNL-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}		; KNL-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; KNL-NEXT: vmovdqa64 %zmm0, (%rsp)		; KNL-NEXT: vmovdqa64 %zmm0, (%rsp)
; KNL-NEXT: andl $7, %edi		; KNL-NEXT: andl $7, %edi
; KNL-NEXT: movl (%rsp,%rdi,8), %eax		; KNL-NEXT: movzbl (%rsp,%rdi,8), %eax
; KNL-NEXT: andl $1, %eax		; KNL-NEXT: andl $1, %eax
; KNL-NEXT: movq %rbp, %rsp		; KNL-NEXT: movq %rbp, %rsp
; KNL-NEXT: popq %rbp		; KNL-NEXT: popq %rbp
; KNL-NEXT: retq		; KNL-NEXT: retq
;		;
; SKX-LABEL: test_extractelement_varible_v8i1:		; SKX-LABEL: test_extractelement_varible_v8i1:
; SKX: ## BB#0:		; SKX: ## BB#0:
; SKX-NEXT: pushq %rbp		; SKX-NEXT: pushq %rbp
; SKX-NEXT: Lcfi39:		; SKX-NEXT: Lcfi39:
; SKX-NEXT: .cfi_def_cfa_offset 16		; SKX-NEXT: .cfi_def_cfa_offset 16
; SKX-NEXT: Lcfi40:		; SKX-NEXT: Lcfi40:
; SKX-NEXT: .cfi_offset %rbp, -16		; SKX-NEXT: .cfi_offset %rbp, -16
; SKX-NEXT: movq %rsp, %rbp		; SKX-NEXT: movq %rsp, %rbp
; SKX-NEXT: Lcfi41:		; SKX-NEXT: Lcfi41:
; SKX-NEXT: .cfi_def_cfa_register %rbp		; SKX-NEXT: .cfi_def_cfa_register %rbp
; SKX-NEXT: andq $-64, %rsp		; SKX-NEXT: andq $-64, %rsp
; SKX-NEXT: subq $128, %rsp		; SKX-NEXT: subq $128, %rsp
; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>		; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
; SKX-NEXT: vpcmpnleud %ymm1, %ymm0, %k0		; SKX-NEXT: vpcmpnleud %ymm1, %ymm0, %k0
; SKX-NEXT: vpmovm2q %k0, %zmm0		; SKX-NEXT: vpmovm2q %k0, %zmm0
; SKX-NEXT: vmovdqa64 %zmm0, (%rsp)		; SKX-NEXT: vmovdqa64 %zmm0, (%rsp)
; SKX-NEXT: andl $7, %edi		; SKX-NEXT: andl $7, %edi
; SKX-NEXT: movl (%rsp,%rdi,8), %eax		; SKX-NEXT: movzbl (%rsp,%rdi,8), %eax
; SKX-NEXT: andl $1, %eax		; SKX-NEXT: andl $1, %eax
; SKX-NEXT: movq %rbp, %rsp		; SKX-NEXT: movq %rbp, %rsp
; SKX-NEXT: popq %rbp		; SKX-NEXT: popq %rbp
; SKX-NEXT: vzeroupper		; SKX-NEXT: vzeroupper
; SKX-NEXT: retq		; SKX-NEXT: retq
%t1 = icmp ugt <8 x i32> %a, %b		%t1 = icmp ugt <8 x i32> %a, %b
%t2 = extractelement <8 x i1> %t1, i32 %index		%t2 = extractelement <8 x i1> %t1, i32 %index
%res = zext i1 %t2 to i8		%res = zext i1 %t2 to i8
Show All 13 Lines
; KNL-NEXT: .cfi_def_cfa_register %rbp		; KNL-NEXT: .cfi_def_cfa_register %rbp
; KNL-NEXT: andq $-64, %rsp		; KNL-NEXT: andq $-64, %rsp
; KNL-NEXT: subq $128, %rsp		; KNL-NEXT: subq $128, %rsp
; KNL-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>		; KNL-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
; KNL-NEXT: vpcmpnleud %zmm1, %zmm0, %k1		; KNL-NEXT: vpcmpnleud %zmm1, %zmm0, %k1
; KNL-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}		; KNL-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; KNL-NEXT: vmovdqa32 %zmm0, (%rsp)		; KNL-NEXT: vmovdqa32 %zmm0, (%rsp)
; KNL-NEXT: andl $15, %edi		; KNL-NEXT: andl $15, %edi
; KNL-NEXT: movl (%rsp,%rdi,4), %eax		; KNL-NEXT: movzbl (%rsp,%rdi,4), %eax
; KNL-NEXT: andl $1, %eax		; KNL-NEXT: andl $1, %eax
; KNL-NEXT: movq %rbp, %rsp		; KNL-NEXT: movq %rbp, %rsp
; KNL-NEXT: popq %rbp		; KNL-NEXT: popq %rbp
; KNL-NEXT: retq		; KNL-NEXT: retq
;		;
; SKX-LABEL: test_extractelement_varible_v16i1:		; SKX-LABEL: test_extractelement_varible_v16i1:
; SKX: ## BB#0:		; SKX: ## BB#0:
; SKX-NEXT: pushq %rbp		; SKX-NEXT: pushq %rbp
; SKX-NEXT: Lcfi42:		; SKX-NEXT: Lcfi42:
; SKX-NEXT: .cfi_def_cfa_offset 16		; SKX-NEXT: .cfi_def_cfa_offset 16
; SKX-NEXT: Lcfi43:		; SKX-NEXT: Lcfi43:
; SKX-NEXT: .cfi_offset %rbp, -16		; SKX-NEXT: .cfi_offset %rbp, -16
; SKX-NEXT: movq %rsp, %rbp		; SKX-NEXT: movq %rsp, %rbp
; SKX-NEXT: Lcfi44:		; SKX-NEXT: Lcfi44:
; SKX-NEXT: .cfi_def_cfa_register %rbp		; SKX-NEXT: .cfi_def_cfa_register %rbp
; SKX-NEXT: andq $-64, %rsp		; SKX-NEXT: andq $-64, %rsp
; SKX-NEXT: subq $128, %rsp		; SKX-NEXT: subq $128, %rsp
; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>		; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
; SKX-NEXT: vpcmpnleud %zmm1, %zmm0, %k0		; SKX-NEXT: vpcmpnleud %zmm1, %zmm0, %k0
; SKX-NEXT: vpmovm2d %k0, %zmm0		; SKX-NEXT: vpmovm2d %k0, %zmm0
; SKX-NEXT: vmovdqa32 %zmm0, (%rsp)		; SKX-NEXT: vmovdqa32 %zmm0, (%rsp)
; SKX-NEXT: andl $15, %edi		; SKX-NEXT: andl $15, %edi
; SKX-NEXT: movl (%rsp,%rdi,4), %eax		; SKX-NEXT: movzbl (%rsp,%rdi,4), %eax
; SKX-NEXT: andl $1, %eax		; SKX-NEXT: andl $1, %eax
; SKX-NEXT: movq %rbp, %rsp		; SKX-NEXT: movq %rbp, %rsp
; SKX-NEXT: popq %rbp		; SKX-NEXT: popq %rbp
; SKX-NEXT: vzeroupper		; SKX-NEXT: vzeroupper
; SKX-NEXT: retq		; SKX-NEXT: retq
%t1 = icmp ugt <16 x i32> %a, %b		%t1 = icmp ugt <16 x i32> %a, %b
%t2 = extractelement <16 x i1> %t1, i32 %index		%t2 = extractelement <16 x i1> %t1, i32 %index
%res = zext i1 %t2 to i8		%res = zext i1 %t2 to i8
Show All 16 Lines
; KNL-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>		; KNL-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
; KNL-NEXT: vmovdqa {{.*#+}} ymm2 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128]		; KNL-NEXT: vmovdqa {{.*#+}} ymm2 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128]
; KNL-NEXT: vpxor %ymm2, %ymm1, %ymm1		; KNL-NEXT: vpxor %ymm2, %ymm1, %ymm1
; KNL-NEXT: vpxor %ymm2, %ymm0, %ymm0		; KNL-NEXT: vpxor %ymm2, %ymm0, %ymm0
; KNL-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm0		; KNL-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm0
; KNL-NEXT: vmovdqa %ymm0, (%rsp)		; KNL-NEXT: vmovdqa %ymm0, (%rsp)
; KNL-NEXT: andl $31, %edi		; KNL-NEXT: andl $31, %edi
; KNL-NEXT: movq %rsp, %rax		; KNL-NEXT: movq %rsp, %rax
; KNL-NEXT: movb (%rdi,%rax), %al		; KNL-NEXT: movzbl (%rdi,%rax), %eax
; KNL-NEXT: andb $1, %al		; KNL-NEXT: andl $1, %eax
; KNL-NEXT: movzbl %al, %eax
; KNL-NEXT: movq %rbp, %rsp		; KNL-NEXT: movq %rbp, %rsp
; KNL-NEXT: popq %rbp		; KNL-NEXT: popq %rbp
; KNL-NEXT: retq		; KNL-NEXT: retq
;		;
; SKX-LABEL: test_extractelement_varible_v32i1:		; SKX-LABEL: test_extractelement_varible_v32i1:
; SKX: ## BB#0:		; SKX: ## BB#0:
; SKX-NEXT: pushq %rbp		; SKX-NEXT: pushq %rbp
; SKX-NEXT: Lcfi45:		; SKX-NEXT: Lcfi45:
; SKX-NEXT: .cfi_def_cfa_offset 16		; SKX-NEXT: .cfi_def_cfa_offset 16
; SKX-NEXT: Lcfi46:		; SKX-NEXT: Lcfi46:
; SKX-NEXT: .cfi_offset %rbp, -16		; SKX-NEXT: .cfi_offset %rbp, -16
; SKX-NEXT: movq %rsp, %rbp		; SKX-NEXT: movq %rsp, %rbp
; SKX-NEXT: Lcfi47:		; SKX-NEXT: Lcfi47:
; SKX-NEXT: .cfi_def_cfa_register %rbp		; SKX-NEXT: .cfi_def_cfa_register %rbp
; SKX-NEXT: andq $-64, %rsp		; SKX-NEXT: andq $-64, %rsp
; SKX-NEXT: subq $128, %rsp		; SKX-NEXT: subq $128, %rsp
; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>		; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
; SKX-NEXT: vpcmpnleub %ymm1, %ymm0, %k0		; SKX-NEXT: vpcmpnleub %ymm1, %ymm0, %k0
; SKX-NEXT: vpmovm2w %k0, %zmm0		; SKX-NEXT: vpmovm2w %k0, %zmm0
; SKX-NEXT: vmovdqu16 %zmm0, (%rsp)		; SKX-NEXT: vmovdqu16 %zmm0, (%rsp)
; SKX-NEXT: andl $31, %edi		; SKX-NEXT: andl $31, %edi
; SKX-NEXT: movzwl (%rsp,%rdi,2), %eax		; SKX-NEXT: movzbl (%rsp,%rdi,2), %eax
; SKX-NEXT: andl $1, %eax		; SKX-NEXT: andl $1, %eax
; SKX-NEXT: movq %rbp, %rsp		; SKX-NEXT: movq %rbp, %rsp
; SKX-NEXT: popq %rbp		; SKX-NEXT: popq %rbp
; SKX-NEXT: vzeroupper		; SKX-NEXT: vzeroupper
; SKX-NEXT: retq		; SKX-NEXT: retq
%t1 = icmp ugt <32 x i8> %a, %b		%t1 = icmp ugt <32 x i8> %a, %b
%t2 = extractelement <32 x i1> %t1, i32 %index		%t2 = extractelement <32 x i1> %t1, i32 %index
%res = zext i1 %t2 to i8		%res = zext i1 %t2 to i8
ret i8 %res		ret i8 %res
}		}

test/CodeGen/X86/avx512-insert-extract_i1.ll

	Show All 16 Lines
	; SKX-NEXT: andq $-64, %rsp			; SKX-NEXT: andq $-64, %rsp
	; SKX-NEXT: subq $128, %rsp			; SKX-NEXT: subq $128, %rsp
	; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>			; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
	; SKX-NEXT: vpcmpnleub %zmm1, %zmm0, %k0			; SKX-NEXT: vpcmpnleub %zmm1, %zmm0, %k0
	; SKX-NEXT: vpmovm2b %k0, %zmm0			; SKX-NEXT: vpmovm2b %k0, %zmm0
	; SKX-NEXT: vmovdqu8 %zmm0, (%rsp)			; SKX-NEXT: vmovdqu8 %zmm0, (%rsp)
	; SKX-NEXT: andl $63, %edi			; SKX-NEXT: andl $63, %edi
	; SKX-NEXT: movq %rsp, %rax			; SKX-NEXT: movq %rsp, %rax
	; SKX-NEXT: movb (%rdi,%rax), %al			; SKX-NEXT: movzbl (%rdi,%rax), %eax
	; SKX-NEXT: andb $1, %al			; SKX-NEXT: andl $1, %eax
	; SKX-NEXT: movzbl %al, %eax
	; SKX-NEXT: movq %rbp, %rsp			; SKX-NEXT: movq %rbp, %rsp
	; SKX-NEXT: popq %rbp			; SKX-NEXT: popq %rbp
	; SKX-NEXT: vzeroupper			; SKX-NEXT: vzeroupper
	; SKX-NEXT: retq			; SKX-NEXT: retq
	%t1 = icmp ugt <64 x i8> %a, %b			%t1 = icmp ugt <64 x i8> %a, %b
	%t2 = extractelement <64 x i1> %t1, i32 %index			%t2 = extractelement <64 x i1> %t1, i32 %index
	%res = zext i1 %t2 to i8			%res = zext i1 %t2 to i8
	ret i8 %res			ret i8 %res
	}			}

test/CodeGen/X86/avx512-intrinsics-upgrade.ll

	Show First 20 Lines • Show All 2,875 Lines • ▼ Show 20 Lines
	}			}

	declare <8 x i64> @llvm.x86.avx512.mask.pmulu.dq.512(<16 x i32>, <16 x i32>, <8 x i64>, i8)			declare <8 x i64> @llvm.x86.avx512.mask.pmulu.dq.512(<16 x i32>, <16 x i32>, <8 x i64>, i8)

	define <4 x float> @test_mask_vextractf32x4(<4 x float> %b, <16 x float> %a, i8 %mask) {			define <4 x float> @test_mask_vextractf32x4(<4 x float> %b, <16 x float> %a, i8 %mask) {
	; CHECK-LABEL: test_mask_vextractf32x4:			; CHECK-LABEL: test_mask_vextractf32x4:
	; CHECK: ## BB#0:			; CHECK: ## BB#0:
	; CHECK-NEXT: vextractf32x4 $2, %zmm1, %xmm1			; CHECK-NEXT: vextractf32x4 $2, %zmm1, %xmm1
	; CHECK-NEXT: kmovw %edi, %k1			; CHECK-NEXT: kmovw %edi, %k0
	; CHECK-NEXT: kshiftlw $12, %k1, %k0			; CHECK-NEXT: kshiftlw $12, %k0, %k1
	; CHECK-NEXT: kshiftrw $15, %k0, %k0			; CHECK-NEXT: kshiftrw $15, %k1, %k1
	; CHECK-NEXT: kshiftlw $13, %k1, %k2			; CHECK-NEXT: kshiftlw $13, %k0, %k2
	; CHECK-NEXT: kshiftrw $15, %k2, %k2			; CHECK-NEXT: kshiftrw $15, %k2, %k2
	; CHECK-NEXT: kshiftlw $15, %k1, %k3			; CHECK-NEXT: kshiftlw $15, %k0, %k3
	; CHECK-NEXT: kshiftrw $15, %k3, %k3			; CHECK-NEXT: kshiftrw $15, %k3, %k3
	; CHECK-NEXT: kshiftlw $14, %k1, %k1			; CHECK-NEXT: kshiftlw $14, %k0, %k0
	; CHECK-NEXT: kshiftrw $15, %k1, %k1			; CHECK-NEXT: kshiftrw $15, %k0, %k0
	; CHECK-NEXT: kmovw %k1, %eax			; CHECK-NEXT: kmovw %k0, %eax
	; CHECK-NEXT: kmovw %k3, %ecx			; CHECK-NEXT: kmovw %k3, %ecx
	; CHECK-NEXT: vmovd %ecx, %xmm2			; CHECK-NEXT: vmovd %ecx, %xmm2
	; CHECK-NEXT: vpinsrd $1, %eax, %xmm2, %xmm2			; CHECK-NEXT: vpinsrb $4, %eax, %xmm2, %xmm2
	; CHECK-NEXT: kmovw %k2, %eax			; CHECK-NEXT: kmovw %k2, %eax
	; CHECK-NEXT: vpinsrd $2, %eax, %xmm2, %xmm2			; CHECK-NEXT: vpinsrb $8, %eax, %xmm2, %xmm2
	; CHECK-NEXT: kmovw %k0, %eax			; CHECK-NEXT: kmovw %k1, %eax
	; CHECK-NEXT: vpinsrd $3, %eax, %xmm2, %xmm2			; CHECK-NEXT: vpinsrb $12, %eax, %xmm2, %xmm2
	; CHECK-NEXT: vpslld $31, %xmm2, %xmm2			; CHECK-NEXT: vpslld $31, %xmm2, %xmm2
	; CHECK-NEXT: vblendvps %xmm2, %xmm1, %xmm0, %xmm0			; CHECK-NEXT: vblendvps %xmm2, %xmm1, %xmm0, %xmm0
	; CHECK-NEXT: retq			; CHECK-NEXT: retq
	%res = call <4 x float> @llvm.x86.avx512.mask.vextractf32x4.512(<16 x float> %a, i32 2, <4 x float> %b, i8 %mask)			%res = call <4 x float> @llvm.x86.avx512.mask.vextractf32x4.512(<16 x float> %a, i32 2, <4 x float> %b, i8 %mask)
	ret <4 x float> %res			ret <4 x float> %res
	}			}

	declare <4 x float> @llvm.x86.avx512.mask.vextractf32x4.512(<16 x float>, i32, <4 x float>, i8)			declare <4 x float> @llvm.x86.avx512.mask.vextractf32x4.512(<16 x float>, i32, <4 x float>, i8)

	define <4 x i64> @test_mask_vextracti64x4(<4 x i64> %b, <8 x i64> %a, i8 %mask) {			define <4 x i64> @test_mask_vextracti64x4(<4 x i64> %b, <8 x i64> %a, i8 %mask) {
	; CHECK-LABEL: test_mask_vextracti64x4:			; CHECK-LABEL: test_mask_vextracti64x4:
	; CHECK: ## BB#0:			; CHECK: ## BB#0:
	; CHECK-NEXT: vextracti64x4 $1, %zmm1, %ymm1			; CHECK-NEXT: vextracti64x4 $1, %zmm1, %ymm1
	; CHECK-NEXT: kmovw %edi, %k1			; CHECK-NEXT: kmovw %edi, %k0
	; CHECK-NEXT: kshiftlw $12, %k1, %k0			; CHECK-NEXT: kshiftlw $12, %k0, %k1
	; CHECK-NEXT: kshiftrw $15, %k0, %k0			; CHECK-NEXT: kshiftrw $15, %k1, %k1
	; CHECK-NEXT: kshiftlw $13, %k1, %k2			; CHECK-NEXT: kshiftlw $13, %k0, %k2
	; CHECK-NEXT: kshiftrw $15, %k2, %k2			; CHECK-NEXT: kshiftrw $15, %k2, %k2
	; CHECK-NEXT: kshiftlw $15, %k1, %k3			; CHECK-NEXT: kshiftlw $15, %k0, %k3
	; CHECK-NEXT: kshiftrw $15, %k3, %k3			; CHECK-NEXT: kshiftrw $15, %k3, %k3
	; CHECK-NEXT: kshiftlw $14, %k1, %k1			; CHECK-NEXT: kshiftlw $14, %k0, %k0
	; CHECK-NEXT: kshiftrw $15, %k1, %k1			; CHECK-NEXT: kshiftrw $15, %k0, %k0
	; CHECK-NEXT: kmovw %k1, %eax			; CHECK-NEXT: kmovw %k0, %eax
	; CHECK-NEXT: kmovw %k3, %ecx			; CHECK-NEXT: kmovw %k3, %ecx
	; CHECK-NEXT: vmovd %ecx, %xmm2			; CHECK-NEXT: vmovd %ecx, %xmm2
	; CHECK-NEXT: vpinsrd $1, %eax, %xmm2, %xmm2			; CHECK-NEXT: vpinsrb $4, %eax, %xmm2, %xmm2
	; CHECK-NEXT: kmovw %k2, %eax			; CHECK-NEXT: kmovw %k2, %eax
	; CHECK-NEXT: vpinsrd $2, %eax, %xmm2, %xmm2			; CHECK-NEXT: vpinsrb $8, %eax, %xmm2, %xmm2
	; CHECK-NEXT: kmovw %k0, %eax			; CHECK-NEXT: kmovw %k1, %eax
	; CHECK-NEXT: vpinsrd $3, %eax, %xmm2, %xmm2			; CHECK-NEXT: vpinsrb $12, %eax, %xmm2, %xmm2
	; CHECK-NEXT: vpslld $31, %xmm2, %xmm2			; CHECK-NEXT: vpslld $31, %xmm2, %xmm2
	; CHECK-NEXT: vpmovsxdq %xmm2, %ymm2			; CHECK-NEXT: vpmovsxdq %xmm2, %ymm2
	; CHECK-NEXT: vblendvpd %ymm2, %ymm1, %ymm0, %ymm0			; CHECK-NEXT: vblendvpd %ymm2, %ymm1, %ymm0, %ymm0
	; CHECK-NEXT: retq			; CHECK-NEXT: retq
	%res = call <4 x i64> @llvm.x86.avx512.mask.vextracti64x4.512(<8 x i64> %a, i32 1, <4 x i64> %b, i8 %mask)			%res = call <4 x i64> @llvm.x86.avx512.mask.vextracti64x4.512(<8 x i64> %a, i32 1, <4 x i64> %b, i8 %mask)
	ret <4 x i64> %res			ret <4 x i64> %res
	}			}

	declare <4 x i64> @llvm.x86.avx512.mask.vextracti64x4.512(<8 x i64>, i32, <4 x i64>, i8)			declare <4 x i64> @llvm.x86.avx512.mask.vextracti64x4.512(<8 x i64>, i32, <4 x i64>, i8)

	define <4 x i32> @test_maskz_vextracti32x4(<16 x i32> %a, i8 %mask) {			define <4 x i32> @test_maskz_vextracti32x4(<16 x i32> %a, i8 %mask) {
	; CHECK-LABEL: test_maskz_vextracti32x4:			; CHECK-LABEL: test_maskz_vextracti32x4:
	; CHECK: ## BB#0:			; CHECK: ## BB#0:
	; CHECK-NEXT: vextracti32x4 $2, %zmm0, %xmm0			; CHECK-NEXT: vextracti32x4 $2, %zmm0, %xmm0
	; CHECK-NEXT: kmovw %edi, %k1			; CHECK-NEXT: kmovw %edi, %k0
	; CHECK-NEXT: kshiftlw $12, %k1, %k0			; CHECK-NEXT: kshiftlw $12, %k0, %k1
	; CHECK-NEXT: kshiftrw $15, %k0, %k0			; CHECK-NEXT: kshiftrw $15, %k1, %k1
	; CHECK-NEXT: kshiftlw $13, %k1, %k2			; CHECK-NEXT: kshiftlw $13, %k0, %k2
	; CHECK-NEXT: kshiftrw $15, %k2, %k2			; CHECK-NEXT: kshiftrw $15, %k2, %k2
	; CHECK-NEXT: kshiftlw $15, %k1, %k3			; CHECK-NEXT: kshiftlw $15, %k0, %k3
	; CHECK-NEXT: kshiftrw $15, %k3, %k3			; CHECK-NEXT: kshiftrw $15, %k3, %k3
	; CHECK-NEXT: kshiftlw $14, %k1, %k1			; CHECK-NEXT: kshiftlw $14, %k0, %k0
	; CHECK-NEXT: kshiftrw $15, %k1, %k1			; CHECK-NEXT: kshiftrw $15, %k0, %k0
	; CHECK-NEXT: kmovw %k1, %eax			; CHECK-NEXT: kmovw %k0, %eax
	; CHECK-NEXT: kmovw %k3, %ecx			; CHECK-NEXT: kmovw %k3, %ecx
	; CHECK-NEXT: vmovd %ecx, %xmm1			; CHECK-NEXT: vmovd %ecx, %xmm1
	; CHECK-NEXT: vpinsrd $1, %eax, %xmm1, %xmm1			; CHECK-NEXT: vpinsrb $4, %eax, %xmm1, %xmm1
	; CHECK-NEXT: kmovw %k2, %eax			; CHECK-NEXT: kmovw %k2, %eax
	; CHECK-NEXT: vpinsrd $2, %eax, %xmm1, %xmm1			; CHECK-NEXT: vpinsrb $8, %eax, %xmm1, %xmm1
	; CHECK-NEXT: kmovw %k0, %eax			; CHECK-NEXT: kmovw %k1, %eax
	; CHECK-NEXT: vpinsrd $3, %eax, %xmm1, %xmm1			; CHECK-NEXT: vpinsrb $12, %eax, %xmm1, %xmm1
	; CHECK-NEXT: vpslld $31, %xmm1, %xmm1			; CHECK-NEXT: vpslld $31, %xmm1, %xmm1
	; CHECK-NEXT: vpsrad $31, %xmm1, %xmm1			; CHECK-NEXT: vpsrad $31, %xmm1, %xmm1
	; CHECK-NEXT: vpand %xmm0, %xmm1, %xmm0			; CHECK-NEXT: vpand %xmm0, %xmm1, %xmm0
	; CHECK-NEXT: retq			; CHECK-NEXT: retq
	%res = call <4 x i32> @llvm.x86.avx512.mask.vextracti32x4.512(<16 x i32> %a, i32 2, <4 x i32> zeroinitializer, i8 %mask)			%res = call <4 x i32> @llvm.x86.avx512.mask.vextracti32x4.512(<16 x i32> %a, i32 2, <4 x i32> zeroinitializer, i8 %mask)
	ret <4 x i32> %res			ret <4 x i32> %res
	}			}

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test/CodeGen/X86/avx512-intrinsics.ll

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; CHECK-LABEL: test_kxnor:		; CHECK-LABEL: test_kxnor:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %esi, %k0		; CHECK-NEXT: kmovw %esi, %k0
; CHECK-NEXT: kmovw %edi, %k1		; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: movw $8, %ax		; CHECK-NEXT: movw $8, %ax
; CHECK-NEXT: kmovw %eax, %k2		; CHECK-NEXT: kmovw %eax, %k2
; CHECK-NEXT: kxorw %k0, %k1, %k0		; CHECK-NEXT: kxorw %k0, %k1, %k0
; CHECK-NEXT: kxorw %k0, %k2, %k0		; CHECK-NEXT: kxorw %k0, %k2, %k0
		; CHECK-NEXT: kxnorw %k0, %k0, %k1
		; CHECK-NEXT: kxnorw %k1, %k0, %k0
		RKSimonUnsubmitted Not Done Reply Inline Actions Any ideas what is going on here? RKSimon: Any ideas what is going on here?
		guyblankAuthorUnsubmitted Not Done Reply Inline Actions SelectionDAG.cpp::FoldConstantArithmetic should eliminate this. but there is a comment there... Avoid BUILD_VECTOR nodes that perform implicit truncation. FIXME: This is valid and could be handled by truncation. without this patch the build vector was v16i1 = build vector i1, i1, ... and with the patch it is v16i1 = build vector i8, i8, ... so now it is unable to eliminate the xnor. i've tried implementing proper handling for implicit truncation but i'm getting some failure in mips that i still need to investigate. is it ok if I fix it in a separate commit? guyblank: SelectionDAG.cpp::FoldConstantArithmetic should eliminate this. but there is a comment there...
		RKSimonUnsubmitted Not Done Reply Inline Actions SelectionDAG::FoldConstantVectorArithmetic does the explicit truncation/extension - not sure if you can use that. RKSimon: SelectionDAG::FoldConstantVectorArithmetic does the explicit truncation/extension - not sure if…
		guyblankAuthorUnsubmitted Not Done Reply Inline Actions Thanks! guyblank: Thanks!
; CHECK-NEXT: kmovw %k0, %eax		; CHECK-NEXT: kmovw %k0, %eax
; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>		; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%t1 = call i16 @llvm.x86.avx512.kxnor.w(i16 %a0, i16 8)		%t1 = call i16 @llvm.x86.avx512.kxnor.w(i16 %a0, i16 8)
%t2 = call i16 @llvm.x86.avx512.kxnor.w(i16 %t1, i16 %a1)		%t2 = call i16 @llvm.x86.avx512.kxnor.w(i16 %t1, i16 %a1)
ret i16 %t2		ret i16 %t2
}		}

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}		}
declare <16 x float> @llvm.x86.avx512.mask.getexp.ps.512(<16 x float>, <16 x float>, i16, i32) nounwind readnone		declare <16 x float> @llvm.x86.avx512.mask.getexp.ps.512(<16 x float>, <16 x float>, i16, i32) nounwind readnone

declare <4 x float> @llvm.x86.avx512.mask.sqrt.ss(<4 x float>, <4 x float>, <4 x float>, i8, i32) nounwind readnone		declare <4 x float> @llvm.x86.avx512.mask.sqrt.ss(<4 x float>, <4 x float>, <4 x float>, i8, i32) nounwind readnone

define <4 x float> @test_sqrt_ss(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) {		define <4 x float> @test_sqrt_ss(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) {
; CHECK-LABEL: test_sqrt_ss:		; CHECK-LABEL: test_sqrt_ss:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: kmovw %edi, %k1		; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vmovaps %xmm2, %xmm3		; CHECK-NEXT: vmovaps %xmm2, %xmm3
; CHECK-NEXT: vsqrtss %xmm1, %xmm0, %xmm3 {%k1}		; CHECK-NEXT: vsqrtss %xmm1, %xmm0, %xmm3 {%k1}
; CHECK-NEXT: vsqrtss {rd-sae}, %xmm1, %xmm0, %xmm2 {%k1}		; CHECK-NEXT: vsqrtss {rd-sae}, %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vsqrtss {ru-sae}, %xmm1, %xmm0, %xmm4 {%k1} {z}		; CHECK-NEXT: vsqrtss {ru-sae}, %xmm1, %xmm0, %xmm4 {%k1} {z}
; CHECK-NEXT: vsqrtss {rz-sae}, %xmm1, %xmm0, %xmm0		; CHECK-NEXT: vsqrtss {rz-sae}, %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vaddps %xmm2, %xmm3, %xmm1		; CHECK-NEXT: vaddps %xmm2, %xmm3, %xmm1
; CHECK-NEXT: vaddps %xmm0, %xmm4, %xmm0		; CHECK-NEXT: vaddps %xmm0, %xmm4, %xmm0
Show All 10 Lines	; CHECK-NEXT: retq
ret <4 x float> %res		ret <4 x float> %res
}		}

declare <2 x double> @llvm.x86.avx512.mask.sqrt.sd(<2 x double>, <2 x double>, <2 x double>, i8, i32) nounwind readnone		declare <2 x double> @llvm.x86.avx512.mask.sqrt.sd(<2 x double>, <2 x double>, <2 x double>, i8, i32) nounwind readnone

define <2 x double> @test_sqrt_sd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) {		define <2 x double> @test_sqrt_sd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) {
; CHECK-LABEL: test_sqrt_sd:		; CHECK-LABEL: test_sqrt_sd:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: kmovw %edi, %k1		; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vmovapd %xmm2, %xmm3		; CHECK-NEXT: vmovapd %xmm2, %xmm3
; CHECK-NEXT: vsqrtsd %xmm1, %xmm0, %xmm3 {%k1}		; CHECK-NEXT: vsqrtsd %xmm1, %xmm0, %xmm3 {%k1}
; CHECK-NEXT: vsqrtsd {rd-sae}, %xmm1, %xmm0, %xmm2 {%k1}		; CHECK-NEXT: vsqrtsd {rd-sae}, %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vsqrtsd {ru-sae}, %xmm1, %xmm0, %xmm4 {%k1} {z}		; CHECK-NEXT: vsqrtsd {ru-sae}, %xmm1, %xmm0, %xmm4 {%k1} {z}
; CHECK-NEXT: vsqrtsd {rz-sae}, %xmm1, %xmm0, %xmm0		; CHECK-NEXT: vsqrtsd {rz-sae}, %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vaddpd %xmm2, %xmm3, %xmm1		; CHECK-NEXT: vaddpd %xmm2, %xmm3, %xmm1
; CHECK-NEXT: vaddpd %xmm0, %xmm4, %xmm0		; CHECK-NEXT: vaddpd %xmm0, %xmm4, %xmm0
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}		}
declare <16 x float> @llvm.x86.avx512.mask.max.ps.512(<16 x float>, <16 x float>, <16 x float>, i16, i32)		declare <16 x float> @llvm.x86.avx512.mask.max.ps.512(<16 x float>, <16 x float>, <16 x float>, i16, i32)

declare <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>, <4 x float>, <4 x float>, i8, i32) nounwind readnone		declare <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>, <4 x float>, <4 x float>, i8, i32) nounwind readnone

define <4 x float> @test_mask_add_ss_rn(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) {		define <4 x float> @test_mask_add_ss_rn(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) {
; CHECK-LABEL: test_mask_add_ss_rn:		; CHECK-LABEL: test_mask_add_ss_rn:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: kmovw %edi, %k1		; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vaddss {rn-sae}, %xmm1, %xmm0, %xmm2 {%k1}		; CHECK-NEXT: vaddss {rn-sae}, %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vmovaps %xmm2, %xmm0		; CHECK-NEXT: vmovaps %xmm2, %xmm0
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%res = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> %a2, i8 %mask, i32 0)		%res = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> %a2, i8 %mask, i32 0)
ret <4 x float> %res		ret <4 x float> %res
}		}

define <4 x float> @test_mask_add_ss_rd(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) {		define <4 x float> @test_mask_add_ss_rd(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) {
; CHECK-LABEL: test_mask_add_ss_rd:		; CHECK-LABEL: test_mask_add_ss_rd:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: kmovw %edi, %k1		; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vaddss {rd-sae}, %xmm1, %xmm0, %xmm2 {%k1}		; CHECK-NEXT: vaddss {rd-sae}, %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vmovaps %xmm2, %xmm0		; CHECK-NEXT: vmovaps %xmm2, %xmm0
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%res = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> %a2, i8 %mask, i32 1)		%res = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> %a2, i8 %mask, i32 1)
ret <4 x float> %res		ret <4 x float> %res
}		}

define <4 x float> @test_mask_add_ss_ru(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) {		define <4 x float> @test_mask_add_ss_ru(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) {
; CHECK-LABEL: test_mask_add_ss_ru:		; CHECK-LABEL: test_mask_add_ss_ru:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: kmovw %edi, %k1		; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vaddss {ru-sae}, %xmm1, %xmm0, %xmm2 {%k1}		; CHECK-NEXT: vaddss {ru-sae}, %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vmovaps %xmm2, %xmm0		; CHECK-NEXT: vmovaps %xmm2, %xmm0
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%res = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> %a2, i8 %mask, i32 2)		%res = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> %a2, i8 %mask, i32 2)
ret <4 x float> %res		ret <4 x float> %res
}		}

define <4 x float> @test_mask_add_ss_rz(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) {		define <4 x float> @test_mask_add_ss_rz(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) {
; CHECK-LABEL: test_mask_add_ss_rz:		; CHECK-LABEL: test_mask_add_ss_rz:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: kmovw %edi, %k1		; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vaddss {rz-sae}, %xmm1, %xmm0, %xmm2 {%k1}		; CHECK-NEXT: vaddss {rz-sae}, %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vmovaps %xmm2, %xmm0		; CHECK-NEXT: vmovaps %xmm2, %xmm0
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%res = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> %a2, i8 %mask, i32 3)		%res = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> %a2, i8 %mask, i32 3)
ret <4 x float> %res		ret <4 x float> %res
}		}

define <4 x float> @test_mask_add_ss_current(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) {		define <4 x float> @test_mask_add_ss_current(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) {
; CHECK-LABEL: test_mask_add_ss_current:		; CHECK-LABEL: test_mask_add_ss_current:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: kmovw %edi, %k1		; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vaddss %xmm1, %xmm0, %xmm2 {%k1}		; CHECK-NEXT: vaddss %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vmovaps %xmm2, %xmm0		; CHECK-NEXT: vmovaps %xmm2, %xmm0
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%res = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> %a2, i8 %mask, i32 4)		%res = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> %a2, i8 %mask, i32 4)
ret <4 x float> %res		ret <4 x float> %res
}		}

define <4 x float> @test_maskz_add_ss_rn(<4 x float> %a0, <4 x float> %a1, i8 %mask) {		define <4 x float> @test_maskz_add_ss_rn(<4 x float> %a0, <4 x float> %a1, i8 %mask) {
; CHECK-LABEL: test_maskz_add_ss_rn:		; CHECK-LABEL: test_maskz_add_ss_rn:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: kmovw %edi, %k1		; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vaddss {rn-sae}, %xmm1, %xmm0, %xmm0 {%k1} {z}		; CHECK-NEXT: vaddss {rn-sae}, %xmm1, %xmm0, %xmm0 {%k1} {z}
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%res = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> zeroinitializer, i8 %mask, i32 0)		%res = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> zeroinitializer, i8 %mask, i32 0)
ret <4 x float> %res		ret <4 x float> %res
}		}

define <4 x float> @test_add_ss_rn(<4 x float> %a0, <4 x float> %a1) {		define <4 x float> @test_add_ss_rn(<4 x float> %a0, <4 x float> %a1) {
; CHECK-LABEL: test_add_ss_rn:		; CHECK-LABEL: test_add_ss_rn:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: vaddss {rn-sae}, %xmm1, %xmm0, %xmm0		; CHECK-NEXT: vaddss {rn-sae}, %xmm1, %xmm0, %xmm0
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%res = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> zeroinitializer, i8 -1, i32 0)		%res = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> zeroinitializer, i8 -1, i32 0)
ret <4 x float> %res		ret <4 x float> %res
}		}

define <4 x float> @test_mask_add_ss_current_memfold(<4 x float> %a0, float* %a1, <4 x float> %a2, i8 %mask) {		define <4 x float> @test_mask_add_ss_current_memfold(<4 x float> %a0, float* %a1, <4 x float> %a2, i8 %mask) {
; CHECK-LABEL: test_mask_add_ss_current_memfold:		; CHECK-LABEL: test_mask_add_ss_current_memfold:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %esi
; CHECK-NEXT: kmovw %esi, %k1		; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: vaddss (%rdi), %xmm0, %xmm1 {%k1}		; CHECK-NEXT: vaddss (%rdi), %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vmovaps %xmm1, %xmm0		; CHECK-NEXT: vmovaps %xmm1, %xmm0
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%a1.val = load float, float* %a1		%a1.val = load float, float* %a1
%a1v0 = insertelement <4 x float> undef, float %a1.val, i32 0		%a1v0 = insertelement <4 x float> undef, float %a1.val, i32 0
%a1v1 = insertelement <4 x float> %a1v0, float 0.000000e+00, i32 1		%a1v1 = insertelement <4 x float> %a1v0, float 0.000000e+00, i32 1
%a1v2 = insertelement <4 x float> %a1v1, float 0.000000e+00, i32 2		%a1v2 = insertelement <4 x float> %a1v1, float 0.000000e+00, i32 2
%a1v = insertelement <4 x float> %a1v2, float 0.000000e+00, i32 3		%a1v = insertelement <4 x float> %a1v2, float 0.000000e+00, i32 3
%res = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>%a0, <4 x float> %a1v, <4 x float> %a2, i8 %mask, i32 4)		%res = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>%a0, <4 x float> %a1v, <4 x float> %a2, i8 %mask, i32 4)
ret <4 x float> %res		ret <4 x float> %res
}		}

define <4 x float> @test_maskz_add_ss_current_memfold(<4 x float> %a0, float* %a1, i8 %mask) {		define <4 x float> @test_maskz_add_ss_current_memfold(<4 x float> %a0, float* %a1, i8 %mask) {
; CHECK-LABEL: test_maskz_add_ss_current_memfold:		; CHECK-LABEL: test_maskz_add_ss_current_memfold:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %esi
; CHECK-NEXT: kmovw %esi, %k1		; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: vaddss (%rdi), %xmm0, %xmm0 {%k1} {z}		; CHECK-NEXT: vaddss (%rdi), %xmm0, %xmm0 {%k1} {z}
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%a1.val = load float, float* %a1		%a1.val = load float, float* %a1
%a1v0 = insertelement <4 x float> undef, float %a1.val, i32 0		%a1v0 = insertelement <4 x float> undef, float %a1.val, i32 0
%a1v1 = insertelement <4 x float> %a1v0, float 0.000000e+00, i32 1		%a1v1 = insertelement <4 x float> %a1v0, float 0.000000e+00, i32 1
%a1v2 = insertelement <4 x float> %a1v1, float 0.000000e+00, i32 2		%a1v2 = insertelement <4 x float> %a1v1, float 0.000000e+00, i32 2
%a1v = insertelement <4 x float> %a1v2, float 0.000000e+00, i32 3		%a1v = insertelement <4 x float> %a1v2, float 0.000000e+00, i32 3
%res = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>%a0, <4 x float> %a1v, <4 x float> zeroinitializer, i8 %mask, i32 4)		%res = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>%a0, <4 x float> %a1v, <4 x float> zeroinitializer, i8 %mask, i32 4)
ret <4 x float> %res		ret <4 x float> %res
}		}

declare <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double>, <2 x double>, <2 x double>, i8, i32) nounwind readnone		declare <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double>, <2 x double>, <2 x double>, i8, i32) nounwind readnone

define <2 x double> @test_mask_add_sd_rn(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) {		define <2 x double> @test_mask_add_sd_rn(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) {
; CHECK-LABEL: test_mask_add_sd_rn:		; CHECK-LABEL: test_mask_add_sd_rn:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: kmovw %edi, %k1		; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vaddsd {rn-sae}, %xmm1, %xmm0, %xmm2 {%k1}		; CHECK-NEXT: vaddsd {rn-sae}, %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vmovapd %xmm2, %xmm0		; CHECK-NEXT: vmovapd %xmm2, %xmm0
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%res = call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> %a2, i8 %mask, i32 0)		%res = call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> %a2, i8 %mask, i32 0)
ret <2 x double> %res		ret <2 x double> %res
}		}

define <2 x double> @test_mask_add_sd_rd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) {		define <2 x double> @test_mask_add_sd_rd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) {
; CHECK-LABEL: test_mask_add_sd_rd:		; CHECK-LABEL: test_mask_add_sd_rd:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: kmovw %edi, %k1		; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vaddsd {rd-sae}, %xmm1, %xmm0, %xmm2 {%k1}		; CHECK-NEXT: vaddsd {rd-sae}, %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vmovapd %xmm2, %xmm0		; CHECK-NEXT: vmovapd %xmm2, %xmm0
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%res = call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> %a2, i8 %mask, i32 1)		%res = call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> %a2, i8 %mask, i32 1)
ret <2 x double> %res		ret <2 x double> %res
}		}

define <2 x double> @test_mask_add_sd_ru(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) {		define <2 x double> @test_mask_add_sd_ru(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) {
; CHECK-LABEL: test_mask_add_sd_ru:		; CHECK-LABEL: test_mask_add_sd_ru:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: kmovw %edi, %k1		; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vaddsd {ru-sae}, %xmm1, %xmm0, %xmm2 {%k1}		; CHECK-NEXT: vaddsd {ru-sae}, %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vmovapd %xmm2, %xmm0		; CHECK-NEXT: vmovapd %xmm2, %xmm0
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%res = call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> %a2, i8 %mask, i32 2)		%res = call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> %a2, i8 %mask, i32 2)
ret <2 x double> %res		ret <2 x double> %res
}		}

define <2 x double> @test_mask_add_sd_rz(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) {		define <2 x double> @test_mask_add_sd_rz(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) {
; CHECK-LABEL: test_mask_add_sd_rz:		; CHECK-LABEL: test_mask_add_sd_rz:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: kmovw %edi, %k1		; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vaddsd {rz-sae}, %xmm1, %xmm0, %xmm2 {%k1}		; CHECK-NEXT: vaddsd {rz-sae}, %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vmovapd %xmm2, %xmm0		; CHECK-NEXT: vmovapd %xmm2, %xmm0
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%res = call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> %a2, i8 %mask, i32 3)		%res = call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> %a2, i8 %mask, i32 3)
ret <2 x double> %res		ret <2 x double> %res
}		}

define <2 x double> @test_mask_add_sd_current(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) {		define <2 x double> @test_mask_add_sd_current(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) {
; CHECK-LABEL: test_mask_add_sd_current:		; CHECK-LABEL: test_mask_add_sd_current:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: kmovw %edi, %k1		; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vaddsd %xmm1, %xmm0, %xmm2 {%k1}		; CHECK-NEXT: vaddsd %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vmovapd %xmm2, %xmm0		; CHECK-NEXT: vmovapd %xmm2, %xmm0
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%res = call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> %a2, i8 %mask, i32 4)		%res = call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> %a2, i8 %mask, i32 4)
ret <2 x double> %res		ret <2 x double> %res
}		}

define <2 x double> @test_maskz_add_sd_rn(<2 x double> %a0, <2 x double> %a1, i8 %mask) {		define <2 x double> @test_maskz_add_sd_rn(<2 x double> %a0, <2 x double> %a1, i8 %mask) {
; CHECK-LABEL: test_maskz_add_sd_rn:		; CHECK-LABEL: test_maskz_add_sd_rn:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: kmovw %edi, %k1		; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vaddsd {rn-sae}, %xmm1, %xmm0, %xmm0 {%k1} {z}		; CHECK-NEXT: vaddsd {rn-sae}, %xmm1, %xmm0, %xmm0 {%k1} {z}
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%res = call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> zeroinitializer, i8 %mask, i32 0)		%res = call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> zeroinitializer, i8 %mask, i32 0)
ret <2 x double> %res		ret <2 x double> %res
}		}

define <2 x double> @test_add_sd_rn(<2 x double> %a0, <2 x double> %a1) {		define <2 x double> @test_add_sd_rn(<2 x double> %a0, <2 x double> %a1) {
; CHECK-LABEL: test_add_sd_rn:		; CHECK-LABEL: test_add_sd_rn:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: vaddsd {rn-sae}, %xmm1, %xmm0, %xmm0		; CHECK-NEXT: vaddsd {rn-sae}, %xmm1, %xmm0, %xmm0
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%res = call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> zeroinitializer, i8 -1, i32 0)		%res = call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> zeroinitializer, i8 -1, i32 0)
ret <2 x double> %res		ret <2 x double> %res
}		}

define <2 x double> @test_mask_add_sd_current_memfold(<2 x double> %a0, double* %a1, <2 x double> %a2, i8 %mask) {		define <2 x double> @test_mask_add_sd_current_memfold(<2 x double> %a0, double* %a1, <2 x double> %a2, i8 %mask) {
; CHECK-LABEL: test_mask_add_sd_current_memfold:		; CHECK-LABEL: test_mask_add_sd_current_memfold:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %esi
; CHECK-NEXT: kmovw %esi, %k1		; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: vaddsd (%rdi), %xmm0, %xmm1 {%k1}		; CHECK-NEXT: vaddsd (%rdi), %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vmovapd %xmm1, %xmm0		; CHECK-NEXT: vmovapd %xmm1, %xmm0
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%a1.val = load double, double* %a1		%a1.val = load double, double* %a1
%a1v0 = insertelement <2 x double> undef, double %a1.val, i32 0		%a1v0 = insertelement <2 x double> undef, double %a1.val, i32 0
%a1v = insertelement <2 x double> %a1v0, double 0.000000e+00, i32 1		%a1v = insertelement <2 x double> %a1v0, double 0.000000e+00, i32 1
%res = call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double>%a0, <2 x double> %a1v, <2 x double> %a2, i8 %mask, i32 4)		%res = call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double>%a0, <2 x double> %a1v, <2 x double> %a2, i8 %mask, i32 4)
ret <2 x double> %res		ret <2 x double> %res
}		}

define <2 x double> @test_maskz_add_sd_current_memfold(<2 x double> %a0, double* %a1, i8 %mask) {		define <2 x double> @test_maskz_add_sd_current_memfold(<2 x double> %a0, double* %a1, i8 %mask) {
; CHECK-LABEL: test_maskz_add_sd_current_memfold:		; CHECK-LABEL: test_maskz_add_sd_current_memfold:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %esi
; CHECK-NEXT: kmovw %esi, %k1		; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: vaddsd (%rdi), %xmm0, %xmm0 {%k1} {z}		; CHECK-NEXT: vaddsd (%rdi), %xmm0, %xmm0 {%k1} {z}
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%a1.val = load double, double* %a1		%a1.val = load double, double* %a1
%a1v0 = insertelement <2 x double> undef, double %a1.val, i32 0		%a1v0 = insertelement <2 x double> undef, double %a1.val, i32 0
%a1v = insertelement <2 x double> %a1v0, double 0.000000e+00, i32 1		%a1v = insertelement <2 x double> %a1v0, double 0.000000e+00, i32 1
%res = call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double>%a0, <2 x double> %a1v, <2 x double> zeroinitializer, i8 %mask, i32 4)		%res = call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double>%a0, <2 x double> %a1v, <2 x double> zeroinitializer, i8 %mask, i32 4)
ret <2 x double> %res		ret <2 x double> %res
}		}

declare <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>, <4 x float>, <4 x float>, i8, i32) nounwind readnone		declare <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>, <4 x float>, <4 x float>, i8, i32) nounwind readnone

define <4 x float> @test_mask_max_ss_sae(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) {		define <4 x float> @test_mask_max_ss_sae(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) {
; CHECK-LABEL: test_mask_max_ss_sae:		; CHECK-LABEL: test_mask_max_ss_sae:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: kmovw %edi, %k1		; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vmaxss {sae}, %xmm1, %xmm0, %xmm2 {%k1}		; CHECK-NEXT: vmaxss {sae}, %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vmovaps %xmm2, %xmm0		; CHECK-NEXT: vmovaps %xmm2, %xmm0
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%res = call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> %a2, i8 %mask, i32 8)		%res = call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> %a2, i8 %mask, i32 8)
ret <4 x float> %res		ret <4 x float> %res
}		}

define <4 x float> @test_maskz_max_ss_sae(<4 x float> %a0, <4 x float> %a1, i8 %mask) {		define <4 x float> @test_maskz_max_ss_sae(<4 x float> %a0, <4 x float> %a1, i8 %mask) {
; CHECK-LABEL: test_maskz_max_ss_sae:		; CHECK-LABEL: test_maskz_max_ss_sae:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: kmovw %edi, %k1		; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vmaxss {sae}, %xmm1, %xmm0, %xmm0 {%k1} {z}		; CHECK-NEXT: vmaxss {sae}, %xmm1, %xmm0, %xmm0 {%k1} {z}
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%res = call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> zeroinitializer, i8 %mask, i32 8)		%res = call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> zeroinitializer, i8 %mask, i32 8)
ret <4 x float> %res		ret <4 x float> %res
}		}

define <4 x float> @test_max_ss_sae(<4 x float> %a0, <4 x float> %a1) {		define <4 x float> @test_max_ss_sae(<4 x float> %a0, <4 x float> %a1) {
; CHECK-LABEL: test_max_ss_sae:		; CHECK-LABEL: test_max_ss_sae:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: vmaxss {sae}, %xmm1, %xmm0, %xmm0		; CHECK-NEXT: vmaxss {sae}, %xmm1, %xmm0, %xmm0
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%res = call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> zeroinitializer, i8 -1, i32 8)		%res = call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> zeroinitializer, i8 -1, i32 8)
ret <4 x float> %res		ret <4 x float> %res
}		}

define <4 x float> @test_mask_max_ss(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) {		define <4 x float> @test_mask_max_ss(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) {
; CHECK-LABEL: test_mask_max_ss:		; CHECK-LABEL: test_mask_max_ss:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: kmovw %edi, %k1		; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm2 {%k1}		; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vmovaps %xmm2, %xmm0		; CHECK-NEXT: vmovaps %xmm2, %xmm0
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%res = call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> %a2, i8 %mask, i32 4)		%res = call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> %a2, i8 %mask, i32 4)
ret <4 x float> %res		ret <4 x float> %res
}		}

define <4 x float> @test_maskz_max_ss(<4 x float> %a0, <4 x float> %a1, i8 %mask) {		define <4 x float> @test_maskz_max_ss(<4 x float> %a0, <4 x float> %a1, i8 %mask) {
; CHECK-LABEL: test_maskz_max_ss:		; CHECK-LABEL: test_maskz_max_ss:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: kmovw %edi, %k1		; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0 {%k1} {z}		; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0 {%k1} {z}
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%res = call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> zeroinitializer, i8 %mask, i32 4)		%res = call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> zeroinitializer, i8 %mask, i32 4)
ret <4 x float> %res		ret <4 x float> %res
}		}

define <4 x float> @test_max_ss(<4 x float> %a0, <4 x float> %a1) {		define <4 x float> @test_max_ss(<4 x float> %a0, <4 x float> %a1) {
; CHECK-LABEL: test_max_ss:		; CHECK-LABEL: test_max_ss:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0		; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%res = call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> zeroinitializer, i8 -1, i32 4)		%res = call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> zeroinitializer, i8 -1, i32 4)
ret <4 x float> %res		ret <4 x float> %res
}		}

define <4 x float> @test_mask_max_ss_memfold(<4 x float> %a0, float* %a1, <4 x float> %a2, i8 %mask) {		define <4 x float> @test_mask_max_ss_memfold(<4 x float> %a0, float* %a1, <4 x float> %a2, i8 %mask) {
; CHECK-LABEL: test_mask_max_ss_memfold:		; CHECK-LABEL: test_mask_max_ss_memfold:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %esi
; CHECK-NEXT: kmovw %esi, %k1		; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: vmaxss (%rdi), %xmm0, %xmm1 {%k1}		; CHECK-NEXT: vmaxss (%rdi), %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vmovaps %xmm1, %xmm0		; CHECK-NEXT: vmovaps %xmm1, %xmm0
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%a1.val = load float, float* %a1		%a1.val = load float, float* %a1
%a1v0 = insertelement <4 x float> undef, float %a1.val, i32 0		%a1v0 = insertelement <4 x float> undef, float %a1.val, i32 0
%a1v1 = insertelement <4 x float> %a1v0, float 0.000000e+00, i32 1		%a1v1 = insertelement <4 x float> %a1v0, float 0.000000e+00, i32 1
%a1v2 = insertelement <4 x float> %a1v1, float 0.000000e+00, i32 2		%a1v2 = insertelement <4 x float> %a1v1, float 0.000000e+00, i32 2
%a1v = insertelement <4 x float> %a1v2, float 0.000000e+00, i32 3		%a1v = insertelement <4 x float> %a1v2, float 0.000000e+00, i32 3
%res = call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>%a0, <4 x float> %a1v, <4 x float> %a2, i8 %mask, i32 4)		%res = call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>%a0, <4 x float> %a1v, <4 x float> %a2, i8 %mask, i32 4)
ret <4 x float> %res		ret <4 x float> %res
}		}

define <4 x float> @test_maskz_max_ss_memfold(<4 x float> %a0, float* %a1, i8 %mask) {		define <4 x float> @test_maskz_max_ss_memfold(<4 x float> %a0, float* %a1, i8 %mask) {
; CHECK-LABEL: test_maskz_max_ss_memfold:		; CHECK-LABEL: test_maskz_max_ss_memfold:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %esi
; CHECK-NEXT: kmovw %esi, %k1		; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: vmaxss (%rdi), %xmm0, %xmm0 {%k1} {z}		; CHECK-NEXT: vmaxss (%rdi), %xmm0, %xmm0 {%k1} {z}
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%a1.val = load float, float* %a1		%a1.val = load float, float* %a1
%a1v0 = insertelement <4 x float> undef, float %a1.val, i32 0		%a1v0 = insertelement <4 x float> undef, float %a1.val, i32 0
%a1v1 = insertelement <4 x float> %a1v0, float 0.000000e+00, i32 1		%a1v1 = insertelement <4 x float> %a1v0, float 0.000000e+00, i32 1
%a1v2 = insertelement <4 x float> %a1v1, float 0.000000e+00, i32 2		%a1v2 = insertelement <4 x float> %a1v1, float 0.000000e+00, i32 2
%a1v = insertelement <4 x float> %a1v2, float 0.000000e+00, i32 3		%a1v = insertelement <4 x float> %a1v2, float 0.000000e+00, i32 3
%res = call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>%a0, <4 x float> %a1v, <4 x float> zeroinitializer, i8 %mask, i32 4)		%res = call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>%a0, <4 x float> %a1v, <4 x float> zeroinitializer, i8 %mask, i32 4)
ret <4 x float> %res		ret <4 x float> %res
}		}
declare <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double>, <2 x double>, <2 x double>, i8, i32) nounwind readnone		declare <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double>, <2 x double>, <2 x double>, i8, i32) nounwind readnone

define <2 x double> @test_mask_max_sd_sae(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) {		define <2 x double> @test_mask_max_sd_sae(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) {
; CHECK-LABEL: test_mask_max_sd_sae:		; CHECK-LABEL: test_mask_max_sd_sae:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: kmovw %edi, %k1		; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vmaxsd {sae}, %xmm1, %xmm0, %xmm2 {%k1}		; CHECK-NEXT: vmaxsd {sae}, %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vmovapd %xmm2, %xmm0		; CHECK-NEXT: vmovapd %xmm2, %xmm0
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%res = call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> %a2, i8 %mask, i32 8)		%res = call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> %a2, i8 %mask, i32 8)
ret <2 x double> %res		ret <2 x double> %res
}		}

define <2 x double> @test_maskz_max_sd_sae(<2 x double> %a0, <2 x double> %a1, i8 %mask) {		define <2 x double> @test_maskz_max_sd_sae(<2 x double> %a0, <2 x double> %a1, i8 %mask) {
; CHECK-LABEL: test_maskz_max_sd_sae:		; CHECK-LABEL: test_maskz_max_sd_sae:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: kmovw %edi, %k1		; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vmaxsd {sae}, %xmm1, %xmm0, %xmm0 {%k1} {z}		; CHECK-NEXT: vmaxsd {sae}, %xmm1, %xmm0, %xmm0 {%k1} {z}
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%res = call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> zeroinitializer, i8 %mask, i32 8)		%res = call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> zeroinitializer, i8 %mask, i32 8)
ret <2 x double> %res		ret <2 x double> %res
}		}

define <2 x double> @test_max_sd_sae(<2 x double> %a0, <2 x double> %a1) {		define <2 x double> @test_max_sd_sae(<2 x double> %a0, <2 x double> %a1) {
; CHECK-LABEL: test_max_sd_sae:		; CHECK-LABEL: test_max_sd_sae:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: vmaxsd {sae}, %xmm1, %xmm0, %xmm0		; CHECK-NEXT: vmaxsd {sae}, %xmm1, %xmm0, %xmm0
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%res = call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> zeroinitializer, i8 -1, i32 8)		%res = call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> zeroinitializer, i8 -1, i32 8)
ret <2 x double> %res		ret <2 x double> %res
}		}

define <2 x double> @test_mask_max_sd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) {		define <2 x double> @test_mask_max_sd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) {
; CHECK-LABEL: test_mask_max_sd:		; CHECK-LABEL: test_mask_max_sd:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: kmovw %edi, %k1		; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vmaxsd %xmm1, %xmm0, %xmm2 {%k1}		; CHECK-NEXT: vmaxsd %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vmovapd %xmm2, %xmm0		; CHECK-NEXT: vmovapd %xmm2, %xmm0
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%res = call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> %a2, i8 %mask, i32 4)		%res = call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> %a2, i8 %mask, i32 4)
ret <2 x double> %res		ret <2 x double> %res
}		}

define <2 x double> @test_maskz_max_sd(<2 x double> %a0, <2 x double> %a1, i8 %mask) {		define <2 x double> @test_maskz_max_sd(<2 x double> %a0, <2 x double> %a1, i8 %mask) {
; CHECK-LABEL: test_maskz_max_sd:		; CHECK-LABEL: test_maskz_max_sd:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: kmovw %edi, %k1		; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vmaxsd %xmm1, %xmm0, %xmm0 {%k1} {z}		; CHECK-NEXT: vmaxsd %xmm1, %xmm0, %xmm0 {%k1} {z}
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%res = call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> zeroinitializer, i8 %mask, i32 4)		%res = call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> zeroinitializer, i8 %mask, i32 4)
ret <2 x double> %res		ret <2 x double> %res
}		}

define <2 x double> @test_max_sd(<2 x double> %a0, <2 x double> %a1) {		define <2 x double> @test_max_sd(<2 x double> %a0, <2 x double> %a1) {
; CHECK-LABEL: test_max_sd:		; CHECK-LABEL: test_max_sd:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: vmaxsd %xmm1, %xmm0, %xmm0		; CHECK-NEXT: vmaxsd %xmm1, %xmm0, %xmm0
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%res = call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> zeroinitializer, i8 -1, i32 4)		%res = call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> zeroinitializer, i8 -1, i32 4)
ret <2 x double> %res		ret <2 x double> %res
}		}

define <2 x double> @test_mask_max_sd_memfold(<2 x double> %a0, double* %a1, <2 x double> %a2, i8 %mask) {		define <2 x double> @test_mask_max_sd_memfold(<2 x double> %a0, double* %a1, <2 x double> %a2, i8 %mask) {
; CHECK-LABEL: test_mask_max_sd_memfold:		; CHECK-LABEL: test_mask_max_sd_memfold:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %esi
; CHECK-NEXT: kmovw %esi, %k1		; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: vmaxsd (%rdi), %xmm0, %xmm1 {%k1}		; CHECK-NEXT: vmaxsd (%rdi), %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vmovapd %xmm1, %xmm0		; CHECK-NEXT: vmovapd %xmm1, %xmm0
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%a1.val = load double, double* %a1		%a1.val = load double, double* %a1
%a1v0 = insertelement <2 x double> undef, double %a1.val, i32 0		%a1v0 = insertelement <2 x double> undef, double %a1.val, i32 0
%a1v = insertelement <2 x double> %a1v0, double 0.000000e+00, i32 1		%a1v = insertelement <2 x double> %a1v0, double 0.000000e+00, i32 1
%res = call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double>%a0, <2 x double> %a1v, <2 x double> %a2, i8 %mask, i32 4)		%res = call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double>%a0, <2 x double> %a1v, <2 x double> %a2, i8 %mask, i32 4)
ret <2 x double> %res		ret <2 x double> %res
}		}

define <2 x double> @test_maskz_max_sd_memfold(<2 x double> %a0, double* %a1, i8 %mask) {		define <2 x double> @test_maskz_max_sd_memfold(<2 x double> %a0, double* %a1, i8 %mask) {
; CHECK-LABEL: test_maskz_max_sd_memfold:		; CHECK-LABEL: test_maskz_max_sd_memfold:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %esi
; CHECK-NEXT: kmovw %esi, %k1		; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: vmaxsd (%rdi), %xmm0, %xmm0 {%k1} {z}		; CHECK-NEXT: vmaxsd (%rdi), %xmm0, %xmm0 {%k1} {z}
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%a1.val = load double, double* %a1		%a1.val = load double, double* %a1
%a1v0 = insertelement <2 x double> undef, double %a1.val, i32 0		%a1v0 = insertelement <2 x double> undef, double %a1.val, i32 0
%a1v = insertelement <2 x double> %a1v0, double 0.000000e+00, i32 1		%a1v = insertelement <2 x double> %a1v0, double 0.000000e+00, i32 1
%res = call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double>%a0, <2 x double> %a1v, <2 x double> zeroinitializer, i8 %mask, i32 4)		%res = call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double>%a0, <2 x double> %a1v, <2 x double> zeroinitializer, i8 %mask, i32 4)
ret <2 x double> %res		ret <2 x double> %res
▲ Show 20 Lines • Show All 1,017 Lines • ▼ Show 20 Lines	; CHECK-NEXT: retq
ret <16 x i32> %res2		ret <16 x i32> %res2
}		}

declare <4 x float> @llvm.x86.avx512.mask.getexp.ss(<4 x float>, <4 x float>, <4 x float>, i8, i32) nounwind readnone		declare <4 x float> @llvm.x86.avx512.mask.getexp.ss(<4 x float>, <4 x float>, <4 x float>, i8, i32) nounwind readnone

define <4 x float> @test_getexp_ss(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) {		define <4 x float> @test_getexp_ss(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) {
; CHECK-LABEL: test_getexp_ss:		; CHECK-LABEL: test_getexp_ss:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: kmovw %edi, %k1		; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vmovaps %xmm2, %xmm3		; CHECK-NEXT: vmovaps %xmm2, %xmm3
; CHECK-NEXT: vgetexpss %xmm1, %xmm0, %xmm3 {%k1}		; CHECK-NEXT: vgetexpss %xmm1, %xmm0, %xmm3 {%k1}
; CHECK-NEXT: vgetexpss {sae}, %xmm1, %xmm0, %xmm2 {%k1}		; CHECK-NEXT: vgetexpss {sae}, %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vgetexpss {sae}, %xmm1, %xmm0, %xmm4 {%k1} {z}		; CHECK-NEXT: vgetexpss {sae}, %xmm1, %xmm0, %xmm4 {%k1} {z}
; CHECK-NEXT: vgetexpss {sae}, %xmm1, %xmm0, %xmm0		; CHECK-NEXT: vgetexpss {sae}, %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vaddps %xmm2, %xmm3, %xmm1		; CHECK-NEXT: vaddps %xmm2, %xmm3, %xmm1
; CHECK-NEXT: vaddps %xmm0, %xmm4, %xmm0		; CHECK-NEXT: vaddps %xmm0, %xmm4, %xmm0
Show All 10 Lines	; CHECK-NEXT: retq
ret <4 x float> %res		ret <4 x float> %res
}		}

declare <2 x double> @llvm.x86.avx512.mask.getexp.sd(<2 x double>, <2 x double>, <2 x double>, i8, i32) nounwind readnone		declare <2 x double> @llvm.x86.avx512.mask.getexp.sd(<2 x double>, <2 x double>, <2 x double>, i8, i32) nounwind readnone

define <2 x double> @test_getexp_sd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) {		define <2 x double> @test_getexp_sd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) {
; CHECK-LABEL: test_getexp_sd:		; CHECK-LABEL: test_getexp_sd:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: kmovw %edi, %k1		; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vmovapd %xmm2, %xmm3		; CHECK-NEXT: vmovapd %xmm2, %xmm3
; CHECK-NEXT: vgetexpsd %xmm1, %xmm0, %xmm3 {%k1}		; CHECK-NEXT: vgetexpsd %xmm1, %xmm0, %xmm3 {%k1}
; CHECK-NEXT: vgetexpsd %xmm1, %xmm0, %xmm4		; CHECK-NEXT: vgetexpsd %xmm1, %xmm0, %xmm4
; CHECK-NEXT: vgetexpsd {sae}, %xmm1, %xmm0, %xmm2 {%k1}		; CHECK-NEXT: vgetexpsd {sae}, %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vgetexpsd {sae}, %xmm1, %xmm0, %xmm0 {%k1} {z}		; CHECK-NEXT: vgetexpsd {sae}, %xmm1, %xmm0, %xmm0 {%k1} {z}
; CHECK-NEXT: vaddpd %xmm2, %xmm3, %xmm1		; CHECK-NEXT: vaddpd %xmm2, %xmm3, %xmm1
; CHECK-NEXT: vaddpd %xmm4, %xmm0, %xmm0		; CHECK-NEXT: vaddpd %xmm4, %xmm0, %xmm0
Show All 10 Lines	; CHECK-NEXT: retq
ret <2 x double> %res		ret <2 x double> %res
}		}

declare i8 @llvm.x86.avx512.mask.cmp.sd(<2 x double>, <2 x double>, i32, i8, i32)		declare i8 @llvm.x86.avx512.mask.cmp.sd(<2 x double>, <2 x double>, i32, i8, i32)

define i8@test_int_x86_avx512_mask_cmp_sd(<2 x double> %x0, <2 x double> %x1, i8 %x3, i32 %x4) {		define i8@test_int_x86_avx512_mask_cmp_sd(<2 x double> %x0, <2 x double> %x1, i8 %x3, i32 %x4) {
; CHECK-LABEL: test_int_x86_avx512_mask_cmp_sd:		; CHECK-LABEL: test_int_x86_avx512_mask_cmp_sd:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: kmovw %edi, %k1		; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vcmpnltsd {sae}, %xmm1, %xmm0, %k0 {%k1}		; CHECK-NEXT: vcmpnltsd {sae}, %xmm1, %xmm0, %k0 {%k1}
; CHECK-NEXT: kmovw %k0, %eax		; CHECK-NEXT: kmovw %k0, %eax
; CHECK-NEXT: andl $1, %eax
; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
; CHECK-NEXT: retq		; CHECK-NEXT: retq

%res4 = call i8 @llvm.x86.avx512.mask.cmp.sd(<2 x double> %x0, <2 x double> %x1, i32 5, i8 %x3, i32 8)		%res4 = call i8 @llvm.x86.avx512.mask.cmp.sd(<2 x double> %x0, <2 x double> %x1, i32 5, i8 %x3, i32 8)
ret i8 %res4		ret i8 %res4
}		}

define i8@test_int_x86_avx512_mask_cmp_sd_all(<2 x double> %x0, <2 x double> %x1, i8 %x3, i32 %x4) {		define i8@test_int_x86_avx512_mask_cmp_sd_all(<2 x double> %x0, <2 x double> %x1, i8 %x3, i32 %x4) {
; CHECK-LABEL: test_int_x86_avx512_mask_cmp_sd_all:		; CHECK-LABEL: test_int_x86_avx512_mask_cmp_sd_all:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
		; CHECK-NEXT: vcmplesd %xmm1, %xmm0, %k0
		; CHECK-NEXT: kmovw %k0, %esi
; CHECK-NEXT: vcmpunordsd {sae}, %xmm1, %xmm0, %k0		; CHECK-NEXT: vcmpunordsd {sae}, %xmm1, %xmm0, %k0
; CHECK-NEXT: vcmplesd %xmm1, %xmm0, %k1		; CHECK-NEXT: kmovw %k0, %edx
; CHECK-NEXT: korw %k0, %k1, %k0		; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vcmpnltsd {sae}, %xmm1, %xmm0, %k1		; CHECK-NEXT: vcmpneqsd %xmm1, %xmm0, %k0 {%k1}
; CHECK-NEXT: vcmpneqsd %xmm1, %xmm0, %k2		; CHECK-NEXT: kmovw %k0, %ecx
; CHECK-NEXT: korw %k1, %k2, %k1		; CHECK-NEXT: vcmpnltsd {sae}, %xmm1, %xmm0, %k0 {%k1}
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: kmovw %edi, %k2
; CHECK-NEXT: kandw %k2, %k1, %k1
; CHECK-NEXT: korw %k1, %k0, %k0
; CHECK-NEXT: kmovw %k0, %eax		; CHECK-NEXT: kmovw %k0, %eax
; CHECK-NEXT: andl $1, %eax		; CHECK-NEXT: orb %sil, %dl
; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>		; CHECK-NEXT: orb %cl, %al
		; CHECK-NEXT: orb %dl, %al
; CHECK-NEXT: retq		; CHECK-NEXT: retq

%res1 = call i8 @llvm.x86.avx512.mask.cmp.sd(<2 x double> %x0, <2 x double> %x1, i32 2, i8 -1, i32 4)		%res1 = call i8 @llvm.x86.avx512.mask.cmp.sd(<2 x double> %x0, <2 x double> %x1, i32 2, i8 -1, i32 4)
%res2 = call i8 @llvm.x86.avx512.mask.cmp.sd(<2 x double> %x0, <2 x double> %x1, i32 3, i8 -1, i32 8)		%res2 = call i8 @llvm.x86.avx512.mask.cmp.sd(<2 x double> %x0, <2 x double> %x1, i32 3, i8 -1, i32 8)
%res3 = call i8 @llvm.x86.avx512.mask.cmp.sd(<2 x double> %x0, <2 x double> %x1, i32 4, i8 %x3, i32 4)		%res3 = call i8 @llvm.x86.avx512.mask.cmp.sd(<2 x double> %x0, <2 x double> %x1, i32 4, i8 %x3, i32 4)
%res4 = call i8 @llvm.x86.avx512.mask.cmp.sd(<2 x double> %x0, <2 x double> %x1, i32 5, i8 %x3, i32 8)		%res4 = call i8 @llvm.x86.avx512.mask.cmp.sd(<2 x double> %x0, <2 x double> %x1, i32 5, i8 %x3, i32 8)

%res11 = or i8 %res1, %res2		%res11 = or i8 %res1, %res2
%res12 = or i8 %res3, %res4		%res12 = or i8 %res3, %res4
%res13 = or i8 %res11, %res12		%res13 = or i8 %res11, %res12
ret i8 %res13		ret i8 %res13
}		}

declare i8 @llvm.x86.avx512.mask.cmp.ss(<4 x float>, <4 x float>, i32, i8, i32)		declare i8 @llvm.x86.avx512.mask.cmp.ss(<4 x float>, <4 x float>, i32, i8, i32)

define i8@test_int_x86_avx512_mask_cmp_ss(<4 x float> %x0, <4 x float> %x1, i8 %x3, i32 %x4) {		define i8@test_int_x86_avx512_mask_cmp_ss(<4 x float> %x0, <4 x float> %x1, i8 %x3, i32 %x4) {
; CHECK-LABEL: test_int_x86_avx512_mask_cmp_ss:		; CHECK-LABEL: test_int_x86_avx512_mask_cmp_ss:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: kmovw %edi, %k1		; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vcmpunordss %xmm1, %xmm0, %k0 {%k1}		; CHECK-NEXT: vcmpunordss %xmm1, %xmm0, %k0 {%k1}
; CHECK-NEXT: kmovw %k0, %eax		; CHECK-NEXT: kmovw %k0, %eax
; CHECK-NEXT: andl $1, %eax
; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
; CHECK-NEXT: retq		; CHECK-NEXT: retq

%res2 = call i8 @llvm.x86.avx512.mask.cmp.ss(<4 x float> %x0, <4 x float> %x1, i32 3, i8 %x3, i32 4)		%res2 = call i8 @llvm.x86.avx512.mask.cmp.ss(<4 x float> %x0, <4 x float> %x1, i32 3, i8 %x3, i32 4)
ret i8 %res2		ret i8 %res2
}		}


define i8@test_int_x86_avx512_mask_cmp_ss_all(<4 x float> %x0, <4 x float> %x1, i8 %x3, i32 %x4) {		define i8@test_int_x86_avx512_mask_cmp_ss_all(<4 x float> %x0, <4 x float> %x1, i8 %x3, i32 %x4) {
; CHECK-LABEL: test_int_x86_avx512_mask_cmp_ss_all:		; CHECK-LABEL: test_int_x86_avx512_mask_cmp_ss_all:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: vcmpless %xmm1, %xmm0, %k1		; CHECK-NEXT: vcmpless %xmm1, %xmm0, %k0
; CHECK-NEXT: vcmpunordss {sae}, %xmm1, %xmm0, %k0 {%k1}		; CHECK-NEXT: kmovw %k0, %esi
; CHECK-NEXT: andl $1, %edi		; CHECK-NEXT: vcmpunordss {sae}, %xmm1, %xmm0, %k0
; CHECK-NEXT: kmovw %edi, %k1		; CHECK-NEXT: kmovw %k0, %edx
; CHECK-NEXT: vcmpneqss %xmm1, %xmm0, %k2 {%k1}		; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %k2, %ecx		; CHECK-NEXT: vcmpneqss %xmm1, %xmm0, %k0 {%k1}
; CHECK-NEXT: vcmpnltss {sae}, %xmm1, %xmm0, %k1 {%k1}		; CHECK-NEXT: kmovw %k0, %ecx
; CHECK-NEXT: kmovw %k1, %edx		; CHECK-NEXT: vcmpnltss {sae}, %xmm1, %xmm0, %k0 {%k1}
; CHECK-NEXT: andl $1, %edx
; CHECK-NEXT: kmovw %k0, %eax		; CHECK-NEXT: kmovw %k0, %eax
		; CHECK-NEXT: andb %sil, %dl
; CHECK-NEXT: andb %cl, %al		; CHECK-NEXT: andb %cl, %al
; CHECK-NEXT: andb %dl, %al		; CHECK-NEXT: andb %dl, %al
; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%res1 = call i8 @llvm.x86.avx512.mask.cmp.ss(<4 x float> %x0, <4 x float> %x1, i32 2, i8 -1, i32 4)		%res1 = call i8 @llvm.x86.avx512.mask.cmp.ss(<4 x float> %x0, <4 x float> %x1, i32 2, i8 -1, i32 4)
%res2 = call i8 @llvm.x86.avx512.mask.cmp.ss(<4 x float> %x0, <4 x float> %x1, i32 3, i8 -1, i32 8)		%res2 = call i8 @llvm.x86.avx512.mask.cmp.ss(<4 x float> %x0, <4 x float> %x1, i32 3, i8 -1, i32 8)
%res3 = call i8 @llvm.x86.avx512.mask.cmp.ss(<4 x float> %x0, <4 x float> %x1, i32 4, i8 %x3, i32 4)		%res3 = call i8 @llvm.x86.avx512.mask.cmp.ss(<4 x float> %x0, <4 x float> %x1, i32 4, i8 %x3, i32 4)
%res4 = call i8 @llvm.x86.avx512.mask.cmp.ss(<4 x float> %x0, <4 x float> %x1, i32 5, i8 %x3, i32 8)		%res4 = call i8 @llvm.x86.avx512.mask.cmp.ss(<4 x float> %x0, <4 x float> %x1, i32 5, i8 %x3, i32 8)

%res11 = and i8 %res1, %res2		%res11 = and i8 %res1, %res2
%res12 = and i8 %res3, %res4		%res12 = and i8 %res3, %res4
▲ Show 20 Lines • Show All 102 Lines • ▼ Show 20 Lines	; CHECK-NEXT: retq
ret <16 x float> %res2		ret <16 x float> %res2
}		}

declare <2 x double> @llvm.x86.avx512.mask.getmant.sd(<2 x double>, <2 x double>, i32, <2 x double>, i8, i32)		declare <2 x double> @llvm.x86.avx512.mask.getmant.sd(<2 x double>, <2 x double>, i32, <2 x double>, i8, i32)

define <2 x double>@test_int_x86_avx512_mask_getmant_sd(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) {		define <2 x double>@test_int_x86_avx512_mask_getmant_sd(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_getmant_sd:		; CHECK-LABEL: test_int_x86_avx512_mask_getmant_sd:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: kmovw %edi, %k1		; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vmovapd %xmm2, %xmm3		; CHECK-NEXT: vmovapd %xmm2, %xmm3
; CHECK-NEXT: vgetmantsd $11, %xmm1, %xmm0, %xmm3 {%k1}		; CHECK-NEXT: vgetmantsd $11, %xmm1, %xmm0, %xmm3 {%k1}
; CHECK-NEXT: vgetmantsd $11, %xmm1, %xmm0, %xmm4 {%k1} {z}		; CHECK-NEXT: vgetmantsd $11, %xmm1, %xmm0, %xmm4 {%k1} {z}
; CHECK-NEXT: vgetmantsd $11, %xmm1, %xmm0, %xmm5		; CHECK-NEXT: vgetmantsd $11, %xmm1, %xmm0, %xmm5
; CHECK-NEXT: vgetmantsd $11, {sae}, %xmm1, %xmm0, %xmm2 {%k1}		; CHECK-NEXT: vgetmantsd $11, {sae}, %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vaddpd %xmm4, %xmm3, %xmm0		; CHECK-NEXT: vaddpd %xmm4, %xmm3, %xmm0
; CHECK-NEXT: vaddpd %xmm5, %xmm2, %xmm1		; CHECK-NEXT: vaddpd %xmm5, %xmm2, %xmm1
Show All 9 Lines	; CHECK-NEXT: retq
ret <2 x double> %res13		ret <2 x double> %res13
}		}

declare <4 x float> @llvm.x86.avx512.mask.getmant.ss(<4 x float>, <4 x float>, i32, <4 x float>, i8, i32)		declare <4 x float> @llvm.x86.avx512.mask.getmant.ss(<4 x float>, <4 x float>, i32, <4 x float>, i8, i32)

define <4 x float>@test_int_x86_avx512_mask_getmant_ss(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) {		define <4 x float>@test_int_x86_avx512_mask_getmant_ss(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_getmant_ss:		; CHECK-LABEL: test_int_x86_avx512_mask_getmant_ss:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: kmovw %edi, %k1		; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vgetmantss $11, %xmm1, %xmm0, %xmm2 {%k1}		; CHECK-NEXT: vgetmantss $11, %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vgetmantss $11, %xmm1, %xmm0, %xmm3 {%k1} {z}		; CHECK-NEXT: vgetmantss $11, %xmm1, %xmm0, %xmm3 {%k1} {z}
; CHECK-NEXT: vgetmantss $11, %xmm1, %xmm0, %xmm4		; CHECK-NEXT: vgetmantss $11, %xmm1, %xmm0, %xmm4
; CHECK-NEXT: vgetmantss $11, {sae}, %xmm1, %xmm0, %xmm0		; CHECK-NEXT: vgetmantss $11, {sae}, %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vaddps %xmm3, %xmm2, %xmm1		; CHECK-NEXT: vaddps %xmm3, %xmm2, %xmm1
; CHECK-NEXT: vaddps %xmm4, %xmm0, %xmm0		; CHECK-NEXT: vaddps %xmm4, %xmm0, %xmm0
; CHECK-NEXT: vaddps %xmm0, %xmm1, %xmm0		; CHECK-NEXT: vaddps %xmm0, %xmm1, %xmm0
▲ Show 20 Lines • Show All 115 Lines • ▼ Show 20 Lines	; CHECK-NEXT: retq
ret <16 x float> %res2		ret <16 x float> %res2
}		}

declare <2 x double> @llvm.x86.avx512.mask.cvtss2sd.round(<2 x double>, <4 x float>, <2 x double>, i8, i32)		declare <2 x double> @llvm.x86.avx512.mask.cvtss2sd.round(<2 x double>, <4 x float>, <2 x double>, i8, i32)

define <2 x double>@test_int_x86_avx512_mask_cvt_ss2sd_round(<2 x double> %x0,<4 x float> %x1, <2 x double> %x2, i8 %x3) {		define <2 x double>@test_int_x86_avx512_mask_cvt_ss2sd_round(<2 x double> %x0,<4 x float> %x1, <2 x double> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_ss2sd_round:		; CHECK-LABEL: test_int_x86_avx512_mask_cvt_ss2sd_round:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: kmovw %edi, %k1		; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vcvtss2sd %xmm1, %xmm0, %xmm2 {%k1}		; CHECK-NEXT: vcvtss2sd %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vcvtss2sd {sae}, %xmm1, %xmm0, %xmm0		; CHECK-NEXT: vcvtss2sd {sae}, %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vaddpd %xmm0, %xmm2, %xmm0		; CHECK-NEXT: vaddpd %xmm0, %xmm2, %xmm0
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%res = call <2 x double> @llvm.x86.avx512.mask.cvtss2sd.round(<2 x double> %x0, <4 x float> %x1, <2 x double> %x2, i8 %x3, i32 4)		%res = call <2 x double> @llvm.x86.avx512.mask.cvtss2sd.round(<2 x double> %x0, <4 x float> %x1, <2 x double> %x2, i8 %x3, i32 4)
%res1 = call <2 x double> @llvm.x86.avx512.mask.cvtss2sd.round(<2 x double> %x0, <4 x float> %x1, <2 x double> %x2, i8 -1, i32 8)		%res1 = call <2 x double> @llvm.x86.avx512.mask.cvtss2sd.round(<2 x double> %x0, <4 x float> %x1, <2 x double> %x2, i8 -1, i32 8)
%res2 = fadd <2 x double> %res, %res1		%res2 = fadd <2 x double> %res, %res1
ret <2 x double> %res2		ret <2 x double> %res2
}		}

declare <4 x float> @llvm.x86.avx512.mask.cvtsd2ss.round(<4 x float>, <2 x double>, <4 x float>, i8, i32)		declare <4 x float> @llvm.x86.avx512.mask.cvtsd2ss.round(<4 x float>, <2 x double>, <4 x float>, i8, i32)

define <4 x float>@test_int_x86_avx512_mask_cvt_sd2ss_round(<4 x float> %x0,<2 x double> %x1, <4 x float> %x2, i8 %x3) {		define <4 x float>@test_int_x86_avx512_mask_cvt_sd2ss_round(<4 x float> %x0,<2 x double> %x1, <4 x float> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_sd2ss_round:		; CHECK-LABEL: test_int_x86_avx512_mask_cvt_sd2ss_round:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: kmovw %edi, %k1		; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vcvtsd2ss {rz-sae}, %xmm1, %xmm0, %xmm2 {%k1}		; CHECK-NEXT: vcvtsd2ss {rz-sae}, %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vcvtsd2ss {rn-sae}, %xmm1, %xmm0, %xmm0		; CHECK-NEXT: vcvtsd2ss {rn-sae}, %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vaddps %xmm0, %xmm2, %xmm0		; CHECK-NEXT: vaddps %xmm0, %xmm2, %xmm0
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%res = call <4 x float> @llvm.x86.avx512.mask.cvtsd2ss.round(<4 x float> %x0, <2 x double> %x1, <4 x float> %x2, i8 %x3, i32 3)		%res = call <4 x float> @llvm.x86.avx512.mask.cvtsd2ss.round(<4 x float> %x0, <2 x double> %x1, <4 x float> %x2, i8 %x3, i32 3)
%res1 = call <4 x float> @llvm.x86.avx512.mask.cvtsd2ss.round(<4 x float> %x0, <2 x double> %x1, <4 x float> %x2, i8 -1, i32 8)		%res1 = call <4 x float> @llvm.x86.avx512.mask.cvtsd2ss.round(<4 x float> %x0, <2 x double> %x1, <4 x float> %x2, i8 -1, i32 8)
%res2 = fadd <4 x float> %res, %res1		%res2 = fadd <4 x float> %res, %res1
▲ Show 20 Lines • Show All 506 Lines • ▼ Show 20 Lines	; CHECK-NEXT: retq
ret <8 x double> %res4		ret <8 x double> %res4
}		}

declare <4 x float> @llvm.x86.avx512.mask.fixupimm.ss(<4 x float>, <4 x float>, <4 x i32>, i32, i8, i32)		declare <4 x float> @llvm.x86.avx512.mask.fixupimm.ss(<4 x float>, <4 x float>, <4 x i32>, i32, i8, i32)

define <4 x float>@test_int_x86_avx512_mask_fixupimm_ss(<4 x float> %x0, <4 x float> %x1, <4 x i32> %x2, i8 %x4) {		define <4 x float>@test_int_x86_avx512_mask_fixupimm_ss(<4 x float> %x0, <4 x float> %x1, <4 x i32> %x2, i8 %x4) {
; CHECK-LABEL: test_int_x86_avx512_mask_fixupimm_ss:		; CHECK-LABEL: test_int_x86_avx512_mask_fixupimm_ss:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: kmovw %edi, %k1		; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vmovaps %xmm0, %xmm3		; CHECK-NEXT: vmovaps %xmm0, %xmm3
; CHECK-NEXT: vfixupimmss $5, %xmm2, %xmm1, %xmm3 {%k1}		; CHECK-NEXT: vfixupimmss $5, %xmm2, %xmm1, %xmm3 {%k1}
; CHECK-NEXT: vxorps %xmm4, %xmm4, %xmm4		; CHECK-NEXT: vxorps %xmm4, %xmm4, %xmm4
; CHECK-NEXT: vmovaps %xmm0, %xmm5		; CHECK-NEXT: vmovaps %xmm0, %xmm5
; CHECK-NEXT: vfixupimmss $5, %xmm4, %xmm1, %xmm5 {%k1}		; CHECK-NEXT: vfixupimmss $5, %xmm4, %xmm1, %xmm5 {%k1}
; CHECK-NEXT: vfixupimmss $5, {sae}, %xmm2, %xmm1, %xmm0		; CHECK-NEXT: vfixupimmss $5, {sae}, %xmm2, %xmm1, %xmm0
; CHECK-NEXT: vaddps %xmm5, %xmm3, %xmm1		; CHECK-NEXT: vaddps %xmm5, %xmm3, %xmm1
; CHECK-NEXT: vaddps %xmm0, %xmm1, %xmm0		; CHECK-NEXT: vaddps %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%res = call <4 x float> @llvm.x86.avx512.mask.fixupimm.ss(<4 x float> %x0, <4 x float> %x1, <4 x i32> %x2, i32 5, i8 %x4, i32 4)		%res = call <4 x float> @llvm.x86.avx512.mask.fixupimm.ss(<4 x float> %x0, <4 x float> %x1, <4 x i32> %x2, i32 5, i8 %x4, i32 4)
%res1 = call <4 x float> @llvm.x86.avx512.mask.fixupimm.ss(<4 x float> %x0, <4 x float> %x1, <4 x i32> zeroinitializer, i32 5, i8 %x4, i32 4)		%res1 = call <4 x float> @llvm.x86.avx512.mask.fixupimm.ss(<4 x float> %x0, <4 x float> %x1, <4 x i32> zeroinitializer, i32 5, i8 %x4, i32 4)
%res2 = call <4 x float> @llvm.x86.avx512.mask.fixupimm.ss(<4 x float> %x0, <4 x float> %x1, <4 x i32> %x2, i32 5, i8 -1, i32 8)		%res2 = call <4 x float> @llvm.x86.avx512.mask.fixupimm.ss(<4 x float> %x0, <4 x float> %x1, <4 x i32> %x2, i32 5, i8 -1, i32 8)
%res3 = fadd <4 x float> %res, %res1		%res3 = fadd <4 x float> %res, %res1
%res4 = fadd <4 x float> %res3, %res2		%res4 = fadd <4 x float> %res3, %res2
ret <4 x float> %res4		ret <4 x float> %res4
}		}

declare <4 x float> @llvm.x86.avx512.maskz.fixupimm.ss(<4 x float>, <4 x float>, <4 x i32>, i32, i8, i32)		declare <4 x float> @llvm.x86.avx512.maskz.fixupimm.ss(<4 x float>, <4 x float>, <4 x i32>, i32, i8, i32)

define <4 x float>@test_int_x86_avx512_maskz_fixupimm_ss(<4 x float> %x0, <4 x float> %x1, <4 x i32> %x2, i8 %x4) {		define <4 x float>@test_int_x86_avx512_maskz_fixupimm_ss(<4 x float> %x0, <4 x float> %x1, <4 x i32> %x2, i8 %x4) {
; CHECK-LABEL: test_int_x86_avx512_maskz_fixupimm_ss:		; CHECK-LABEL: test_int_x86_avx512_maskz_fixupimm_ss:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: kmovw %edi, %k1		; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vmovaps %xmm0, %xmm3		; CHECK-NEXT: vmovaps %xmm0, %xmm3
; CHECK-NEXT: vfixupimmss $5, %xmm2, %xmm1, %xmm3 {%k1} {z}		; CHECK-NEXT: vfixupimmss $5, %xmm2, %xmm1, %xmm3 {%k1} {z}
; CHECK-NEXT: vmovaps %xmm0, %xmm4		; CHECK-NEXT: vmovaps %xmm0, %xmm4
; CHECK-NEXT: vfixupimmss $5, %xmm2, %xmm1, %xmm4		; CHECK-NEXT: vfixupimmss $5, %xmm2, %xmm1, %xmm4
; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2		; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
; CHECK-NEXT: vfixupimmss $5, {sae}, %xmm2, %xmm1, %xmm0 {%k1} {z}		; CHECK-NEXT: vfixupimmss $5, {sae}, %xmm2, %xmm1, %xmm0 {%k1} {z}
; CHECK-NEXT: vaddps %xmm0, %xmm3, %xmm0		; CHECK-NEXT: vaddps %xmm0, %xmm3, %xmm0
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines	; CHECK-NEXT: retq
ret <16 x float> %res4		ret <16 x float> %res4
}		}

declare <2 x double> @llvm.x86.avx512.mask.fixupimm.sd(<2 x double>, <2 x double>, <2 x i64>, i32, i8, i32)		declare <2 x double> @llvm.x86.avx512.mask.fixupimm.sd(<2 x double>, <2 x double>, <2 x i64>, i32, i8, i32)

define <2 x double>@test_int_x86_avx512_mask_fixupimm_sd(<2 x double> %x0, <2 x double> %x1, <2 x i64> %x2, i8 %x4) {		define <2 x double>@test_int_x86_avx512_mask_fixupimm_sd(<2 x double> %x0, <2 x double> %x1, <2 x i64> %x2, i8 %x4) {
; CHECK-LABEL: test_int_x86_avx512_mask_fixupimm_sd:		; CHECK-LABEL: test_int_x86_avx512_mask_fixupimm_sd:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: kmovw %edi, %k1		; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vmovapd %xmm0, %xmm3		; CHECK-NEXT: vmovapd %xmm0, %xmm3
; CHECK-NEXT: vfixupimmsd $5, %xmm2, %xmm1, %xmm3 {%k1}		; CHECK-NEXT: vfixupimmsd $5, %xmm2, %xmm1, %xmm3 {%k1}
; CHECK-NEXT: vmovapd %xmm0, %xmm4		; CHECK-NEXT: vmovapd %xmm0, %xmm4
; CHECK-NEXT: vfixupimmsd $5, %xmm2, %xmm1, %xmm4		; CHECK-NEXT: vfixupimmsd $5, %xmm2, %xmm1, %xmm4
; CHECK-NEXT: vxorpd %xmm2, %xmm2, %xmm2		; CHECK-NEXT: vxorpd %xmm2, %xmm2, %xmm2
; CHECK-NEXT: vfixupimmsd $5, {sae}, %xmm2, %xmm1, %xmm0 {%k1}		; CHECK-NEXT: vfixupimmsd $5, {sae}, %xmm2, %xmm1, %xmm0 {%k1}
; CHECK-NEXT: vaddpd %xmm0, %xmm3, %xmm0		; CHECK-NEXT: vaddpd %xmm0, %xmm3, %xmm0
; CHECK-NEXT: vaddpd %xmm4, %xmm0, %xmm0		; CHECK-NEXT: vaddpd %xmm4, %xmm0, %xmm0
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%res = call <2 x double> @llvm.x86.avx512.mask.fixupimm.sd(<2 x double> %x0, <2 x double> %x1, <2 x i64> %x2, i32 5, i8 %x4, i32 4)		%res = call <2 x double> @llvm.x86.avx512.mask.fixupimm.sd(<2 x double> %x0, <2 x double> %x1, <2 x i64> %x2, i32 5, i8 %x4, i32 4)
%res1 = call <2 x double> @llvm.x86.avx512.mask.fixupimm.sd(<2 x double> %x0, <2 x double> %x1, <2 x i64> zeroinitializer, i32 5, i8 %x4, i32 8)		%res1 = call <2 x double> @llvm.x86.avx512.mask.fixupimm.sd(<2 x double> %x0, <2 x double> %x1, <2 x i64> zeroinitializer, i32 5, i8 %x4, i32 8)
%res2 = call <2 x double> @llvm.x86.avx512.mask.fixupimm.sd(<2 x double> %x0, <2 x double> %x1, <2 x i64> %x2, i32 5, i8 -1, i32 4)		%res2 = call <2 x double> @llvm.x86.avx512.mask.fixupimm.sd(<2 x double> %x0, <2 x double> %x1, <2 x i64> %x2, i32 5, i8 -1, i32 4)
%res3 = fadd <2 x double> %res, %res1		%res3 = fadd <2 x double> %res, %res1
%res4 = fadd <2 x double> %res3, %res2		%res4 = fadd <2 x double> %res3, %res2
ret <2 x double> %res4		ret <2 x double> %res4
}		}

declare <2 x double> @llvm.x86.avx512.maskz.fixupimm.sd(<2 x double>, <2 x double>, <2 x i64>, i32, i8, i32)		declare <2 x double> @llvm.x86.avx512.maskz.fixupimm.sd(<2 x double>, <2 x double>, <2 x i64>, i32, i8, i32)

define <2 x double>@test_int_x86_avx512_maskz_fixupimm_sd(<2 x double> %x0, <2 x double> %x1, <2 x i64> %x2, i8 %x4) {		define <2 x double>@test_int_x86_avx512_maskz_fixupimm_sd(<2 x double> %x0, <2 x double> %x1, <2 x i64> %x2, i8 %x4) {
; CHECK-LABEL: test_int_x86_avx512_maskz_fixupimm_sd:		; CHECK-LABEL: test_int_x86_avx512_maskz_fixupimm_sd:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: kmovw %edi, %k1		; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vmovapd %xmm0, %xmm3		; CHECK-NEXT: vmovapd %xmm0, %xmm3
; CHECK-NEXT: vfixupimmsd $5, %xmm2, %xmm1, %xmm3 {%k1} {z}		; CHECK-NEXT: vfixupimmsd $5, %xmm2, %xmm1, %xmm3 {%k1} {z}
; CHECK-NEXT: vxorpd %xmm4, %xmm4, %xmm4		; CHECK-NEXT: vxorpd %xmm4, %xmm4, %xmm4
; CHECK-NEXT: vmovapd %xmm0, %xmm5		; CHECK-NEXT: vmovapd %xmm0, %xmm5
; CHECK-NEXT: vfixupimmsd $5, {sae}, %xmm4, %xmm1, %xmm5 {%k1} {z}		; CHECK-NEXT: vfixupimmsd $5, {sae}, %xmm4, %xmm1, %xmm5 {%k1} {z}
; CHECK-NEXT: vfixupimmsd $5, {sae}, %xmm2, %xmm1, %xmm0 {%k1} {z}		; CHECK-NEXT: vfixupimmsd $5, {sae}, %xmm2, %xmm1, %xmm0 {%k1} {z}
; CHECK-NEXT: vaddpd %xmm5, %xmm3, %xmm1		; CHECK-NEXT: vaddpd %xmm5, %xmm3, %xmm1
▲ Show 20 Lines • Show All 84 Lines • ▼ Show 20 Lines
}		}
declare <8 x i64> @llvm.x86.avx512.mask.pbroadcast.q.gpr.512(i64, <8 x i64>, i8)		declare <8 x i64> @llvm.x86.avx512.mask.pbroadcast.q.gpr.512(i64, <8 x i64>, i8)

declare <2 x double> @llvm.x86.avx512.mask.vfmadd.sd(<2 x double>, <2 x double>, <2 x double>, i8, i32)		declare <2 x double> @llvm.x86.avx512.mask.vfmadd.sd(<2 x double>, <2 x double>, <2 x double>, i8, i32)

define <2 x double>@test_int_x86_avx512_mask_vfmadd_sd(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3,i32 %x4 ){		define <2 x double>@test_int_x86_avx512_mask_vfmadd_sd(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3,i32 %x4 ){
; CHECK-LABEL: test_int_x86_avx512_mask_vfmadd_sd:		; CHECK-LABEL: test_int_x86_avx512_mask_vfmadd_sd:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: kmovw %edi, %k1		; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vmovapd %xmm0, %xmm3		; CHECK-NEXT: vmovapd %xmm0, %xmm3
; CHECK-NEXT: vfmadd213sd %xmm2, %xmm1, %xmm3 {%k1}		; CHECK-NEXT: vfmadd213sd %xmm2, %xmm1, %xmm3 {%k1}
; CHECK-NEXT: vmovapd %xmm0, %xmm4		; CHECK-NEXT: vmovapd %xmm0, %xmm4
; CHECK-NEXT: vfmadd213sd %xmm2, %xmm1, %xmm4		; CHECK-NEXT: vfmadd213sd %xmm2, %xmm1, %xmm4
; CHECK-NEXT: vmovapd %xmm0, %xmm5		; CHECK-NEXT: vmovapd %xmm0, %xmm5
; CHECK-NEXT: vfmadd213sd {rz-sae}, %xmm2, %xmm1, %xmm5 {%k1}		; CHECK-NEXT: vfmadd213sd {rz-sae}, %xmm2, %xmm1, %xmm5 {%k1}
; CHECK-NEXT: vfmadd213sd {rz-sae}, %xmm2, %xmm1, %xmm0		; CHECK-NEXT: vfmadd213sd {rz-sae}, %xmm2, %xmm1, %xmm0
Show All 11 Lines	; CHECK-NEXT: retq
ret <2 x double> %res6		ret <2 x double> %res6
}		}

declare <4 x float> @llvm.x86.avx512.mask.vfmadd.ss(<4 x float>, <4 x float>, <4 x float>, i8, i32)		declare <4 x float> @llvm.x86.avx512.mask.vfmadd.ss(<4 x float>, <4 x float>, <4 x float>, i8, i32)

define <4 x float>@test_int_x86_avx512_mask_vfmadd_ss(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3,i32 %x4 ){		define <4 x float>@test_int_x86_avx512_mask_vfmadd_ss(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3,i32 %x4 ){
; CHECK-LABEL: test_int_x86_avx512_mask_vfmadd_ss:		; CHECK-LABEL: test_int_x86_avx512_mask_vfmadd_ss:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: kmovw %edi, %k1		; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vmovaps %xmm0, %xmm3		; CHECK-NEXT: vmovaps %xmm0, %xmm3
; CHECK-NEXT: vfmadd213ss %xmm2, %xmm1, %xmm3 {%k1}		; CHECK-NEXT: vfmadd213ss %xmm2, %xmm1, %xmm3 {%k1}
; CHECK-NEXT: vmovaps %xmm0, %xmm4		; CHECK-NEXT: vmovaps %xmm0, %xmm4
; CHECK-NEXT: vfmadd213ss %xmm2, %xmm1, %xmm4		; CHECK-NEXT: vfmadd213ss %xmm2, %xmm1, %xmm4
; CHECK-NEXT: vmovaps %xmm0, %xmm5		; CHECK-NEXT: vmovaps %xmm0, %xmm5
; CHECK-NEXT: vfmadd213ss {rz-sae}, %xmm2, %xmm1, %xmm5 {%k1}		; CHECK-NEXT: vfmadd213ss {rz-sae}, %xmm2, %xmm1, %xmm5 {%k1}
; CHECK-NEXT: vfmadd213ss {rz-sae}, %xmm2, %xmm1, %xmm0		; CHECK-NEXT: vfmadd213ss {rz-sae}, %xmm2, %xmm1, %xmm0
Show All 11 Lines	; CHECK-NEXT: retq
ret <4 x float> %res6		ret <4 x float> %res6
}		}

declare <2 x double> @llvm.x86.avx512.maskz.vfmadd.sd(<2 x double>, <2 x double>, <2 x double>, i8, i32)		declare <2 x double> @llvm.x86.avx512.maskz.vfmadd.sd(<2 x double>, <2 x double>, <2 x double>, i8, i32)

define <2 x double>@test_int_x86_avx512_maskz_vfmadd_sd(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3,i32 %x4 ){		define <2 x double>@test_int_x86_avx512_maskz_vfmadd_sd(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3,i32 %x4 ){
; CHECK-LABEL: test_int_x86_avx512_maskz_vfmadd_sd:		; CHECK-LABEL: test_int_x86_avx512_maskz_vfmadd_sd:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: kmovw %edi, %k1		; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vmovapd %xmm0, %xmm3		; CHECK-NEXT: vmovapd %xmm0, %xmm3
; CHECK-NEXT: vfmadd213sd %xmm2, %xmm1, %xmm3 {%k1} {z}		; CHECK-NEXT: vfmadd213sd %xmm2, %xmm1, %xmm3 {%k1} {z}
; CHECK-NEXT: vfmadd213sd {rz-sae}, %xmm2, %xmm1, %xmm0 {%k1} {z}		; CHECK-NEXT: vfmadd213sd {rz-sae}, %xmm2, %xmm1, %xmm0 {%k1} {z}
; CHECK-NEXT: vaddpd %xmm0, %xmm3, %xmm0		; CHECK-NEXT: vaddpd %xmm0, %xmm3, %xmm0
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%res = call <2 x double> @llvm.x86.avx512.maskz.vfmadd.sd(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3, i32 4)		%res = call <2 x double> @llvm.x86.avx512.maskz.vfmadd.sd(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3, i32 4)
%res1 = call <2 x double> @llvm.x86.avx512.maskz.vfmadd.sd(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3, i32 3)		%res1 = call <2 x double> @llvm.x86.avx512.maskz.vfmadd.sd(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3, i32 3)
%res2 = fadd <2 x double> %res, %res1		%res2 = fadd <2 x double> %res, %res1
ret <2 x double> %res2		ret <2 x double> %res2
}		}

declare <4 x float> @llvm.x86.avx512.maskz.vfmadd.ss(<4 x float>, <4 x float>, <4 x float>, i8, i32)		declare <4 x float> @llvm.x86.avx512.maskz.vfmadd.ss(<4 x float>, <4 x float>, <4 x float>, i8, i32)

define <4 x float>@test_int_x86_avx512_maskz_vfmadd_ss(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3,i32 %x4 ){		define <4 x float>@test_int_x86_avx512_maskz_vfmadd_ss(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3,i32 %x4 ){
; CHECK-LABEL: test_int_x86_avx512_maskz_vfmadd_ss:		; CHECK-LABEL: test_int_x86_avx512_maskz_vfmadd_ss:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: kmovw %edi, %k1		; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vfmadd213ss %xmm2, %xmm1, %xmm0 {%k1} {z}		; CHECK-NEXT: vfmadd213ss %xmm2, %xmm1, %xmm0 {%k1} {z}
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%res = call <4 x float> @llvm.x86.avx512.maskz.vfmadd.ss(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3, i32 4)		%res = call <4 x float> @llvm.x86.avx512.maskz.vfmadd.ss(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3, i32 4)
%res1 = call <4 x float> @llvm.x86.avx512.maskz.vfmadd.ss(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3, i32 3)		%res1 = call <4 x float> @llvm.x86.avx512.maskz.vfmadd.ss(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3, i32 3)
%res2 = fadd <4 x float> %res, %res1		%res2 = fadd <4 x float> %res, %res1
ret <4 x float> %res		ret <4 x float> %res
}		}
declare <2 x double> @llvm.x86.avx512.mask3.vfmadd.sd(<2 x double>, <2 x double>, <2 x double>, i8, i32)		declare <2 x double> @llvm.x86.avx512.mask3.vfmadd.sd(<2 x double>, <2 x double>, <2 x double>, i8, i32)

define <2 x double>@test_int_x86_avx512_mask3_vfmadd_sd(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3,i32 %x4 ){		define <2 x double>@test_int_x86_avx512_mask3_vfmadd_sd(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3,i32 %x4 ){
; CHECK-LABEL: test_int_x86_avx512_mask3_vfmadd_sd:		; CHECK-LABEL: test_int_x86_avx512_mask3_vfmadd_sd:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: kmovw %edi, %k1		; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vmovapd %xmm2, %xmm3		; CHECK-NEXT: vmovapd %xmm2, %xmm3
; CHECK-NEXT: vfmadd231sd %xmm1, %xmm0, %xmm3 {%k1}		; CHECK-NEXT: vfmadd231sd %xmm1, %xmm0, %xmm3 {%k1}
; CHECK-NEXT: vmovapd %xmm2, %xmm4		; CHECK-NEXT: vmovapd %xmm2, %xmm4
; CHECK-NEXT: vfmadd231sd %xmm1, %xmm0, %xmm4		; CHECK-NEXT: vfmadd231sd %xmm1, %xmm0, %xmm4
; CHECK-NEXT: vmovapd %xmm2, %xmm5		; CHECK-NEXT: vmovapd %xmm2, %xmm5
; CHECK-NEXT: vfmadd231sd {rz-sae}, %xmm1, %xmm0, %xmm5 {%k1}		; CHECK-NEXT: vfmadd231sd {rz-sae}, %xmm1, %xmm0, %xmm5 {%k1}
; CHECK-NEXT: vfmadd231sd {rz-sae}, %xmm1, %xmm0, %xmm2		; CHECK-NEXT: vfmadd231sd {rz-sae}, %xmm1, %xmm0, %xmm2
Show All 11 Lines	; CHECK-NEXT: retq
ret <2 x double> %res6		ret <2 x double> %res6
}		}

declare <4 x float> @llvm.x86.avx512.mask3.vfmadd.ss(<4 x float>, <4 x float>, <4 x float>, i8, i32)		declare <4 x float> @llvm.x86.avx512.mask3.vfmadd.ss(<4 x float>, <4 x float>, <4 x float>, i8, i32)

define <4 x float>@test_int_x86_avx512_mask3_vfmadd_ss(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3,i32 %x4 ){		define <4 x float>@test_int_x86_avx512_mask3_vfmadd_ss(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3,i32 %x4 ){
; CHECK-LABEL: test_int_x86_avx512_mask3_vfmadd_ss:		; CHECK-LABEL: test_int_x86_avx512_mask3_vfmadd_ss:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: kmovw %edi, %k1		; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vmovaps %xmm2, %xmm3		; CHECK-NEXT: vmovaps %xmm2, %xmm3
; CHECK-NEXT: vfmadd231ss %xmm1, %xmm0, %xmm3 {%k1}		; CHECK-NEXT: vfmadd231ss %xmm1, %xmm0, %xmm3 {%k1}
; CHECK-NEXT: vmovaps %xmm2, %xmm4		; CHECK-NEXT: vmovaps %xmm2, %xmm4
; CHECK-NEXT: vfmadd231ss %xmm1, %xmm0, %xmm4		; CHECK-NEXT: vfmadd231ss %xmm1, %xmm0, %xmm4
; CHECK-NEXT: vmovaps %xmm2, %xmm5		; CHECK-NEXT: vmovaps %xmm2, %xmm5
; CHECK-NEXT: vfmadd231ss {rz-sae}, %xmm1, %xmm0, %xmm5 {%k1}		; CHECK-NEXT: vfmadd231ss {rz-sae}, %xmm1, %xmm0, %xmm5 {%k1}
; CHECK-NEXT: vfmadd231ss {rz-sae}, %xmm1, %xmm0, %xmm2		; CHECK-NEXT: vfmadd231ss {rz-sae}, %xmm1, %xmm0, %xmm2
Show All 10 Lines	; CHECK-NEXT: retq
%res6 = fadd <4 x float> %res4, %res5		%res6 = fadd <4 x float> %res4, %res5
ret <4 x float> %res6		ret <4 x float> %res6
}		}

define void @fmadd_ss_mask_memfold(float* %a, float* %b, i8 %c) {		define void @fmadd_ss_mask_memfold(float* %a, float* %b, i8 %c) {
; CHECK-LABEL: fmadd_ss_mask_memfold:		; CHECK-LABEL: fmadd_ss_mask_memfold:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero		; CHECK-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-NEXT: andl $1, %edx
; CHECK-NEXT: kmovw %edx, %k1		; CHECK-NEXT: kmovw %edx, %k1
; CHECK-NEXT: vfmadd132ss (%rsi), %xmm0, %xmm0 {%k1}		; CHECK-NEXT: vfmadd132ss (%rsi), %xmm0, %xmm0 {%k1}
; CHECK-NEXT: vmovss %xmm0, (%rdi)		; CHECK-NEXT: vmovss %xmm0, (%rdi)
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%a.val = load float, float* %a		%a.val = load float, float* %a
%av0 = insertelement <4 x float> undef, float %a.val, i32 0		%av0 = insertelement <4 x float> undef, float %a.val, i32 0
%av1 = insertelement <4 x float> %av0, float 0.000000e+00, i32 1		%av1 = insertelement <4 x float> %av0, float 0.000000e+00, i32 1
%av2 = insertelement <4 x float> %av1, float 0.000000e+00, i32 2		%av2 = insertelement <4 x float> %av1, float 0.000000e+00, i32 2
Show All 11 Lines	; CHECK-NEXT: retq
store float %sr, float* %a		store float %sr, float* %a
ret void		ret void
}		}

define void @fmadd_ss_maskz_memfold(float* %a, float* %b, i8 %c) {		define void @fmadd_ss_maskz_memfold(float* %a, float* %b, i8 %c) {
; CHECK-LABEL: fmadd_ss_maskz_memfold:		; CHECK-LABEL: fmadd_ss_maskz_memfold:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero		; CHECK-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-NEXT: andl $1, %edx
; CHECK-NEXT: kmovw %edx, %k1		; CHECK-NEXT: kmovw %edx, %k1
; CHECK-NEXT: vfmadd132ss (%rsi), %xmm0, %xmm0 {%k1} {z}		; CHECK-NEXT: vfmadd132ss (%rsi), %xmm0, %xmm0 {%k1} {z}
; CHECK-NEXT: vmovss %xmm0, (%rdi)		; CHECK-NEXT: vmovss %xmm0, (%rdi)
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%a.val = load float, float* %a		%a.val = load float, float* %a
%av0 = insertelement <4 x float> undef, float %a.val, i32 0		%av0 = insertelement <4 x float> undef, float %a.val, i32 0
%av1 = insertelement <4 x float> %av0, float 0.000000e+00, i32 1		%av1 = insertelement <4 x float> %av0, float 0.000000e+00, i32 1
%av2 = insertelement <4 x float> %av1, float 0.000000e+00, i32 2		%av2 = insertelement <4 x float> %av1, float 0.000000e+00, i32 2
Show All 11 Lines	; CHECK-NEXT: retq
store float %sr, float* %a		store float %sr, float* %a
ret void		ret void
}		}

define void @fmadd_sd_mask_memfold(double* %a, double* %b, i8 %c) {		define void @fmadd_sd_mask_memfold(double* %a, double* %b, i8 %c) {
; CHECK-LABEL: fmadd_sd_mask_memfold:		; CHECK-LABEL: fmadd_sd_mask_memfold:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero		; CHECK-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: andl $1, %edx
; CHECK-NEXT: kmovw %edx, %k1		; CHECK-NEXT: kmovw %edx, %k1
; CHECK-NEXT: vfmadd132sd (%rsi), %xmm0, %xmm0 {%k1}		; CHECK-NEXT: vfmadd132sd (%rsi), %xmm0, %xmm0 {%k1}
; CHECK-NEXT: vmovlpd %xmm0, (%rdi)		; CHECK-NEXT: vmovlpd %xmm0, (%rdi)
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%a.val = load double, double* %a		%a.val = load double, double* %a
%av0 = insertelement <2 x double> undef, double %a.val, i32 0		%av0 = insertelement <2 x double> undef, double %a.val, i32 0
%av = insertelement <2 x double> %av0, double 0.000000e+00, i32 1		%av = insertelement <2 x double> %av0, double 0.000000e+00, i32 1

%b.val = load double, double* %b		%b.val = load double, double* %b
%bv0 = insertelement <2 x double> undef, double %b.val, i32 0		%bv0 = insertelement <2 x double> undef, double %b.val, i32 0
%bv = insertelement <2 x double> %bv0, double 0.000000e+00, i32 1		%bv = insertelement <2 x double> %bv0, double 0.000000e+00, i32 1

%vr = call <2 x double> @llvm.x86.avx512.mask.vfmadd.sd(<2 x double> %av, <2 x double> %bv, <2 x double> %av, i8 %c, i32 4)		%vr = call <2 x double> @llvm.x86.avx512.mask.vfmadd.sd(<2 x double> %av, <2 x double> %bv, <2 x double> %av, i8 %c, i32 4)

%sr = extractelement <2 x double> %vr, i32 0		%sr = extractelement <2 x double> %vr, i32 0
store double %sr, double* %a		store double %sr, double* %a
ret void		ret void
}		}

define void @fmadd_sd_maskz_memfold(double* %a, double* %b, i8 %c) {		define void @fmadd_sd_maskz_memfold(double* %a, double* %b, i8 %c) {
; CHECK-LABEL: fmadd_sd_maskz_memfold:		; CHECK-LABEL: fmadd_sd_maskz_memfold:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero		; CHECK-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: andl $1, %edx
; CHECK-NEXT: kmovw %edx, %k1		; CHECK-NEXT: kmovw %edx, %k1
; CHECK-NEXT: vfmadd132sd (%rsi), %xmm0, %xmm0 {%k1} {z}		; CHECK-NEXT: vfmadd132sd (%rsi), %xmm0, %xmm0 {%k1} {z}
; CHECK-NEXT: vmovlpd %xmm0, (%rdi)		; CHECK-NEXT: vmovlpd %xmm0, (%rdi)
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%a.val = load double, double* %a		%a.val = load double, double* %a
%av0 = insertelement <2 x double> undef, double %a.val, i32 0		%av0 = insertelement <2 x double> undef, double %a.val, i32 0
%av = insertelement <2 x double> %av0, double 0.000000e+00, i32 1		%av = insertelement <2 x double> %av0, double 0.000000e+00, i32 1

%b.val = load double, double* %b		%b.val = load double, double* %b
%bv0 = insertelement <2 x double> undef, double %b.val, i32 0		%bv0 = insertelement <2 x double> undef, double %b.val, i32 0
%bv = insertelement <2 x double> %bv0, double 0.000000e+00, i32 1		%bv = insertelement <2 x double> %bv0, double 0.000000e+00, i32 1

%vr = call <2 x double> @llvm.x86.avx512.maskz.vfmadd.sd(<2 x double> %av, <2 x double> %bv, <2 x double> %av, i8 %c, i32 4)		%vr = call <2 x double> @llvm.x86.avx512.maskz.vfmadd.sd(<2 x double> %av, <2 x double> %bv, <2 x double> %av, i8 %c, i32 4)

%sr = extractelement <2 x double> %vr, i32 0		%sr = extractelement <2 x double> %vr, i32 0
store double %sr, double* %a		store double %sr, double* %a
ret void		ret void
}		}

declare <2 x double> @llvm.x86.avx512.mask3.vfmsub.sd(<2 x double>, <2 x double>, <2 x double>, i8, i32)		declare <2 x double> @llvm.x86.avx512.mask3.vfmsub.sd(<2 x double>, <2 x double>, <2 x double>, i8, i32)

define <2 x double>@test_int_x86_avx512_mask3_vfmsub_sd(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3,i32 %x4 ){		define <2 x double>@test_int_x86_avx512_mask3_vfmsub_sd(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3,i32 %x4 ){
; CHECK-LABEL: test_int_x86_avx512_mask3_vfmsub_sd:		; CHECK-LABEL: test_int_x86_avx512_mask3_vfmsub_sd:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: kmovw %edi, %k1		; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vmovapd %xmm2, %xmm3		; CHECK-NEXT: vmovapd %xmm2, %xmm3
; CHECK-NEXT: vfmsub231sd %xmm1, %xmm0, %xmm3 {%k1}		; CHECK-NEXT: vfmsub231sd %xmm1, %xmm0, %xmm3 {%k1}
; CHECK-NEXT: vmovapd %xmm2, %xmm4		; CHECK-NEXT: vmovapd %xmm2, %xmm4
; CHECK-NEXT: vfmsub231sd %xmm1, %xmm0, %xmm4		; CHECK-NEXT: vfmsub231sd %xmm1, %xmm0, %xmm4
; CHECK-NEXT: vmovapd %xmm2, %xmm5		; CHECK-NEXT: vmovapd %xmm2, %xmm5
; CHECK-NEXT: vfmsub231sd {rz-sae}, %xmm1, %xmm0, %xmm5 {%k1}		; CHECK-NEXT: vfmsub231sd {rz-sae}, %xmm1, %xmm0, %xmm5 {%k1}
; CHECK-NEXT: vfmsub231sd {rz-sae}, %xmm1, %xmm0, %xmm2		; CHECK-NEXT: vfmsub231sd {rz-sae}, %xmm1, %xmm0, %xmm2
Show All 11 Lines	; CHECK-NEXT: retq
ret <2 x double> %res6		ret <2 x double> %res6
}		}

declare <4 x float> @llvm.x86.avx512.mask3.vfmsub.ss(<4 x float>, <4 x float>, <4 x float>, i8, i32)		declare <4 x float> @llvm.x86.avx512.mask3.vfmsub.ss(<4 x float>, <4 x float>, <4 x float>, i8, i32)

define <4 x float>@test_int_x86_avx512_mask3_vfmsub_ss(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3,i32 %x4 ){		define <4 x float>@test_int_x86_avx512_mask3_vfmsub_ss(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3,i32 %x4 ){
; CHECK-LABEL: test_int_x86_avx512_mask3_vfmsub_ss:		; CHECK-LABEL: test_int_x86_avx512_mask3_vfmsub_ss:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: kmovw %edi, %k1		; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vmovaps %xmm2, %xmm3		; CHECK-NEXT: vmovaps %xmm2, %xmm3
; CHECK-NEXT: vfmsub231ss %xmm1, %xmm0, %xmm3 {%k1}		; CHECK-NEXT: vfmsub231ss %xmm1, %xmm0, %xmm3 {%k1}
; CHECK-NEXT: vmovaps %xmm2, %xmm4		; CHECK-NEXT: vmovaps %xmm2, %xmm4
; CHECK-NEXT: vfmsub231ss %xmm1, %xmm0, %xmm4		; CHECK-NEXT: vfmsub231ss %xmm1, %xmm0, %xmm4
; CHECK-NEXT: vmovaps %xmm2, %xmm5		; CHECK-NEXT: vmovaps %xmm2, %xmm5
; CHECK-NEXT: vfmsub231ss {rz-sae}, %xmm1, %xmm0, %xmm5 {%k1}		; CHECK-NEXT: vfmsub231ss {rz-sae}, %xmm1, %xmm0, %xmm5 {%k1}
; CHECK-NEXT: vfmsub231ss {rz-sae}, %xmm1, %xmm0, %xmm2		; CHECK-NEXT: vfmsub231ss {rz-sae}, %xmm1, %xmm0, %xmm2
Show All 11 Lines	; CHECK-NEXT: retq
ret <4 x float> %res6		ret <4 x float> %res6
}		}

declare <2 x double> @llvm.x86.avx512.mask3.vfnmsub.sd(<2 x double>, <2 x double>, <2 x double>, i8, i32)		declare <2 x double> @llvm.x86.avx512.mask3.vfnmsub.sd(<2 x double>, <2 x double>, <2 x double>, i8, i32)

define <2 x double>@test_int_x86_avx512_mask3_vfnmsub_sd(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3,i32 %x4 ){		define <2 x double>@test_int_x86_avx512_mask3_vfnmsub_sd(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3,i32 %x4 ){
; CHECK-LABEL: test_int_x86_avx512_mask3_vfnmsub_sd:		; CHECK-LABEL: test_int_x86_avx512_mask3_vfnmsub_sd:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: kmovw %edi, %k1		; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vmovapd %xmm2, %xmm3		; CHECK-NEXT: vmovapd %xmm2, %xmm3
; CHECK-NEXT: vfnmsub231sd %xmm1, %xmm0, %xmm3 {%k1}		; CHECK-NEXT: vfnmsub231sd %xmm1, %xmm0, %xmm3 {%k1}
; CHECK-NEXT: vmovapd %xmm2, %xmm4		; CHECK-NEXT: vmovapd %xmm2, %xmm4
; CHECK-NEXT: vfnmsub231sd %xmm1, %xmm0, %xmm4		; CHECK-NEXT: vfnmsub231sd %xmm1, %xmm0, %xmm4
; CHECK-NEXT: vmovapd %xmm2, %xmm5		; CHECK-NEXT: vmovapd %xmm2, %xmm5
; CHECK-NEXT: vfnmsub231sd {rz-sae}, %xmm1, %xmm0, %xmm5 {%k1}		; CHECK-NEXT: vfnmsub231sd {rz-sae}, %xmm1, %xmm0, %xmm5 {%k1}
; CHECK-NEXT: vfnmsub231sd {rz-sae}, %xmm1, %xmm0, %xmm2		; CHECK-NEXT: vfnmsub231sd {rz-sae}, %xmm1, %xmm0, %xmm2
Show All 11 Lines	; CHECK-NEXT: retq
ret <2 x double> %res6		ret <2 x double> %res6
}		}

declare <4 x float> @llvm.x86.avx512.mask3.vfnmsub.ss(<4 x float>, <4 x float>, <4 x float>, i8, i32)		declare <4 x float> @llvm.x86.avx512.mask3.vfnmsub.ss(<4 x float>, <4 x float>, <4 x float>, i8, i32)

define <4 x float>@test_int_x86_avx512_mask3_vfnmsub_ss(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3,i32 %x4 ){		define <4 x float>@test_int_x86_avx512_mask3_vfnmsub_ss(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3,i32 %x4 ){
; CHECK-LABEL: test_int_x86_avx512_mask3_vfnmsub_ss:		; CHECK-LABEL: test_int_x86_avx512_mask3_vfnmsub_ss:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: kmovw %edi, %k1		; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vmovaps %xmm2, %xmm3		; CHECK-NEXT: vmovaps %xmm2, %xmm3
; CHECK-NEXT: vfnmsub231ss %xmm1, %xmm0, %xmm3 {%k1}		; CHECK-NEXT: vfnmsub231ss %xmm1, %xmm0, %xmm3 {%k1}
; CHECK-NEXT: vmovaps %xmm2, %xmm4		; CHECK-NEXT: vmovaps %xmm2, %xmm4
; CHECK-NEXT: vfnmsub231ss %xmm1, %xmm0, %xmm4		; CHECK-NEXT: vfnmsub231ss %xmm1, %xmm0, %xmm4
; CHECK-NEXT: vmovaps %xmm2, %xmm5		; CHECK-NEXT: vmovaps %xmm2, %xmm5
; CHECK-NEXT: vfnmsub231ss {rz-sae}, %xmm1, %xmm0, %xmm5 {%k1}		; CHECK-NEXT: vfnmsub231ss {rz-sae}, %xmm1, %xmm0, %xmm5 {%k1}
; CHECK-NEXT: vfnmsub231ss {rz-sae}, %xmm1, %xmm0, %xmm2		; CHECK-NEXT: vfnmsub231ss {rz-sae}, %xmm1, %xmm0, %xmm2
Show All 9 Lines	; CHECK-NEXT: retq
%res5 = fadd <4 x float> %res2, %res3		%res5 = fadd <4 x float> %res2, %res3
%res6 = fadd <4 x float> %res4, %res5		%res6 = fadd <4 x float> %res4, %res5
ret <4 x float> %res6		ret <4 x float> %res6
}		}

define <4 x float>@test_int_x86_avx512_mask3_vfmadd_ss_rm(<4 x float> %x0, <4 x float> %x1, float *%ptr_b ,i8 %x3,i32 %x4) {		define <4 x float>@test_int_x86_avx512_mask3_vfmadd_ss_rm(<4 x float> %x0, <4 x float> %x1, float *%ptr_b ,i8 %x3,i32 %x4) {
; CHECK-LABEL: test_int_x86_avx512_mask3_vfmadd_ss_rm:		; CHECK-LABEL: test_int_x86_avx512_mask3_vfmadd_ss_rm:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %esi
; CHECK-NEXT: kmovw %esi, %k1		; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: vfmadd231ss (%rdi), %xmm0, %xmm1 {%k1}		; CHECK-NEXT: vfmadd231ss (%rdi), %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vmovaps %xmm1, %xmm0		; CHECK-NEXT: vmovaps %xmm1, %xmm0
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%q = load float, float* %ptr_b		%q = load float, float* %ptr_b
%vecinit.i = insertelement <4 x float> undef, float %q, i32 0		%vecinit.i = insertelement <4 x float> undef, float %q, i32 0
%res = call <4 x float> @llvm.x86.avx512.mask3.vfmadd.ss(<4 x float> %x0, <4 x float> %vecinit.i, <4 x float> %x1, i8 %x3, i32 4)		%res = call <4 x float> @llvm.x86.avx512.mask3.vfmadd.ss(<4 x float> %x0, <4 x float> %vecinit.i, <4 x float> %x1, i8 %x3, i32 4)
ret < 4 x float> %res		ret < 4 x float> %res
}		}

define <4 x float>@test_int_x86_avx512_mask_vfmadd_ss_rm(<4 x float> %x0, <4 x float> %x1,float *%ptr_b ,i8 %x3,i32 %x4) {		define <4 x float>@test_int_x86_avx512_mask_vfmadd_ss_rm(<4 x float> %x0, <4 x float> %x1,float *%ptr_b ,i8 %x3,i32 %x4) {
; CHECK-LABEL: test_int_x86_avx512_mask_vfmadd_ss_rm:		; CHECK-LABEL: test_int_x86_avx512_mask_vfmadd_ss_rm:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %esi
; CHECK-NEXT: kmovw %esi, %k1		; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: vfmadd132ss (%rdi), %xmm1, %xmm0 {%k1}		; CHECK-NEXT: vfmadd132ss (%rdi), %xmm1, %xmm0 {%k1}
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%q = load float, float* %ptr_b		%q = load float, float* %ptr_b
%vecinit.i = insertelement <4 x float> undef, float %q, i32 0		%vecinit.i = insertelement <4 x float> undef, float %q, i32 0
%res = call <4 x float> @llvm.x86.avx512.mask.vfmadd.ss(<4 x float> %x0,<4 x float> %vecinit.i, <4 x float> %x1, i8 %x3, i32 4)		%res = call <4 x float> @llvm.x86.avx512.mask.vfmadd.ss(<4 x float> %x0,<4 x float> %vecinit.i, <4 x float> %x1, i8 %x3, i32 4)
ret < 4 x float> %res		ret < 4 x float> %res
}		}


define <4 x float>@test_int_x86_avx512_maskz_vfmadd_ss_rm(<4 x float> %x0, <4 x float> %x1,float *%ptr_b ,i8 %x3,i32 %x4) {		define <4 x float>@test_int_x86_avx512_maskz_vfmadd_ss_rm(<4 x float> %x0, <4 x float> %x1,float *%ptr_b ,i8 %x3,i32 %x4) {
; CHECK-LABEL: test_int_x86_avx512_maskz_vfmadd_ss_rm:		; CHECK-LABEL: test_int_x86_avx512_maskz_vfmadd_ss_rm:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: kxorw %k0, %k0, %k1		; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vfmadd213ss (%rdi), %xmm1, %xmm0 {%k1} {z}
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%q = load float, float* %ptr_b		%q = load float, float* %ptr_b
%vecinit.i = insertelement <4 x float> undef, float %q, i32 0		%vecinit.i = insertelement <4 x float> undef, float %q, i32 0
%res = call <4 x float> @llvm.x86.avx512.maskz.vfmadd.ss(<4 x float> %x0, <4 x float> %x1, <4 x float> %vecinit.i, i8 0, i32 4)		%res = call <4 x float> @llvm.x86.avx512.maskz.vfmadd.ss(<4 x float> %x0, <4 x float> %x1, <4 x float> %vecinit.i, i8 0, i32 4)
ret < 4 x float> %res		ret < 4 x float> %res
}		}

define <16 x i32> @test_x86_avx512_psll_d_512(<16 x i32> %a0, <4 x i32> %a1) {		define <16 x i32> @test_x86_avx512_psll_d_512(<16 x i32> %a0, <4 x i32> %a1) {
▲ Show 20 Lines • Show All 624 Lines • Show Last 20 Lines

test/CodeGen/X86/avx512-load-store.ll

	; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py			; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
	; RUN: llc < %s -O2 -mattr=avx512f -mtriple=x86_64-unknown \| FileCheck %s --check-prefix=CHECK --check-prefix=CHECK64			; RUN: llc < %s -O2 -mattr=avx512f -mtriple=x86_64-unknown \| FileCheck %s --check-prefix=CHECK --check-prefix=CHECK64
	; RUN: llc < %s -O2 -mattr=avx512f -mtriple=i386-unknown \| FileCheck %s --check-prefix=CHECK --check-prefix=CHECK32			; RUN: llc < %s -O2 -mattr=avx512f -mtriple=i386-unknown \| FileCheck %s --check-prefix=CHECK --check-prefix=CHECK32

	define <4 x float> @test_mm_mask_move_ss(<4 x float> %__W, i8 zeroext %__U, <4 x float> %__A, <4 x float> %__B) local_unnamed_addr #0 {			define <4 x float> @test_mm_mask_move_ss(<4 x float> %__W, i8 zeroext %__U, <4 x float> %__A, <4 x float> %__B) local_unnamed_addr #0 {
	; CHECK64-LABEL: test_mm_mask_move_ss:			; CHECK64-LABEL: test_mm_mask_move_ss:
	; CHECK64: # BB#0: # %entry			; CHECK64: # BB#0: # %entry
	; CHECK64-NEXT: kmovw %edi, %k1			; CHECK64-NEXT: kmovw %edi, %k1
	; CHECK64-NEXT: vmovss %xmm2, %xmm1, %xmm0 {%k1}			; CHECK64-NEXT: vmovss %xmm2, %xmm1, %xmm0 {%k1}
	; CHECK64-NEXT: retq			; CHECK64-NEXT: retq
	;			;
	; CHECK32-LABEL: test_mm_mask_move_ss:			; CHECK32-LABEL: test_mm_mask_move_ss:
	; CHECK32: # BB#0: # %entry			; CHECK32: # BB#0: # %entry
	; CHECK32-NEXT: movb {{[0-9]+}}(%esp), %al			; CHECK32-NEXT: movb {{[0-9]+}}(%esp), %al
	; CHECK32-NEXT: andl $1, %eax			; CHECK32-NEXT: andb $1, %al
	; CHECK32-NEXT: kmovw %eax, %k1			; CHECK32-NEXT: kmovw %eax, %k1
	; CHECK32-NEXT: vmovss %xmm2, %xmm0, %xmm0 {%k1}			; CHECK32-NEXT: vmovss %xmm2, %xmm0, %xmm0 {%k1}
	; CHECK32-NEXT: vmovss {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]			; CHECK32-NEXT: vmovss {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
	; CHECK32-NEXT: retl			; CHECK32-NEXT: retl
	entry:			entry:
	%0 = and i8 %__U, 1			%0 = and i8 %__U, 1
	%tobool.i = icmp ne i8 %0, 0			%tobool.i = icmp ne i8 %0, 0
	%__B.elt.i = extractelement <4 x float> %__B, i32 0			%__B.elt.i = extractelement <4 x float> %__B, i32 0
	%__W.elt.i = extractelement <4 x float> %__W, i32 0			%__W.elt.i = extractelement <4 x float> %__W, i32 0
	%vecext1.i = select i1 %tobool.i, float %__B.elt.i, float %__W.elt.i			%vecext1.i = select i1 %tobool.i, float %__B.elt.i, float %__W.elt.i
	%vecins.i = insertelement <4 x float> %__A, float %vecext1.i, i32 0			%vecins.i = insertelement <4 x float> %__A, float %vecext1.i, i32 0
	ret <4 x float> %vecins.i			ret <4 x float> %vecins.i
	}			}

	define <4 x float> @test_mm_maskz_move_ss(i8 zeroext %__U, <4 x float> %__A, <4 x float> %__B) local_unnamed_addr #0 {			define <4 x float> @test_mm_maskz_move_ss(i8 zeroext %__U, <4 x float> %__A, <4 x float> %__B) local_unnamed_addr #0 {
	; CHECK64-LABEL: test_mm_maskz_move_ss:			; CHECK64-LABEL: test_mm_maskz_move_ss:
	; CHECK64: # BB#0: # %entry			; CHECK64: # BB#0: # %entry
	; CHECK64-NEXT: kmovw %edi, %k1			; CHECK64-NEXT: kmovw %edi, %k1
	; CHECK64-NEXT: vmovss %xmm1, %xmm0, %xmm0 {%k1} {z}			; CHECK64-NEXT: vmovss %xmm1, %xmm0, %xmm0 {%k1} {z}
	; CHECK64-NEXT: retq			; CHECK64-NEXT: retq
	;			;
	; CHECK32-LABEL: test_mm_maskz_move_ss:			; CHECK32-LABEL: test_mm_maskz_move_ss:
	; CHECK32: # BB#0: # %entry			; CHECK32: # BB#0: # %entry
	; CHECK32-NEXT: movb {{[0-9]+}}(%esp), %al			; CHECK32-NEXT: movb {{[0-9]+}}(%esp), %al
	; CHECK32-NEXT: andl $1, %eax			; CHECK32-NEXT: andb $1, %al
	; CHECK32-NEXT: kmovw %eax, %k1
	; CHECK32-NEXT: vxorps %xmm2, %xmm2, %xmm2			; CHECK32-NEXT: vxorps %xmm2, %xmm2, %xmm2
				; CHECK32-NEXT: kmovw %eax, %k1
	; CHECK32-NEXT: vmovss %xmm1, %xmm0, %xmm2 {%k1}			; CHECK32-NEXT: vmovss %xmm1, %xmm0, %xmm2 {%k1}
	; CHECK32-NEXT: vmovss {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3]			; CHECK32-NEXT: vmovss {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3]
	; CHECK32-NEXT: retl			; CHECK32-NEXT: retl
	entry:			entry:
	%0 = and i8 %__U, 1			%0 = and i8 %__U, 1
	%tobool.i = icmp ne i8 %0, 0			%tobool.i = icmp ne i8 %0, 0
	%vecext.i = extractelement <4 x float> %__B, i32 0			%vecext.i = extractelement <4 x float> %__B, i32 0
	%cond.i = select i1 %tobool.i, float %vecext.i, float 0.000000e+00			%cond.i = select i1 %tobool.i, float %vecext.i, float 0.000000e+00
	%vecins.i = insertelement <4 x float> %__A, float %cond.i, i32 0			%vecins.i = insertelement <4 x float> %__A, float %cond.i, i32 0
	ret <4 x float> %vecins.i			ret <4 x float> %vecins.i
	}			}

	define <2 x double> @test_mm_mask_move_sd(<2 x double> %__W, i8 zeroext %__U, <2 x double> %__A, <2 x double> %__B) local_unnamed_addr #0 {			define <2 x double> @test_mm_mask_move_sd(<2 x double> %__W, i8 zeroext %__U, <2 x double> %__A, <2 x double> %__B) local_unnamed_addr #0 {
	; CHECK64-LABEL: test_mm_mask_move_sd:			; CHECK64-LABEL: test_mm_mask_move_sd:
	; CHECK64: # BB#0: # %entry			; CHECK64: # BB#0: # %entry
	; CHECK64-NEXT: kmovw %edi, %k1			; CHECK64-NEXT: kmovw %edi, %k1
	; CHECK64-NEXT: vmovsd %xmm2, %xmm1, %xmm0 {%k1}			; CHECK64-NEXT: vmovsd %xmm2, %xmm1, %xmm0 {%k1}
	; CHECK64-NEXT: retq			; CHECK64-NEXT: retq
	;			;
	; CHECK32-LABEL: test_mm_mask_move_sd:			; CHECK32-LABEL: test_mm_mask_move_sd:
	; CHECK32: # BB#0: # %entry			; CHECK32: # BB#0: # %entry
	; CHECK32-NEXT: movb {{[0-9]+}}(%esp), %al			; CHECK32-NEXT: movb {{[0-9]+}}(%esp), %al
	; CHECK32-NEXT: andl $1, %eax			; CHECK32-NEXT: andb $1, %al
	; CHECK32-NEXT: kmovw %eax, %k1			; CHECK32-NEXT: kmovw %eax, %k1
	; CHECK32-NEXT: vmovsd %xmm2, %xmm0, %xmm0 {%k1}			; CHECK32-NEXT: vmovsd %xmm2, %xmm0, %xmm0 {%k1}
	; CHECK32-NEXT: vmovsd {{.*#+}} xmm0 = xmm0[0],xmm1[1]			; CHECK32-NEXT: vmovsd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
	; CHECK32-NEXT: retl			; CHECK32-NEXT: retl
	entry:			entry:
	%0 = and i8 %__U, 1			%0 = and i8 %__U, 1
	%tobool.i = icmp ne i8 %0, 0			%tobool.i = icmp ne i8 %0, 0
	%__B.elt.i = extractelement <2 x double> %__B, i32 0			%__B.elt.i = extractelement <2 x double> %__B, i32 0
	%__W.elt.i = extractelement <2 x double> %__W, i32 0			%__W.elt.i = extractelement <2 x double> %__W, i32 0
	%vecext1.i = select i1 %tobool.i, double %__B.elt.i, double %__W.elt.i			%vecext1.i = select i1 %tobool.i, double %__B.elt.i, double %__W.elt.i
	%vecins.i = insertelement <2 x double> %__A, double %vecext1.i, i32 0			%vecins.i = insertelement <2 x double> %__A, double %vecext1.i, i32 0
	ret <2 x double> %vecins.i			ret <2 x double> %vecins.i
	}			}

	define <2 x double> @test_mm_maskz_move_sd(i8 zeroext %__U, <2 x double> %__A, <2 x double> %__B) local_unnamed_addr #0 {			define <2 x double> @test_mm_maskz_move_sd(i8 zeroext %__U, <2 x double> %__A, <2 x double> %__B) local_unnamed_addr #0 {
	; CHECK64-LABEL: test_mm_maskz_move_sd:			; CHECK64-LABEL: test_mm_maskz_move_sd:
	; CHECK64: # BB#0: # %entry			; CHECK64: # BB#0: # %entry
	; CHECK64-NEXT: kmovw %edi, %k1			; CHECK64-NEXT: kmovw %edi, %k1
	; CHECK64-NEXT: vmovsd %xmm1, %xmm0, %xmm0 {%k1} {z}			; CHECK64-NEXT: vmovsd %xmm1, %xmm0, %xmm0 {%k1} {z}
	; CHECK64-NEXT: retq			; CHECK64-NEXT: retq
	;			;
	; CHECK32-LABEL: test_mm_maskz_move_sd:			; CHECK32-LABEL: test_mm_maskz_move_sd:
	; CHECK32: # BB#0: # %entry			; CHECK32: # BB#0: # %entry
	; CHECK32-NEXT: movb {{[0-9]+}}(%esp), %al			; CHECK32-NEXT: movb {{[0-9]+}}(%esp), %al
	; CHECK32-NEXT: andl $1, %eax			; CHECK32-NEXT: andb $1, %al
	; CHECK32-NEXT: kmovw %eax, %k1
	; CHECK32-NEXT: vxorpd %xmm2, %xmm2, %xmm2			; CHECK32-NEXT: vxorpd %xmm2, %xmm2, %xmm2
				; CHECK32-NEXT: kmovw %eax, %k1
	; CHECK32-NEXT: vmovsd %xmm1, %xmm0, %xmm2 {%k1}			; CHECK32-NEXT: vmovsd %xmm1, %xmm0, %xmm2 {%k1}
	; CHECK32-NEXT: vmovsd {{.*#+}} xmm0 = xmm2[0],xmm0[1]			; CHECK32-NEXT: vmovsd {{.*#+}} xmm0 = xmm2[0],xmm0[1]
	; CHECK32-NEXT: retl			; CHECK32-NEXT: retl
	entry:			entry:
	%0 = and i8 %__U, 1			%0 = and i8 %__U, 1
	%tobool.i = icmp ne i8 %0, 0			%tobool.i = icmp ne i8 %0, 0
	%vecext.i = extractelement <2 x double> %__B, i32 0			%vecext.i = extractelement <2 x double> %__B, i32 0
	%cond.i = select i1 %tobool.i, double %vecext.i, double 0.000000e+00			%cond.i = select i1 %tobool.i, double %vecext.i, double 0.000000e+00
	▲ Show 20 Lines • Show All 156 Lines • Show Last 20 Lines

test/CodeGen/X86/avx512-mask-bugfix.ll

This file was deleted.

	; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl \| FileCheck %s

	; ModuleID = 'foo.ll'
	target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
	target triple = "x86_64-unknown-linux-gnu"

	; Function Attrs: nounwind readnone
	declare i32 @llvm.x86.avx.movmsk.ps.256(<8 x float>) #0

	; Function Attrs: nounwind readnone
	declare i64 @llvm.cttz.i64(i64, i1) #0

	; Function Attrs: nounwind
	define void @foo(float* noalias %aFOO, float %b, i32 %a) {
	allocas:
	%full_mask_memory.i57 = alloca <8 x float>
	%return_value_memory.i60 = alloca i1
	%cmp.i = icmp eq i32 %a, 65535
	br i1 %cmp.i, label %all_on, label %some_on

	all_on:
	%mask0 = load <8 x float>, <8 x float>* %full_mask_memory.i57
	%v0.i.i.i70 = call i32 @llvm.x86.avx.movmsk.ps.256(<8 x float> %mask0) #0
	%allon.i.i76 = icmp eq i32 %v0.i.i.i70, 65535
	br i1 %allon.i.i76, label %check_neighbors.i.i121, label %domixed.i.i100

	domixed.i.i100:
	br label %check_neighbors.i.i121

	check_neighbors.i.i121:
	%v1.i5.i.i116 = call i32 @llvm.x86.avx.movmsk.ps.256(<8 x float> %mask0) #0
	%alleq.i.i120 = icmp eq i32 %v1.i5.i.i116, 65535
	br i1 %alleq.i.i120, label %all_equal.i.i123, label %not_all_equal.i.i124

	; CHECK: kxnorw %k0, %k0, %k0
	; CHECK: kshiftrw $15, %k0, %k0
	; CHECK: jmp
	; CHECK: kxorw %k0, %k0, %k0

	all_equal.i.i123:
	br label %reduce_equal___vyi.exit128

	not_all_equal.i.i124:
	br label %reduce_equal___vyi.exit128

	reduce_equal___vyi.exit128:
	%calltmp2.i125 = phi i1 [ true, %all_equal.i.i123 ], [ false, %not_all_equal.i.i124 ]
	store i1 %calltmp2.i125, i1* %return_value_memory.i60
	%return_value.i126 = load i1, i1* %return_value_memory.i60
	%. = select i1 %return_value.i126, i32 1, i32 0
	%select_to_float = sitofp i32 %. to float
	ret void

	some_on:
	ret void
	}

test/CodeGen/X86/avx512-mask-op.ll

Show First 20 Lines • Show All 412 Lines • ▼ Show 20 Lines

define i8 @zext_test3(<16 x i32> %a, <16 x i32> %b) {		define i8 @zext_test3(<16 x i32> %a, <16 x i32> %b) {
; KNL-LABEL: zext_test3:		; KNL-LABEL: zext_test3:
; KNL: ## BB#0:		; KNL: ## BB#0:
; KNL-NEXT: vpcmpnleud %zmm1, %zmm0, %k0		; KNL-NEXT: vpcmpnleud %zmm1, %zmm0, %k0
; KNL-NEXT: kshiftlw $10, %k0, %k0		; KNL-NEXT: kshiftlw $10, %k0, %k0
; KNL-NEXT: kshiftrw $15, %k0, %k0		; KNL-NEXT: kshiftrw $15, %k0, %k0
; KNL-NEXT: kmovw %k0, %eax		; KNL-NEXT: kmovw %k0, %eax
; KNL-NEXT: andl $1, %eax		; KNL-NEXT: andb $1, %al
; KNL-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
; KNL-NEXT: retq		; KNL-NEXT: retq
;		;
; SKX-LABEL: zext_test3:		; SKX-LABEL: zext_test3:
; SKX: ## BB#0:		; SKX: ## BB#0:
; SKX-NEXT: vpcmpnleud %zmm1, %zmm0, %k0		; SKX-NEXT: vpcmpnleud %zmm1, %zmm0, %k0
; SKX-NEXT: kshiftlw $10, %k0, %k0		; SKX-NEXT: kshiftlw $10, %k0, %k0
; SKX-NEXT: kshiftrw $15, %k0, %k0		; SKX-NEXT: kshiftrw $15, %k0, %k0
; SKX-NEXT: kmovd %k0, %eax		; SKX-NEXT: kmovb %k0, %eax
; SKX-NEXT: andl $1, %eax		; SKX-NEXT: andb $1, %al
; SKX-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
; SKX-NEXT: vzeroupper		; SKX-NEXT: vzeroupper
; SKX-NEXT: retq		; SKX-NEXT: retq
;		;
; AVX512BW-LABEL: zext_test3:		; AVX512BW-LABEL: zext_test3:
; AVX512BW: ## BB#0:		; AVX512BW: ## BB#0:
; AVX512BW-NEXT: vpcmpnleud %zmm1, %zmm0, %k0		; AVX512BW-NEXT: vpcmpnleud %zmm1, %zmm0, %k0
; AVX512BW-NEXT: kshiftlw $10, %k0, %k0		; AVX512BW-NEXT: kshiftlw $10, %k0, %k0
; AVX512BW-NEXT: kshiftrw $15, %k0, %k0		; AVX512BW-NEXT: kshiftrw $15, %k0, %k0
; AVX512BW-NEXT: kmovd %k0, %eax		; AVX512BW-NEXT: kmovw %k0, %eax
; AVX512BW-NEXT: andl $1, %eax		; AVX512BW-NEXT: andb $1, %al
; AVX512BW-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
; AVX512BW-NEXT: vzeroupper		; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq		; AVX512BW-NEXT: retq
;		;
; AVX512DQ-LABEL: zext_test3:		; AVX512DQ-LABEL: zext_test3:
; AVX512DQ: ## BB#0:		; AVX512DQ: ## BB#0:
; AVX512DQ-NEXT: vpcmpnleud %zmm1, %zmm0, %k0		; AVX512DQ-NEXT: vpcmpnleud %zmm1, %zmm0, %k0
; AVX512DQ-NEXT: kshiftlw $10, %k0, %k0		; AVX512DQ-NEXT: kshiftlw $10, %k0, %k0
; AVX512DQ-NEXT: kshiftrw $15, %k0, %k0		; AVX512DQ-NEXT: kshiftrw $15, %k0, %k0
; AVX512DQ-NEXT: kmovw %k0, %eax		; AVX512DQ-NEXT: kmovb %k0, %eax
; AVX512DQ-NEXT: andl $1, %eax		; AVX512DQ-NEXT: andb $1, %al
; AVX512DQ-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
; AVX512DQ-NEXT: vzeroupper		; AVX512DQ-NEXT: vzeroupper
; AVX512DQ-NEXT: retq		; AVX512DQ-NEXT: retq
%cmp_res = icmp ugt <16 x i32> %a, %b		%cmp_res = icmp ugt <16 x i32> %a, %b
%cmp_res.i1 = extractelement <16 x i1> %cmp_res, i32 5		%cmp_res.i1 = extractelement <16 x i1> %cmp_res, i32 5
%res = zext i1 %cmp_res.i1 to i8		%res = zext i1 %cmp_res.i1 to i8
ret i8 %res		ret i8 %res
}		}

▲ Show 20 Lines • Show All 497 Lines • ▼ Show 20 Lines
; KNL-NEXT: vpcmpgtb %ymm0, %ymm2, %ymm0		; KNL-NEXT: vpcmpgtb %ymm0, %ymm2, %ymm0
; KNL-NEXT: movq %rbp, %rsp		; KNL-NEXT: movq %rbp, %rsp
; KNL-NEXT: popq %rbp		; KNL-NEXT: popq %rbp
; KNL-NEXT: retq		; KNL-NEXT: retq
;		;
; SKX-LABEL: test16:		; SKX-LABEL: test16:
; SKX: ## BB#0:		; SKX: ## BB#0:
; SKX-NEXT: kmovq %rdi, %k0		; SKX-NEXT: kmovq %rdi, %k0
; SKX-NEXT: kxnorw %k0, %k0, %k1		; SKX-NEXT: movb $1, %al
; SKX-NEXT: kshiftrw $15, %k1, %k1		; SKX-NEXT: kmovb %eax, %k1
; SKX-NEXT: vpmovm2b %k1, %zmm0		; SKX-NEXT: vpmovm2b %k1, %zmm0
; SKX-NEXT: vpsllq $40, %xmm0, %xmm0		; SKX-NEXT: vpsllq $40, %xmm0, %xmm0
; SKX-NEXT: vpmovm2b %k0, %zmm1		; SKX-NEXT: vpmovm2b %k0, %zmm1
; SKX-NEXT: movl $32, %eax		; SKX-NEXT: movl $32, %eax
; SKX-NEXT: kmovd %eax, %k1		; SKX-NEXT: kmovd %eax, %k1
; SKX-NEXT: vpblendmb %ymm0, %ymm1, %ymm0 {%k1}		; SKX-NEXT: vpblendmb %ymm0, %ymm1, %ymm0 {%k1}
; SKX-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm0[0,1,2,3],zmm1[4,5,6,7]		; SKX-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm0[0,1,2,3],zmm1[4,5,6,7]
; SKX-NEXT: vpmovb2m %zmm0, %k0		; SKX-NEXT: vpmovb2m %zmm0, %k0
; SKX-NEXT: vpmovm2b %k0, %zmm0		; SKX-NEXT: vpmovm2b %k0, %zmm0
; SKX-NEXT: retq		; SKX-NEXT: retq
;		;
; AVX512BW-LABEL: test16:		; AVX512BW-LABEL: test16:
; AVX512BW: ## BB#0:		; AVX512BW: ## BB#0:
; AVX512BW-NEXT: kmovq %rdi, %k0		; AVX512BW-NEXT: kmovq %rdi, %k0
; AVX512BW-NEXT: kxnorw %k0, %k0, %k1		; AVX512BW-NEXT: movb $1, %al
; AVX512BW-NEXT: kshiftrw $15, %k1, %k1		; AVX512BW-NEXT: kmovw %eax, %k1
; AVX512BW-NEXT: vpmovm2b %k1, %zmm0		; AVX512BW-NEXT: vpmovm2b %k1, %zmm0
; AVX512BW-NEXT: vpsllq $40, %xmm0, %xmm0		; AVX512BW-NEXT: vpsllq $40, %xmm0, %xmm0
; AVX512BW-NEXT: vpmovm2b %k0, %zmm1		; AVX512BW-NEXT: vpmovm2b %k0, %zmm1
; AVX512BW-NEXT: vmovdqa {{.*#+}} ymm2 = [255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]		; AVX512BW-NEXT: vmovdqa {{.*#+}} ymm2 = [255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512BW-NEXT: vpblendvb %ymm2, %ymm1, %ymm0, %ymm0		; AVX512BW-NEXT: vpblendvb %ymm2, %ymm1, %ymm0, %ymm0
; AVX512BW-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm0[0,1,2,3],zmm1[4,5,6,7]		; AVX512BW-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm0[0,1,2,3],zmm1[4,5,6,7]
; AVX512BW-NEXT: vpmovb2m %zmm0, %k0		; AVX512BW-NEXT: vpmovb2m %zmm0, %k0
; AVX512BW-NEXT: vpmovm2b %k0, %zmm0		; AVX512BW-NEXT: vpmovm2b %k0, %zmm0
▲ Show 20 Lines • Show All 86 Lines • ▼ Show 20 Lines
; KNL-NEXT: popq %rbp		; KNL-NEXT: popq %rbp
; KNL-NEXT: retq		; KNL-NEXT: retq
;		;
; SKX-LABEL: test17:		; SKX-LABEL: test17:
; SKX: ## BB#0:		; SKX: ## BB#0:
; SKX-NEXT: kmovq %rdi, %k0		; SKX-NEXT: kmovq %rdi, %k0
; SKX-NEXT: cmpl %edx, %esi		; SKX-NEXT: cmpl %edx, %esi
; SKX-NEXT: setg %al		; SKX-NEXT: setg %al
; SKX-NEXT: andl $1, %eax		; SKX-NEXT: kmovb %eax, %k1
; SKX-NEXT: kmovd %eax, %k1
; SKX-NEXT: vpmovm2b %k1, %zmm0		; SKX-NEXT: vpmovm2b %k1, %zmm0
; SKX-NEXT: vpsllq $40, %xmm0, %xmm0		; SKX-NEXT: vpsllq $40, %xmm0, %xmm0
; SKX-NEXT: vpmovm2b %k0, %zmm1		; SKX-NEXT: vpmovm2b %k0, %zmm1
; SKX-NEXT: movl $32, %eax		; SKX-NEXT: movl $32, %eax
; SKX-NEXT: kmovd %eax, %k1		; SKX-NEXT: kmovd %eax, %k1
; SKX-NEXT: vpblendmb %ymm0, %ymm1, %ymm0 {%k1}		; SKX-NEXT: vpblendmb %ymm0, %ymm1, %ymm0 {%k1}
; SKX-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm0[0,1,2,3],zmm1[4,5,6,7]		; SKX-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm0[0,1,2,3],zmm1[4,5,6,7]
; SKX-NEXT: vpmovb2m %zmm0, %k0		; SKX-NEXT: vpmovb2m %zmm0, %k0
; SKX-NEXT: vpmovm2b %k0, %zmm0		; SKX-NEXT: vpmovm2b %k0, %zmm0
; SKX-NEXT: retq		; SKX-NEXT: retq
;		;
; AVX512BW-LABEL: test17:		; AVX512BW-LABEL: test17:
; AVX512BW: ## BB#0:		; AVX512BW: ## BB#0:
; AVX512BW-NEXT: kmovq %rdi, %k0		; AVX512BW-NEXT: kmovq %rdi, %k0
; AVX512BW-NEXT: cmpl %edx, %esi		; AVX512BW-NEXT: cmpl %edx, %esi
; AVX512BW-NEXT: setg %al		; AVX512BW-NEXT: setg %al
; AVX512BW-NEXT: andl $1, %eax		; AVX512BW-NEXT: kmovw %eax, %k1
; AVX512BW-NEXT: kmovd %eax, %k1
; AVX512BW-NEXT: vpmovm2b %k1, %zmm0		; AVX512BW-NEXT: vpmovm2b %k1, %zmm0
; AVX512BW-NEXT: vpsllq $40, %xmm0, %xmm0		; AVX512BW-NEXT: vpsllq $40, %xmm0, %xmm0
; AVX512BW-NEXT: vpmovm2b %k0, %zmm1		; AVX512BW-NEXT: vpmovm2b %k0, %zmm1
; AVX512BW-NEXT: vmovdqa {{.*#+}} ymm2 = [255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]		; AVX512BW-NEXT: vmovdqa {{.*#+}} ymm2 = [255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512BW-NEXT: vpblendvb %ymm2, %ymm1, %ymm0, %ymm0		; AVX512BW-NEXT: vpblendvb %ymm2, %ymm1, %ymm0, %ymm0
; AVX512BW-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm0[0,1,2,3],zmm1[4,5,6,7]		; AVX512BW-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm0[0,1,2,3],zmm1[4,5,6,7]
; AVX512BW-NEXT: vpmovb2m %zmm0, %k0		; AVX512BW-NEXT: vpmovb2m %zmm0, %k0
; AVX512BW-NEXT: vpmovm2b %k0, %zmm0		; AVX512BW-NEXT: vpmovm2b %k0, %zmm0
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines	; AVX512DQ-NEXT: retq
%d = sext <64 x i1>%c to <64 x i8>		%d = sext <64 x i1>%c to <64 x i8>
ret <64 x i8>%d		ret <64 x i8>%d
}		}

define <8 x i1> @test18(i8 %a, i16 %y) {		define <8 x i1> @test18(i8 %a, i16 %y) {
; KNL-LABEL: test18:		; KNL-LABEL: test18:
; KNL: ## BB#0:		; KNL: ## BB#0:
; KNL-NEXT: kmovw %edi, %k1		; KNL-NEXT: kmovw %edi, %k1
; KNL-NEXT: kmovw %esi, %k2		; KNL-NEXT: kmovw %esi, %k0
; KNL-NEXT: kshiftlw $7, %k2, %k0		; KNL-NEXT: kshiftlw $7, %k0, %k2
; KNL-NEXT: kshiftrw $15, %k0, %k0
; KNL-NEXT: kshiftlw $6, %k2, %k2
; KNL-NEXT: kshiftrw $15, %k2, %k2		; KNL-NEXT: kshiftrw $15, %k2, %k2
		; KNL-NEXT: kshiftlw $6, %k0, %k0
		; KNL-NEXT: kshiftrw $15, %k0, %k3
; KNL-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}		; KNL-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; KNL-NEXT: vpternlogq $255, %zmm1, %zmm1, %zmm1 {%k2} {z}		; KNL-NEXT: vpternlogq $255, %zmm1, %zmm1, %zmm1 {%k3} {z}
; KNL-NEXT: vmovdqa64 {{.*#+}} zmm2 = [0,1,2,3,4,5,8,7]		; KNL-NEXT: vmovdqa64 {{.*#+}} zmm2 = [0,1,2,3,4,5,8,7]
; KNL-NEXT: vpermi2q %zmm1, %zmm0, %zmm2		; KNL-NEXT: vpermi2q %zmm1, %zmm0, %zmm2
; KNL-NEXT: vpsllq $63, %zmm2, %zmm0		; KNL-NEXT: vpsllq $63, %zmm2, %zmm0
; KNL-NEXT: vptestmq %zmm0, %zmm0, %k1		; KNL-NEXT: vptestmq %zmm0, %zmm0, %k0
; KNL-NEXT: kshiftlw $1, %k1, %k1		; KNL-NEXT: kshiftlw $1, %k0, %k0
; KNL-NEXT: kshiftrw $1, %k1, %k1		; KNL-NEXT: kshiftrw $1, %k0, %k0
; KNL-NEXT: kshiftlw $7, %k0, %k0		; KNL-NEXT: kshiftlw $7, %k2, %k1
; KNL-NEXT: korw %k0, %k1, %k1		; KNL-NEXT: korw %k1, %k0, %k1
; KNL-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}		; KNL-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; KNL-NEXT: vpmovqw %zmm0, %xmm0		; KNL-NEXT: vpmovqw %zmm0, %xmm0
; KNL-NEXT: retq		; KNL-NEXT: retq
;		;
; SKX-LABEL: test18:		; SKX-LABEL: test18:
; SKX: ## BB#0:		; SKX: ## BB#0:
; SKX-NEXT: kmovd %edi, %k0		; SKX-NEXT: kmovd %edi, %k0
; SKX-NEXT: kmovd %esi, %k1		; SKX-NEXT: kmovd %esi, %k1
Show All 12 Lines
; SKX-NEXT: korb %k1, %k0, %k0		; SKX-NEXT: korb %k1, %k0, %k0
; SKX-NEXT: vpmovm2w %k0, %xmm0		; SKX-NEXT: vpmovm2w %k0, %xmm0
; SKX-NEXT: vzeroupper		; SKX-NEXT: vzeroupper
; SKX-NEXT: retq		; SKX-NEXT: retq
;		;
; AVX512BW-LABEL: test18:		; AVX512BW-LABEL: test18:
; AVX512BW: ## BB#0:		; AVX512BW: ## BB#0:
; AVX512BW-NEXT: kmovd %edi, %k1		; AVX512BW-NEXT: kmovd %edi, %k1
; AVX512BW-NEXT: kmovd %esi, %k2		; AVX512BW-NEXT: kmovd %esi, %k0
; AVX512BW-NEXT: kshiftlw $7, %k2, %k0		; AVX512BW-NEXT: kshiftlw $7, %k0, %k2
; AVX512BW-NEXT: kshiftrw $15, %k0, %k0
; AVX512BW-NEXT: kshiftlw $6, %k2, %k2
; AVX512BW-NEXT: kshiftrw $15, %k2, %k2		; AVX512BW-NEXT: kshiftrw $15, %k2, %k2
		; AVX512BW-NEXT: kshiftlw $6, %k0, %k0
		; AVX512BW-NEXT: kshiftrw $15, %k0, %k3
; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}		; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512BW-NEXT: vpternlogq $255, %zmm1, %zmm1, %zmm1 {%k2} {z}		; AVX512BW-NEXT: vpternlogq $255, %zmm1, %zmm1, %zmm1 {%k3} {z}
; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm2 = [0,1,2,3,4,5,8,7]		; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm2 = [0,1,2,3,4,5,8,7]
; AVX512BW-NEXT: vpermi2q %zmm1, %zmm0, %zmm2		; AVX512BW-NEXT: vpermi2q %zmm1, %zmm0, %zmm2
; AVX512BW-NEXT: vpsllq $63, %zmm2, %zmm0		; AVX512BW-NEXT: vpsllq $63, %zmm2, %zmm0
; AVX512BW-NEXT: vptestmq %zmm0, %zmm0, %k1		; AVX512BW-NEXT: vptestmq %zmm0, %zmm0, %k0
; AVX512BW-NEXT: kshiftlw $1, %k1, %k1		; AVX512BW-NEXT: kshiftlw $1, %k0, %k0
; AVX512BW-NEXT: kshiftrw $1, %k1, %k1		; AVX512BW-NEXT: kshiftrw $1, %k0, %k0
; AVX512BW-NEXT: kshiftlw $7, %k0, %k0		; AVX512BW-NEXT: kshiftlw $7, %k2, %k1
; AVX512BW-NEXT: korw %k0, %k1, %k0		; AVX512BW-NEXT: korw %k1, %k0, %k0
; AVX512BW-NEXT: vpmovm2w %k0, %zmm0		; AVX512BW-NEXT: vpmovm2w %k0, %zmm0
; AVX512BW-NEXT: ## kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>		; AVX512BW-NEXT: ## kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
; AVX512BW-NEXT: vzeroupper		; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq		; AVX512BW-NEXT: retq
;		;
; AVX512DQ-LABEL: test18:		; AVX512DQ-LABEL: test18:
; AVX512DQ: ## BB#0:		; AVX512DQ: ## BB#0:
; AVX512DQ-NEXT: kmovw %edi, %k0		; AVX512DQ-NEXT: kmovw %edi, %k0
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; AVX512DQ-NEXT: retq		; AVX512DQ-NEXT: retq
store <2 x i1> %a, <2 x i1>* %addr		store <2 x i1> %a, <2 x i1>* %addr
ret void		ret void
}		}

define void @store_v1i1(<1 x i1> %c , <1 x i1>* %ptr) {		define void @store_v1i1(<1 x i1> %c , <1 x i1>* %ptr) {
; KNL-LABEL: store_v1i1:		; KNL-LABEL: store_v1i1:
; KNL: ## BB#0:		; KNL: ## BB#0:
; KNL-NEXT: andl $1, %edi
; KNL-NEXT: kmovw %edi, %k0		; KNL-NEXT: kmovw %edi, %k0
; KNL-NEXT: kxnorw %k0, %k0, %k1		; KNL-NEXT: kxnorw %k0, %k0, %k1
; KNL-NEXT: kshiftrw $15, %k1, %k1
; KNL-NEXT: kxorw %k1, %k0, %k0		; KNL-NEXT: kxorw %k1, %k0, %k0
; KNL-NEXT: kmovw %k0, %eax		; KNL-NEXT: kmovw %k0, %eax
; KNL-NEXT: movb %al, (%rsi)		; KNL-NEXT: movb %al, (%rsi)
; KNL-NEXT: retq		; KNL-NEXT: retq
;		;
; SKX-LABEL: store_v1i1:		; SKX-LABEL: store_v1i1:
; SKX: ## BB#0:		; SKX: ## BB#0:
; SKX-NEXT: andl $1, %edi
; SKX-NEXT: kmovd %edi, %k0		; SKX-NEXT: kmovd %edi, %k0
; SKX-NEXT: kxnorw %k0, %k0, %k1		; SKX-NEXT: kxnorw %k0, %k0, %k1
; SKX-NEXT: kshiftrw $15, %k1, %k1
; SKX-NEXT: kxorw %k1, %k0, %k0		; SKX-NEXT: kxorw %k1, %k0, %k0
; SKX-NEXT: kmovb %k0, (%rsi)		; SKX-NEXT: kmovb %k0, (%rsi)
; SKX-NEXT: retq		; SKX-NEXT: retq
;		;
; AVX512BW-LABEL: store_v1i1:		; AVX512BW-LABEL: store_v1i1:
; AVX512BW: ## BB#0:		; AVX512BW: ## BB#0:
; AVX512BW-NEXT: andl $1, %edi
; AVX512BW-NEXT: kmovd %edi, %k0		; AVX512BW-NEXT: kmovd %edi, %k0
; AVX512BW-NEXT: kxnorw %k0, %k0, %k1		; AVX512BW-NEXT: kxnorw %k0, %k0, %k1
; AVX512BW-NEXT: kshiftrw $15, %k1, %k1
; AVX512BW-NEXT: kxorw %k1, %k0, %k0		; AVX512BW-NEXT: kxorw %k1, %k0, %k0
; AVX512BW-NEXT: kmovd %k0, %eax		; AVX512BW-NEXT: kmovd %k0, %eax
; AVX512BW-NEXT: movb %al, (%rsi)		; AVX512BW-NEXT: movb %al, (%rsi)
; AVX512BW-NEXT: retq		; AVX512BW-NEXT: retq
;		;
; AVX512DQ-LABEL: store_v1i1:		; AVX512DQ-LABEL: store_v1i1:
; AVX512DQ: ## BB#0:		; AVX512DQ: ## BB#0:
; AVX512DQ-NEXT: andl $1, %edi
; AVX512DQ-NEXT: kmovw %edi, %k0		; AVX512DQ-NEXT: kmovw %edi, %k0
; AVX512DQ-NEXT: kxnorw %k0, %k0, %k1		; AVX512DQ-NEXT: kxnorw %k0, %k0, %k1
; AVX512DQ-NEXT: kshiftrw $15, %k1, %k1
; AVX512DQ-NEXT: kxorw %k1, %k0, %k0		; AVX512DQ-NEXT: kxorw %k1, %k0, %k0
; AVX512DQ-NEXT: kmovb %k0, (%rsi)		; AVX512DQ-NEXT: kmovb %k0, (%rsi)
; AVX512DQ-NEXT: retq		; AVX512DQ-NEXT: retq
%x = xor <1 x i1> %c, <i1 1>		%x = xor <1 x i1> %c, <i1 1>
store <1 x i1> %x, <1 x i1>* %ptr, align 4		store <1 x i1> %x, <1 x i1>* %ptr, align 4
ret void		ret void
}		}

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; else		; else
; v = 0;		; v = 0;
; f2(v);		; f2(v);
;}		;}

@f1.v = internal unnamed_addr global i1 false, align 4		@f1.v = internal unnamed_addr global i1 false, align 4

define void @f1(i32 %c) {		define void @f1(i32 %c) {
; KNL-LABEL: f1:		; CHECK-LABEL: f1:
; KNL: ## BB#0: ## %entry		; CHECK: ## BB#0: ## %entry
; KNL-NEXT: movzbl {{.*}}(%rip), %edi		; CHECK-NEXT: movzbl {{.*}}(%rip), %edi
; KNL-NEXT: movl %edi, %eax		; CHECK-NEXT: movl %edi, %eax
; KNL-NEXT: andl $1, %eax		; CHECK-NEXT: xorb $1, %al
; KNL-NEXT: kmovw %eax, %k0		; CHECK-NEXT: movb %al, {{.*}}(%rip)
; KNL-NEXT: kxnorw %k0, %k0, %k1		; CHECK-NEXT: xorl $1, %edi
; KNL-NEXT: kshiftrw $15, %k1, %k1		; CHECK-NEXT: jmp _f2 ## TAILCALL
; KNL-NEXT: kxorw %k1, %k0, %k0
; KNL-NEXT: kmovw %k0, %eax
; KNL-NEXT: movb %al, {{.*}}(%rip)
; KNL-NEXT: xorl $1, %edi
; KNL-NEXT: jmp _f2 ## TAILCALL
;
; SKX-LABEL: f1:
; SKX: ## BB#0: ## %entry
; SKX-NEXT: movzbl {{.*}}(%rip), %edi
; SKX-NEXT: movl %edi, %eax
; SKX-NEXT: andl $1, %eax
; SKX-NEXT: kmovd %eax, %k0
; SKX-NEXT: kxnorw %k0, %k0, %k1
; SKX-NEXT: kshiftrw $15, %k1, %k1
; SKX-NEXT: kxorw %k1, %k0, %k0
; SKX-NEXT: kmovb %k0, {{.*}}(%rip)
; SKX-NEXT: xorl $1, %edi
; SKX-NEXT: jmp _f2 ## TAILCALL
;
; AVX512BW-LABEL: f1:
; AVX512BW: ## BB#0: ## %entry
; AVX512BW-NEXT: movzbl {{.*}}(%rip), %edi
; AVX512BW-NEXT: movl %edi, %eax
; AVX512BW-NEXT: andl $1, %eax
; AVX512BW-NEXT: kmovd %eax, %k0
; AVX512BW-NEXT: kxnorw %k0, %k0, %k1
; AVX512BW-NEXT: kshiftrw $15, %k1, %k1
; AVX512BW-NEXT: kxorw %k1, %k0, %k0
; AVX512BW-NEXT: kmovd %k0, %eax
; AVX512BW-NEXT: movb %al, {{.*}}(%rip)
; AVX512BW-NEXT: xorl $1, %edi
; AVX512BW-NEXT: jmp _f2 ## TAILCALL
;
; AVX512DQ-LABEL: f1:
; AVX512DQ: ## BB#0: ## %entry
; AVX512DQ-NEXT: movzbl {{.*}}(%rip), %edi
; AVX512DQ-NEXT: movl %edi, %eax
; AVX512DQ-NEXT: andl $1, %eax
; AVX512DQ-NEXT: kmovw %eax, %k0
; AVX512DQ-NEXT: kxnorw %k0, %k0, %k1
; AVX512DQ-NEXT: kshiftrw $15, %k1, %k1
; AVX512DQ-NEXT: kxorw %k1, %k0, %k0
; AVX512DQ-NEXT: kmovb %k0, {{.*}}(%rip)
; AVX512DQ-NEXT: xorl $1, %edi
; AVX512DQ-NEXT: jmp _f2 ## TAILCALL
entry:		entry:
%.b1 = load i1, i1* @f1.v, align 4		%.b1 = load i1, i1* @f1.v, align 4
%not..b1 = xor i1 %.b1, true		%not..b1 = xor i1 %.b1, true
store i1 %not..b1, i1* @f1.v, align 4		store i1 %not..b1, i1* @f1.v, align 4
%0 = zext i1 %not..b1 to i32		%0 = zext i1 %not..b1 to i32
tail call void @f2(i32 %0) #2		tail call void @f2(i32 %0) #2
ret void		ret void
}		}
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test/CodeGen/X86/avx512-memfold.ll

	; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py			; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
	; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mcpu=knl \| FileCheck %s			; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mcpu=knl \| FileCheck %s

	define i8 @test_int_x86_avx512_mask_cmp_ss(<4 x float> %a, float* %b, i8 %mask) {			define i8 @test_int_x86_avx512_mask_cmp_ss(<4 x float> %a, float* %b, i8 %mask) {
	; CHECK-LABEL: test_int_x86_avx512_mask_cmp_ss:			; CHECK-LABEL: test_int_x86_avx512_mask_cmp_ss:
	; CHECK: ## BB#0:			; CHECK: ## BB#0:
	; CHECK-NEXT: andl $1, %esi
	; CHECK-NEXT: kmovw %esi, %k1			; CHECK-NEXT: kmovw %esi, %k1
	; CHECK-NEXT: vcmpunordss (%rdi), %xmm0, %k0 {%k1}			; CHECK-NEXT: vcmpunordss (%rdi), %xmm0, %k0 {%k1}
	; CHECK-NEXT: kmovw %k0, %eax			; CHECK-NEXT: kmovw %k0, %eax
	; CHECK-NEXT: andl $1, %eax
	; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
	; CHECK-NEXT: retq			; CHECK-NEXT: retq
	%b.val = load float, float* %b			%b.val = load float, float* %b
	%bv0 = insertelement <4 x float> undef, float %b.val, i32 0			%bv0 = insertelement <4 x float> undef, float %b.val, i32 0
	%bv1 = insertelement <4 x float> %bv0, float 0.000000e+00, i32 1			%bv1 = insertelement <4 x float> %bv0, float 0.000000e+00, i32 1
	%bv2 = insertelement <4 x float> %bv1, float 0.000000e+00, i32 2			%bv2 = insertelement <4 x float> %bv1, float 0.000000e+00, i32 2
	%bv = insertelement <4 x float> %bv2, float 0.000000e+00, i32 3			%bv = insertelement <4 x float> %bv2, float 0.000000e+00, i32 3
	%res2 = call i8 @llvm.x86.avx512.mask.cmp.ss(<4 x float> %a, <4 x float> %bv, i32 3, i8 %mask, i32 4)			%res2 = call i8 @llvm.x86.avx512.mask.cmp.ss(<4 x float> %a, <4 x float> %bv, i32 3, i8 %mask, i32 4)
	ret i8 %res2			ret i8 %res2
	}			}
	declare i8 @llvm.x86.avx512.mask.cmp.ss(<4 x float>, <4 x float>, i32, i8, i32)			declare i8 @llvm.x86.avx512.mask.cmp.ss(<4 x float>, <4 x float>, i32, i8, i32)

	define <4 x float> @test_mask_max_ss(<4 x float> %a, float* %b, i8 %mask) {			define <4 x float> @test_mask_max_ss(<4 x float> %a, float* %b, i8 %mask) {
	; CHECK-LABEL: test_mask_max_ss:			; CHECK-LABEL: test_mask_max_ss:
	; CHECK: ## BB#0:			; CHECK: ## BB#0:
	; CHECK-NEXT: andl $1, %esi
	; CHECK-NEXT: kmovw %esi, %k1			; CHECK-NEXT: kmovw %esi, %k1
	; CHECK-NEXT: vmaxss (%rdi), %xmm0, %xmm0 {%k1} {z}			; CHECK-NEXT: vmaxss (%rdi), %xmm0, %xmm0 {%k1} {z}
	; CHECK-NEXT: retq			; CHECK-NEXT: retq
	%b.val = load float, float* %b			%b.val = load float, float* %b
	%bv0 = insertelement <4 x float> undef, float %b.val, i32 0			%bv0 = insertelement <4 x float> undef, float %b.val, i32 0
	%bv1 = insertelement <4 x float> %bv0, float 0.000000e+00, i32 1			%bv1 = insertelement <4 x float> %bv0, float 0.000000e+00, i32 1
	%bv2 = insertelement <4 x float> %bv1, float 0.000000e+00, i32 2			%bv2 = insertelement <4 x float> %bv1, float 0.000000e+00, i32 2
	%bv = insertelement <4 x float> %bv2, float 0.000000e+00, i32 3			%bv = insertelement <4 x float> %bv2, float 0.000000e+00, i32 3
	%res = call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>%a, <4 x float> %bv, <4 x float> zeroinitializer, i8 %mask, i32 4)			%res = call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>%a, <4 x float> %bv, <4 x float> zeroinitializer, i8 %mask, i32 4)
	ret <4 x float> %res			ret <4 x float> %res
	}			}
	declare <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>, <4 x float>, <4 x float>, i8, i32) nounwind readnone			declare <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>, <4 x float>, <4 x float>, i8, i32) nounwind readnone

	define <4 x float> @test_maskz_add_ss(<4 x float> %a, float* %b, i8 %mask) {			define <4 x float> @test_maskz_add_ss(<4 x float> %a, float* %b, i8 %mask) {
	; CHECK-LABEL: test_maskz_add_ss:			; CHECK-LABEL: test_maskz_add_ss:
	; CHECK: ## BB#0:			; CHECK: ## BB#0:
	; CHECK-NEXT: andl $1, %esi
	; CHECK-NEXT: kmovw %esi, %k1			; CHECK-NEXT: kmovw %esi, %k1
	; CHECK-NEXT: vaddss (%rdi), %xmm0, %xmm0 {%k1} {z}			; CHECK-NEXT: vaddss (%rdi), %xmm0, %xmm0 {%k1} {z}
	; CHECK-NEXT: retq			; CHECK-NEXT: retq
	%b.val = load float, float* %b			%b.val = load float, float* %b
	%bv0 = insertelement <4 x float> undef, float %b.val, i32 0			%bv0 = insertelement <4 x float> undef, float %b.val, i32 0
	%bv1 = insertelement <4 x float> %bv0, float 0.000000e+00, i32 1			%bv1 = insertelement <4 x float> %bv0, float 0.000000e+00, i32 1
	%bv2 = insertelement <4 x float> %bv1, float 0.000000e+00, i32 2			%bv2 = insertelement <4 x float> %bv1, float 0.000000e+00, i32 2
	%bv = insertelement <4 x float> %bv2, float 0.000000e+00, i32 3			%bv = insertelement <4 x float> %bv2, float 0.000000e+00, i32 3
	%res = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>%a, <4 x float> %bv, <4 x float> zeroinitializer, i8 %mask, i32 4)			%res = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>%a, <4 x float> %bv, <4 x float> zeroinitializer, i8 %mask, i32 4)
	ret <4 x float> %res			ret <4 x float> %res
	}			}

	declare <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>, <4 x float>, <4 x float>, i8, i32) nounwind readnone			declare <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>, <4 x float>, <4 x float>, i8, i32) nounwind readnone

	declare <2 x double> @llvm.x86.avx512.mask.vfmadd.sd(<2 x double>, <2 x double>, <2 x double>, i8, i32)			declare <2 x double> @llvm.x86.avx512.mask.vfmadd.sd(<2 x double>, <2 x double>, <2 x double>, i8, i32)

	define <2 x double> @test_int_x86_avx512_mask_vfmadd_sd(<2 x double> %a, <2 x double> %b, double* %c, i8 %mask){			define <2 x double> @test_int_x86_avx512_mask_vfmadd_sd(<2 x double> %a, <2 x double> %b, double* %c, i8 %mask){
	; CHECK-LABEL: test_int_x86_avx512_mask_vfmadd_sd:			; CHECK-LABEL: test_int_x86_avx512_mask_vfmadd_sd:
	; CHECK: ## BB#0:			; CHECK: ## BB#0:
	; CHECK-NEXT: andl $1, %esi
	; CHECK-NEXT: kmovw %esi, %k1			; CHECK-NEXT: kmovw %esi, %k1
	; CHECK-NEXT: vfmadd213sd (%rdi), %xmm1, %xmm0 {%k1}			; CHECK-NEXT: vfmadd213sd (%rdi), %xmm1, %xmm0 {%k1}
	; CHECK-NEXT: retq			; CHECK-NEXT: retq
	%c.val = load double, double* %c			%c.val = load double, double* %c
	%cv0 = insertelement <2 x double> undef, double %c.val, i32 0			%cv0 = insertelement <2 x double> undef, double %c.val, i32 0
	%cv = insertelement <2 x double> %cv0, double 0.000000e+00, i32 1			%cv = insertelement <2 x double> %cv0, double 0.000000e+00, i32 1
	%res = call <2 x double> @llvm.x86.avx512.mask.vfmadd.sd(<2 x double> %a, <2 x double> %b, <2 x double> %cv, i8 %mask, i32 4)			%res = call <2 x double> @llvm.x86.avx512.mask.vfmadd.sd(<2 x double> %a, <2 x double> %b, <2 x double> %cv, i8 %mask, i32 4)
	ret <2 x double> %res			ret <2 x double> %res
	}			}

test/CodeGen/X86/avx512-regcall-NoMask.ll

	; RUN: llc < %s -mtriple=i386-pc-win32 -mattr=+avx512f -mattr=+avx512vl -mattr=+avx512bw -mattr=+avx512dq \| FileCheck --check-prefix=X32 %s			; RUN: llc < %s -mtriple=i386-pc-win32 -mattr=+avx512f -mattr=+avx512vl -mattr=+avx512bw -mattr=+avx512dq \| FileCheck --check-prefix=ALL --check-prefix=X32 %s
	; RUN: llc < %s -mtriple=x86_64-win32 -mattr=+avx512f -mattr=+avx512vl -mattr=+avx512bw -mattr=+avx512dq \| FileCheck --check-prefix=WIN64 %s			; RUN: llc < %s -mtriple=x86_64-win32 -mattr=+avx512f -mattr=+avx512vl -mattr=+avx512bw -mattr=+avx512dq \| FileCheck --check-prefix=ALL --check-prefix=WIN64 %s
	; RUN: llc < %s -mtriple=x86_64-linux-gnu -mattr=+avx512f -mattr=+avx512vl -mattr=+avx512bw -mattr=+avx512dq \| FileCheck --check-prefix=LINUXOSX64 %s			; RUN: llc < %s -mtriple=x86_64-linux-gnu -mattr=+avx512f -mattr=+avx512vl -mattr=+avx512bw -mattr=+avx512dq \| FileCheck --check-prefix=LINUXOSX64 %s

	; X32-LABEL: test_argReti1:			; ALL-LABEL: test_argReti1:
	; X32: kmov{{.*}} %eax, %k{{[0-7]}}			; ALL: incb %al
	; X32: kmov{{.*}} %k{{[0-7]}}, %eax			; ALL: ret{{.*}}
	; X32: ret{{.*}}

	; WIN64-LABEL: test_argReti1:
	; WIN64: kmov{{.*}} %eax, %k{{[0-7]}}
	; WIN64: kmov{{.*}} %k{{[0-7]}}, %eax
	; WIN64: ret{{.*}}

	; Test regcall when receiving/returning i1			; Test regcall when receiving/returning i1
	define x86_regcallcc i1 @test_argReti1(i1 %a) {			define x86_regcallcc i1 @test_argReti1(i1 %a) {
	%add = add i1 %a, 1			%add = add i1 %a, 1
	ret i1 %add			ret i1 %add
	}			}

	; X32-LABEL: test_CallargReti1:			; ALL-LABEL: test_CallargReti1:
	; X32: kmov{{.*}} %k{{[0-7]}}, %eax			; ALL: movzbl %al, %eax
	; X32: call{{.}} {{.}}test_argReti1			; ALL: call{{.*}}test_argReti1
	; X32: kmov{{.*}} %eax, %k{{[0-7]}}			; ALL: incb %al
	; X32: ret{{.*}}			; ALL: ret{{.*}}

	; WIN64-LABEL: test_CallargReti1:
	; WIN64: kmov{{.*}} %k{{[0-7]}}, %eax
	; WIN64: call{{.}} {{.}}test_argReti1
	; WIN64: kmov{{.*}} %eax, %k{{[0-7]}}
	; WIN64: ret{{.*}}

	; Test regcall when passing/retrieving i1			; Test regcall when passing/retrieving i1
	define x86_regcallcc i1 @test_CallargReti1(i1 %a) {			define x86_regcallcc i1 @test_CallargReti1(i1 %a) {
	%b = add i1 %a, 1			%b = add i1 %a, 1
	%c = call x86_regcallcc i1 @test_argReti1(i1 %b)			%c = call x86_regcallcc i1 @test_argReti1(i1 %b)
	%d = add i1 %c, 1			%d = add i1 %c, 1
	ret i1 %d			ret i1 %d
	}			}
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test/CodeGen/X86/avx512-select.ll

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	; CHECK-NEXT: retq			; CHECK-NEXT: retq
	%v = select i1 undef , i64 1, i64 2			%v = select i1 undef , i64 1, i64 2
	ret i64 %v			ret i64 %v
	}			}

	define double @pr30561_f64(double %b, double %a, i1 %c) {			define double @pr30561_f64(double %b, double %a, i1 %c) {
	; CHECK-LABEL: pr30561_f64:			; CHECK-LABEL: pr30561_f64:
	; CHECK: ## BB#0:			; CHECK: ## BB#0:
	; CHECK-NEXT: andl $1, %edi			; CHECK-NEXT: andb $1, %dil
	; CHECK-NEXT: kmovw %edi, %k1			; CHECK-NEXT: kmovw %edi, %k1
	; CHECK-NEXT: vmovsd %xmm1, %xmm0, %xmm0 {%k1}			; CHECK-NEXT: vmovsd %xmm1, %xmm0, %xmm0 {%k1}
	; CHECK-NEXT: retq			; CHECK-NEXT: retq
	%cond = select i1 %c, double %a, double %b			%cond = select i1 %c, double %a, double %b
	ret double %cond			ret double %cond
	}			}

	define float @pr30561_f32(float %b, float %a, i1 %c) {			define float @pr30561_f32(float %b, float %a, i1 %c) {
	; CHECK-LABEL: pr30561_f32:			; CHECK-LABEL: pr30561_f32:
	; CHECK: ## BB#0:			; CHECK: ## BB#0:
	; CHECK-NEXT: andl $1, %edi			; CHECK-NEXT: andb $1, %dil
	; CHECK-NEXT: kmovw %edi, %k1			; CHECK-NEXT: kmovw %edi, %k1
	; CHECK-NEXT: vmovss %xmm1, %xmm0, %xmm0 {%k1}			; CHECK-NEXT: vmovss %xmm1, %xmm0, %xmm0 {%k1}
	; CHECK-NEXT: retq			; CHECK-NEXT: retq
	%cond = select i1 %c, float %a, float %b			%cond = select i1 %c, float %a, float %b
	ret float %cond			ret float %cond
	}			}

	define <16 x i16> @pr31515(<16 x i1> %a, <16 x i1> %b, <16 x i16> %c) nounwind {			define <16 x i16> @pr31515(<16 x i1> %a, <16 x i1> %b, <16 x i16> %c) nounwind {
	Show All 17 Lines

test/CodeGen/X86/avx512dq-intrinsics-upgrade.ll

	; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py			; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
	; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl -mattr=+avx512dq \| FileCheck %s			; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl -mattr=+avx512dq \| FileCheck %s

	declare <2 x double> @llvm.x86.avx512.mask.vextractf64x2.512(<8 x double>, i32, <2 x double>, i8)			declare <2 x double> @llvm.x86.avx512.mask.vextractf64x2.512(<8 x double>, i32, <2 x double>, i8)

	define <2 x double>@test_int_x86_avx512_mask_vextractf64x2_512(<8 x double> %x0, <2 x double> %x2, i8 %x3) {			define <2 x double>@test_int_x86_avx512_mask_vextractf64x2_512(<8 x double> %x0, <2 x double> %x2, i8 %x3) {
	; CHECK-LABEL: test_int_x86_avx512_mask_vextractf64x2_512:			; CHECK-LABEL: test_int_x86_avx512_mask_vextractf64x2_512:
	; CHECK: ## BB#0:			; CHECK: ## BB#0:
	; CHECK-NEXT: vextractf64x2 $1, %zmm0, %xmm0			; CHECK-NEXT: vextractf64x2 $1, %zmm0, %xmm0
	; CHECK-NEXT: kmovw %edi, %k0			; CHECK-NEXT: kmovw %edi, %k0
	; CHECK-NEXT: kshiftlb $7, %k0, %k1			; CHECK-NEXT: kshiftlb $7, %k0, %k1
	; CHECK-NEXT: kshiftrb $7, %k1, %k1			; CHECK-NEXT: kshiftrb $7, %k1, %k1
	; CHECK-NEXT: kshiftlb $6, %k0, %k0			; CHECK-NEXT: kshiftlb $6, %k0, %k0
	; CHECK-NEXT: kshiftrb $7, %k0, %k0			; CHECK-NEXT: kshiftrb $7, %k0, %k0
	; CHECK-NEXT: kmovw %k0, %eax			; CHECK-NEXT: kmovw %k0, %eax
	; CHECK-NEXT: vmovq %rax, %xmm2			; CHECK-NEXT: kmovw %k1, %ecx
	; CHECK-NEXT: kmovw %k1, %eax			; CHECK-NEXT: vmovd %ecx, %xmm2
	; CHECK-NEXT: vmovq %rax, %xmm3			; CHECK-NEXT: vpinsrb $8, %eax, %xmm2, %xmm2
	; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm3[0],xmm2[0]
	; CHECK-NEXT: vpsllq $63, %xmm2, %xmm2			; CHECK-NEXT: vpsllq $63, %xmm2, %xmm2
	; CHECK-NEXT: vpsraq $63, %zmm2, %zmm2			; CHECK-NEXT: vpsraq $63, %zmm2, %zmm2
	; CHECK-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm1			; CHECK-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm1
	; CHECK-NEXT: vandpd %xmm0, %xmm2, %xmm2			; CHECK-NEXT: vandpd %xmm0, %xmm2, %xmm2
	; CHECK-NEXT: vaddpd %xmm0, %xmm1, %xmm0			; CHECK-NEXT: vaddpd %xmm0, %xmm1, %xmm0
	; CHECK-NEXT: vaddpd %xmm0, %xmm2, %xmm0			; CHECK-NEXT: vaddpd %xmm0, %xmm2, %xmm0
	; CHECK-NEXT: retq			; CHECK-NEXT: retq
	%res = call <2 x double> @llvm.x86.avx512.mask.vextractf64x2.512(<8 x double> %x0,i32 1, <2 x double> %x2, i8 %x3)			%res = call <2 x double> @llvm.x86.avx512.mask.vextractf64x2.512(<8 x double> %x0,i32 1, <2 x double> %x2, i8 %x3)
	▲ Show 20 Lines • Show All 131 Lines • Show Last 20 Lines

test/CodeGen/X86/avx512dq-intrinsics.ll

Show First 20 Lines • Show All 256 Lines • ▼ Show 20 Lines	; CHECK-NEXT: retq
ret <16 x float> %res2		ret <16 x float> %res2
}		}

declare <4 x float> @llvm.x86.avx512.mask.reduce.ss(<4 x float>, <4 x float>,<4 x float>, i8, i32, i32)		declare <4 x float> @llvm.x86.avx512.mask.reduce.ss(<4 x float>, <4 x float>,<4 x float>, i8, i32, i32)

define <4 x float>@test_int_x86_avx512_mask_reduce_ss(<4 x float> %x0, <4 x float> %x1, <4 x float> %x3, i8 %x4) {		define <4 x float>@test_int_x86_avx512_mask_reduce_ss(<4 x float> %x0, <4 x float> %x1, <4 x float> %x3, i8 %x4) {
; CHECK-LABEL: test_int_x86_avx512_mask_reduce_ss:		; CHECK-LABEL: test_int_x86_avx512_mask_reduce_ss:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %edi		; CHECK-NEXT: kmovb %edi, %k1
; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vreducess $4, %xmm1, %xmm0, %xmm2 {%k1}		; CHECK-NEXT: vreducess $4, %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vreducess $4, {sae}, %xmm1, %xmm0, %xmm0		; CHECK-NEXT: vreducess $4, {sae}, %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vaddps %xmm0, %xmm2, %xmm0		; CHECK-NEXT: vaddps %xmm0, %xmm2, %xmm0
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%res = call <4 x float> @llvm.x86.avx512.mask.reduce.ss(<4 x float> %x0, <4 x float> %x1, <4 x float> %x3, i8 %x4, i32 4, i32 4)		%res = call <4 x float> @llvm.x86.avx512.mask.reduce.ss(<4 x float> %x0, <4 x float> %x1, <4 x float> %x3, i8 %x4, i32 4, i32 4)
%res1 = call <4 x float> @llvm.x86.avx512.mask.reduce.ss(<4 x float> %x0, <4 x float> %x1, <4 x float> %x3, i8 -1, i32 4, i32 8)		%res1 = call <4 x float> @llvm.x86.avx512.mask.reduce.ss(<4 x float> %x0, <4 x float> %x1, <4 x float> %x3, i8 -1, i32 4, i32 8)
%res2 = fadd <4 x float> %res, %res1		%res2 = fadd <4 x float> %res, %res1
ret <4 x float> %res2		ret <4 x float> %res2
}		}

declare <4 x float> @llvm.x86.avx512.mask.range.ss(<4 x float>, <4 x float>,<4 x float>, i8, i32, i32)		declare <4 x float> @llvm.x86.avx512.mask.range.ss(<4 x float>, <4 x float>,<4 x float>, i8, i32, i32)

define <4 x float>@test_int_x86_avx512_mask_range_ss(<4 x float> %x0, <4 x float> %x1, <4 x float> %x3, i8 %x4) {		define <4 x float>@test_int_x86_avx512_mask_range_ss(<4 x float> %x0, <4 x float> %x1, <4 x float> %x3, i8 %x4) {
; CHECK-LABEL: test_int_x86_avx512_mask_range_ss:		; CHECK-LABEL: test_int_x86_avx512_mask_range_ss:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %edi		; CHECK-NEXT: kmovb %edi, %k1
; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vrangess $4, {sae}, %xmm1, %xmm0, %xmm2 {%k1}		; CHECK-NEXT: vrangess $4, {sae}, %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vrangess $4, {sae}, %xmm1, %xmm0, %xmm0		; CHECK-NEXT: vrangess $4, {sae}, %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vaddps %xmm0, %xmm2, %xmm0		; CHECK-NEXT: vaddps %xmm0, %xmm2, %xmm0
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%res = call <4 x float> @llvm.x86.avx512.mask.range.ss(<4 x float> %x0, <4 x float> %x1, <4 x float> %x3, i8 %x4, i32 4, i32 8)		%res = call <4 x float> @llvm.x86.avx512.mask.range.ss(<4 x float> %x0, <4 x float> %x1, <4 x float> %x3, i8 %x4, i32 4, i32 8)
%res1 = call <4 x float> @llvm.x86.avx512.mask.range.ss(<4 x float> %x0, <4 x float> %x1, <4 x float> %x3, i8 -1, i32 4, i32 8)		%res1 = call <4 x float> @llvm.x86.avx512.mask.range.ss(<4 x float> %x0, <4 x float> %x1, <4 x float> %x3, i8 -1, i32 4, i32 8)
%res2 = fadd <4 x float> %res, %res1		%res2 = fadd <4 x float> %res, %res1
ret <4 x float> %res2		ret <4 x float> %res2
}		}

declare <2 x double> @llvm.x86.avx512.mask.reduce.sd(<2 x double>, <2 x double>,<2 x double>, i8, i32, i32)		declare <2 x double> @llvm.x86.avx512.mask.reduce.sd(<2 x double>, <2 x double>,<2 x double>, i8, i32, i32)

define <2 x double>@test_int_x86_avx512_mask_reduce_sd(<2 x double> %x0, <2 x double> %x1, <2 x double> %x3, i8 %x4) {		define <2 x double>@test_int_x86_avx512_mask_reduce_sd(<2 x double> %x0, <2 x double> %x1, <2 x double> %x3, i8 %x4) {
; CHECK-LABEL: test_int_x86_avx512_mask_reduce_sd:		; CHECK-LABEL: test_int_x86_avx512_mask_reduce_sd:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %edi		; CHECK-NEXT: kmovb %edi, %k1
; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vreducesd $4, %xmm1, %xmm0, %xmm2 {%k1}		; CHECK-NEXT: vreducesd $4, %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vreducesd $4, {sae}, %xmm1, %xmm0, %xmm0		; CHECK-NEXT: vreducesd $4, {sae}, %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vaddpd %xmm0, %xmm2, %xmm0		; CHECK-NEXT: vaddpd %xmm0, %xmm2, %xmm0
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%res = call <2 x double> @llvm.x86.avx512.mask.reduce.sd(<2 x double> %x0, <2 x double> %x1, <2 x double> %x3, i8 %x4, i32 4, i32 4)		%res = call <2 x double> @llvm.x86.avx512.mask.reduce.sd(<2 x double> %x0, <2 x double> %x1, <2 x double> %x3, i8 %x4, i32 4, i32 4)
%res1 = call <2 x double> @llvm.x86.avx512.mask.reduce.sd(<2 x double> %x0, <2 x double> %x1, <2 x double> %x3, i8 -1, i32 4, i32 8)		%res1 = call <2 x double> @llvm.x86.avx512.mask.reduce.sd(<2 x double> %x0, <2 x double> %x1, <2 x double> %x3, i8 -1, i32 4, i32 8)
%res2 = fadd <2 x double> %res, %res1		%res2 = fadd <2 x double> %res, %res1
ret <2 x double> %res2		ret <2 x double> %res2
}		}

declare <2 x double> @llvm.x86.avx512.mask.range.sd(<2 x double>, <2 x double>,<2 x double>, i8, i32, i32)		declare <2 x double> @llvm.x86.avx512.mask.range.sd(<2 x double>, <2 x double>,<2 x double>, i8, i32, i32)

define <2 x double>@test_int_x86_avx512_mask_range_sd(<2 x double> %x0, <2 x double> %x1, <2 x double> %x3, i8 %x4) {		define <2 x double>@test_int_x86_avx512_mask_range_sd(<2 x double> %x0, <2 x double> %x1, <2 x double> %x3, i8 %x4) {
; CHECK-LABEL: test_int_x86_avx512_mask_range_sd:		; CHECK-LABEL: test_int_x86_avx512_mask_range_sd:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %edi		; CHECK-NEXT: kmovb %edi, %k1
; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vrangesd $4, %xmm1, %xmm0, %xmm2 {%k1}		; CHECK-NEXT: vrangesd $4, %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vrangesd $4, {sae}, %xmm1, %xmm0, %xmm0		; CHECK-NEXT: vrangesd $4, {sae}, %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vaddpd %xmm0, %xmm2, %xmm0		; CHECK-NEXT: vaddpd %xmm0, %xmm2, %xmm0
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%res = call <2 x double> @llvm.x86.avx512.mask.range.sd(<2 x double> %x0, <2 x double> %x1, <2 x double> %x3, i8 %x4, i32 4, i32 4)		%res = call <2 x double> @llvm.x86.avx512.mask.range.sd(<2 x double> %x0, <2 x double> %x1, <2 x double> %x3, i8 %x4, i32 4, i32 4)
%res1 = call <2 x double> @llvm.x86.avx512.mask.range.sd(<2 x double> %x0, <2 x double> %x1, <2 x double> %x3, i8 -1, i32 4, i32 8)		%res1 = call <2 x double> @llvm.x86.avx512.mask.range.sd(<2 x double> %x0, <2 x double> %x1, <2 x double> %x3, i8 -1, i32 4, i32 8)
%res2 = fadd <2 x double> %res, %res1		%res2 = fadd <2 x double> %res, %res1
ret <2 x double> %res2		ret <2 x double> %res2
Show All 36 Lines	; CHECK-NEXT: retq
ret i16 %res2		ret i16 %res2
}		}

declare i8 @llvm.x86.avx512.mask.fpclass.sd(<2 x double>, i32, i8)		declare i8 @llvm.x86.avx512.mask.fpclass.sd(<2 x double>, i32, i8)

define i8 @test_int_x86_avx512_mask_fpclass_sd(<2 x double> %x0, i8 %x1) {		define i8 @test_int_x86_avx512_mask_fpclass_sd(<2 x double> %x0, i8 %x1) {
; CHECK-LABEL: test_int_x86_avx512_mask_fpclass_sd:		; CHECK-LABEL: test_int_x86_avx512_mask_fpclass_sd:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %edi		; CHECK-NEXT: kmovb %edi, %k1
; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vfpclasssd $2, %xmm0, %k0 {%k1}		; CHECK-NEXT: vfpclasssd $2, %xmm0, %k0 {%k1}
; CHECK-NEXT: kmovw %k0, %ecx		; CHECK-NEXT: kmovb %k0, %ecx
; CHECK-NEXT: andl $1, %ecx
; CHECK-NEXT: vfpclasssd $4, %xmm0, %k0		; CHECK-NEXT: vfpclasssd $4, %xmm0, %k0
; CHECK-NEXT: kmovw %k0, %eax		; CHECK-NEXT: kmovb %k0, %eax
; CHECK-NEXT: andl $1, %eax
; CHECK-NEXT: addb %cl, %al		; CHECK-NEXT: addb %cl, %al
; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%res = call i8 @llvm.x86.avx512.mask.fpclass.sd(<2 x double> %x0, i32 2, i8 %x1)		%res = call i8 @llvm.x86.avx512.mask.fpclass.sd(<2 x double> %x0, i32 2, i8 %x1)
%res1 = call i8 @llvm.x86.avx512.mask.fpclass.sd(<2 x double> %x0, i32 4, i8 -1)		%res1 = call i8 @llvm.x86.avx512.mask.fpclass.sd(<2 x double> %x0, i32 4, i8 -1)
%res2 = add i8 %res, %res1		%res2 = add i8 %res, %res1
ret i8 %res2		ret i8 %res2
}		}

declare i8 @llvm.x86.avx512.mask.fpclass.ss(<4 x float>, i32, i8)		declare i8 @llvm.x86.avx512.mask.fpclass.ss(<4 x float>, i32, i8)

define i8 @test_int_x86_avx512_mask_fpclass_ss(<4 x float> %x0, i8 %x1) {		define i8 @test_int_x86_avx512_mask_fpclass_ss(<4 x float> %x0, i8 %x1) {
; CHECK-LABEL: test_int_x86_avx512_mask_fpclass_ss:		; CHECK-LABEL: test_int_x86_avx512_mask_fpclass_ss:
; CHECK: ## BB#0:		; CHECK: ## BB#0:
; CHECK-NEXT: andl $1, %edi		; CHECK-NEXT: kmovb %edi, %k1
; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vfpclassss $4, %xmm0, %k0 {%k1}		; CHECK-NEXT: vfpclassss $4, %xmm0, %k0 {%k1}
; CHECK-NEXT: kmovw %k0, %ecx		; CHECK-NEXT: kmovb %k0, %ecx
; CHECK-NEXT: andl $1, %ecx
; CHECK-NEXT: vfpclassss $4, %xmm0, %k0		; CHECK-NEXT: vfpclassss $4, %xmm0, %k0
; CHECK-NEXT: kmovw %k0, %eax		; CHECK-NEXT: kmovb %k0, %eax
; CHECK-NEXT: andl $1, %eax
; CHECK-NEXT: addb %cl, %al		; CHECK-NEXT: addb %cl, %al
; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
; CHECK-NEXT: retq		; CHECK-NEXT: retq
%res = call i8 @llvm.x86.avx512.mask.fpclass.ss(<4 x float> %x0, i32 4, i8 %x1)		%res = call i8 @llvm.x86.avx512.mask.fpclass.ss(<4 x float> %x0, i32 4, i8 %x1)
%res1 = call i8 @llvm.x86.avx512.mask.fpclass.ss(<4 x float> %x0, i32 4, i8 -1)		%res1 = call i8 @llvm.x86.avx512.mask.fpclass.ss(<4 x float> %x0, i32 4, i8 -1)
%res2 = add i8 %res, %res1		%res2 = add i8 %res, %res1
ret i8 %res2		ret i8 %res2
}		}

declare <16 x float> @llvm.x86.avx512.mask.broadcastf32x2.512(<4 x float>, <16 x float>, i16)		declare <16 x float> @llvm.x86.avx512.mask.broadcastf32x2.512(<4 x float>, <16 x float>, i16)
▲ Show 20 Lines • Show All 204 Lines • Show Last 20 Lines

test/CodeGen/X86/avx512er-intrinsics.ll

Show First 20 Lines • Show All 115 Lines • ▼ Show 20 Lines	; CHECK-NEXT: retq # encoding: [0xc3]
%res = call <4 x float> @llvm.x86.avx512.rcp28.ss(<4 x float> %a0, <4 x float> %a0, <4 x float> zeroinitializer, i8 -1, i32 8) ; <<4 x float>> [#uses=1]		%res = call <4 x float> @llvm.x86.avx512.rcp28.ss(<4 x float> %a0, <4 x float> %a0, <4 x float> zeroinitializer, i8 -1, i32 8) ; <<4 x float>> [#uses=1]
ret <4 x float> %res		ret <4 x float> %res
}		}
declare <4 x float> @llvm.x86.avx512.rcp28.ss(<4 x float>, <4 x float>, <4 x float>, i8, i32) nounwind readnone		declare <4 x float> @llvm.x86.avx512.rcp28.ss(<4 x float>, <4 x float>, <4 x float>, i8, i32) nounwind readnone

define <4 x float> @test_rsqrt28_ss_maskz(<4 x float> %a0) {		define <4 x float> @test_rsqrt28_ss_maskz(<4 x float> %a0) {
; CHECK-LABEL: test_rsqrt28_ss_maskz:		; CHECK-LABEL: test_rsqrt28_ss_maskz:
; CHECK: # BB#0:		; CHECK: # BB#0:
; CHECK-NEXT: kxnorw %k0, %k0, %k0 # encoding: [0xc5,0xfc,0x46,0xc0]		; CHECK-NEXT: vrsqrt28ss {sae}, %xmm0, %xmm0, %xmm0 # encoding: [0x62,0xf2,0x7d,0x18,0xcd,0xc0]
; CHECK-NEXT: kshiftrw $15, %k0, %k1 # encoding: [0xc4,0xe3,0xf9,0x30,0xc8,0x0f]
; CHECK-NEXT: vrsqrt28ss {sae}, %xmm0, %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf2,0x7d,0x99,0xcd,0xc0]
; CHECK-NEXT: retq # encoding: [0xc3]		; CHECK-NEXT: retq # encoding: [0xc3]
%res = call <4 x float> @llvm.x86.avx512.rsqrt28.ss(<4 x float> %a0, <4 x float> %a0, <4 x float> zeroinitializer, i8 7, i32 8) ;		%res = call <4 x float> @llvm.x86.avx512.rsqrt28.ss(<4 x float> %a0, <4 x float> %a0, <4 x float> zeroinitializer, i8 7, i32 8) ;
ret <4 x float> %res		ret <4 x float> %res
}		}

define <4 x float> @test_rsqrt28_ss_mask(<4 x float> %a0, <4 x float> %b0, <4 x float> %c0) {		define <4 x float> @test_rsqrt28_ss_mask(<4 x float> %a0, <4 x float> %b0, <4 x float> %c0) {
; CHECK-LABEL: test_rsqrt28_ss_mask:		; CHECK-LABEL: test_rsqrt28_ss_mask:
; CHECK: # BB#0:		; CHECK: # BB#0:
; CHECK-NEXT: kxnorw %k0, %k0, %k0 # encoding: [0xc5,0xfc,0x46,0xc0]		; CHECK-NEXT: vrsqrt28ss {sae}, %xmm1, %xmm0, %xmm0 # encoding: [0x62,0xf2,0x7d,0x18,0xcd,0xc1]
; CHECK-NEXT: kshiftrw $15, %k0, %k1 # encoding: [0xc4,0xe3,0xf9,0x30,0xc8,0x0f]
; CHECK-NEXT: vrsqrt28ss {sae}, %xmm1, %xmm0, %xmm2 {%k1} # encoding: [0x62,0xf2,0x7d,0x19,0xcd,0xd1]
; CHECK-NEXT: vmovaps %xmm2, %xmm0 # encoding: [0xc5,0xf8,0x28,0xc2]
; CHECK-NEXT: retq # encoding: [0xc3]		; CHECK-NEXT: retq # encoding: [0xc3]
%res = call <4 x float> @llvm.x86.avx512.rsqrt28.ss(<4 x float> %a0, <4 x float> %b0, <4 x float> %c0, i8 7, i32 8) ;		%res = call <4 x float> @llvm.x86.avx512.rsqrt28.ss(<4 x float> %a0, <4 x float> %b0, <4 x float> %c0, i8 7, i32 8) ;
ret <4 x float> %res		ret <4 x float> %res
}		}

define <2 x double> @test_rsqrt28_sd_maskz(<2 x double> %a0) {		define <2 x double> @test_rsqrt28_sd_maskz(<2 x double> %a0) {
; CHECK-LABEL: test_rsqrt28_sd_maskz:		; CHECK-LABEL: test_rsqrt28_sd_maskz:
; CHECK: # BB#0:		; CHECK: # BB#0:
; CHECK-NEXT: kxnorw %k0, %k0, %k0 # encoding: [0xc5,0xfc,0x46,0xc0]		; CHECK-NEXT: vrsqrt28sd {sae}, %xmm0, %xmm0, %xmm0 # encoding: [0x62,0xf2,0xfd,0x18,0xcd,0xc0]
; CHECK-NEXT: kshiftrw $15, %k0, %k1 # encoding: [0xc4,0xe3,0xf9,0x30,0xc8,0x0f]
; CHECK-NEXT: vrsqrt28sd {sae}, %xmm0, %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf2,0xfd,0x99,0xcd,0xc0]
; CHECK-NEXT: retq # encoding: [0xc3]		; CHECK-NEXT: retq # encoding: [0xc3]
%res = call <2 x double> @llvm.x86.avx512.rsqrt28.sd(<2 x double> %a0, <2 x double> %a0, <2 x double> zeroinitializer, i8 7, i32 8) ;		%res = call <2 x double> @llvm.x86.avx512.rsqrt28.sd(<2 x double> %a0, <2 x double> %a0, <2 x double> zeroinitializer, i8 7, i32 8) ;
ret <2 x double> %res		ret <2 x double> %res
}		}

define <2 x double> @test_rsqrt28_sd_mask(<2 x double> %a0, <2 x double> %b0, <2 x double> %c0) {		define <2 x double> @test_rsqrt28_sd_mask(<2 x double> %a0, <2 x double> %b0, <2 x double> %c0) {
; CHECK-LABEL: test_rsqrt28_sd_mask:		; CHECK-LABEL: test_rsqrt28_sd_mask:
; CHECK: # BB#0:		; CHECK: # BB#0:
; CHECK-NEXT: kxnorw %k0, %k0, %k0 # encoding: [0xc5,0xfc,0x46,0xc0]		; CHECK-NEXT: vrsqrt28sd {sae}, %xmm1, %xmm0, %xmm0 # encoding: [0x62,0xf2,0xfd,0x18,0xcd,0xc1]
; CHECK-NEXT: kshiftrw $15, %k0, %k1 # encoding: [0xc4,0xe3,0xf9,0x30,0xc8,0x0f]
; CHECK-NEXT: vrsqrt28sd {sae}, %xmm1, %xmm0, %xmm2 {%k1} # encoding: [0x62,0xf2,0xfd,0x19,0xcd,0xd1]
; CHECK-NEXT: vmovapd %xmm2, %xmm0 # encoding: [0xc5,0xf9,0x28,0xc2]
; CHECK-NEXT: retq # encoding: [0xc3]		; CHECK-NEXT: retq # encoding: [0xc3]
%res = call <2 x double> @llvm.x86.avx512.rsqrt28.sd(<2 x double> %a0, <2 x double> %b0, <2 x double> %c0, i8 7, i32 8) ;		%res = call <2 x double> @llvm.x86.avx512.rsqrt28.sd(<2 x double> %a0, <2 x double> %b0, <2 x double> %c0, i8 7, i32 8) ;
ret <2 x double> %res		ret <2 x double> %res
}		}

declare <2 x double> @llvm.x86.avx512.rsqrt28.sd(<2 x double>, <2 x double>, <2 x double>, i8, i32) nounwind readnone		declare <2 x double> @llvm.x86.avx512.rsqrt28.sd(<2 x double>, <2 x double>, <2 x double>, i8, i32) nounwind readnone

define <2 x double> @test_rsqrt28_sd_maskz_mem(<2 x double> %a0, double* %ptr ) {		define <2 x double> @test_rsqrt28_sd_maskz_mem(<2 x double> %a0, double* %ptr ) {
; CHECK-LABEL: test_rsqrt28_sd_maskz_mem:		; CHECK-LABEL: test_rsqrt28_sd_maskz_mem:
; CHECK: # BB#0:		; CHECK: # BB#0:
; CHECK-NEXT: kxnorw %k0, %k0, %k0 # encoding: [0xc5,0xfc,0x46,0xc0]		; CHECK-NEXT: vrsqrt28sd (%rdi), %xmm0, %xmm0 # encoding: [0x62,0xf2,0xfd,0x08,0xcd,0x07]
; CHECK-NEXT: kshiftrw $15, %k0, %k1 # encoding: [0xc4,0xe3,0xf9,0x30,0xc8,0x0f]
; CHECK-NEXT: vrsqrt28sd (%rdi), %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf2,0xfd,0x89,0xcd,0x07]
; CHECK-NEXT: retq # encoding: [0xc3]		; CHECK-NEXT: retq # encoding: [0xc3]
%mem = load double , double * %ptr, align 8		%mem = load double , double * %ptr, align 8
%mem_v = insertelement <2 x double> undef, double %mem, i32 0		%mem_v = insertelement <2 x double> undef, double %mem, i32 0
%res = call <2 x double> @llvm.x86.avx512.rsqrt28.sd(<2 x double> %a0, <2 x double> %mem_v, <2 x double> zeroinitializer, i8 7, i32 4) ;		%res = call <2 x double> @llvm.x86.avx512.rsqrt28.sd(<2 x double> %a0, <2 x double> %mem_v, <2 x double> zeroinitializer, i8 7, i32 4) ;
ret <2 x double> %res		ret <2 x double> %res
}		}

define <2 x double> @test_rsqrt28_sd_maskz_mem_offset(<2 x double> %a0, double* %ptr ) {		define <2 x double> @test_rsqrt28_sd_maskz_mem_offset(<2 x double> %a0, double* %ptr ) {
; CHECK-LABEL: test_rsqrt28_sd_maskz_mem_offset:		; CHECK-LABEL: test_rsqrt28_sd_maskz_mem_offset:
; CHECK: # BB#0:		; CHECK: # BB#0:
; CHECK-NEXT: kxnorw %k0, %k0, %k0 # encoding: [0xc5,0xfc,0x46,0xc0]		; CHECK-NEXT: vrsqrt28sd 144(%rdi), %xmm0, %xmm0 # encoding: [0x62,0xf2,0xfd,0x08,0xcd,0x47,0x12]
; CHECK-NEXT: kshiftrw $15, %k0, %k1 # encoding: [0xc4,0xe3,0xf9,0x30,0xc8,0x0f]
; CHECK-NEXT: vrsqrt28sd 144(%rdi), %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf2,0xfd,0x89,0xcd,0x47,0x12]
; CHECK-NEXT: retq # encoding: [0xc3]		; CHECK-NEXT: retq # encoding: [0xc3]
%ptr1 = getelementptr double, double* %ptr, i32 18		%ptr1 = getelementptr double, double* %ptr, i32 18
%mem = load double , double * %ptr1, align 8		%mem = load double , double * %ptr1, align 8
%mem_v = insertelement <2 x double> undef, double %mem, i32 0		%mem_v = insertelement <2 x double> undef, double %mem, i32 0
%res = call <2 x double> @llvm.x86.avx512.rsqrt28.sd(<2 x double> %a0, <2 x double> %mem_v, <2 x double> zeroinitializer, i8 7, i32 4) ;		%res = call <2 x double> @llvm.x86.avx512.rsqrt28.sd(<2 x double> %a0, <2 x double> %mem_v, <2 x double> zeroinitializer, i8 7, i32 4) ;
ret <2 x double> %res		ret <2 x double> %res
}		}

test/CodeGen/X86/fast-isel-load-i1.ll

	; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py			; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
	; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-linux-gnu -mattr=+avx512f \| FileCheck %s			; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-linux-gnu -mattr=+avx512f \| FileCheck %s

	define i1 @test_i1(i1* %b) {			define i1 @test_i1(i1* %b) {
	; CHECK-LABEL: test_i1:			; CHECK-LABEL: test_i1:
	; CHECK: # BB#0: # %entry			; CHECK: # BB#0: # %entry
	; CHECK-NEXT: movzbl (%rdi), %eax			; CHECK-NEXT: testb $1, (%rdi)
	; CHECK-NEXT: andl $1, %eax
	; CHECK-NEXT: testb $1, %al
	; CHECK-NEXT: je .LBB0_2			; CHECK-NEXT: je .LBB0_2
	; CHECK-NEXT: # BB#1: # %in			; CHECK-NEXT: # BB#1: # %in
	; CHECK-NEXT: xorl %eax, %eax			; CHECK-NEXT: xorl %eax, %eax
	; CHECK-NEXT: retq			; CHECK-NEXT: retq
	; CHECK-NEXT: .LBB0_2: # %out			; CHECK-NEXT: .LBB0_2: # %out
	; CHECK-NEXT: movb $1, %al			; CHECK-NEXT: movb $1, %al
	; CHECK-NEXT: retq			; CHECK-NEXT: retq
	entry:			entry:
	%0 = load i1, i1* %b, align 1			%0 = load i1, i1* %b, align 1
	br i1 %0, label %in, label %out			br i1 %0, label %in, label %out
	in:			in:
	ret i1 0			ret i1 0
	out:			out:
	ret i1 1			ret i1 1
	}			}

test/CodeGen/X86/fma-fneg-combine.ll

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}		}

declare <2 x double> @llvm.x86.avx512.mask.vfmadd.sd(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8, i32)		declare <2 x double> @llvm.x86.avx512.mask.vfmadd.sd(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8, i32)

define <4 x float> @test11(<4 x float> %a, <4 x float> %b, <4 x float> %c, i8 zeroext %mask) local_unnamed_addr #0 {		define <4 x float> @test11(<4 x float> %a, <4 x float> %b, <4 x float> %c, i8 zeroext %mask) local_unnamed_addr #0 {
; SKX-LABEL: test11:		; SKX-LABEL: test11:
; SKX: # BB#0: # %entry		; SKX: # BB#0: # %entry
; SKX-NEXT: vxorps {{.*}}(%rip){1to4}, %xmm2, %xmm0		; SKX-NEXT: vxorps {{.*}}(%rip){1to4}, %xmm2, %xmm0
; SKX-NEXT: andl $1, %edi		; SKX-NEXT: kmovb %edi, %k1
; SKX-NEXT: kmovd %edi, %k1
; SKX-NEXT: vfmadd231ss %xmm1, %xmm1, %xmm0 {%k1}		; SKX-NEXT: vfmadd231ss %xmm1, %xmm1, %xmm0 {%k1}
; SKX-NEXT: retq		; SKX-NEXT: retq
;		;
; KNL-LABEL: test11:		; KNL-LABEL: test11:
; KNL: # BB#0: # %entry		; KNL: # BB#0: # %entry
; KNL-NEXT: vbroadcastss {{.*}}(%rip), %xmm0		; KNL-NEXT: vbroadcastss {{.*}}(%rip), %xmm0
; KNL-NEXT: vxorps %xmm0, %xmm2, %xmm0		; KNL-NEXT: vxorps %xmm0, %xmm2, %xmm0
; KNL-NEXT: andl $1, %edi
; KNL-NEXT: kmovw %edi, %k1		; KNL-NEXT: kmovw %edi, %k1
; KNL-NEXT: vfmadd231ss %xmm1, %xmm1, %xmm0 {%k1}		; KNL-NEXT: vfmadd231ss %xmm1, %xmm1, %xmm0 {%k1}
; KNL-NEXT: retq		; KNL-NEXT: retq
entry:		entry:
%sub.i = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %c		%sub.i = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %c
%0 = tail call <4 x float> @llvm.x86.avx512.mask3.vfmadd.ss(<4 x float> %b, <4 x float> %b, <4 x float> %sub.i, i8 %mask, i32 4) #10		%0 = tail call <4 x float> @llvm.x86.avx512.mask3.vfmadd.ss(<4 x float> %b, <4 x float> %b, <4 x float> %sub.i, i8 %mask, i32 4) #10
ret <4 x float> %0		ret <4 x float> %0
}		}
Show All 19 Lines	entry:
%sub.i = fsub <8 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %0		%sub.i = fsub <8 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %0
ret <8 x double> %sub.i		ret <8 x double> %sub.i
}		}

define <2 x double> @test13(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) {		define <2 x double> @test13(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) {
; SKX-LABEL: test13:		; SKX-LABEL: test13:
; SKX: # BB#0: # %entry		; SKX: # BB#0: # %entry
; SKX-NEXT: vxorpd {{.*}}(%rip), %xmm0, %xmm0		; SKX-NEXT: vxorpd {{.*}}(%rip), %xmm0, %xmm0
; SKX-NEXT: andl $1, %edi		; SKX-NEXT: kmovb %edi, %k1
; SKX-NEXT: kmovd %edi, %k1
; SKX-NEXT: vfmadd213sd %xmm2, %xmm1, %xmm0 {%k1}		; SKX-NEXT: vfmadd213sd %xmm2, %xmm1, %xmm0 {%k1}
; SKX-NEXT: retq		; SKX-NEXT: retq
;		;
; KNL-LABEL: test13:		; KNL-LABEL: test13:
; KNL: # BB#0: # %entry		; KNL: # BB#0: # %entry
; KNL-NEXT: vxorpd {{.*}}(%rip), %xmm0, %xmm0		; KNL-NEXT: vxorpd {{.*}}(%rip), %xmm0, %xmm0
; KNL-NEXT: andl $1, %edi
; KNL-NEXT: kmovw %edi, %k1		; KNL-NEXT: kmovw %edi, %k1
; KNL-NEXT: vfmadd213sd %xmm2, %xmm1, %xmm0 {%k1}		; KNL-NEXT: vfmadd213sd %xmm2, %xmm1, %xmm0 {%k1}
; KNL-NEXT: retq		; KNL-NEXT: retq

entry:		entry:
%sub.i = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %a		%sub.i = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %a
%0 = tail call <2 x double> @llvm.x86.avx512.mask.vfmadd.sd(<2 x double> %sub.i, <2 x double> %b, <2 x double> %c, i8 %mask, i32 4)		%0 = tail call <2 x double> @llvm.x86.avx512.mask.vfmadd.sd(<2 x double> %sub.i, <2 x double> %b, <2 x double> %c, i8 %mask, i32 4)
ret <2 x double> %0		ret <2 x double> %0
}		}

define <16 x float> @test14(<16 x float> %a, <16 x float> %b, <16 x float> %c, i16 %mask) {		define <16 x float> @test14(<16 x float> %a, <16 x float> %b, <16 x float> %c, i16 %mask) {
; SKX-LABEL: test14:		; SKX-LABEL: test14:
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test/CodeGen/X86/masked_gather_scatter.ll

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; KNL_64-NEXT: kxnorw %k0, %k0, %k2		; KNL_64-NEXT: kxnorw %k0, %k0, %k2
; KNL_64-NEXT: vpgatherqd (,%zmm1), %ymm2 {%k2}		; KNL_64-NEXT: vpgatherqd (,%zmm1), %ymm2 {%k2}
; KNL_64-NEXT: vpscatterqd %ymm0, (,%zmm1) {%k1}		; KNL_64-NEXT: vpscatterqd %ymm0, (,%zmm1) {%k1}
; KNL_64-NEXT: vmovdqa %ymm2, %ymm0		; KNL_64-NEXT: vmovdqa %ymm2, %ymm0
; KNL_64-NEXT: retq		; KNL_64-NEXT: retq
;		;
; KNL_32-LABEL: test6:		; KNL_32-LABEL: test6:
; KNL_32: # BB#0:		; KNL_32: # BB#0:
; KNL_32-NEXT: kxnorw %k0, %k0, %k1
; KNL_32-NEXT: vpmovsxdq %ymm1, %zmm2		; KNL_32-NEXT: vpmovsxdq %ymm1, %zmm2
		; KNL_32-NEXT: kxnorw %k0, %k0, %k1
; KNL_32-NEXT: kxnorw %k0, %k0, %k2		; KNL_32-NEXT: kxnorw %k0, %k0, %k2
; KNL_32-NEXT: vpgatherqd (,%zmm2), %ymm1 {%k2}		; KNL_32-NEXT: vpgatherqd (,%zmm2), %ymm1 {%k2}
; KNL_32-NEXT: vpscatterqd %ymm0, (,%zmm2) {%k1}		; KNL_32-NEXT: vpscatterqd %ymm0, (,%zmm2) {%k1}
; KNL_32-NEXT: vmovdqa %ymm1, %ymm0		; KNL_32-NEXT: vmovdqa %ymm1, %ymm0
; KNL_32-NEXT: retl		; KNL_32-NEXT: retl
;		;
; SKX-LABEL: test6:		; SKX-LABEL: test6:
; SKX: # BB#0:		; SKX: # BB#0:
▲ Show 20 Lines • Show All 1,257 Lines • ▼ Show 20 Lines	; SKX_32-NEXT: retl

%res = call <16 x float> @llvm.masked.gather.v16f32(<16 x float*> %gep.random, i32 4, <16 x i1> <i1 false, i1 false, i1 true, i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <16 x float> undef)		%res = call <16 x float> @llvm.masked.gather.v16f32(<16 x float*> %gep.random, i32 4, <16 x i1> <i1 false, i1 false, i1 true, i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <16 x float> undef)
ret <16 x float>%res		ret <16 x float>%res
}		}

; Check non-power-of-2 case. It should be scalarized.		; Check non-power-of-2 case. It should be scalarized.
declare <3 x i32> @llvm.masked.gather.v3i32(<3 x i32*>, i32, <3 x i1>, <3 x i32>)		declare <3 x i32> @llvm.masked.gather.v3i32(<3 x i32*>, i32, <3 x i1>, <3 x i32>)
define <3 x i32> @test30(<3 x i32*> %base, <3 x i32> %ind, <3 x i1> %mask, <3 x i32> %src0) {		define <3 x i32> @test30(<3 x i32*> %base, <3 x i32> %ind, <3 x i1> %mask, <3 x i32> %src0) {
; ALL-LABEL: test30:		; ALL-LABEL: test30
; ALL-NOT: gather		; ALL-NOT: gather

%sext_ind = sext <3 x i32> %ind to <3 x i64>		%sext_ind = sext <3 x i32> %ind to <3 x i64>
%gep.random = getelementptr i32, <3 x i32*> %base, <3 x i64> %sext_ind		%gep.random = getelementptr i32, <3 x i32*> %base, <3 x i64> %sext_ind
%res = call <3 x i32> @llvm.masked.gather.v3i32(<3 x i32*> %gep.random, i32 4, <3 x i1> %mask, <3 x i32> %src0)		%res = call <3 x i32> @llvm.masked.gather.v3i32(<3 x i32*> %gep.random, i32 4, <3 x i1> %mask, <3 x i32> %src0)
ret <3 x i32>%res		ret <3 x i32>%res
}		}

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; KNL_64-NEXT: vpgatherqq (,%zmm1), %zmm4 {%k2}		; KNL_64-NEXT: vpgatherqq (,%zmm1), %zmm4 {%k2}
; KNL_64-NEXT: vmovdqa64 %zmm3, %zmm0		; KNL_64-NEXT: vmovdqa64 %zmm3, %zmm0
; KNL_64-NEXT: vmovdqa64 %zmm4, %zmm1		; KNL_64-NEXT: vmovdqa64 %zmm4, %zmm1
; KNL_64-NEXT: retq		; KNL_64-NEXT: retq
;		;
; KNL_32-LABEL: test_gather_16i64:		; KNL_32-LABEL: test_gather_16i64:
; KNL_32: # BB#0:		; KNL_32: # BB#0:
; KNL_32-NEXT: pushl %ebp		; KNL_32-NEXT: pushl %ebp
; KNL_32-NEXT: .Lcfi4:		; KNL_32-NEXT: .Lcfi0:
; KNL_32-NEXT: .cfi_def_cfa_offset 8		; KNL_32-NEXT: .cfi_def_cfa_offset 8
; KNL_32-NEXT: .Lcfi5:		; KNL_32-NEXT: .Lcfi1:
; KNL_32-NEXT: .cfi_offset %ebp, -8		; KNL_32-NEXT: .cfi_offset %ebp, -8
; KNL_32-NEXT: movl %esp, %ebp		; KNL_32-NEXT: movl %esp, %ebp
; KNL_32-NEXT: .Lcfi6:		; KNL_32-NEXT: .Lcfi2:
; KNL_32-NEXT: .cfi_def_cfa_register %ebp		; KNL_32-NEXT: .cfi_def_cfa_register %ebp
; KNL_32-NEXT: andl $-64, %esp		; KNL_32-NEXT: andl $-64, %esp
; KNL_32-NEXT: subl $64, %esp		; KNL_32-NEXT: subl $64, %esp
; KNL_32-NEXT: vpmovsxbd %xmm1, %zmm1		; KNL_32-NEXT: vpmovsxbd %xmm1, %zmm1
; KNL_32-NEXT: vpslld $31, %zmm1, %zmm1		; KNL_32-NEXT: vpslld $31, %zmm1, %zmm1
; KNL_32-NEXT: vptestmd %zmm1, %zmm1, %k1		; KNL_32-NEXT: vptestmd %zmm1, %zmm1, %k1
; KNL_32-NEXT: vmovdqa64 8(%ebp), %zmm1		; KNL_32-NEXT: vmovdqa64 8(%ebp), %zmm1
; KNL_32-NEXT: kshiftrw $8, %k1, %k2		; KNL_32-NEXT: kshiftrw $8, %k1, %k2
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; KNL_64-NEXT: vgatherqpd (,%zmm1), %zmm4 {%k2}		; KNL_64-NEXT: vgatherqpd (,%zmm1), %zmm4 {%k2}
; KNL_64-NEXT: vmovapd %zmm3, %zmm0		; KNL_64-NEXT: vmovapd %zmm3, %zmm0
; KNL_64-NEXT: vmovapd %zmm4, %zmm1		; KNL_64-NEXT: vmovapd %zmm4, %zmm1
; KNL_64-NEXT: retq		; KNL_64-NEXT: retq
;		;
; KNL_32-LABEL: test_gather_16f64:		; KNL_32-LABEL: test_gather_16f64:
; KNL_32: # BB#0:		; KNL_32: # BB#0:
; KNL_32-NEXT: pushl %ebp		; KNL_32-NEXT: pushl %ebp
; KNL_32-NEXT: .Lcfi7:		; KNL_32-NEXT: .Lcfi3:
; KNL_32-NEXT: .cfi_def_cfa_offset 8		; KNL_32-NEXT: .cfi_def_cfa_offset 8
; KNL_32-NEXT: .Lcfi8:		; KNL_32-NEXT: .Lcfi4:
; KNL_32-NEXT: .cfi_offset %ebp, -8		; KNL_32-NEXT: .cfi_offset %ebp, -8
; KNL_32-NEXT: movl %esp, %ebp		; KNL_32-NEXT: movl %esp, %ebp
; KNL_32-NEXT: .Lcfi9:		; KNL_32-NEXT: .Lcfi5:
; KNL_32-NEXT: .cfi_def_cfa_register %ebp		; KNL_32-NEXT: .cfi_def_cfa_register %ebp
; KNL_32-NEXT: andl $-64, %esp		; KNL_32-NEXT: andl $-64, %esp
; KNL_32-NEXT: subl $64, %esp		; KNL_32-NEXT: subl $64, %esp
; KNL_32-NEXT: vpmovsxbd %xmm1, %zmm1		; KNL_32-NEXT: vpmovsxbd %xmm1, %zmm1
; KNL_32-NEXT: vpslld $31, %zmm1, %zmm1		; KNL_32-NEXT: vpslld $31, %zmm1, %zmm1
; KNL_32-NEXT: vptestmd %zmm1, %zmm1, %k1		; KNL_32-NEXT: vptestmd %zmm1, %zmm1, %k1
; KNL_32-NEXT: vmovapd 8(%ebp), %zmm1		; KNL_32-NEXT: vmovapd 8(%ebp), %zmm1
; KNL_32-NEXT: kshiftrw $8, %k1, %k2		; KNL_32-NEXT: kshiftrw $8, %k1, %k2
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; KNL_64-NEXT: vpscatterqq %zmm3, (,%zmm0) {%k1}		; KNL_64-NEXT: vpscatterqq %zmm3, (,%zmm0) {%k1}
; KNL_64-NEXT: vpscatterqq %zmm4, (,%zmm1) {%k2}		; KNL_64-NEXT: vpscatterqq %zmm4, (,%zmm1) {%k2}
; KNL_64-NEXT: vzeroupper		; KNL_64-NEXT: vzeroupper
; KNL_64-NEXT: retq		; KNL_64-NEXT: retq
;		;
; KNL_32-LABEL: test_scatter_16i64:		; KNL_32-LABEL: test_scatter_16i64:
; KNL_32: # BB#0:		; KNL_32: # BB#0:
; KNL_32-NEXT: pushl %ebp		; KNL_32-NEXT: pushl %ebp
; KNL_32-NEXT: .Lcfi10:		; KNL_32-NEXT: .Lcfi6:
; KNL_32-NEXT: .cfi_def_cfa_offset 8		; KNL_32-NEXT: .cfi_def_cfa_offset 8
; KNL_32-NEXT: .Lcfi11:		; KNL_32-NEXT: .Lcfi7:
; KNL_32-NEXT: .cfi_offset %ebp, -8		; KNL_32-NEXT: .cfi_offset %ebp, -8
; KNL_32-NEXT: movl %esp, %ebp		; KNL_32-NEXT: movl %esp, %ebp
; KNL_32-NEXT: .Lcfi12:		; KNL_32-NEXT: .Lcfi8:
; KNL_32-NEXT: .cfi_def_cfa_register %ebp		; KNL_32-NEXT: .cfi_def_cfa_register %ebp
; KNL_32-NEXT: andl $-64, %esp		; KNL_32-NEXT: andl $-64, %esp
; KNL_32-NEXT: subl $64, %esp		; KNL_32-NEXT: subl $64, %esp
; KNL_32-NEXT: vpmovsxbd %xmm1, %zmm1		; KNL_32-NEXT: vpmovsxbd %xmm1, %zmm1
; KNL_32-NEXT: vpslld $31, %zmm1, %zmm1		; KNL_32-NEXT: vpslld $31, %zmm1, %zmm1
; KNL_32-NEXT: vptestmd %zmm1, %zmm1, %k1		; KNL_32-NEXT: vptestmd %zmm1, %zmm1, %k1
; KNL_32-NEXT: vmovdqa64 8(%ebp), %zmm1		; KNL_32-NEXT: vmovdqa64 8(%ebp), %zmm1
; KNL_32-NEXT: kshiftrw $8, %k1, %k2		; KNL_32-NEXT: kshiftrw $8, %k1, %k2
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; KNL_64-NEXT: vscatterqpd %zmm3, (,%zmm0) {%k1}		; KNL_64-NEXT: vscatterqpd %zmm3, (,%zmm0) {%k1}
; KNL_64-NEXT: vscatterqpd %zmm4, (,%zmm1) {%k2}		; KNL_64-NEXT: vscatterqpd %zmm4, (,%zmm1) {%k2}
; KNL_64-NEXT: vzeroupper		; KNL_64-NEXT: vzeroupper
; KNL_64-NEXT: retq		; KNL_64-NEXT: retq
;		;
; KNL_32-LABEL: test_scatter_16f64:		; KNL_32-LABEL: test_scatter_16f64:
; KNL_32: # BB#0:		; KNL_32: # BB#0:
; KNL_32-NEXT: pushl %ebp		; KNL_32-NEXT: pushl %ebp
; KNL_32-NEXT: .Lcfi13:		; KNL_32-NEXT: .Lcfi9:
; KNL_32-NEXT: .cfi_def_cfa_offset 8		; KNL_32-NEXT: .cfi_def_cfa_offset 8
; KNL_32-NEXT: .Lcfi14:		; KNL_32-NEXT: .Lcfi10:
; KNL_32-NEXT: .cfi_offset %ebp, -8		; KNL_32-NEXT: .cfi_offset %ebp, -8
; KNL_32-NEXT: movl %esp, %ebp		; KNL_32-NEXT: movl %esp, %ebp
; KNL_32-NEXT: .Lcfi15:		; KNL_32-NEXT: .Lcfi11:
; KNL_32-NEXT: .cfi_def_cfa_register %ebp		; KNL_32-NEXT: .cfi_def_cfa_register %ebp
; KNL_32-NEXT: andl $-64, %esp		; KNL_32-NEXT: andl $-64, %esp
; KNL_32-NEXT: subl $64, %esp		; KNL_32-NEXT: subl $64, %esp
; KNL_32-NEXT: vpmovsxbd %xmm1, %zmm1		; KNL_32-NEXT: vpmovsxbd %xmm1, %zmm1
; KNL_32-NEXT: vpslld $31, %zmm1, %zmm1		; KNL_32-NEXT: vpslld $31, %zmm1, %zmm1
; KNL_32-NEXT: vptestmd %zmm1, %zmm1, %k1		; KNL_32-NEXT: vptestmd %zmm1, %zmm1, %k1
; KNL_32-NEXT: vmovapd 8(%ebp), %zmm1		; KNL_32-NEXT: vmovapd 8(%ebp), %zmm1
; KNL_32-NEXT: kshiftrw $8, %k1, %k2		; KNL_32-NEXT: kshiftrw $8, %k1, %k2
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; KNL_64-NEXT: vpgatherqq (,%zmm0), %zmm1 {%k1}		; KNL_64-NEXT: vpgatherqq (,%zmm0), %zmm1 {%k1}
; KNL_64-NEXT: vpaddq %ymm1, %ymm1, %ymm0		; KNL_64-NEXT: vpaddq %ymm1, %ymm1, %ymm0
; KNL_64-NEXT: vpaddq %ymm0, %ymm1, %ymm0		; KNL_64-NEXT: vpaddq %ymm0, %ymm1, %ymm0
; KNL_64-NEXT: retq		; KNL_64-NEXT: retq
;		;
; KNL_32-LABEL: test_pr28312:		; KNL_32-LABEL: test_pr28312:
; KNL_32: # BB#0:		; KNL_32: # BB#0:
; KNL_32-NEXT: pushl %ebp		; KNL_32-NEXT: pushl %ebp
; KNL_32-NEXT: .Lcfi16:		; KNL_32-NEXT: .Lcfi12:
; KNL_32-NEXT: .cfi_def_cfa_offset 8		; KNL_32-NEXT: .cfi_def_cfa_offset 8
; KNL_32-NEXT: .Lcfi17:		; KNL_32-NEXT: .Lcfi13:
; KNL_32-NEXT: .cfi_offset %ebp, -8		; KNL_32-NEXT: .cfi_offset %ebp, -8
; KNL_32-NEXT: movl %esp, %ebp		; KNL_32-NEXT: movl %esp, %ebp
; KNL_32-NEXT: .Lcfi18:		; KNL_32-NEXT: .Lcfi14:
; KNL_32-NEXT: .cfi_def_cfa_register %ebp		; KNL_32-NEXT: .cfi_def_cfa_register %ebp
; KNL_32-NEXT: andl $-32, %esp		; KNL_32-NEXT: andl $-32, %esp
; KNL_32-NEXT: subl $32, %esp		; KNL_32-NEXT: subl $32, %esp
; KNL_32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>		; KNL_32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
; KNL_32-NEXT: vpslld $31, %xmm1, %xmm1		; KNL_32-NEXT: vpslld $31, %xmm1, %xmm1
; KNL_32-NEXT: vpsrad $31, %xmm1, %xmm1		; KNL_32-NEXT: vpsrad $31, %xmm1, %xmm1
; KNL_32-NEXT: vpmovsxdq %xmm1, %ymm1		; KNL_32-NEXT: vpmovsxdq %xmm1, %ymm1
; KNL_32-NEXT: vpxord %zmm2, %zmm2, %zmm2		; KNL_32-NEXT: vpxord %zmm2, %zmm2, %zmm2
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test/CodeGen/X86/pr27591.ll

	; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py			; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
	; RUN: llc -o - -O0 < %s \| FileCheck %s			; RUN: llc -o - -O0 < %s \| FileCheck %s
	target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"			target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
	target triple = "x86_64-unknown-linux-gnu"			target triple = "x86_64-unknown-linux-gnu"

	define void @test1(i32 %x) #0 {			define void @test1(i32 %x) #0 {
	; CHECK-LABEL: test1:			; CHECK-LABEL: test1:
	; CHECK: # BB#0: # %entry			; CHECK: # BB#0: # %entry
	; CHECK-NEXT: pushq %rax			; CHECK-NEXT: pushq %rax
	; CHECK-NEXT: testl %edi, %edi			; CHECK-NEXT: testl %edi, %edi
	; CHECK-NEXT: setne %al			; CHECK-NEXT: setne %al
	; CHECK-NEXT: # implicit-def: %EDI
	; CHECK-NEXT: movb %al, %dil
	; CHECK-NEXT: andl $1, %edi
	; CHECK-NEXT: kmovd %edi, %k0
	; CHECK-NEXT: kmovd %k0, %edi
	; CHECK-NEXT: movb %dil, %al
	; CHECK-NEXT: andb $1, %al			; CHECK-NEXT: andb $1, %al
	; CHECK-NEXT: movzbl %al, %edi			; CHECK-NEXT: movzbl %al, %edi
	; CHECK-NEXT: callq callee1			; CHECK-NEXT: callq callee1
	; CHECK-NEXT: popq %rax			; CHECK-NEXT: popq %rax
	; CHECK-NEXT: retq			; CHECK-NEXT: retq
	entry:			entry:
	%tobool = icmp ne i32 %x, 0			%tobool = icmp ne i32 %x, 0
	call void @callee1(i1 zeroext %tobool)			call void @callee1(i1 zeroext %tobool)
	ret void			ret void
	}			}

	define void @test2(i32 %x) #0 {			define void @test2(i32 %x) #0 {
	; CHECK-LABEL: test2:			; CHECK-LABEL: test2:
	; CHECK: # BB#0: # %entry			; CHECK: # BB#0: # %entry
	; CHECK-NEXT: pushq %rax			; CHECK-NEXT: pushq %rax
	; CHECK-NEXT: testl %edi, %edi			; CHECK-NEXT: testl %edi, %edi
	; CHECK-NEXT: setne %al			; CHECK-NEXT: setne %al
	; CHECK-NEXT: # implicit-def: %EDI			; CHECK-NEXT: movzbl %al, %edi
	; CHECK-NEXT: movb %al, %dil
	; CHECK-NEXT: andl $1, %edi
	; CHECK-NEXT: kmovd %edi, %k0
	; CHECK-NEXT: kmovd %k0, %edi
	; CHECK-NEXT: andl $1, %edi			; CHECK-NEXT: andl $1, %edi
	; CHECK-NEXT: movb %dil, %al			; CHECK-NEXT: negl %edi
	; CHECK-NEXT: xorl %edi, %edi
	; CHECK-NEXT: testb %al, %al
	; CHECK-NEXT: movl $-1, %ecx
	; CHECK-NEXT: cmovnel %ecx, %edi
	; CHECK-NEXT: callq callee2			; CHECK-NEXT: callq callee2
	; CHECK-NEXT: popq %rax			; CHECK-NEXT: popq %rax
	; CHECK-NEXT: retq			; CHECK-NEXT: retq
	entry:			entry:
	%tobool = icmp ne i32 %x, 0			%tobool = icmp ne i32 %x, 0
	call void @callee2(i1 signext %tobool)			call void @callee2(i1 signext %tobool)
	ret void			ret void
	}			}

	declare void @callee1(i1 zeroext)			declare void @callee1(i1 zeroext)
	declare void @callee2(i1 signext)			declare void @callee2(i1 signext)

	attributes #0 = { nounwind "target-cpu"="skylake-avx512" }			attributes #0 = { nounwind "target-cpu"="skylake-avx512" }

test/CodeGen/X86/pr28173.ll

	; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py			; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
	; RUN: llc < %s -mattr=+avx512f \| FileCheck %s --check-prefix=CHECK --check-prefix=KNL			; RUN: llc < %s -mattr=+avx512f \| FileCheck %s --check-prefix=CHECK --check-prefix=KNL
	; RUN: llc < %s -mattr=+avx512f,+avx512vl,+avx512bw,+avx512dq \| FileCheck %s --check-prefix=CHECK --check-prefix=SKX			; RUN: llc < %s -mattr=+avx512f,+avx512vl,+avx512bw,+avx512dq \| FileCheck %s --check-prefix=CHECK --check-prefix=SKX

	target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"			target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
	target triple = "x86_64-unknown-linux-gnu"			target triple = "x86_64-unknown-linux-gnu"

	define i64 @foo64(i1 zeroext %i) #0 {			define i64 @foo64(i1 zeroext %i) #0 {
	; CHECK-LABEL: foo64:			; CHECK-LABEL: foo64:
	; CHECK: # BB#0:			; CHECK: # BB#0:
	; CHECK-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>			; CHECK-NEXT: movzbl %dil, %eax
	; CHECK-NEXT: orq $-2, %rdi			; CHECK-NEXT: orq $-2, %rax
	; CHECK-NEXT: movq %rdi, %rax
	; CHECK-NEXT: retq			; CHECK-NEXT: retq
	br label %bb			br label %bb

	bb:			bb:
	%z = zext i1 %i to i64			%z = zext i1 %i to i64
	%v = or i64 %z, -2			%v = or i64 %z, -2
	br label %end			br label %end

	end:			end:
	ret i64 %v			ret i64 %v
	}			}

	define i16 @foo16(i1 zeroext %i) #0 {			define i16 @foo16(i1 zeroext %i) #0 {
	; CHECK-LABEL: foo16:			; CHECK-LABEL: foo16:
	; CHECK: # BB#0:			; CHECK: # BB#0:
	; CHECK-NEXT: orl $65534, %edi # imm = 0xFFFE			; CHECK-NEXT: movzbl %dil, %eax
	; CHECK-NEXT: movl %edi, %eax			; CHECK-NEXT: orl $65534, %eax # imm = 0xFFFE
				; CHECK-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
	; CHECK-NEXT: retq			; CHECK-NEXT: retq
	br label %bb			br label %bb

	bb:			bb:
	%z = zext i1 %i to i16			%z = zext i1 %i to i16
	%v = or i16 %z, -2			%v = or i16 %z, -2
	br label %end			br label %end

	end:			end:
	ret i16 %v			ret i16 %v
	}			}

	define i16 @foo16_1(i1 zeroext %i, i32 %j) #0 {			define i16 @foo16_1(i1 zeroext %i, i32 %j) #0 {
	; CHECK-LABEL: foo16_1:			; CHECK-LABEL: foo16_1:
	; CHECK: # BB#0:			; CHECK: # BB#0:
	; CHECK-NEXT: andl $1, %edi			; CHECK-NEXT: movzbl %dil, %eax
	; CHECK-NEXT: orl $2, %edi			; CHECK-NEXT: orl $2, %eax
	; CHECK-NEXT: movl %edi, %eax			; CHECK-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
	; CHECK-NEXT: retq			; CHECK-NEXT: retq
	br label %bb			br label %bb

	bb:			bb:
	%z = zext i1 %i to i16			%z = zext i1 %i to i16
	%v = or i16 %z, 2			%v = or i16 %z, 2
	br label %end			br label %end

	end:			end:
	ret i16 %v			ret i16 %v
	}			}

	define i32 @foo32(i1 zeroext %i) #0 {			define i32 @foo32(i1 zeroext %i) #0 {
	; CHECK-LABEL: foo32:			; CHECK-LABEL: foo32:
	; CHECK: # BB#0:			; CHECK: # BB#0:
	; CHECK-NEXT: orl $-2, %edi			; CHECK-NEXT: movzbl %dil, %eax
	; CHECK-NEXT: movl %edi, %eax			; CHECK-NEXT: orl $-2, %eax
	; CHECK-NEXT: retq			; CHECK-NEXT: retq
	br label %bb			br label %bb

	bb:			bb:
	%z = zext i1 %i to i32			%z = zext i1 %i to i32
	%v = or i32 %z, -2			%v = or i32 %z, -2
	br label %end			br label %end

	Show All 21 Lines

test/CodeGen/X86/pr32241.ll

	; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py			; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
	; RUN: llc < %s -fast-isel -mtriple=i686-unknown-unknown -O0 -mcpu=skx \| FileCheck %s			; RUN: llc < %s -fast-isel -mtriple=i686-unknown-unknown -O0 -mcpu=skx \| FileCheck %s

	define i32 @_Z3foov() {			define i32 @_Z3foov() {
	; CHECK-LABEL: _Z3foov:			; CHECK-LABEL: _Z3foov:
	; CHECK: # BB#0: # %entry			; CHECK: # BB#0: # %entry
	; CHECK-NEXT: subl $20, %esp			; CHECK-NEXT: pushl %esi
	; CHECK-NEXT: .Lcfi0:			; CHECK-NEXT: .Lcfi0:
	; CHECK-NEXT: .cfi_def_cfa_offset 24			; CHECK-NEXT: .cfi_def_cfa_offset 8
				; CHECK-NEXT: subl $24, %esp
				; CHECK-NEXT: .Lcfi1:
				; CHECK-NEXT: .cfi_def_cfa_offset 32
				; CHECK-NEXT: .Lcfi2:
				; CHECK-NEXT: .cfi_offset %esi, -8
				; CHECK-NEXT: movb $1, %al
	; CHECK-NEXT: movw $10959, {{[0-9]+}}(%esp) # imm = 0x2ACF			; CHECK-NEXT: movw $10959, {{[0-9]+}}(%esp) # imm = 0x2ACF
	; CHECK-NEXT: movw $-15498, {{[0-9]+}}(%esp) # imm = 0xC376			; CHECK-NEXT: movw $-15498, {{[0-9]+}}(%esp) # imm = 0xC376
	; CHECK-NEXT: movw $19417, {{[0-9]+}}(%esp) # imm = 0x4BD9			; CHECK-NEXT: movw $19417, {{[0-9]+}}(%esp) # imm = 0x4BD9
	; CHECK-NEXT: movzwl {{[0-9]+}}(%esp), %eax			; CHECK-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
	; CHECK-NEXT: movw {{[0-9]+}}(%esp), %cx			; CHECK-NEXT: cmpw $0, {{[0-9]+}}(%esp)
	; CHECK-NEXT: kxnorw %k0, %k0, %k0			; CHECK-NEXT: movl %ecx, {{[0-9]+}}(%esp) # 4-byte Spill
	; CHECK-NEXT: kshiftrw $15, %k0, %k0			; CHECK-NEXT: movb %al, {{[0-9]+}}(%esp) # 1-byte Spill
	; CHECK-NEXT: testw %cx, %cx
	; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp) # 4-byte Spill
	; CHECK-NEXT: kmovw %k0, {{[0-9]+}}(%esp) # 2-byte Spill
	; CHECK-NEXT: jne .LBB0_2			; CHECK-NEXT: jne .LBB0_2
	; CHECK-NEXT: jmp .LBB0_1			; CHECK-NEXT: # BB#1: # %lor.rhs
	; CHECK-NEXT: .LBB0_1: # %lor.rhs
	; CHECK-NEXT: xorl %eax, %eax			; CHECK-NEXT: xorl %eax, %eax
	; CHECK-NEXT: kmovd %eax, %k0			; CHECK-NEXT: kmovd %eax, %k0
	; CHECK-NEXT: kmovw %k0, {{[0-9]+}}(%esp) # 2-byte Spill			; CHECK-NEXT: kmovb %k0, %ecx
				; CHECK-NEXT: movb %cl, {{[0-9]+}}(%esp) # 1-byte Spill
	; CHECK-NEXT: jmp .LBB0_2			; CHECK-NEXT: jmp .LBB0_2
	; CHECK-NEXT: .LBB0_2: # %lor.end			; CHECK-NEXT: .LBB0_2: # %lor.end
	; CHECK-NEXT: kmovw {{[0-9]+}}(%esp), %k0 # 2-byte Reload			; CHECK-NEXT: movb {{[0-9]+}}(%esp), %al # 1-byte Reload
	; CHECK-NEXT: kxnorw %k0, %k0, %k1			; CHECK-NEXT: movb $1, %cl
	; CHECK-NEXT: kshiftrw $15, %k1, %k1			; CHECK-NEXT: andb $1, %al
	; CHECK-NEXT: movb $1, %al			; CHECK-NEXT: movzbl %al, %edx
	; CHECK-NEXT: testb %al, %al			; CHECK-NEXT: movl {{[0-9]+}}(%esp), %esi # 4-byte Reload
	; CHECK-NEXT: kmovw %k0, {{[0-9]+}}(%esp) # 2-byte Spill			; CHECK-NEXT: subl %edx, %esi
	; CHECK-NEXT: kmovw %k1, {{[0-9]+}}(%esp) # 2-byte Spill			; CHECK-NEXT: setl %al
				; CHECK-NEXT: andb $1, %al
				; CHECK-NEXT: movzbl %al, %edx
				; CHECK-NEXT: xorl $-1, %edx
				; CHECK-NEXT: cmpl $0, %edx
				; CHECK-NEXT: movl %esi, {{[0-9]+}}(%esp) # 4-byte Spill
				; CHECK-NEXT: movb %cl, {{[0-9]+}}(%esp) # 1-byte Spill
	; CHECK-NEXT: jne .LBB0_4			; CHECK-NEXT: jne .LBB0_4
	; CHECK-NEXT: jmp .LBB0_3			; CHECK-NEXT: # BB#3: # %lor.rhs4
	; CHECK-NEXT: .LBB0_3: # %lor.rhs4
	; CHECK-NEXT: xorl %eax, %eax			; CHECK-NEXT: xorl %eax, %eax
	; CHECK-NEXT: kmovd %eax, %k0			; CHECK-NEXT: kmovd %eax, %k0
	; CHECK-NEXT: kmovw %k0, {{[0-9]+}}(%esp) # 2-byte Spill			; CHECK-NEXT: kmovb %k0, %ecx
				; CHECK-NEXT: movb %cl, {{[0-9]+}}(%esp) # 1-byte Spill
	; CHECK-NEXT: jmp .LBB0_4			; CHECK-NEXT: jmp .LBB0_4
	; CHECK-NEXT: .LBB0_4: # %lor.end5			; CHECK-NEXT: .LBB0_4: # %lor.end5
	; CHECK-NEXT: kmovw {{[0-9]+}}(%esp), %k0 # 2-byte Reload			; CHECK-NEXT: movb {{[0-9]+}}(%esp), %al # 1-byte Reload
	; CHECK-NEXT: kmovd %k0, %eax			; CHECK-NEXT: andb $1, %al
	; CHECK-NEXT: andl $1, %eax			; CHECK-NEXT: movzbl %al, %ecx
	; CHECK-NEXT: movw %ax, %cx			; CHECK-NEXT: movw %cx, %dx
	; CHECK-NEXT: movw %cx, {{[0-9]+}}(%esp)			; CHECK-NEXT: movw %dx, {{[0-9]+}}(%esp)
	; CHECK-NEXT: movzwl {{[0-9]+}}(%esp), %eax			; CHECK-NEXT: movzwl {{[0-9]+}}(%esp), %eax
	; CHECK-NEXT: addl $20, %esp			; CHECK-NEXT: addl $24, %esp
				; CHECK-NEXT: popl %esi
	; CHECK-NEXT: retl			; CHECK-NEXT: retl
	entry:			entry:
	%aa = alloca i16, align 2			%aa = alloca i16, align 2
	%bb = alloca i16, align 2			%bb = alloca i16, align 2
	%cc = alloca i16, align 2			%cc = alloca i16, align 2
	store i16 10959, i16* %aa, align 2			store i16 10959, i16* %aa, align 2
	store i16 -15498, i16* %bb, align 2			store i16 -15498, i16* %bb, align 2
	store i16 19417, i16* %cc, align 2			store i16 19417, i16* %cc, align 2
	Show All 29 Lines

test/CodeGen/X86/pr32256.ll

	; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py			; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
	; RUN: llc < %s -fast-isel -mtriple=i686-unknown-unknown -O0 -mcpu=skx \| FileCheck %s			; RUN: llc < %s -fast-isel -mtriple=i686-unknown-unknown -O0 -mcpu=skx \| FileCheck %s

	@c = external global i8, align 1			@c = external global i8, align 1

	; Function Attrs: noinline nounwind			; Function Attrs: noinline nounwind
	define void @_Z1av() {			define void @_Z1av() {
	; CHECK-LABEL: _Z1av:			; CHECK-LABEL: _Z1av:
	; CHECK: # BB#0: # %entry			; CHECK: # BB#0: # %entry
	; CHECK-NEXT: subl $6, %esp			; CHECK-NEXT: subl $2, %esp
	; CHECK-NEXT: .Lcfi0:			; CHECK-NEXT: .Lcfi0:
	; CHECK-NEXT: .cfi_def_cfa_offset 10			; CHECK-NEXT: .cfi_def_cfa_offset 6
	; CHECK-NEXT: xorl %eax, %eax			; CHECK-NEXT: xorl %eax, %eax
	; CHECK-NEXT: kmovd %eax, %k0			; CHECK-NEXT: kmovd %eax, %k0
	; CHECK-NEXT: movb c, %cl			; CHECK-NEXT: movb c, %cl
	; CHECK-NEXT: # implicit-def: %EAX			; CHECK-NEXT: xorb $-1, %cl
	; CHECK-NEXT: movb %cl, %al
	; CHECK-NEXT: andl $1, %eax
	; CHECK-NEXT: kmovd %eax, %k1
	; CHECK-NEXT: kmovq %k1, %k2
	; CHECK-NEXT: kxnorw %k0, %k0, %k3
	; CHECK-NEXT: kshiftrw $15, %k3, %k3
	; CHECK-NEXT: kxorw %k3, %k1, %k1
	; CHECK-NEXT: kmovd %k1, %eax
	; CHECK-NEXT: movb %al, %cl
	; CHECK-NEXT: testb $1, %cl			; CHECK-NEXT: testb $1, %cl
	; CHECK-NEXT: kmovw %k2, {{[0-9]+}}(%esp) # 2-byte Spill			; CHECK-NEXT: kmovb %k0, %ecx
	; CHECK-NEXT: kmovw %k0, (%esp) # 2-byte Spill			; CHECK-NEXT: movb %cl, (%esp) # 1-byte Spill
	; CHECK-NEXT: jne .LBB0_1			; CHECK-NEXT: jne .LBB0_1
	; CHECK-NEXT: jmp .LBB0_2			; CHECK-NEXT: jmp .LBB0_2
	; CHECK-NEXT: .LBB0_1: # %land.rhs			; CHECK-NEXT: .LBB0_1: # %land.rhs
	; CHECK-NEXT: xorl %eax, %eax			; CHECK-NEXT: xorl %eax, %eax
	; CHECK-NEXT: kmovd %eax, %k0			; CHECK-NEXT: kmovd %eax, %k0
	; CHECK-NEXT: kmovw %k0, (%esp) # 2-byte Spill			; CHECK-NEXT: kmovb %k0, %ecx
				; CHECK-NEXT: movb %cl, (%esp) # 1-byte Spill
	; CHECK-NEXT: jmp .LBB0_2			; CHECK-NEXT: jmp .LBB0_2
	; CHECK-NEXT: .LBB0_2: # %land.end			; CHECK-NEXT: .LBB0_2: # %land.end
	; CHECK-NEXT: kmovw (%esp), %k0 # 2-byte Reload			; CHECK-NEXT: movb (%esp), %al # 1-byte Reload
	; CHECK-NEXT: kmovd %k0, %eax			; CHECK-NEXT: andb $1, %al
	; CHECK-NEXT: movb %al, %cl			; CHECK-NEXT: movb %al, {{[0-9]+}}(%esp)
	; CHECK-NEXT: andb $1, %cl			; CHECK-NEXT: addl $2, %esp
	; CHECK-NEXT: movb %cl, {{[0-9]+}}(%esp)
	; CHECK-NEXT: addl $6, %esp
	; CHECK-NEXT: retl			; CHECK-NEXT: retl
	entry:			entry:
	%b = alloca i8, align 1			%b = alloca i8, align 1
	%0 = load i8, i8* @c, align 1			%0 = load i8, i8* @c, align 1
	%tobool = trunc i8 %0 to i1			%tobool = trunc i8 %0 to i1
	%lnot = xor i1 %tobool, true			%lnot = xor i1 %tobool, true
	br i1 %lnot, label %land.rhs, label %land.end			br i1 %lnot, label %land.rhs, label %land.end

	Show All 9 Lines

test/CodeGen/X86/pr32284.ll

	Show All 34 Lines
	; X86-O0-NEXT: setne %cl			; X86-O0-NEXT: setne %cl
	; X86-O0-NEXT: movl %eax, %edx			; X86-O0-NEXT: movl %eax, %edx
	; X86-O0-NEXT: movb %dl, %ch			; X86-O0-NEXT: movb %dl, %ch
	; X86-O0-NEXT: testb %ch, %ch			; X86-O0-NEXT: testb %ch, %ch
	; X86-O0-NEXT: setne {{[0-9]+}}(%esp)			; X86-O0-NEXT: setne {{[0-9]+}}(%esp)
	; X86-O0-NEXT: movzbl %cl, %edx			; X86-O0-NEXT: movzbl %cl, %edx
	; X86-O0-NEXT: subl %eax, %edx			; X86-O0-NEXT: subl %eax, %edx
	; X86-O0-NEXT: setle %cl			; X86-O0-NEXT: setle %cl
	; X86-O0-NEXT: # implicit-def: %EAX
	; X86-O0-NEXT: movb %cl, %al
	; X86-O0-NEXT: andl $1, %eax
	; X86-O0-NEXT: kmovd %eax, %k0
	; X86-O0-NEXT: kmovd %k0, %eax
	; X86-O0-NEXT: movb %al, %cl
	; X86-O0-NEXT: andb $1, %cl			; X86-O0-NEXT: andb $1, %cl
	; X86-O0-NEXT: movzbl %cl, %eax			; X86-O0-NEXT: movzbl %cl, %eax
	; X86-O0-NEXT: movl %eax, {{[0-9]+}}(%esp)			; X86-O0-NEXT: movl %eax, {{[0-9]+}}(%esp)
	; X86-O0-NEXT: movl %edx, (%esp) # 4-byte Spill			; X86-O0-NEXT: movl %edx, (%esp) # 4-byte Spill
	; X86-O0-NEXT: addl $12, %esp			; X86-O0-NEXT: addl $12, %esp
	; X86-O0-NEXT: retl			; X86-O0-NEXT: retl
	;			;
	; X64-LABEL: foo:			; X64-LABEL: foo:
	Show All 18 Lines
	; X64-O0-NEXT: movl %ecx, %eax			; X64-O0-NEXT: movl %ecx, %eax
	; X64-O0-NEXT: testq %rcx, %rcx			; X64-O0-NEXT: testq %rcx, %rcx
	; X64-O0-NEXT: setne %sil			; X64-O0-NEXT: setne %sil
	; X64-O0-NEXT: testb %dl, %dl			; X64-O0-NEXT: testb %dl, %dl
	; X64-O0-NEXT: setne -{{[0-9]+}}(%rsp)			; X64-O0-NEXT: setne -{{[0-9]+}}(%rsp)
	; X64-O0-NEXT: movzbl %sil, %edi			; X64-O0-NEXT: movzbl %sil, %edi
	; X64-O0-NEXT: subl %eax, %edi			; X64-O0-NEXT: subl %eax, %edi
	; X64-O0-NEXT: setle %dl			; X64-O0-NEXT: setle %dl
	; X64-O0-NEXT: # implicit-def: %EAX
	; X64-O0-NEXT: movb %dl, %al
	; X64-O0-NEXT: andl $1, %eax
	; X64-O0-NEXT: kmovd %eax, %k0
	; X64-O0-NEXT: kmovd %k0, %eax
	; X64-O0-NEXT: movb %al, %dl
	; X64-O0-NEXT: andb $1, %dl			; X64-O0-NEXT: andb $1, %dl
	; X64-O0-NEXT: movzbl %dl, %eax			; X64-O0-NEXT: movzbl %dl, %eax
	; X64-O0-NEXT: movl %eax, -{{[0-9]+}}(%rsp)			; X64-O0-NEXT: movl %eax, -{{[0-9]+}}(%rsp)
	; X64-O0-NEXT: movl %edi, -{{[0-9]+}}(%rsp) # 4-byte Spill			; X64-O0-NEXT: movl %edi, -{{[0-9]+}}(%rsp) # 4-byte Spill
	; X64-O0-NEXT: retq			; X64-O0-NEXT: retq
	entry:			entry:
	%a = alloca i8, align 1			%a = alloca i8, align 1
	%b = alloca i32, align 4			%b = alloca i32, align 4
	Show All 21 Lines

test/CodeGen/X86/pr32451.ll

	Show All 19 Lines
	; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax			; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
	; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp) # 4-byte Spill			; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp) # 4-byte Spill
	; CHECK-NEXT: calll julia.gc_root_decl			; CHECK-NEXT: calll julia.gc_root_decl
	; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp) # 4-byte Spill			; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp) # 4-byte Spill
	; CHECK-NEXT: calll jl_get_ptls_states			; CHECK-NEXT: calll jl_get_ptls_states
	; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx # 4-byte Reload			; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx # 4-byte Reload
	; CHECK-NEXT: movl 4(%ecx), %edx			; CHECK-NEXT: movl 4(%ecx), %edx
	; CHECK-NEXT: movb (%edx), %bl			; CHECK-NEXT: movb (%edx), %bl
	; CHECK-NEXT: # implicit-def: %EDX
	; CHECK-NEXT: movb %bl, %dl
	; CHECK-NEXT: andl $1, %edx
	; CHECK-NEXT: kmovw %edx, %k0
	; CHECK-NEXT: kmovw %k0, %edx
	; CHECK-NEXT: movb %dl, %bl
	; CHECK-NEXT: andb $1, %bl			; CHECK-NEXT: andb $1, %bl
	; CHECK-NEXT: movzbl %bl, %edx			; CHECK-NEXT: movzbl %bl, %edx
	; CHECK-NEXT: movl %edx, (%esp)			; CHECK-NEXT: movl %edx, (%esp)
	; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp) # 4-byte Spill			; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp) # 4-byte Spill
	; CHECK-NEXT: calll jl_box_int32			; CHECK-NEXT: calll jl_box_int32
	; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx # 4-byte Reload			; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx # 4-byte Reload
	; CHECK-NEXT: movl %eax, (%ecx)			; CHECK-NEXT: movl %eax, (%ecx)
	; CHECK-NEXT: addl $16, %esp			; CHECK-NEXT: addl $16, %esp
	Show All 28 Lines

test/CodeGen/X86/sse-scalar-fp-arith.ll

	Show First 20 Lines • Show All 1,113 Lines • ▼ Show 20 Lines
	; AVX1-NEXT: # BB#1:			; AVX1-NEXT: # BB#1:
	; AVX1-NEXT: vaddss %xmm1, %xmm0, %xmm2			; AVX1-NEXT: vaddss %xmm1, %xmm0, %xmm2
	; AVX1-NEXT: .LBB62_2:			; AVX1-NEXT: .LBB62_2:
	; AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3]			; AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3]
	; AVX1-NEXT: retq			; AVX1-NEXT: retq
	;			;
	; AVX512-LABEL: add_ss_mask:			; AVX512-LABEL: add_ss_mask:
	; AVX512: # BB#0:			; AVX512: # BB#0:
	; AVX512-NEXT: andl $1, %edi			; AVX512-NEXT: vaddss %xmm1, %xmm0, %xmm1
	; AVX512-NEXT: kmovw %edi, %k1			; AVX512-NEXT: kmovw %edi, %k1
	; AVX512-NEXT: vaddss %xmm1, %xmm0, %xmm2 {%k1}			; AVX512-NEXT: vmovss %xmm1, %xmm0, %xmm2 {%k1}
	; AVX512-NEXT: vmovaps %xmm2, %xmm0			; AVX512-NEXT: vmovaps %xmm2, %xmm0
	; AVX512-NEXT: retq			; AVX512-NEXT: retq
	%1 = extractelement <4 x float> %a, i64 0			%1 = extractelement <4 x float> %a, i64 0
	%2 = extractelement <4 x float> %b, i64 0			%2 = extractelement <4 x float> %b, i64 0
	%3 = fadd float %1, %2			%3 = fadd float %1, %2
	%4 = extractelement <4 x float> %c, i32 0			%4 = extractelement <4 x float> %c, i32 0
	%5 = bitcast i8 %mask to <8 x i1>			%5 = bitcast i8 %mask to <8 x i1>
	%6 = extractelement <8 x i1> %5, i64 0			%6 = extractelement <8 x i1> %5, i64 0
	Show All 36 Lines
	; AVX1-NEXT: # BB#1:			; AVX1-NEXT: # BB#1:
	; AVX1-NEXT: vaddsd %xmm1, %xmm0, %xmm2			; AVX1-NEXT: vaddsd %xmm1, %xmm0, %xmm2
	; AVX1-NEXT: .LBB63_2:			; AVX1-NEXT: .LBB63_2:
	; AVX1-NEXT: vblendpd {{.*#+}} xmm0 = xmm2[0],xmm0[1]			; AVX1-NEXT: vblendpd {{.*#+}} xmm0 = xmm2[0],xmm0[1]
	; AVX1-NEXT: retq			; AVX1-NEXT: retq
	;			;
	; AVX512-LABEL: add_sd_mask:			; AVX512-LABEL: add_sd_mask:
	; AVX512: # BB#0:			; AVX512: # BB#0:
	; AVX512-NEXT: andl $1, %edi			; AVX512-NEXT: vaddsd %xmm1, %xmm0, %xmm1
	; AVX512-NEXT: kmovw %edi, %k1			; AVX512-NEXT: kmovw %edi, %k1
	; AVX512-NEXT: vaddsd %xmm1, %xmm0, %xmm2 {%k1}			; AVX512-NEXT: vmovsd %xmm1, %xmm0, %xmm2 {%k1}
	; AVX512-NEXT: vmovapd %xmm2, %xmm0			; AVX512-NEXT: vmovapd %xmm2, %xmm0
	; AVX512-NEXT: retq			; AVX512-NEXT: retq
	%1 = extractelement <2 x double> %a, i64 0			%1 = extractelement <2 x double> %a, i64 0
	%2 = extractelement <2 x double> %b, i64 0			%2 = extractelement <2 x double> %b, i64 0
	%3 = fadd double %1, %2			%3 = fadd double %1, %2
	%4 = extractelement <2 x double> %c, i32 0			%4 = extractelement <2 x double> %c, i32 0
	%5 = bitcast i8 %mask to <8 x i1>			%5 = bitcast i8 %mask to <8 x i1>
	%6 = extractelement <8 x i1> %5, i64 0			%6 = extractelement <8 x i1> %5, i64 0
	%7 = select i1 %6, double %3, double %4			%7 = select i1 %6, double %3, double %4
	%8 = insertelement <2 x double> %a, double %7, i64 0			%8 = insertelement <2 x double> %a, double %7, i64 0
	ret <2 x double> %8			ret <2 x double> %8
	}			}

test/CodeGen/X86/xmulo.ll

	Show First 20 Lines • Show All 706 Lines • ▼ Show 20 Lines
	; FAST-NEXT: movq %rdi, %rax			; FAST-NEXT: movq %rdi, %rax
	; FAST-NEXT: mulq %rcx			; FAST-NEXT: mulq %rcx
	; FAST-NEXT: seto %al			; FAST-NEXT: seto %al
	; FAST-NEXT: orb %sil, %al			; FAST-NEXT: orb %sil, %al
	; FAST-NEXT: retq			; FAST-NEXT: retq
	;			;
	; KNL-LABEL: bug27873:			; KNL-LABEL: bug27873:
	; KNL: ## BB#0:			; KNL: ## BB#0:
	; KNL-NEXT: andl $1, %esi
	; KNL-NEXT: movl $160, %ecx			; KNL-NEXT: movl $160, %ecx
	; KNL-NEXT: movq %rdi, %rax			; KNL-NEXT: movq %rdi, %rax
	; KNL-NEXT: mulq %rcx			; KNL-NEXT: mulq %rcx
	; KNL-NEXT: kmovw %esi, %k0
	; KNL-NEXT: seto %al			; KNL-NEXT: seto %al
	; KNL-NEXT: andl $1, %eax			; KNL-NEXT: orb %sil, %al
	; KNL-NEXT: kmovw %eax, %k1
	; KNL-NEXT: korw %k1, %k0, %k0
	; KNL-NEXT: kmovw %k0, %eax
	; KNL-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
	; KNL-NEXT: retq			; KNL-NEXT: retq
	%mul = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %c1, i64 160)			%mul = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %c1, i64 160)
	%mul.overflow = extractvalue { i64, i1 } %mul, 1			%mul.overflow = extractvalue { i64, i1 } %mul, 1
	%x1 = or i1 %c2, %mul.overflow			%x1 = or i1 %c2, %mul.overflow
	ret i1 %x1			ret i1 %x1
	}			}

	declare {i8, i1} @llvm.smul.with.overflow.i8 (i8, i8 ) nounwind readnone			declare {i8, i1} @llvm.smul.with.overflow.i8 (i8, i8 ) nounwind readnone
	Show All 9 Lines

test/CodeGen/X86/xor-select-i1-combine.ll

	; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py			; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
	;RUN: llc < %s -O2 -mattr=+avx512f -mtriple=x86_64-unknown \| FileCheck %s			;RUN: llc < %s -O2 -mattr=+avx512f -mtriple=x86_64-unknown \| FileCheck %s

	@n = common global i32 0, align 4			@n = common global i32 0, align 4
	@m = common global i32 0, align 4			@m = common global i32 0, align 4

	define i32 @main(i8 %small) {			define i32 @main(i8 %small) {
	; CHECK-LABEL: main:			; CHECK-LABEL: main:
	; CHECK: # BB#0: # %entry			; CHECK: # BB#0: # %entry
	; CHECK-NEXT: movl $n, %eax
	; CHECK-NEXT: movl $m, %ecx
	; CHECK-NEXT: testb $1, %dil			; CHECK-NEXT: testb $1, %dil
	; CHECK-NEXT: cmovneq %rax, %rcx			; CHECK-NEXT: movl $m, %eax
				; CHECK-NEXT: movl $n, %ecx
				; CHECK-NEXT: cmoveq %rax, %rcx
	; CHECK-NEXT: movl (%rcx), %eax			; CHECK-NEXT: movl (%rcx), %eax
	; CHECK-NEXT: retq			; CHECK-NEXT: retq
	entry:			entry:
	%0 = and i8 %small, 1			%0 = and i8 %small, 1
	%cmp = icmp eq i8 %0, 0			%cmp = icmp eq i8 %0, 0
	%m.n = select i1 %cmp, i32* @m, i32* @n			%m.n = select i1 %cmp, i32* @m, i32* @n
	%retval = load volatile i32, i32* %m.n, align 4			%retval = load volatile i32, i32* %m.n, align 4
	ret i32 %retval			ret i32 %retval
	Show All 19 Lines

test/TableGen/intrinsic-varargs.td

Show All 17 Lines	class Intrinsic<string name, list<LLVMType> param_types = []> {
bit isTarget = 0;		bit isTarget = 0;
string TargetPrefix = "";		string TargetPrefix = "";
list<LLVMType> RetTypes = [];		list<LLVMType> RetTypes = [];
list<LLVMType> ParamTypes = param_types;		list<LLVMType> ParamTypes = param_types;
list<IntrinsicProperty> IntrProperties = [];		list<IntrinsicProperty> IntrProperties = [];
}		}

// isVoid needs to match the definition in ValueTypes.td		// isVoid needs to match the definition in ValueTypes.td
def isVoid : ValueType<0, 66>; // Produces no value		def isVoid : ValueType<0, 67>; // Produces no value
def llvm_vararg_ty : LLVMType<isVoid>; // this means vararg here		def llvm_vararg_ty : LLVMType<isVoid>; // this means vararg here

// CHECK: /* 0 */ 0, 29, 0,		// CHECK: /* 0 */ 0, 29, 0,
def int_foo : Intrinsic<"llvm.foo", [llvm_vararg_ty]>;		def int_foo : Intrinsic<"llvm.foo", [llvm_vararg_ty]>;

utils/TableGen/CodeGenTarget.cpp

Show First 20 Lines • Show All 69 Lines • ▼ Show 20 Lines	StringRef llvm::getEnumName(MVT::SimpleValueType T) {
case MVT::f32: return "MVT::f32";		case MVT::f32: return "MVT::f32";
case MVT::f64: return "MVT::f64";		case MVT::f64: return "MVT::f64";
case MVT::f80: return "MVT::f80";		case MVT::f80: return "MVT::f80";
case MVT::f128: return "MVT::f128";		case MVT::f128: return "MVT::f128";
case MVT::ppcf128: return "MVT::ppcf128";		case MVT::ppcf128: return "MVT::ppcf128";
case MVT::x86mmx: return "MVT::x86mmx";		case MVT::x86mmx: return "MVT::x86mmx";
case MVT::Glue: return "MVT::Glue";		case MVT::Glue: return "MVT::Glue";
case MVT::isVoid: return "MVT::isVoid";		case MVT::isVoid: return "MVT::isVoid";
		case MVT::v1i1: return "MVT::v1i1";
case MVT::v2i1: return "MVT::v2i1";		case MVT::v2i1: return "MVT::v2i1";
case MVT::v4i1: return "MVT::v4i1";		case MVT::v4i1: return "MVT::v4i1";
case MVT::v8i1: return "MVT::v8i1";		case MVT::v8i1: return "MVT::v8i1";
case MVT::v16i1: return "MVT::v16i1";		case MVT::v16i1: return "MVT::v16i1";
case MVT::v32i1: return "MVT::v32i1";		case MVT::v32i1: return "MVT::v32i1";
case MVT::v64i1: return "MVT::v64i1";		case MVT::v64i1: return "MVT::v64i1";
case MVT::v512i1: return "MVT::v512i1";		case MVT::v512i1: return "MVT::v512i1";
case MVT::v1024i1: return "MVT::v1024i1";		case MVT::v1024i1: return "MVT::v1024i1";
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This is an archive of the discontinued LLVM Phabricator instance.

[X86][AVX512] Make i1 illegal in the CodeGenClosedPublic

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Diff Detail

Event Timeline

Revision Contents

Diff 95897

include/llvm/CodeGen/MachineValueType.h

include/llvm/CodeGen/ValueTypes.td

lib/IR/ValueTypes.cpp

lib/Target/X86/X86CallingConv.td

lib/Target/X86/X86ISelLowering.cpp

lib/Target/X86/X86InstrAVX512.td

lib/Target/X86/X86InstrFragmentsSIMD.td

lib/Target/X86/X86InstrInfo.cpp

lib/Target/X86/X86RegisterInfo.td

test/CodeGen/X86/avx512-cmp.ll

test/CodeGen/X86/avx512-cvt.ll

test/CodeGen/X86/avx512-ext.ll

test/CodeGen/X86/avx512-fsel.ll

test/CodeGen/X86/avx512-i1test.ll

test/CodeGen/X86/avx512-insert-extract.ll

test/CodeGen/X86/avx512-insert-extract_i1.ll

test/CodeGen/X86/avx512-intrinsics-upgrade.ll

test/CodeGen/X86/avx512-intrinsics.ll

test/CodeGen/X86/avx512-load-store.ll

test/CodeGen/X86/avx512-mask-bugfix.ll

test/CodeGen/X86/avx512-mask-op.ll

test/CodeGen/X86/avx512-memfold.ll

test/CodeGen/X86/avx512-regcall-NoMask.ll

test/CodeGen/X86/avx512-select.ll

test/CodeGen/X86/avx512dq-intrinsics-upgrade.ll

test/CodeGen/X86/avx512dq-intrinsics.ll

test/CodeGen/X86/avx512er-intrinsics.ll

test/CodeGen/X86/fast-isel-load-i1.ll

test/CodeGen/X86/fma-fneg-combine.ll

test/CodeGen/X86/masked_gather_scatter.ll

test/CodeGen/X86/pr27591.ll

test/CodeGen/X86/pr28173.ll

test/CodeGen/X86/pr32241.ll

test/CodeGen/X86/pr32256.ll

test/CodeGen/X86/pr32284.ll

test/CodeGen/X86/pr32451.ll

test/CodeGen/X86/sse-scalar-fp-arith.ll

test/CodeGen/X86/xmulo.ll

test/CodeGen/X86/xor-select-i1-combine.ll

test/TableGen/intrinsic-varargs.td

utils/TableGen/CodeGenTarget.cpp

[X86][AVX512] Make i1 illegal in the CodeGen
ClosedPublic