Subtarget support for parametrized register class information

[kparzysz]

Summary

Implement "checkFeatures" and emitting hw mode check code.

[asb]

Looks good to me.

[MatzeB]

llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h

113–114

Please add a comment to public API.

Looking at how getHwMode() is used at the moment I also wonder if you need this to be a virtual function in the base class. Right now it seems to be only ever calls from specific classes, so it may be enough to let tablegen generate it in the subclasses. That way maybe you can also use a more specific type than unsigned.

llvm/trunk/include/llvm/MC/MCSubtargetInfo.h

public:
   /// ToggleFeature - Toggle a set of features and returns the re-computed
   /// feature bits. This version will also change all implied bits.
   FeatureBitset ToggleFeature(StringRef FS);
 
   /// Apply a feature flag and return the re-computed feature bits, including
   /// all feature bits implied by the flag.
   FeatureBitset ApplyFeatureFlag(StringRef FS);
 
+  /// Check whether the subtarget features are enabled/disabled as per
+  /// the provided string, ignoring all other features.
+  bool checkFeatures(StringRef FS) const;
+
   /// getSchedModelForCPU - Get the machine model of a CPU.
   ///
   const MCSchedModel &getSchedModelForCPU(StringRef CPU) const;
 
   /// Get the machine model for this subtarget's CPU.
   const MCSchedModel &getSchedModel() const { return *CPUSchedModel; }
 
   /// Return an iterator at the first process resource consumed by the given

llvm/trunk/include/llvm/MC/SubtargetFeature.h

public:
   static void ApplyFeatureFlag(FeatureBitset &Bits, StringRef Feature,
                                ArrayRef<SubtargetFeatureKV> FeatureTable);
 
   /// Returns feature bits of a CPU.
   FeatureBitset getFeatureBits(StringRef CPU,
                                ArrayRef<SubtargetFeatureKV> CPUTable,
                                ArrayRef<SubtargetFeatureKV> FeatureTable);
 
+  /// Returns the vector of individual subtarget features.
+  const std::vector<std::string> &getFeatures() const { return Features; }
+
   /// Prints feature string.
   void print(raw_ostream &OS) const;
 
   // Dumps feature info.
   void dump() const;
 
   /// Adds the default features for the specified target triple.
   void getDefaultSubtargetFeatures(const Triple& Triple);
 };
 
 } // end namespace llvm
 
 #endif // LLVM_MC_SUBTARGETFEATURE_H

llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h

public:
   // FIXME: This lets targets specialize the selector by subtarget (which lets
   // us do things like a dedicated avx512 selector).  However, we might want
   // to also specialize selectors by MachineFunction, which would let us be
   // aware of optsize/optnone and such.
   virtual const InstructionSelector *getInstructionSelector() const {
     return nullptr;
   }
 
+  virtual unsigned getHwMode() const { return 0; }
+
   /// Target can subclass this hook to select a different DAG scheduler.
   virtual RegisterScheduler::FunctionPassCtor
       getDAGScheduler(CodeGenOpt::Level) const {
     return nullptr;
   }
 
   virtual const LegalizerInfo *getLegalizerInfo() const { return nullptr; }
 

llvm/trunk/lib/MC/MCSubtargetInfo.cpp

FeatureBitset MCSubtargetInfo::ToggleFeature(StringRef FS) {
   return FeatureBits;
 }
 
 FeatureBitset MCSubtargetInfo::ApplyFeatureFlag(StringRef FS) {
   SubtargetFeatures::ApplyFeatureFlag(FeatureBits, FS, ProcFeatures);
   return FeatureBits;
 }
 
+bool MCSubtargetInfo::checkFeatures(StringRef FS) const {
+  SubtargetFeatures T(FS);
+  FeatureBitset Set, All;
+  for (std::string F : T.getFeatures()) {
+    SubtargetFeatures::ApplyFeatureFlag(Set, F, ProcFeatures);
+    if (F[0] == '-')
+      F[0] = '+';
+    SubtargetFeatures::ApplyFeatureFlag(All, F, ProcFeatures);
+  }
+  return (FeatureBits & All) == Set;
+}
+
 const MCSchedModel &MCSubtargetInfo::getSchedModelForCPU(StringRef CPU) const {
   assert(ProcSchedModels && "Processor machine model not available!");
 
   ArrayRef<SubtargetInfoKV> SchedModels(ProcSchedModels, ProcDesc.size());
 
   assert(std::is_sorted(SchedModels.begin(), SchedModels.end(),
                     [](const SubtargetInfoKV &LHS, const SubtargetInfoKV &RHS) {
                       return strcmp(LHS.Key, RHS.Key) < 0;

llvm/trunk/utils/TableGen/SubtargetEmitter.cpp

class SubtargetEmitter {
 
   struct LessWriteProcResources {
     bool operator()(const MCWriteProcResEntry &LHS,
                     const MCWriteProcResEntry &RHS) {
       return LHS.ProcResourceIdx < RHS.ProcResourceIdx;
     }
   };
 
+  const CodeGenTarget &TGT;
   RecordKeeper &Records;
   CodeGenSchedModels &SchedModels;
   std::string Target;
 
   void Enumeration(raw_ostream &OS);
   unsigned FeatureKeyValues(raw_ostream &OS);
   unsigned CPUKeyValues(raw_ostream &OS);
   void FormItineraryStageString(const std::string &Names,
void ExpandProcResources(RecVec &PRVec, std::vector<int64_t> &Cycles,
                            const CodeGenProcModel &ProcModel);
   void GenSchedClassTables(const CodeGenProcModel &ProcModel,
                            SchedClassTables &SchedTables);
   void EmitSchedClassTables(SchedClassTables &SchedTables, raw_ostream &OS);
   void EmitProcessorModels(raw_ostream &OS);
   void EmitProcessorLookup(raw_ostream &OS);
   void EmitSchedModelHelpers(const std::string &ClassName, raw_ostream &OS);
   void EmitSchedModel(raw_ostream &OS);
+  void EmitHwModeCheck(const std::string &ClassName, raw_ostream &OS);
   void ParseFeaturesFunction(raw_ostream &OS, unsigned NumFeatures,
                              unsigned NumProcs);
 
 public:
-  SubtargetEmitter(RecordKeeper &R, CodeGenTarget &TGT):
-    Records(R), SchedModels(TGT.getSchedModels()), Target(TGT.getName()) {}
+  SubtargetEmitter(RecordKeeper &R, CodeGenTarget &TGT)
+    : TGT(TGT), Records(R), SchedModels(TGT.getSchedModels()),
+      Target(TGT.getName()) {}
 
   void run(raw_ostream &o);
 };
 
 } // end anonymous namespace
 
 //
 // Enumeration - Emit the specified class as an enumeration.
for (unsigned VC : VariantClasses) {
       OS << "    break;\n";
     }
     OS << "  };\n";
   }
   OS << "  report_fatal_error(\"Expected a variant SchedClass\");\n"
      << "} // " << ClassName << "::resolveSchedClass\n";
 }
 
+void SubtargetEmitter::EmitHwModeCheck(const std::string &ClassName,
+                                       raw_ostream &OS) {
+  const CodeGenHwModes &CGH = TGT.getHwModes();
+  assert(CGH.getNumModeIds() > 0);
+  if (CGH.getNumModeIds() == 1)
+    return;
+
+  OS << "unsigned " << ClassName << "::getHwMode() const {\n";
+  for (unsigned M = 1, NumModes = CGH.getNumModeIds(); M != NumModes; ++M) {
+    const HwMode &HM = CGH.getMode(M);
+    OS << "  if (checkFeatures(\"" << HM.Features
+       << "\")) return " << M << ";\n";
+  }
+  OS << "  return 0;\n}\n";
+}
+
 //
 // ParseFeaturesFunction - Produces a subtarget specific function for parsing
 // the subtarget features string.
 //
 void SubtargetEmitter::ParseFeaturesFunction(raw_ostream &OS,
                                              unsigned NumFeatures,
                                              unsigned NumProcs) {
   std::vector<Record*> Features =
#endif
   OS << "struct " << ClassName << " : public TargetSubtargetInfo {\n"
      << "  explicit " << ClassName << "(const Triple &TT, StringRef CPU, "
      << "StringRef FS);\n"
      << "public:\n"
      << "  unsigned resolveSchedClass(unsigned SchedClass, "
      << " const MachineInstr *DefMI,"
      << " const TargetSchedModel *SchedModel) const override;\n"
      << "  DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID)"
-     << " const;\n"
-     << "};\n";
-  OS << "} // end namespace llvm\n\n";
+     << " const;\n";
+  if (TGT.getHwModes().getNumModeIds() > 1)
+    OS << "  unsigned getHwMode() const override;\n";
+  OS << "};\n"
+     << "} // end namespace llvm\n\n";
 
   OS << "#endif // GET_SUBTARGETINFO_HEADER\n\n";
 
   OS << "\n#ifdef GET_SUBTARGETINFO_CTOR\n";
   OS << "#undef GET_SUBTARGETINFO_CTOR\n\n";
 
   OS << "#include \"llvm/CodeGen/TargetSchedule.h\"\n\n";
   OS << "namespace llvm {\n";
if (SchedModels.hasItineraries()) {
     OS << Target << "Stages, "
        << Target << "OperandCycles, "
        << Target << "ForwardingPaths";
   } else
     OS << "nullptr, nullptr, nullptr";
   OS << ") {}\n\n";
 
   EmitSchedModelHelpers(ClassName, OS);
+  EmitHwModeCheck(ClassName, OS);
 
   OS << "} // end namespace llvm\n\n";
 
   OS << "#endif // GET_SUBTARGETINFO_CTOR\n\n";
 }
 
 namespace llvm {
 
 void EmitSubtarget(RecordKeeper &RK, raw_ostream &OS) {
   CodeGenTarget CGTarget(RK);
   SubtargetEmitter(RK, CGTarget).run(OS);
 }
 
 } // end namespace llvm