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Differential D31589

[AMDGPU] Add A5 to data layout for amdgiz environment
ClosedPublic

Authored by yaxunl on Apr 2 2017, 7:43 PM.

Details

Reviewers
t-tye
arsenm
Commits
rGe95df719e1ee: [AMDGPU] Add A5 to data layout for amdgiz environment
rL299964: [AMDGPU] Add A5 to data layout for amdgiz environment
Summary

This patch changes alloca address space to be 5 for amdgiz environment.

It depends on https://reviews.llvm.org/D31042

Diff Detail

Repository
rL LLVM

Event Timeline

yaxunl created this revision.Apr 2 2017, 7:43 PM
Herald added subscribers: tpr, dstuttard, nhaehnle and 2 others. · View Herald TranscriptApr 2 2017, 7:43 PM
t-tye accepted this revision.Apr 2 2017, 11:18 PM

LGTM

This revision is now accepted and ready to land.Apr 2 2017, 11:18 PM
Closed by commit rL299964: [AMDGPU] Add A5 to data layout for amdgiz environment (authored by yaxunl). · Explain WhyApr 11 2017, 10:30 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
AMDGPU/
2 lines
test/
CodeGen/
AMDGPU/
2 lines
2 lines

Diff 94854

llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

Show First 20 Lines • Show All 208 Lines • ▼ Show 20 Linesstatic StringRef computeDataLayout(const Triple &TT) {
} }
// 32-bit private, local, and region pointers. 64-bit global, constant and // 32-bit private, local, and region pointers. 64-bit global, constant and
// flat. // flat.
if (TT.getEnvironmentName() == "amdgiz" || if (TT.getEnvironmentName() == "amdgiz" ||
TT.getEnvironmentName() == "amdgizcl") TT.getEnvironmentName() == "amdgizcl")
return "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32" return "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32"
"-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
"-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5";
return "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32" return "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32"
"-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
"-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
} }
LLVM_READNONE LLVM_READNONE
static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) { static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
if (!GPU.empty()) if (!GPU.empty())
▲ Show 20 Lines • Show All 598 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/AMDGPU/env-amdgiz.ll

; RUN: llc -march=amdgcn -mtriple=amdgcn-amd-amdhsa-amdgiz -verify-machineinstrs < %s ; RUN: llc -march=amdgcn -mtriple=amdgcn-amd-amdhsa-amdgiz -verify-machineinstrs < %s
; Just check the target feature and data layout is accepted without error. ; Just check the target feature and data layout is accepted without error.
target datalayout = "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64" target datalayout = "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5"
target triple = "amdgcn-amd-amdhsa-amdgiz" target triple = "amdgcn-amd-amdhsa-amdgiz"
define void @foo() { define void @foo() {
entry: entry:
ret void ret void
} }

llvm/trunk/test/CodeGen/AMDGPU/env-amdgizcl.ll

; RUN: llc -march=amdgcn -mtriple=amdgcn-amd-amdhsa-amdgizcl -verify-machineinstrs < %s ; RUN: llc -march=amdgcn -mtriple=amdgcn-amd-amdhsa-amdgizcl -verify-machineinstrs < %s
; Just check the target feature and data layout is accepted without error. ; Just check the target feature and data layout is accepted without error.
target datalayout = "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64" target datalayout = "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5"
target triple = "amdgcn-amd-amdhsa-amdgizcl" target triple = "amdgcn-amd-amdhsa-amdgizcl"
define void @foo() { define void @foo() {
entry: entry:
ret void ret void
} }