[PowerPC] Pretty-print CR bits the way the binutils disassembler does

[nemanjai]

Summary

This is a small patch that allows the PPC back end to print these registers in a more human-readable form the way the binutils tools print them.

I'm not sure if anyone uses this option much, but it's nice to have when debugging.

[hfinkel]

This seems like a good thing to do.

lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp

451 ↗

(On Diff #93464)

This ShowVSRNumsAsVR seems broken ; should we just get rid of it?

453 ↗

(On Diff #93464)

Hrmm. Is TRI available here? The real way of doing this is to get the encoding value for the register. From PPCAsmPrinter.cpp, for example, we have this:

unsigned Mask = 0x80 >> OutContext.getRegisterInfo()
                        ->getEncodingValue(MI->getOperand(0).getReg());

It is possible that just using MRI.getEncodingValue(RegNum) will work here. It looks like it might (MCInstPrinter has an MRI protected member, and because the encoding values come from TableGen, I think that MCRegisterInfo should have them).

[echristo]

Were we going to pick this up again? Still seems useful.

[nemanjai]

lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp

451 ↗

(On Diff #93464)

Can you elaborate a bit on why you feel it's broken? It should just display things like vs34 as v2 and we use it here just to prevent the v from getting stripped from the output.

453 ↗

(On Diff #93464)

Ah, thanks for the pointer. This makes perfect sense.

[nemanjai]

Updated to use the actual register encoding that comes from the MRI rather than converting the string representation.

[hfinkel]

lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp

451 ↗

(On Diff #93464)

I should have been more specific. I meant that it seems incorrect that ShowVSRNumsAsVR is equivalent to FullRegNames here (it is affecting much more than just the vector registers).

[nemanjai]

lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp

451 ↗

(On Diff #93464)

Ah, that makes sense. Basically get rid of the semantics where ShowVSRNumsAsVR implies FullRegNames.

[nemanjai]

Removed the "show vsr nums as vr" implies "print full register names" semantics.

[nemanjai]

Ping.

[echristo]

LGTM.

-eric

llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp

if (useSubstituteMnemonic) {
       O << ", ";
       printOperand(MI, 1, O);
       O << ", " << (unsigned int)SH;
 
       printAnnotation(O, Annot);
       return;
     }
   }
-  
   if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) &&
       MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
     O << "\tmr ";
     printOperand(MI, 0, O);
     O << ", ";
     printOperand(MI, 1, O);
     printAnnotation(O, Annot);
     return;
   }
-  
   if (MI->getOpcode() == PPC::RLDICR ||
       MI->getOpcode() == PPC::RLDICR_32) {
     unsigned char SH = MI->getOperand(2).getImm();
     unsigned char ME = MI->getOperand(3).getImm();
     // rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
     if (63-SH == ME) {
       O << "\tsldi ";
       printOperand(MI, 0, O);
if (!L || L == 1 || L == 3) {
       printOperand(MI, 1, O);
       O << ", ";
       printOperand(MI, 2, O);
 
       printAnnotation(O, Annot);
       return;
     }
   }
-  
   if (!printAliasInstr(MI, O))
     printInstruction(MI, O);
   printAnnotation(O, Annot);
 }
 
 
 void PPCInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,
                                            raw_ostream &O, 
case PPC::PRED_NU_PLUS:
       O << "+";
       return;
     case PPC::PRED_BIT_SET:
     case PPC::PRED_BIT_UNSET:
       llvm_unreachable("Invalid use of bit predicate code");
     }
     llvm_unreachable("Invalid predicate code");
   }
-  
   assert(StringRef(Modifier) == "reg" &&
          "Need to specify 'cc', 'pm' or 'reg' as predicate op modifier!");
   printOperand(MI, OpNo+1, O);
 }
 
 void PPCInstPrinter::printATBitsAsHint(const MCInst *MI, unsigned OpNo,
                                        raw_ostream &O) {
   unsigned Code = MI->getOperand(OpNo).getImm();
void PPCInstPrinter::printTLSCall(const MCInst *MI, unsigned OpNo,
   O << ')';
   if (refExp.getKind() != MCSymbolRefExpr::VK_None)
     O << '@' << MCSymbolRefExpr::getVariantKindName(refExp.getKind());
 }
 
 
 /// stripRegisterPrefix - This method strips the character prefix from a
 /// register name so that only the number is left.  Used by for linux asm.
-static const char *stripRegisterPrefix(const char *RegName) {
-  if (FullRegNames || ShowVSRNumsAsVR)
+static const char *stripRegisterPrefix(const char *RegName, unsigned RegNum,
+                                       unsigned RegEncoding) {
+  if (FullRegNames) {
+    if (RegNum >= PPC::CR0EQ && RegNum <= PPC::CR7UN) {
+      const char *CRBits[] =
+      { "lt", "gt", "eq", "un",
+        "4*cr1+lt", "4*cr1+gt", "4*cr1+eq", "4*cr1+un",
+        "4*cr2+lt", "4*cr2+gt", "4*cr2+eq", "4*cr2+un",
+        "4*cr3+lt", "4*cr3+gt", "4*cr3+eq", "4*cr3+un",
+        "4*cr4+lt", "4*cr4+gt", "4*cr4+eq", "4*cr4+un",
+        "4*cr5+lt", "4*cr5+gt", "4*cr5+eq", "4*cr5+un",
+        "4*cr6+lt", "4*cr6+gt", "4*cr6+eq", "4*cr6+un",
+        "4*cr7+lt", "4*cr7+gt", "4*cr7+eq", "4*cr7+un"
+      };
+      return CRBits[RegEncoding];
+    }
     return RegName;
+  }
 
   switch (RegName[0]) {
   case 'r':
   case 'f':
   case 'q': // for QPX
   case 'v':
     if (RegName[1] == 's')
       return RegName + 2;
     return RegName + 1;
   case 'c': if (RegName[1] == 'r') return RegName + 2;
   }
-  
   return RegName;
 }
 
 void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
                                   raw_ostream &O) {
   const MCOperand &Op = MI->getOperand(OpNo);
   if (Op.isReg()) {
     unsigned Reg = Op.getReg();
if ((MII.get(MI->getOpcode()).TSFlags & PPCII::UseVSXReg) &&
         Reg = PPC::VSX32 + (Reg - PPC::V0);
       else if (PPCInstrInfo::isVFRegister(Reg))
         Reg = PPC::VSX32 + (Reg - PPC::VF0);
     }
 
     const char *RegName = getRegisterName(Reg);
     // The linux and AIX assembler does not take register prefixes.
     if (!isDarwinSyntax())
-      RegName = stripRegisterPrefix(RegName);
-    
+      RegName = stripRegisterPrefix(RegName, Reg, MRI.getEncodingValue(Reg));
     O << RegName;
     return;
   }
-  
   if (Op.isImm()) {
     O << Op.getImm();
     return;
   }
-  
   assert(Op.isExpr() && "unknown operand kind in printOperand");
   Op.getExpr()->print(O, &MAI);
 }
 

llvm/trunk/test/CodeGen/PowerPC/build-vector-tests.ll

-; RUN: llc -mcpu=pwr9 -ppc-vsr-nums-as-vr -mtriple=powerpc64-unknown-unknown \
-; RUN:   < %s | FileCheck %s -check-prefix=P9BE -implicit-check-not frsp
-; RUN: llc -mcpu=pwr9 -ppc-vsr-nums-as-vr -mtriple=powerpc64le-unknown-unknown \
-; RUN:   < %s | FileCheck %s -check-prefix=P9LE -implicit-check-not frsp
-; RUN: llc -mcpu=pwr8 -ppc-vsr-nums-as-vr -mtriple=powerpc64-unknown-unknown \
-; RUN:   < %s | FileCheck %s -check-prefix=P8BE -implicit-check-not frsp
-; RUN: llc -mcpu=pwr8 -ppc-vsr-nums-as-vr -mtriple=powerpc64le-unknown-unknown \
-; RUN:   < %s | FileCheck %s -check-prefix=P8LE -implicit-check-not frsp
+; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN:   -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \
+; RUN:   -check-prefix=P9BE -implicit-check-not frsp
+; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN:   -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \
+; RUN:   -check-prefix=P9LE -implicit-check-not frsp
+; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN:   -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \
+; RUN:   -check-prefix=P8BE -implicit-check-not frsp
+; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN:   -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \
+; RUN:   -check-prefix=P8LE -implicit-check-not frsp
 
 ; This test case comes from the following C test case (included as it may be
 ; slightly more readable than the LLVM IR.
 
 ;/*  This test case provides various ways of building vectors to ensure we
 ;    produce optimal code for all cases. The cases are (for each type):
 ;    - All zeros
 ;    - All ones

llvm/trunk/test/CodeGen/PowerPC/expand-contiguous-isel.ll

_ZNK4llvm9StringRef6substrEmm.exit:               ; preds = %_ZNK4llvm9StringRef6substrEmm.exit.loopexit132, %_ZNK4llvm9StringRef6substrEmm.exit.loopexit, %if.end10
   %sub.i = add i64 %.sink76, -1
   %add.ptr.i = getelementptr inbounds i8, i8* %7, i64 1
   %8 = ptrtoint i8* %add.ptr.i to i64
   br label %while.cond.outer
 
 ; CHECK-LABEL: @_Z3fn1N4llvm9StringRefE
 ; CHECK-GEN-ISEL-TRUE: isel [[SAME:r[0-9]+]], [[SAME]], [[SAME]]
 ; CHECK-GEN-ISEL-TRUE: isel [[SAME:r[0-9]+]], {{r[0-9]+}}, [[SAME]]
-; CHECK: bc 12, 2, [[TRUE:.LBB[0-9]+]]
+; CHECK: bc 12, eq, [[TRUE:.LBB[0-9]+]]
 ; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
 ; CHECK-NEXT: [[TRUE]]
 ; CHECK-NEXT: addi {{r[0-9]+}}, {{r[0-9]+}}, 0
 ; CHECK-NEXT: [[SUCCESSOR]]
 }
 
 
 

llvm/trunk/test/CodeGen/PowerPC/expand-isel.ll

 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 ; RUN: llc -verify-machineinstrs -O2 -ppc-asm-full-reg-names -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck %s --implicit-check-not isel
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @testExpandISELToIfElse(i32 signext %i, i32 signext %j) {
 entry:
   %cmp = icmp sgt i32 %i, 0
   %add = add nsw i32 %i, 1
   %cond = select i1 %cmp, i32 %add, i32 %j
   ret i32 %cond
 
 ; CHECK-LABEL: @testExpandISELToIfElse
 ; CHECK: addi r5, r3, 1
 ; CHECK-NEXT: cmpwi cr0, r3, 0
-; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
 ; CHECK: ori r3, r4, 0
 ; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
 ; CHECK-NEXT:  [[TRUE]]
 ; CHECK-NEXT: addi r3, r5, 0
 ; CHECK-NEXT: [[SUCCESSOR]]
 ; CHECK-NEXT: extsw r3, r3
 ; CHECK-NEXT: blr
 }
 
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @testExpandISELToIf(i32 signext %i, i32 signext %j) {
 entry:
   %cmp = icmp sgt i32 %i, 0
   %cond = select i1 %cmp, i32 %j, i32 %i
   ret i32 %cond
 
 ; CHECK-LABEL: @testExpandISELToIf
 ; CHECK: cmpwi   r3, 0
-; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
 ; CHECK-NEXT: blr
 ; CHECK-NEXT:  [[TRUE]]
 ; CHECK-NEXT: addi r3, r4, 0
 ; CHECK-NEXT: blr
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @testExpandISELToElse(i32 signext %i, i32 signext %j) {
 entry:
   %cmp = icmp sgt i32 %i, 0
   %cond = select i1 %cmp, i32 %i, i32 %j
   ret i32 %cond
 
 ; CHECK-LABEL: @testExpandISELToElse
 ; CHECK: cmpwi   r3, 0
-; CHECK-NEXT: bclr 12, 1, 0
+; CHECK-NEXT: bclr 12, gt, 0
 ; CHECK: ori r3, r4, 0
 ; CHECK-NEXT: blr
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @testReplaceISELWithCopy(i32 signext %i, i32 signext %j) {
 entry:
   %cmp = icmp sgt i32 %i, 0
entry:
   %cmp = icmp sgt i32 %g, 0
   %a.b = select i1 %cmp, i32 %g, i32 %b
   %d.f = select i1 %cmp, i32 %d, i32 %f
   %add = add nsw i32 %a.b, %d.f
   ret i32 %add
 
 ; CHECK-LABEL: @testExpandISELsTo2ORIs2ADDIs
 ; CHECK: cmpwi r7, 0
-; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
 ; CHECK: ori r3, r4, 0
 ; CHECK-NEXT: ori r12, r6, 0
 ; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
 ; CHECK-NEXT:  [[TRUE]]
 ; CHECK-NEXT: addi r3, r7, 0
 ; CHECK-NEXT: addi r12, r5, 0
 ; CHECK-NEXT: [[SUCCESSOR]]
 ; CHECK-NEXT: add r3, r3, r12
entry:
   %cmp = icmp sgt i32 %g, 0
   %a.b = select i1 %cmp, i32 %a, i32 %b
   %d.f = select i1 %cmp, i32 %d, i32 %f
   %add = add nsw i32 %a.b, %d.f
   ret i32 %add
 
 ; CHECK-LABEL: @testExpandISELsTo2ORIs1ADDI
 ; CHECK: cmpwi cr0, r7, 0
-; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
 ; CHECK: ori r3, r4, 0
 ; CHECK-NEXT: ori r12, r6, 0
 ; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
 ; CHECK-NEXT: [[TRUE]]
 ; CHECK-NEXT: addi r12, r5, 0
 ; CHECK-NEXT:  [[SUCCESSOR]]
 ; CHECK-NEXT: add r3, r3, r12
 ; CHECK-NEXT: extsw r3, r3
entry:
   %a.b = select i1 %cmp, i32 %a, i32 %b
   %d.f = select i1 %cmp, i32 %d, i32 %f
   %add1 = add nsw i32 %a.b, %d.f
   %add2 = add nsw i32 %a, %add1
   ret i32 %add2
 
 ; CHECK-LABEL: @testExpandISELsTo1ORI1ADDI
 ; CHECK: cmpwi cr0, r7, 0
-; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
 ; CHECK: ori r5, r6, 0
 ; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
 ; CHECK-NEXT: [[TRUE]]
 ; CHECK-NEXT: addi r4, r3, 0
 ; CHECK-NEXT:  [[SUCCESSOR]]
 ; CHECK-NEXT: add r4, r4, r5
 ; CHECK-NEXT: add r3, r3, r4
 ; CHECK-NEXT: extsw r3, r3
entry:
   %d.f = select i1 %cmp, i32 %d, i32 %f
   %add1 = add nsw i32 %a.b, %d.f
   %add2 = add nsw i32 %a, %add1
   %sub1 = sub nsw i32 %add2, %d
   ret i32 %sub1
 
 ; CHECK-LABEL: @testExpandISELsTo0ORI2ADDIs
 ; CHECK: cmpwi cr0, r7, 0
-; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
 ; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
 ; CHECK-NEXT:  [[TRUE]]
 ; CHECK-NEXT: addi r4, r3, 0
 ; CHECK-NEXT: addi r6, r5, 0
 ; CHECK-NEXT:  [[SUCCESSOR]]
 ; CHECK-NEXT: add r4, r4, r6
 ; CHECK-NEXT: add r3, r3, r4
 ; CHECK-NEXT: subf r3, r5, r3

llvm/trunk/test/CodeGen/PowerPC/logic-ops-on-compares.ll

 ; CHECK-NEXT:    li r6, 55
 ; CHECK-NEXT:    xor r5, r5, r6
 ; CHECK-NEXT:    or r7, r7, r4
 ; CHECK-NEXT:    cntlzw r5, r5
 ; CHECK-NEXT:    cntlzw r6, r7
 ; CHECK-NEXT:    srwi r6, r6, 5
 ; CHECK-NEXT:    srwi r5, r5, 5
 ; CHECK-NEXT:    or. r5, r6, r5
-; CHECK-NEXT:    bc 4, 1
+; CHECK-NEXT:    bc 4, gt
 entry:
   %tobool = icmp eq i32 %a, %b
   %tobool1 = icmp eq i32 %b, 0
   %or.cond = and i1 %tobool, %tobool1
   %tobool3 = icmp eq i32 %c, 55
   %or.cond5 = or i1 %or.cond, %tobool3
   br i1 %or.cond5, label %if.end, label %if.then
 
return:                                           ; preds = %if.end, %if.then
   ret i32 %retval.0
 }
 
 define void @neg_truncate_i32_eq(i32 *%ptr) {
 ; CHECK-LABEL: neg_truncate_i32_eq:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    lwz r3, 0(r3)
 ; CHECK-NEXT:    rldicl. r3, r3, 0, 63
-; CHECK-NEXT:    bclr 12, 2, 0
+; CHECK-NEXT:    bclr 12, eq, 0
 ; CHECK-NEXT:  # BB#1: # %if.end29.thread136
 ; CHECK-NEXT:  .LBB1_2: # %if.end29
 entry:
   %0 = load i32, i32* %ptr, align 4
   %rem17127 = and i32 %0, 1
   %cmp18 = icmp eq i32 %rem17127, 0
   br label %if.else
 

 ; CHECK-NEXT:    li r6, 55
 ; CHECK-NEXT:    xor r5, r5, r6
 ; CHECK-NEXT:    or r7, r7, r4
 ; CHECK-NEXT:    cntlzd r6, r7
 ; CHECK-NEXT:    cntlzd r5, r5
 ; CHECK-NEXT:    rldicl r6, r6, 58, 63
 ; CHECK-NEXT:    rldicl r5, r5, 58, 63
 ; CHECK-NEXT:    or. r5, r6, r5
-; CHECK-NEXT:    bc 4, 1
+; CHECK-NEXT:    bc 4, gt
 entry:
   %tobool = icmp eq i64 %a, %b
   %tobool1 = icmp eq i64 %b, 0
   %or.cond = and i1 %tobool, %tobool1
   %tobool3 = icmp eq i64 %c, 55
   %or.cond5 = or i1 %or.cond, %tobool3
   br i1 %or.cond5, label %if.end, label %if.then
 
return:                                           ; preds = %if.end, %if.then
   ret i64 %retval.0
 }
 
 define void @neg_truncate_i64_eq(i64 *%ptr) {
 ; CHECK-LABEL: neg_truncate_i64_eq:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    ld r3, 0(r3)
 ; CHECK-NEXT:    rldicl. r3, r3, 0, 63
-; CHECK-NEXT:    bclr 12, 2, 0
+; CHECK-NEXT:    bclr 12, eq, 0
 ; CHECK-NEXT:  # BB#1: # %if.end29.thread136
 ; CHECK-NEXT:  .LBB3_2: # %if.end29
 entry:
   %0 = load i64, i64* %ptr, align 4
   %rem17127 = and i64 %0, 1
   %cmp18 = icmp eq i64 %rem17127, 0
   br label %if.else
 

 ; CHECK-NEXT:    xor r5, r5, r6
 ; CHECK-NEXT:    subfe r7, r8, r7
 ; CHECK-NEXT:    cntlzd r5, r5
 ; CHECK-NEXT:    addic r12, r4, -1
 ; CHECK-NEXT:    rldicl r5, r5, 58, 63
 ; CHECK-NEXT:    subfe r6, r12, r4
 ; CHECK-NEXT:    and r6, r7, r6
 ; CHECK-NEXT:    or. r5, r6, r5
-; CHECK-NEXT:    bc 4, 1
+; CHECK-NEXT:    bc 4, gt
 entry:
   %tobool = icmp ne i64 %a, %b
   %tobool1 = icmp ne i64 %b, 0
   %or.cond = and i1 %tobool, %tobool1
   %tobool3 = icmp eq i64 %c, 55
   %or.cond5 = or i1 %or.cond, %tobool3
   br i1 %or.cond5, label %if.end, label %if.then
 
return:                                           ; preds = %if.end, %if.then
   ret i64 %retval.0
 }
 
 define void @neg_truncate_i64_ne(i64 *%ptr) {
 ; CHECK-LABEL: neg_truncate_i64_ne:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    ld r3, 0(r3)
 ; CHECK-NEXT:    andi. r3, r3, 1
-; CHECK-NEXT:    bclr 12, 1, 0
+; CHECK-NEXT:    bclr 12, gt, 0
 ; CHECK-NEXT:  # BB#1: # %if.end29.thread136
 ; CHECK-NEXT:  .LBB5_2: # %if.end29
 entry:
   %0 = load i64, i64* %ptr, align 4
   %rem17127 = and i64 %0, 1
   %cmp18 = icmp ne i64 %rem17127, 0
   br label %if.else
 

llvm/trunk/test/CodeGen/PowerPC/mtvsrdd.ll

-; RUN: llc -mcpu=pwr9 -ppc-vsr-nums-as-vr -mtriple=powerpc64le-unknown-unknown \
-; RUN:   < %s | FileCheck %s
+; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN:   -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
 
 ; This test case checks r0 is used as constant 0 in instruction mtvsrdd.
 
 define <2 x i64> @const0(i64 %a) {
   %vecinit = insertelement <2 x i64> undef, i64 %a, i32 0
   %vecinit1 = insertelement <2 x i64> %vecinit, i64 0, i32 1
   ret <2 x i64> %vecinit1
 ; CHECK-LABEL: const0

llvm/trunk/test/CodeGen/PowerPC/ppc64-i128-abi.ll

 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-BE-NOVSX
 
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr8 -mattr=-vsx < %s | \
 ; RUN:   FileCheck %s -check-prefix=CHECK-LE-NOVSX --implicit-check-not xxswapd
 
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
-; RUN:   -mcpu=pwr9 -ppc-vsr-nums-as-vr < %s | FileCheck %s \
-; RUN:   -check-prefix=CHECK-P9 --implicit-check-not xxswapd
+; RUN:   -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN:   FileCheck %s -check-prefix=CHECK-P9 --implicit-check-not xxswapd
 
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr9 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-NOVSX \
 ; RUN:   --implicit-check-not xxswapd
 
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr9 -mattr=-power9-vector -mattr=-direct-move < %s | \
 ; RUN:   FileCheck %s -check-prefix=CHECK-LE --implicit-check-not xxswapd