[PowerPC] Pretty-print CR bits the way the binutils disassembler does

[nemanjai]

Summary

This is a small patch that allows the PPC back end to print these registers in a more human-readable form the way the binutils tools print them.

I'm not sure if anyone uses this option much, but it's nice to have when debugging.

[hfinkel]

This seems like a good thing to do.

lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp

452

This ShowVSRNumsAsVR seems broken ; should we just get rid of it?

454

Hrmm. Is TRI available here? The real way of doing this is to get the encoding value for the register. From PPCAsmPrinter.cpp, for example, we have this:

unsigned Mask = 0x80 >> OutContext.getRegisterInfo()
                        ->getEncodingValue(MI->getOperand(0).getReg());

It is possible that just using MRI.getEncodingValue(RegNum) will work here. It looks like it might (MCInstPrinter has an MRI protected member, and because the encoding values come from TableGen, I think that MCRegisterInfo should have them).

[echristo]

Were we going to pick this up again? Still seems useful.

[nemanjai]

lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp

452

Can you elaborate a bit on why you feel it's broken? It should just display things like vs34 as v2 and we use it here just to prevent the v from getting stripped from the output.

454

Ah, thanks for the pointer. This makes perfect sense.

[nemanjai]

Updated to use the actual register encoding that comes from the MRI rather than converting the string representation.

[hfinkel]

lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp

452

I should have been more specific. I meant that it seems incorrect that ShowVSRNumsAsVR is equivalent to FullRegNames here (it is affecting much more than just the vector registers).

[nemanjai]

lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp

452

Ah, that makes sense. Basically get rid of the semantics where ShowVSRNumsAsVR implies FullRegNames.

[nemanjai]

Removed the "show vsr nums as vr" implies "print full register names" semantics.

[nemanjai]

Ping.

[echristo]

LGTM.

-eric

lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp

if (useSubstituteMnemonic) {
       O << ", ";
       printOperand(MI, 1, O);
       O << ", " << (unsigned int)SH;
 
       printAnnotation(O, Annot);
       return;
     }
   }
-  
   if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) &&
       MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
     O << "\tmr ";
     printOperand(MI, 0, O);
     O << ", ";
     printOperand(MI, 1, O);
     printAnnotation(O, Annot);
     return;
   }
-  
   if (MI->getOpcode() == PPC::RLDICR ||
       MI->getOpcode() == PPC::RLDICR_32) {
     unsigned char SH = MI->getOperand(2).getImm();
     unsigned char ME = MI->getOperand(3).getImm();
     // rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
     if (63-SH == ME) {
       O << "\tsldi ";
       printOperand(MI, 0, O);
if (!L || L == 1 || L == 3) {
       printOperand(MI, 1, O);
       O << ", ";
       printOperand(MI, 2, O);
 
       printAnnotation(O, Annot);
       return;
     }
   }
-  
   if (!printAliasInstr(MI, O))
     printInstruction(MI, O);
   printAnnotation(O, Annot);
 }
 
 
 void PPCInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,
                                            raw_ostream &O, 
case PPC::PRED_NU_PLUS:
       O << "+";
       return;
     case PPC::PRED_BIT_SET:
     case PPC::PRED_BIT_UNSET:
       llvm_unreachable("Invalid use of bit predicate code");
     }
     llvm_unreachable("Invalid predicate code");
   }
-  
   assert(StringRef(Modifier) == "reg" &&
          "Need to specify 'cc', 'pm' or 'reg' as predicate op modifier!");
   printOperand(MI, OpNo+1, O);
 }
 
 void PPCInstPrinter::printATBitsAsHint(const MCInst *MI, unsigned OpNo,
                                        raw_ostream &O) {
   unsigned Code = MI->getOperand(OpNo).getImm();
void PPCInstPrinter::printTLSCall(const MCInst *MI, unsigned OpNo,
   O << ')';
   if (refExp.getKind() != MCSymbolRefExpr::VK_None)
     O << '@' << MCSymbolRefExpr::getVariantKindName(refExp.getKind());
 }
 
 
 /// stripRegisterPrefix - This method strips the character prefix from a
 /// register name so that only the number is left.  Used by for linux asm.
-static const char *stripRegisterPrefix(const char *RegName) {
-  if (FullRegNames || ShowVSRNumsAsVR)
+static const char *stripRegisterPrefix(const char *RegName, unsigned RegNum,
+                                       unsigned RegEncoding) {
+  if (FullRegNames || ShowVSRNumsAsVR) {
+    if (RegNum >= PPC::CR0EQ && RegNum <= PPC::CR7UN) {
+      const char *CRBits[] =
+      { "lt", "gt", "eq", "un",
+        "4*cr1+lt", "4*cr1+gt", "4*cr1+eq", "4*cr1+un",
+        "4*cr2+lt", "4*cr2+gt", "4*cr2+eq", "4*cr2+un",
+        "4*cr3+lt", "4*cr3+gt", "4*cr3+eq", "4*cr3+un",
+        "4*cr4+lt", "4*cr4+gt", "4*cr4+eq", "4*cr4+un",
+        "4*cr5+lt", "4*cr5+gt", "4*cr5+eq", "4*cr5+un",
+        "4*cr6+lt", "4*cr6+gt", "4*cr6+eq", "4*cr6+un",
+        "4*cr7+lt", "4*cr7+gt", "4*cr7+eq", "4*cr7+un"
+      };
+      return CRBits[RegEncoding];
+    }
     return RegName;
+  }
 
   switch (RegName[0]) {
   case 'r':
   case 'f':
   case 'q': // for QPX
   case 'v':
     if (RegName[1] == 's')
       return RegName + 2;
     return RegName + 1;
   case 'c': if (RegName[1] == 'r') return RegName + 2;
   }
-  
   return RegName;
 }
 
 void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
                                   raw_ostream &O) {
   const MCOperand &Op = MI->getOperand(OpNo);
   if (Op.isReg()) {
     unsigned Reg = Op.getReg();
if ((MII.get(MI->getOpcode()).TSFlags & PPCII::UseVSXReg) &&
         Reg = PPC::VSX32 + (Reg - PPC::V0);
       else if (PPCInstrInfo::isVFRegister(Reg))
         Reg = PPC::VSX32 + (Reg - PPC::VF0);
     }
 
     const char *RegName = getRegisterName(Reg);
     // The linux and AIX assembler does not take register prefixes.
     if (!isDarwinSyntax())
-      RegName = stripRegisterPrefix(RegName);
-    
+      RegName = stripRegisterPrefix(RegName, Reg, MRI.getEncodingValue(Reg));
     O << RegName;
     return;
   }
-  
   if (Op.isImm()) {
     O << Op.getImm();
     return;
   }
-  
   assert(Op.isExpr() && "unknown operand kind in printOperand");
   Op.getExpr()->print(O, &MAI);
 }
 

test/CodeGen/PowerPC/expand-contiguous-isel.ll

_ZNK4llvm9StringRef6substrEmm.exit:               ; preds = %_ZNK4llvm9StringRef6substrEmm.exit.loopexit132, %_ZNK4llvm9StringRef6substrEmm.exit.loopexit, %if.end10
   %sub.i = add i64 %.sink76, -1
   %add.ptr.i = getelementptr inbounds i8, i8* %7, i64 1
   %8 = ptrtoint i8* %add.ptr.i to i64
   br label %while.cond.outer
 
 ; CHECK-LABEL: @_Z3fn1N4llvm9StringRefE
 ; CHECK-GEN-ISEL-TRUE: isel [[SAME:r[0-9]+]], [[SAME]], [[SAME]]
 ; CHECK-GEN-ISEL-TRUE: isel [[SAME:r[0-9]+]], {{r[0-9]+}}, [[SAME]]
-; CHECK: bc 12, 2, [[TRUE:.LBB[0-9]+]]
+; CHECK: bc 12, eq, [[TRUE:.LBB[0-9]+]]
 ; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
 ; CHECK-NEXT: [[TRUE]]
 ; CHECK-NEXT: addi {{r[0-9]+}}, {{r[0-9]+}}, 0
 ; CHECK-NEXT: [[SUCCESSOR]]
 }
 
 
 

test/CodeGen/PowerPC/expand-isel.ll

 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 ; RUN: llc -verify-machineinstrs -O2 -ppc-asm-full-reg-names -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck %s --implicit-check-not isel
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @testExpandISELToIfElse(i32 signext %i, i32 signext %j) {
 entry:
   %cmp = icmp sgt i32 %i, 0
   %add = add nsw i32 %i, 1
   %cond = select i1 %cmp, i32 %add, i32 %j
   ret i32 %cond
 
 ; CHECK-LABEL: @testExpandISELToIfElse
 ; CHECK: addi r5, r3, 1
 ; CHECK-NEXT: cmpwi cr0, r3, 0
-; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
 ; CHECK: ori r3, r4, 0
 ; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
 ; CHECK-NEXT:  [[TRUE]]
 ; CHECK-NEXT: addi r3, r5, 0
 ; CHECK-NEXT: [[SUCCESSOR]]
 ; CHECK-NEXT: extsw r3, r3
 ; CHECK-NEXT: blr
 }
 
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @testExpandISELToIf(i32 signext %i, i32 signext %j) {
 entry:
   %cmp = icmp sgt i32 %i, 0
   %cond = select i1 %cmp, i32 %j, i32 %i
   ret i32 %cond
 
 ; CHECK-LABEL: @testExpandISELToIf
 ; CHECK: cmpwi   r3, 0
-; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
 ; CHECK-NEXT: blr
 ; CHECK-NEXT:  [[TRUE]]
 ; CHECK-NEXT: addi r3, r4, 0
 ; CHECK-NEXT: blr
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @testExpandISELToElse(i32 signext %i, i32 signext %j) {
 entry:
   %cmp = icmp sgt i32 %i, 0
   %cond = select i1 %cmp, i32 %i, i32 %j
   ret i32 %cond
 
 ; CHECK-LABEL: @testExpandISELToElse
 ; CHECK: cmpwi   r3, 0
-; CHECK-NEXT: bclr 12, 1, 0
+; CHECK-NEXT: bclr 12, gt, 0
 ; CHECK: ori r3, r4, 0
 ; CHECK-NEXT: blr
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @testReplaceISELWithCopy(i32 signext %i, i32 signext %j) {
 entry:
   %cmp = icmp sgt i32 %i, 0
entry:
   %cmp = icmp sgt i32 %g, 0
   %a.b = select i1 %cmp, i32 %g, i32 %b
   %d.f = select i1 %cmp, i32 %d, i32 %f
   %add = add nsw i32 %a.b, %d.f
   ret i32 %add
 
 ; CHECK-LABEL: @testExpandISELsTo2ORIs2ADDIs
 ; CHECK: cmpwi r7, 0
-; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
 ; CHECK: ori r3, r4, 0
 ; CHECK-NEXT: ori r12, r6, 0
 ; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
 ; CHECK-NEXT:  [[TRUE]]
 ; CHECK-NEXT: addi r3, r7, 0
 ; CHECK-NEXT: addi r12, r5, 0
 ; CHECK-NEXT: [[SUCCESSOR]]
 ; CHECK-NEXT: add r3, r3, r12
entry:
   %cmp = icmp sgt i32 %g, 0
   %a.b = select i1 %cmp, i32 %a, i32 %b
   %d.f = select i1 %cmp, i32 %d, i32 %f
   %add = add nsw i32 %a.b, %d.f
   ret i32 %add
 
 ; CHECK-LABEL: @testExpandISELsTo2ORIs1ADDI
 ; CHECK: cmpwi cr0, r7, 0
-; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
 ; CHECK: ori r3, r4, 0
 ; CHECK-NEXT: ori r12, r6, 0
 ; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
 ; CHECK-NEXT: [[TRUE]]
 ; CHECK-NEXT: addi r12, r5, 0
 ; CHECK-NEXT:  [[SUCCESSOR]]
 ; CHECK-NEXT: add r3, r3, r12
 ; CHECK-NEXT: extsw r3, r3
entry:
   %a.b = select i1 %cmp, i32 %a, i32 %b
   %d.f = select i1 %cmp, i32 %d, i32 %f
   %add1 = add nsw i32 %a.b, %d.f
   %add2 = add nsw i32 %a, %add1
   ret i32 %add2
 
 ; CHECK-LABEL: @testExpandISELsTo1ORI1ADDI
 ; CHECK: cmpwi cr0, r7, 0
-; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
 ; CHECK: ori r5, r6, 0
 ; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
 ; CHECK-NEXT: [[TRUE]]
 ; CHECK-NEXT: addi r4, r3, 0
 ; CHECK-NEXT:  [[SUCCESSOR]]
 ; CHECK-NEXT: add r4, r4, r5
 ; CHECK-NEXT: add r3, r3, r4
 ; CHECK-NEXT: extsw r3, r3
entry:
   %d.f = select i1 %cmp, i32 %d, i32 %f
   %add1 = add nsw i32 %a.b, %d.f
   %add2 = add nsw i32 %a, %add1
   %sub1 = sub nsw i32 %add2, %d
   ret i32 %sub1
 
 ; CHECK-LABEL: @testExpandISELsTo0ORI2ADDIs
 ; CHECK: cmpwi cr0, r7, 0
-; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
 ; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
 ; CHECK-NEXT:  [[TRUE]]
 ; CHECK-NEXT: addi r4, r3, 0
 ; CHECK-NEXT: addi r6, r5, 0
 ; CHECK-NEXT:  [[SUCCESSOR]]
 ; CHECK-NEXT: add r4, r4, r6
 ; CHECK-NEXT: add r3, r3, r4
 ; CHECK-NEXT: subf r3, r5, r3
if.end:
   %conv3 = zext i1 %cmp to i32
   br label %cleanup
 
 cleanup:
   %retval.0 = phi i32 [ %conv3, %if.end ], [ 1, %entry ]
   ret i32 %retval.0
 
 ; CHECK-LABEL: @testComplexISEL
-; CHECK: bc 12, 2, [[TRUE:.LBB[0-9]+]]
+; CHECK: bc 12, eq, [[TRUE:.LBB[0-9]+]]
 ; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
 ; CHECK-NEXT:  [[TRUE]]
 ; CHECK-NEXT: addi r3, r12, 0
 ; CHECK-NEXT: [[SUCCESSOR]]
 ; CHECK-NEXT: clrldi r3, r3, 32
 ; CHECK-NEXT: blr
 }
 
 !1 = !{!2, !2, i64 0}
 !2 = !{!"int", !3, i64 0}
 !3 = !{!"omnipotent char", !4, i64 0}
 !4 = !{!"Simple C/C++ TBAA"}