AMDGPU: Don't emit amd_kernel_code_t for callable functions

[arsenm]

Summary

This is inserted directly in the text section. The relocation
for the function ends up resolving to the beginning of the
amd_kernel_code_t header rather than the actual function
entry point.

Also skip some of the comments for initialization
that only makes sense for kernels.

[kzhuravl]

LGTM. Can you run pre-checkin before committing this?

[arsenm]

r300736

lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

bool AMDGPUAsmPrinter::isBlockOnlyReachableByFallthrough(
 
   // If this is a block implementing a long branch, an expression relative to
   // the start of the block is needed.  to the start of the block.
   // XXX - Is there a smarter way to check this?
   return (MBB->back().getOpcode() != AMDGPU::S_SETPC_B64);
 }
 
 void AMDGPUAsmPrinter::EmitFunctionBodyStart() {
+  const AMDGPUMachineFunction *MFI = MF->getInfo<AMDGPUMachineFunction>();
+  if (!MFI->isEntryFunction())
+    return;
+
   const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>();
   SIProgramInfo KernelInfo;
   amd_kernel_code_t KernelCode;
   if (STM.isAmdCodeObjectV2(*MF)) {
     getSIProgramInfo(KernelInfo, *MF);
     getAmdKernelCode(KernelCode, KernelInfo, *MF);
 
     OutStreamer->SwitchSection(getObjFileLowering().getTextSection());
bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
   EmitFunctionBody();
 
   if (isVerbose()) {
     MCSectionELF *CommentSection =
         Context.getELFSection(".AMDGPU.csdata", ELF::SHT_PROGBITS, 0);
     OutStreamer->SwitchSection(CommentSection);
 
     if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
+      if (MFI->isEntryFunction()) {
         OutStreamer->emitRawComment(" Kernel info:", false);
+      } else {
+        OutStreamer->emitRawComment(" Function info:", false);
+      }
+
       OutStreamer->emitRawComment(" codeLenInByte = " +
                                   Twine(getFunctionCodeSize(MF)), false);
       OutStreamer->emitRawComment(" NumSgprs: " + Twine(KernelInfo.NumSGPR),
                                   false);
       OutStreamer->emitRawComment(" NumVgprs: " + Twine(KernelInfo.NumVGPR),
                                   false);
+
       OutStreamer->emitRawComment(" FloatMode: " + Twine(KernelInfo.FloatMode),
                                   false);
       OutStreamer->emitRawComment(" IeeeMode: " + Twine(KernelInfo.IEEEMode),
                                   false);
       OutStreamer->emitRawComment(" ScratchSize: " + Twine(KernelInfo.ScratchSize),
                                   false);
       OutStreamer->emitRawComment(" LDSByteSize: " + Twine(KernelInfo.LDSSize) +
                                   " bytes/workgroup (compile time only)", false);
 
+      if (!MFI->isEntryFunction())
+        return false;
+
       OutStreamer->emitRawComment(" SGPRBlocks: " +
                                   Twine(KernelInfo.SGPRBlocks), false);
       OutStreamer->emitRawComment(" VGPRBlocks: " +
                                   Twine(KernelInfo.VGPRBlocks), false);
 
       OutStreamer->emitRawComment(" NumSGPRsForWavesPerEU: " +
                                   Twine(KernelInfo.NumSGPRsForWavesPerEU), false);
       OutStreamer->emitRawComment(" NumVGPRsForWavesPerEU: " +

test/CodeGen/AMDGPU/hsa-func.ll

 ; ELF: 0010: 02000000 01000000 04000000 1B000000
 
 ; ELF: 0020: 03000000 414D4400 04000700 07000000
 ; ELF: 0030: 00000000 00000000 414D4400 414D4447
 ; ELF: 0040: 50550000
 
 ; ELF: Symbol {
 ; ELF: Name: simple
-; ELF: Size: 304
+; ELF: Size: 48
 ; ELF: Type: Function (0x2)
 ; ELF: }
 
 ; HSA: .text
 ; HSA: .hsa_code_object_version 2,1
 ; HSA-CI: .hsa_code_object_isa 7,0,0,"AMD","AMDGPU"
 ; HSA-VI: .hsa_code_object_isa 8,0,1,"AMD","AMDGPU"
 
 ; HSA-NOT: .amdgpu_hsa_kernel simple
 ; HSA: .globl simple
 ; HSA: .p2align 2
 ; HSA: {{^}}simple:
-; HSA: .amd_kernel_code_t
-; HSA: enable_sgpr_private_segment_buffer = 0
-; HSA: enable_sgpr_kernarg_segment_ptr = 0
-; HSA: .end_amd_kernel_code_t
+; HSA-NOT: amd_kernel_code_t
 ; HSA-NOT: s_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x0
 
 ; Make sure we are setting the ATC bit:
 ; HSA-CI: s_mov_b32 s[[HI:[0-9]+]], 0x100f000
 ; On VI+ we also need to set MTYPE = 2
 ; HSA-VI: s_mov_b32 s[[HI:[0-9]+]], 0x1100f000
 ; Make sure we generate flat store for HSA
 ; HSA: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}
 
 ; HSA: .Lfunc_end0:
 ; HSA: .size   simple, .Lfunc_end0-simple
-
+; HSA: ; Function info:
+; HSA-NOT: COMPUTE_PGM_RSRC2
 define void @simple(i32 addrspace(1)* addrspace(2)* %ptr.out) {
 entry:
   %out = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(2)* %ptr.out
   store i32 0, i32 addrspace(1)* %out
   ret void
 }
 
 ; Ignore explicit alignment that is too low.
 ; HSA: .globl simple_align2
 ; HSA: .p2align 2
 define void @simple_align2(i32 addrspace(1)* addrspace(2)* %ptr.out) align 2 {
 entry:
   %out = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(2)* %ptr.out
   store i32 0, i32 addrspace(1)* %out
   ret void
 }