[AMDGPU][MC] Fix for Bug 28167 + LIT tests

[dp]

Summary

Corrected src0 for v_writelane_b32:

• Enabled inline constants and literals for SI/CI (VOP2)
• Enabled inline constants for VI (VOP3)

[vpykhtin]

LGTM.

[arsenm]

lib/Target/AMDGPU/VOP2Instructions.td

581

s/offline literals/inline immediates. Or you can just drop the comment, it is already on the operand type definition

[dp]

lib/Target/AMDGPU/VOP2Instructions.td

581

ok, I'll remove this comment

[dp]

Closed by commit rL299555: [AMDGPU][MC] Fix for Bug 28167 + LIT tests

lib/Target/AMDGPU/VOP2Instructions.td

def VOP_READLANE : VOPProfile<[i32, i32, i32]> {
   let Ins64 = Ins32;
   let Asm32 = " $vdst, $src0, $src1";
   let Asm64 = Asm32;
 }
 
 def VOP_WRITELANE : VOPProfile<[i32, i32, i32]> {
   let Outs32 = (outs VGPR_32:$vdst);
   let Outs64 = Outs32;
-  let Ins32 = (ins SReg_32:$src0, SCSrc_b32:$src1);
+  let Ins32 = (ins SCSrc_b32:$src0, SCSrc_b32:$src1);
   let Ins64 = Ins32;
   let Asm32 = " $vdst, $src0, $src1";
   let Asm64 = Asm32;
 }
 
 //===----------------------------------------------------------------------===//
 // VOP2 Instructions
 //===----------------------------------------------------------------------===//

 defm V_ADD_I32            : VOP2be_Real_e32e64_si <0x25>;
 defm V_SUB_I32            : VOP2be_Real_e32e64_si <0x26>;
 defm V_SUBREV_I32         : VOP2be_Real_e32e64_si <0x27>;
 defm V_ADDC_U32           : VOP2be_Real_e32e64_si <0x28>;
 defm V_SUBB_U32           : VOP2be_Real_e32e64_si <0x29>;
 defm V_SUBBREV_U32        : VOP2be_Real_e32e64_si <0x2a>;
 
 defm V_READLANE_B32       : VOP2_Real_si <0x01>;
+
+// Enable offline literals for src0
+let InOperandList = (ins SSrc_b32:$src0, SCSrc_b32:$src1) in {
 defm V_WRITELANE_B32      : VOP2_Real_si <0x02>;
+}
 
 defm V_MAC_LEGACY_F32     : VOP2_Real_e32e64_si <0x6>;
 defm V_MIN_LEGACY_F32     : VOP2_Real_e32e64_si <0xd>;
 defm V_MAX_LEGACY_F32     : VOP2_Real_e32e64_si <0xe>;
 defm V_LSHR_B32           : VOP2_Real_e32e64_si <0x15>;
 defm V_ASHR_I32           : VOP2_Real_e32e64_si <0x17>;
 defm V_LSHL_B32           : VOP2_Real_e32e64_si <0x19>;
 

test/MC/AMDGPU/vop2.s

 // SICI: v_readlane_b32 s1, v2, s3 ; encoding: [0x02,0x07,0x02,0x02]
 // VI:   v_readlane_b32 s1, v2, s3 ; encoding: [0x01,0x00,0x89,0xd2,0x02,0x07,0x00,0x00]
 v_readlane_b32 s1, v2, s3
 
 // SICI: v_writelane_b32 v1, s2, 4 ; encoding: [0x02,0x08,0x03,0x04]
 // VI:   v_writelane_b32 v1, s2, 4 ; encoding: [0x01,0x00,0x8a,0xd2,0x02,0x08,0x01,0x00]
 v_writelane_b32 v1, s2, 4
 
+// SICI: v_writelane_b32 v2, 1, s4 ; encoding: [0x81,0x08,0x04,0x04]
+// VI:   v_writelane_b32 v2, 1, s4 ; encoding: [0x02,0x00,0x8a,0xd2,0x81,0x08,0x00,0x00]
+v_writelane_b32 v2, 1, s4
+
+// SICI: v_writelane_b32 v255, 0xaf123456, 2 ; encoding: [0xff,0x04,0xff,0x05,0x56,0x34,0x12,0xaf]
+// NOVI: error: instruction not supported on this GPU
+v_writelane_b32 v255, 0xaf123456, 2
+
 // SICI: v_add_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x06]
 // VI:   v_add_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x02]
 v_add_f32 v1, v2, v3
 
 // SICI: v_sub_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x08]
 // VI:   v_sub_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x04]
 v_sub_f32 v1, v2, v3