[GlobalISel]: Simple helper functions used across GISel pipeline

[aditya_nandakumar]

Summary

Add functional equivalents to SelectionDAGs isFloatingPoint(), getConstantOperandVal() which frequently is used during selection.

[ab]

include/llvm/CodeGen/GlobalISel/Utils.h

65

This name is too generic to live in the llvm namespace (I would expect the function to take Instruction:: opcodes).

More importantly, AArch64RegisterBankInfo.cpp has a 'isPreISelGenericFloatingPointOpcode', which has a different behavior (it ignores itofp, because it interprets 'floating point opcode' as 'all operands are FP values')

IMO that shows that this is too nebulous to be shared. Keep it next to your use?

Otherwise, maybe we could make this precise enough that we could share it? For instance, 'isFloatingPointVRegDef' that takes a vreg, checks its definition, and returns true if the def is known to be FP?

76

I added a 'getConstantVRegVal' in r298855, but that's only in the selector; the Optional hopefully lets it replace all three functions (after extracting it from the selector) ?

[aditya_nandakumar]

include/llvm/CodeGen/GlobalISel/Utils.h

65

Yup - The precise definition would work. Should I rename that helper function and change the behavior to take a vreg instead?

76

Yes - getConstantVRegVal would totally replace the above functions. I'll update the backend code to use that instead.

include/llvm/CodeGen/GlobalISel/Utils.h

 #include "llvm/ADT/StringRef.h"
 
 namespace llvm {
 
 class MachineFunction;
 class MachineInstr;
 class MachineOptimizationRemarkEmitter;
 class MachineOptimizationRemarkMissed;
+class MachineOperand;
 class MachineRegisterInfo;
 class MCInstrDesc;
 class RegisterBankInfo;
 class TargetInstrInfo;
 class TargetPassConfig;
 class TargetRegisterInfo;
 class Twine;
 
void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
                         MachineOptimizationRemarkEmitter &MORE,
                         MachineOptimizationRemarkMissed &R);
 
 void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
                         MachineOptimizationRemarkEmitter &MORE,
                         const char *PassName, StringRef Msg,
                         const MachineInstr &MI);
 
+/// Check whether \p Opc is floating point opcode
+bool isFloatingPointOpc(unsigned Opc);
+
+/// Check whether \p MO is immediate (G_CONSTANT)
+bool isConstantOperand(const MachineOperand &MO,
+                       const MachineRegisterInfo &MRI);
+
+/// Returns the integer value of an Operand \p MO
+uint64_t getConstantVal(const MachineOperand &MO,
+                        const MachineRegisterInfo &MRI);
+
+/// Helper function to get integer value from \p MI at \p Idx
+uint64_t getConstantOperandVal(const MachineInstr &MI, unsigned Idx,
+                               const MachineRegisterInfo &MRI);
 } // End namespace llvm.
 #endif

lib/CodeGen/GlobalISel/Utils.cpp

 #include "llvm/CodeGen/GlobalISel/Utils.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/TargetPassConfig.h"
+#include "llvm/IR/Constants.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetRegisterInfo.h"
 
 #define DEBUG_TYPE "globalisel-utils"
 
 using namespace llvm;
 
 unsigned llvm::constrainOperandRegClass(
void llvm::reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
                               MachineOptimizationRemarkEmitter &MORE,
                               const char *PassName, StringRef Msg,
                               const MachineInstr &MI) {
   MachineOptimizationRemarkMissed R(PassName, "GISelFailure: ",
                                     MI.getDebugLoc(), MI.getParent());
   R << Msg << ": " << ore::MNV("Inst", MI);
   reportGISelFailure(MF, TPC, MORE, R);
 }
+
+bool llvm::isFloatingPointOpc(unsigned Opc) {
+  switch (Opc) {
+  case TargetOpcode::G_FADD:
+  case TargetOpcode::G_FCMP:
+  case TargetOpcode::G_FSUB:
+  case TargetOpcode::G_FDIV:
+  case TargetOpcode::G_FMUL:
+  case TargetOpcode::G_FPOW:
+  case TargetOpcode::G_FREM:
+  case TargetOpcode::G_FPEXT:
+  case TargetOpcode::G_UITOFP:
+  case TargetOpcode::G_SITOFP:
+  case TargetOpcode::G_FPTRUNC:
+  case TargetOpcode::G_FNEG:
+  case TargetOpcode::G_FCONSTANT:
+    return true;
+  default:
+    return false;
+  }
+}
+bool llvm::isConstantOperand(const MachineOperand &MO,
+                             const MachineRegisterInfo &MRI) {
+  if (!MO.isReg())
+    return false;
+  return MRI.def_begin(MO.getReg())->getParent()->getOpcode() ==
+         TargetOpcode::G_CONSTANT;
+}
+uint64_t llvm::getConstantVal(const MachineOperand &MO,
+                              const MachineRegisterInfo &MRI) {
+  assert(MO.isReg() && "Expecting a register");
+  auto DefMI = MRI.def_begin(MO.isReg())->getParent();
+  assert(TargetOpcode::G_CONSTANT == DefMI->getOpcode() &&
+         "Expecting a G_CONSTANT");
+  auto &CMO = DefMI->getOperand(1);
+  if (CMO.isImm())
+    return CMO.getImm();
+  return CMO.getCImm()->getZExtValue();
+}
+uint64_t llvm::getConstantOperandVal(const MachineInstr &MI, unsigned Idx,
+                                     const MachineRegisterInfo &MRI) {
+  return llvm::getConstantVal(MI.getOperand(Idx), MRI);
+}