[AMDGPU] Run always inliner early in opt

[kzhuravl]

Not sure which bug you were trying to solve by original change, but moving if we move it "Internalize" then we would have to make function in early-inline.ll amdgpu_kernel. Would that be ok? I added a separate option for now.

[rampitec]

lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

98

No need in separate option. It falls under the same ideology as internalize. Having a separate option would mean we need pass it from RT as well.

[rampitec]

In D31141#705482, @kzhuravl wrote:

Not sure which bug you were trying to solve by original change, but moving if we move it "Internalize" then we would have to make function in early-inline.ll amdgpu_kernel. Would that be ok? I added a separate option for now.

In D31141#705482, @kzhuravl wrote:

Not sure which bug you were trying to solve by original change, but moving if we move it "Internalize" then we would have to make function in early-inline.ll amdgpu_kernel. Would that be ok? I added a separate option for now.

In D31141#705482, @kzhuravl wrote:

Not sure which bug you were trying to solve by original change, but moving if we move it "Internalize" then we would have to make function in early-inline.ll amdgpu_kernel. Would that be ok? I added a separate option for now.

Yes, changing caller to be a kernel is good.

[kzhuravl]

Address review feedback.

[rampitec]

Thanks!

lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

 
 // Option to run internalize pass.
 static cl::opt<bool> InternalizeSymbols(
   "amdgpu-internalize-symbols",
   cl::desc("Enable elimination of non-kernel functions and unused globals"),
   cl::init(false),
   cl::Hidden);
 
+// Option to enable early inlining.
+static cl::opt<bool> EnableEarlyInline(
+  "amdgpu-early-inline",
+  cl::desc("Enable early inlining"),
+  cl::init(false),
+  cl::Hidden);
+
 // Enable address space based alias analysis
 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
   cl::desc("Enable AMDGPU Alias Analysis"),
   cl::init(true));
 
 extern "C" void LLVMInitializeAMDGPUTarget() {
   // Register the target
   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());

 }
 
 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
   Builder.DivergentTarget = true;
 
   bool Internalize = InternalizeSymbols &&
                      (getOptLevel() > CodeGenOpt::None) &&
                      (getTargetTriple().getArch() == Triple::amdgcn);
+  bool EarlyInline = EnableEarlyInline &&
+                     (getOptLevel() > CodeGenOpt::None) &&
+                     (getTargetTriple().getArch() == Triple::amdgcn);
   Builder.addExtension(
     PassManagerBuilder::EP_ModuleOptimizerEarly,
-    [Internalize](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
+    [Internalize, EarlyInline](const PassManagerBuilder &,
+                               legacy::PassManagerBase &PM) {
       PM.add(createAMDGPUUnifyMetadataPass());
       if (Internalize) {
         PM.add(createInternalizePass([=](const GlobalValue &GV) -> bool {
           if (const Function *F = dyn_cast<Function>(&GV)) {
             if (F->isDeclaration())
                 return true;
             switch (F->getCallingConv()) {
             default:
               return false;
             case CallingConv::AMDGPU_VS:
             case CallingConv::AMDGPU_GS:
             case CallingConv::AMDGPU_PS:
             case CallingConv::AMDGPU_CS:
             case CallingConv::AMDGPU_KERNEL:
             case CallingConv::SPIR_KERNEL:
               return true;
             }
           }
           return !GV.use_empty();
         }));
         PM.add(createGlobalDCEPass());
       }
+
+      if (EarlyInline)
+        PM.add(createAMDGPUAlwaysInlinePass());
   });
 }
 
 //===----------------------------------------------------------------------===//
 // R600 Target Machine (R600 -> Cayman)
 //===----------------------------------------------------------------------===//
 
 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,

test/CodeGen/AMDGPU/early-inline-alias.ll

+; RUN: opt -mtriple=amdgcn-- -O1 -S -inline-threshold=1 %s | FileCheck %s
+
+; CHECK: @add1alias = alias i32 (i32), i32 (i32)* @add1
+; CHECK: @add1alias2 = alias i32 (i32), i32 (i32)* @add1
+
+@add1alias = alias i32 (i32), i32 (i32)* @add1
+@add1alias2 = alias i32 (i32), i32 (i32)* @add1
+
+define i32 @add1(i32) {
+  %2 = add nsw i32 %0, 1
+  ret i32 %2
+}

test/CodeGen/AMDGPU/early-inline.ll

+; RUN: opt -mtriple=amdgcn-- -O1 -S -inline-threshold=1 -amdgpu-early-inline %s | FileCheck %s
+
+define i32 @callee(i32 %x) {
+entry:
+  %mul1 = mul i32 %x, %x
+  %mul2 = mul i32 %mul1, %x
+  %mul3 = mul i32 %mul1, %mul2
+  %mul4 = mul i32 %mul3, %mul2
+  %mul5 = mul i32 %mul4, %mul3
+  ret i32 %mul5
+}
+
+; CHECK-LABEL: @caller
+; CHECK: mul i32
+; CHECK-NOT: call i32
+
+define i32 @caller(i32 %x) {
+entry:
+  %res = call i32 @callee(i32 %x)
+  ret i32 %res
+}