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Differential D30979

[GlobalISel][X86] G_LOAD/G_STORE, add alternative RegisterBank mapping.
ClosedPublic

Authored by igorb on Mar 15 2017, 6:09 AM.

Details

Reviewers
qcolombet
rovka
zvi
ab
Summary

G_LOAD/G_STORE, add alternative RegisterBank mapping.
For G_LOAD, Fast and Greedy mode choose the same RegisterBank mapping (GprRegBank ) for the G_GLOAD + G_FADD , can't get rid of cross register bank copy GprRegBank->VecRegBank.

Diff Detail

Repository
rL LLVM

Event Timeline

igorb created this revision.Mar 15 2017, 6:09 AM
Herald added subscribers: kristof.beyls, dberris. · View Herald TranscriptMar 15 2017, 6:09 AM
igorb added a parent revision: D30973: [GlobalISel][X86] Support G_STORE/G_LOAD operation.Mar 15 2017, 6:10 AM
igorb added a child revision: D30980: [GlobalISel][X86] support G_FRAME_INDEX instruction selection..Mar 15 2017, 6:47 AM
igorb removed a child revision: D30980: [GlobalISel][X86] support G_FRAME_INDEX instruction selection..Mar 26 2017, 1:30 AM
igorb added a comment.Mar 26 2017, 1:46 AM

ping

zvi accepted this revision.Mar 26 2017, 5:59 AM

LGTM

lib/Target/X86/X86RegisterBankInfo.cpp
124

Consider passing an ArrayRef instead

This revision is now accepted and ready to land.Mar 26 2017, 5:59 AM
igorb closed this revision.Mar 28 2017, 3:37 AM

Closed by commit rL298907

Revision Contents

PathSize
lib/
Target/
X86/
20 lines
104 lines
test/
CodeGen/
X86/
GlobalISel/
54 lines
8 lines
86 lines
4 lines

Diff 91856

lib/Target/X86/X86RegisterBankInfo.h

Show First 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
class X86RegisterBankInfo final : public X86GenRegisterBankInfo { class X86RegisterBankInfo final : public X86GenRegisterBankInfo {
private: private:
/// Get an instruction mapping. /// Get an instruction mapping.
/// \return An InstructionMappings with a statically allocated /// \return An InstructionMappings with a statically allocated
/// OperandsMapping. /// OperandsMapping.
static InstructionMapping getSameOperandsMapping(const MachineInstr &MI, static InstructionMapping getSameOperandsMapping(const MachineInstr &MI,
bool isFP); bool isFP);
/// Track the bank of each instruction operand(register)
/// \return An instruction PartialMappingIdxs.
static void
getInstrPartialMappingIdxs(const MachineInstr &MI,
const MachineRegisterInfo &MRI, const bool isFP,
SmallVectorImpl<PartialMappingIdx> &OpRegBankIdx);
/// Construct the instruction ValueMapping from PartialMappingIdxs
/// \return true if mapping succeeded.
static bool
getInstrValueMapping(const MachineInstr &MI,
const SmallVectorImpl<PartialMappingIdx> &OpRegBankIdx,
SmallVectorImpl<const ValueMapping *> &OpdsMapping);
public: public:
X86RegisterBankInfo(const TargetRegisterInfo &TRI); X86RegisterBankInfo(const TargetRegisterInfo &TRI);
const RegisterBank & const RegisterBank &
getRegBankFromRegClass(const TargetRegisterClass &RC) const override; getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
InstructionMappings
getInstrAlternativeMappings(const MachineInstr &MI) const override;
/// See RegisterBankInfo::applyMapping.
void applyMappingImpl(const OperandsMapper &OpdMapper) const override;
InstructionMapping getInstrMapping(const MachineInstr &MI) const override; InstructionMapping getInstrMapping(const MachineInstr &MI) const override;
}; };
} // namespace llvm } // namespace llvm
#endif #endif

lib/Target/X86/X86RegisterBankInfo.cpp

Show First 20 Lines • Show All 99 Lines • ▼ Show 20 Lines if ((Ty.isScalar() && !isFP) || Ty.isPointer()) {
default: default:
llvm_unreachable("Unsupported register size."); llvm_unreachable("Unsupported register size.");
} }
} }
return PMI_None; return PMI_None;
} }
void X86RegisterBankInfo::getInstrPartialMappingIdxs(
const MachineInstr &MI, const MachineRegisterInfo &MRI, const bool isFP,
SmallVectorImpl<PartialMappingIdx> &OpRegBankIdx) {
unsigned NumOperands = MI.getNumOperands();
for (unsigned Idx = 0; Idx < NumOperands; ++Idx) {
auto &MO = MI.getOperand(Idx);
if (!MO.isReg())
OpRegBankIdx[Idx] = PMI_None;
else
OpRegBankIdx[Idx] = getPartialMappingIdx(MRI.getType(MO.getReg()), isFP);
}
}
bool X86RegisterBankInfo::getInstrValueMapping(
const MachineInstr &MI,
const SmallVectorImpl<PartialMappingIdx> &OpRegBankIdx,
zviUnsubmitted
Not Done
ReplyInline Actions

Consider passing an ArrayRef instead

zvi: Consider passing an ArrayRef instead
SmallVectorImpl<const ValueMapping *> &OpdsMapping) {
unsigned NumOperands = MI.getNumOperands();
for (unsigned Idx = 0; Idx < NumOperands; ++Idx) {
if (!MI.getOperand(Idx).isReg())
continue;
auto Mapping = getValueMapping(OpRegBankIdx[Idx], 1);
if (!Mapping->isValid())
return false;
OpdsMapping[Idx] = Mapping;
}
return true;
}
RegisterBankInfo::InstructionMapping RegisterBankInfo::InstructionMapping
X86RegisterBankInfo::getSameOperandsMapping(const MachineInstr &MI, bool isFP) { X86RegisterBankInfo::getSameOperandsMapping(const MachineInstr &MI, bool isFP) {
const MachineFunction &MF = *MI.getParent()->getParent(); const MachineFunction &MF = *MI.getParent()->getParent();
const MachineRegisterInfo &MRI = MF.getRegInfo(); const MachineRegisterInfo &MRI = MF.getRegInfo();
unsigned NumOperands = MI.getNumOperands(); unsigned NumOperands = MI.getNumOperands();
LLT Ty = MRI.getType(MI.getOperand(0).getReg()); LLT Ty = MRI.getType(MI.getOperand(0).getReg());
Show All 30 LinesX86RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
case TargetOpcode::G_FDIV: case TargetOpcode::G_FDIV:
return getSameOperandsMapping(MI, true); return getSameOperandsMapping(MI, true);
break; break;
default: default:
break; break;
} }
unsigned NumOperands = MI.getNumOperands(); unsigned NumOperands = MI.getNumOperands();
unsigned Cost = 1; // set dafault cost
// Track the bank of each register. // Track the bank of each register, use NotFP mapping (all scalars in GPRs)
SmallVector<PartialMappingIdx, 4> OpRegBankIdx(NumOperands); SmallVector<PartialMappingIdx, 4> OpRegBankIdx(NumOperands);
for (unsigned Idx = 0; Idx < NumOperands; ++Idx) { getInstrPartialMappingIdxs(MI, MRI, /* isFP */ false, OpRegBankIdx);
auto &MO = MI.getOperand(Idx);
if (!MO.isReg())
continue;
// As a top-level guess, use NotFP mapping (all scalars in GPRs)
OpRegBankIdx[Idx] = getPartialMappingIdx(MRI.getType(MO.getReg()), false);
}
// Finally construct the computed mapping. // Finally construct the computed mapping.
RegisterBankInfo::InstructionMapping Mapping =
InstructionMapping{DefaultMappingID, Cost, nullptr, NumOperands};
SmallVector<const ValueMapping *, 8> OpdsMapping(NumOperands); SmallVector<const ValueMapping *, 8> OpdsMapping(NumOperands);
for (unsigned Idx = 0; Idx < NumOperands; ++Idx) { if (!getInstrValueMapping(MI, OpRegBankIdx, OpdsMapping))
if (MI.getOperand(Idx).isReg()) {
auto Mapping = getValueMapping(OpRegBankIdx[Idx], 1);
if (!Mapping->isValid())
return InstructionMapping(); return InstructionMapping();
OpdsMapping[Idx] = Mapping; return InstructionMapping{DefaultMappingID, /* Cost */ 1,
getOperandsMapping(OpdsMapping), NumOperands};
} }
void X86RegisterBankInfo::applyMappingImpl(
const OperandsMapper &OpdMapper) const {
return applyDefaultMapping(OpdMapper);
} }
Mapping.setOperandsMapping(getOperandsMapping(OpdsMapping)); RegisterBankInfo::InstructionMappings
return Mapping; X86RegisterBankInfo::getInstrAlternativeMappings(const MachineInstr &MI) const {
const MachineFunction &MF = *MI.getParent()->getParent();
const TargetSubtargetInfo &STI = MF.getSubtarget();
const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
const MachineRegisterInfo &MRI = MF.getRegInfo();
switch (MI.getOpcode()) {
case TargetOpcode::G_LOAD:
case TargetOpcode::G_STORE: {
// we going to try to map 32/64 bit to PMI_FP32/PMI_FP64
unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI);
if (Size != 32 && Size != 64)
break;
unsigned NumOperands = MI.getNumOperands();
// Track the bank of each register, use FP mapping (all scalars in VEC)
SmallVector<PartialMappingIdx, 4> OpRegBankIdx(NumOperands);
getInstrPartialMappingIdxs(MI, MRI, /* isFP */ true, OpRegBankIdx);
// Finally construct the computed mapping.
SmallVector<const ValueMapping *, 8> OpdsMapping(NumOperands);
if (!getInstrValueMapping(MI, OpRegBankIdx, OpdsMapping))
break;
RegisterBankInfo::InstructionMapping Mapping = InstructionMapping{
/*ID*/ 1, /*Cost*/ 1, getOperandsMapping(OpdsMapping), NumOperands};
InstructionMappings AltMappings;
AltMappings.emplace_back(std::move(Mapping));
return AltMappings;
}
default:
break;
}
return RegisterBankInfo::getInstrAlternativeMappings(MI);
} }

test/CodeGen/X86/GlobalISel/X86-regbankselect.mir

# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=regbankselect %s -o - | FileCheck %s # RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=regbankselect %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=FAST
# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -regbankselect-greedy -run-pass=regbankselect %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=GREEDY
--- | --- |
; ModuleID = 'tmp.ll' ; ModuleID = 'tmp.ll'
source_filename = "tmp.ll" source_filename = "tmp.ll"
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64--linux-gnu" target triple = "x86_64--linux-gnu"
define i8 @test_add_i8(i8 %arg1, i8 %arg2) { define i8 @test_add_i8(i8 %arg1, i8 %arg2) {
Show All 21 Lines define float @test_add_float(float %arg1, float %arg2) {
ret float %ret ret float %ret
} }
define double @test_add_double(double %arg1, double %arg2) { define double @test_add_double(double %arg1, double %arg2) {
%ret = fadd double %arg1, %arg2 %ret = fadd double %arg1, %arg2
ret double %ret ret double %ret
} }
define <4 x i32> @test_add_v4i32(<4 x i32> %arg1, <4 x i32> %arg2) { define <4 x i32> @test_add_v4i32(<4 x i32> %arg1, <4 x i32> %arg2) {
%ret = add <4 x i32> %arg1, %arg2 %ret = add <4 x i32> %arg1, %arg2
ret <4 x i32> %ret ret <4 x i32> %ret
} }
define <4 x float> @test_add_v4f32(<4 x float> %arg1, <4 x float> %arg2) { define <4 x float> @test_add_v4f32(<4 x float> %arg1, <4 x float> %arg2) {
%ret = fadd <4 x float> %arg1, %arg2 %ret = fadd <4 x float> %arg1, %arg2
ret <4 x float> %ret ret <4 x float> %ret
} }
define i8 @test_load_i8(i8* %p1) { define i8 @test_load_i8(i8* %p1) {
%r = load i8, i8* %p1 %r = load i8, i8* %p1
ret i8 %r ret i8 %r
} }
define i16 @test_load_i16(i16* %p1) { define i16 @test_load_i16(i16* %p1) {
▲ Show 20 Lines • Show All 476 Lines • ▼ Show 20 Lines
--- ---
name: test_store_float name: test_store_float
alignment: 4 alignment: 4
legalized: true legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
# CHECK-LABEL: name: test_store_float # CHECK-LABEL: name: test_store_float
# CHECK: registers: # CHECK: registers:
# CHECK: - { id: 0, class: vecr }
# CHECK: - { id: 1, class: gpr } # FAST-NEXT: - { id: 0, class: vecr }
# CHECK: - { id: 2, class: gpr } # FAST-NEXT: - { id: 1, class: gpr }
# FAST-NEXT: - { id: 2, class: gpr }
# GREEDY-NEXT: - { id: 0, class: vecr }
# GREEDY-NEXT: - { id: 1, class: gpr }
registers: registers:
- { id: 0, class: _ } - { id: 0, class: _ }
- { id: 1, class: _ } - { id: 1, class: _ }
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: %rdi, %xmm0 liveins: %rdi, %xmm0
%0(s32) = COPY %xmm0 %0(s32) = COPY %xmm0
%1(p0) = COPY %rdi %1(p0) = COPY %rdi
; CHECK: %2(s32) = COPY %0(s32) ; CHECK: %1(p0) = COPY %rdi
; CHECK: G_STORE %2(s32), %1(p0) :: (store 4 into %ir.p1)
; FAST-NEXT: %2(s32) = COPY %0(s32)
; FAST-NEXT: G_STORE %2(s32), %1(p0) :: (store 4 into %ir.p1)
; GREEDY-NEXT: G_STORE %0(s32), %1(p0) :: (store 4 into %ir.p1)
G_STORE %0(s32), %1(p0) :: (store 4 into %ir.p1) G_STORE %0(s32), %1(p0) :: (store 4 into %ir.p1)
%rax = COPY %1(p0) %rax = COPY %1(p0)
RET 0, implicit %rax RET 0, implicit %rax
... ...
--- ---
name: test_store_double name: test_store_double
alignment: 4 alignment: 4
legalized: true legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
# CHECK-LABEL: name: test_store_double # CHECK-LABEL: name: test_store_double
# CHECK: registers: # CHECK: registers:
# CHECK: - { id: 0, class: vecr }
# CHECK: - { id: 1, class: gpr } # FAST-NEXT: - { id: 0, class: vecr }
# CHECK: - { id: 2, class: gpr } # FAST-NEXT: - { id: 1, class: gpr }
# FAST-NEXT: - { id: 2, class: gpr }
# GREEDY-NEXT: - { id: 0, class: vecr }
# GREEDY-NEXT: - { id: 1, class: gpr }
registers: registers:
- { id: 0, class: _ } - { id: 0, class: _ }
- { id: 1, class: _ } - { id: 1, class: _ }
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: %rdi, %xmm0 liveins: %rdi, %xmm0
%0(s64) = COPY %xmm0 %0(s64) = COPY %xmm0
%1(p0) = COPY %rdi %1(p0) = COPY %rdi
; CHECK: %2(s64) = COPY %0(s64)
; CHECK: G_STORE %2(s64), %1(p0) :: (store 8 into %ir.p1) ; CHECK: %1(p0) = COPY %rdi
; FAST-NEXT: %2(s64) = COPY %0(s64)
; FAST-NEXT: G_STORE %2(s64), %1(p0) :: (store 8 into %ir.p1)
; GREEDY-NEXT: G_STORE %0(s64), %1(p0) :: (store 8 into %ir.p1)
G_STORE %0(s64), %1(p0) :: (store 8 into %ir.p1) G_STORE %0(s64), %1(p0) :: (store 8 into %ir.p1)
%rax = COPY %1(p0) %rax = COPY %1(p0)
RET 0, implicit %rax RET 0, implicit %rax
... ...

test/CodeGen/X86/GlobalISel/binop-isel.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=x86_64-linux-gnu -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=SSE ; RUN: llc -mtriple=x86_64-linux-gnu -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=SSE
; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=ALL_AVX --check-prefix=AVX ; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=ALL_AVX --check-prefix=AVX
; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=ALL_AVX --check-prefix=AVX512F ; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=ALL_AVX --check-prefix=AVX512F
; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=ALL_AVX --check-prefix=AVX512VL ; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -mattr=+avx512vl -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=ALL_AVX --check-prefix=AVX512VL
define i64 @test_add_i64(i64 %arg1, i64 %arg2) { define i64 @test_add_i64(i64 %arg1, i64 %arg2) {
; ALL-LABEL: test_add_i64: ; ALL-LABEL: test_add_i64:
; ALL: # BB#0: ; ALL: # BB#0:
; ALL-NEXT: leaq (%rsi,%rdi), %rax ; ALL-NEXT: leaq (%rsi,%rdi), %rax
; ALL-NEXT: retq ; ALL-NEXT: retq
%ret = add i64 %arg1, %arg2 %ret = add i64 %arg1, %arg2
ret i64 %ret ret i64 %ret
▲ Show 20 Lines • Show All 173 Lines • Show Last 20 Lines

test/CodeGen/X86/GlobalISel/memop-isel.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=x86_64-linux-gnu -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=SSE ; RUN: llc -mtriple=x86_64-linux-gnu -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE_FAST
; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=ALL_AVX --check-prefix=AVX ; RUN: llc -mtriple=x86_64-linux-gnu -regbankselect-greedy -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE_GREEDY
; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=ALL_AVX --check-prefix=AVX512F ; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=ALL_AVX --check-prefix=ALL_AVX_FAST --check-prefix=AVX_FAST
; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=ALL_AVX --check-prefix=AVX512VL ; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -regbankselect-greedy -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=ALL_AVX --check-prefix=ALL_AVX_GREEDY --check-prefix=AVX_GREEDY
; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=ALL_AVX --check-prefix=ALL_AVX_FAST --check-prefix=AVX512F_FAST
; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -regbankselect-greedy -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=ALL_AVX --check-prefix=ALL_AVX_GREEDY --check-prefix=AVX512F_GREEDY
; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -mattr=+avx512vl -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=ALL_AVX --check-prefix=ALL_AVX_FAST --check-prefix=AVX512VL_FAST
; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -mattr=+avx512vl -regbankselect-greedy -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=ALL_AVX --check-prefix=ALL_AVX_GREEDY --check-prefix=AVX512VL_GREEDY
define i8 @test_load_i8(i8 * %p1) { define i8 @test_load_i8(i8 * %p1) {
; ALL-LABEL: test_load_i8: ; ALL-LABEL: test_load_i8:
; ALL: # BB#0: ; ALL: # BB#0:
; ALL-NEXT: movb (%rdi), %al ; ALL-NEXT: movb (%rdi), %al
; ALL-NEXT: retq ; ALL-NEXT: retq
%r = load i8, i8* %p1 %r = load i8, i8* %p1
▲ Show 20 Lines • Show All 103 Lines • ▼ Show 20 Lines
; ALL-NEXT: movq %rdi, (%rsi) ; ALL-NEXT: movq %rdi, (%rsi)
; ALL-NEXT: movq %rsi, %rax ; ALL-NEXT: movq %rsi, %rax
; ALL-NEXT: retq ; ALL-NEXT: retq
store i64 %val, i64* %p1 store i64 %val, i64* %p1
ret i64 * %p1; ret i64 * %p1;
} }
define float * @test_store_float(float %val, float * %p1) { define float * @test_store_float(float %val, float * %p1) {
; SSE-LABEL: test_store_float:
; SSE: # BB#0:
; SSE-NEXT: movd %xmm0, %eax
; SSE-NEXT: movl %eax, (%rdi)
; SSE-NEXT: movq %rdi, %rax
; SSE-NEXT: retq
; ;
; ALL_AVX-LABEL: test_store_float: ; SSE_FAST-LABEL: test_store_float:
; ALL_AVX: # BB#0: ; SSE_FAST: # BB#0:
; ALL_AVX-NEXT: vmovd %xmm0, %eax ; SSE_FAST-NEXT: movd %xmm0, %eax
; ALL_AVX-NEXT: movl %eax, (%rdi) ; SSE_FAST-NEXT: movl %eax, (%rdi)
; ALL_AVX-NEXT: movq %rdi, %rax ; SSE_FAST-NEXT: movq %rdi, %rax
; ALL_AVX-NEXT: retq ; SSE_FAST-NEXT: retq
;
; SSE_GREEDY-LABEL: test_store_float:
; SSE_GREEDY: # BB#0:
; SSE_GREEDY-NEXT: movss %xmm0, (%rdi)
; SSE_GREEDY-NEXT: movq %rdi, %rax
; SSE_GREEDY-NEXT: retq
;
; ALL_AVX_FAST-LABEL: test_store_float:
; ALL_AVX_FAST: # BB#0:
; ALL_AVX_FAST-NEXT: vmovd %xmm0, %eax
; ALL_AVX_FAST-NEXT: movl %eax, (%rdi)
; ALL_AVX_FAST-NEXT: movq %rdi, %rax
; ALL_AVX_FAST-NEXT: retq
;
; ALL_AVX_GREEDY-LABEL: test_store_float:
; ALL_AVX_GREEDY: # BB#0:
; ALL_AVX_GREEDY-NEXT: vmovss %xmm0, (%rdi)
; ALL_AVX_GREEDY-NEXT: movq %rdi, %rax
; ALL_AVX_GREEDY-NEXT: retq
store float %val, float* %p1 store float %val, float* %p1
ret float * %p1; ret float * %p1;
} }
define double * @test_store_double(double %val, double * %p1) { define double * @test_store_double(double %val, double * %p1) {
; SSE-LABEL: test_store_double:
; SSE: # BB#0:
; SSE-NEXT: movd %xmm0, %rax
; SSE-NEXT: movq %rax, (%rdi)
; SSE-NEXT: movq %rdi, %rax
; SSE-NEXT: retq
; ;
; ALL_AVX-LABEL: test_store_double: ; SSE_FAST-LABEL: test_store_double:
; ALL_AVX: # BB#0: ; SSE_FAST: # BB#0:
; ALL_AVX-NEXT: vmovq %xmm0, %rax ; SSE_FAST-NEXT: movd %xmm0, %rax
; ALL_AVX-NEXT: movq %rax, (%rdi) ; SSE_FAST-NEXT: movq %rax, (%rdi)
; ALL_AVX-NEXT: movq %rdi, %rax ; SSE_FAST-NEXT: movq %rdi, %rax
; ALL_AVX-NEXT: retq ; SSE_FAST-NEXT: retq
;
; SSE_GREEDY-LABEL: test_store_double:
; SSE_GREEDY: # BB#0:
; SSE_GREEDY-NEXT: movsd %xmm0, (%rdi)
; SSE_GREEDY-NEXT: movq %rdi, %rax
; SSE_GREEDY-NEXT: retq
;
; ALL_AVX_FAST-LABEL: test_store_double:
; ALL_AVX_FAST: # BB#0:
; ALL_AVX_FAST-NEXT: vmovq %xmm0, %rax
; ALL_AVX_FAST-NEXT: movq %rax, (%rdi)
; ALL_AVX_FAST-NEXT: movq %rdi, %rax
; ALL_AVX_FAST-NEXT: retq
;
; ALL_AVX_GREEDY-LABEL: test_store_double:
; ALL_AVX_GREEDY: # BB#0:
; ALL_AVX_GREEDY-NEXT: vmovsd %xmm0, (%rdi)
; ALL_AVX_GREEDY-NEXT: movq %rdi, %rax
; ALL_AVX_GREEDY-NEXT: retq
store double %val, double* %p1 store double %val, double* %p1
ret double * %p1; ret double * %p1;
} }

test/CodeGen/X86/GlobalISel/x86_64-instructionselect.mir

Show First 20 Lines • Show All 57 Lines • ▼ Show 20 Lines define <4 x float> @test_add_v4f32(<4 x float> %arg1, <4 x float> %arg2) {
%ret = fadd <4 x float> %arg1, %arg2 %ret = fadd <4 x float> %arg1, %arg2
ret <4 x float> %ret ret <4 x float> %ret
} }
define <4 x float> @test_sub_v4f32(<4 x float> %arg1, <4 x float> %arg2) { define <4 x float> @test_sub_v4f32(<4 x float> %arg1, <4 x float> %arg2) {
%ret = fsub <4 x float> %arg1, %arg2 %ret = fsub <4 x float> %arg1, %arg2
ret <4 x float> %ret ret <4 x float> %ret
} }
define i8 @test_load_i8(i8* %p1) { define i8 @test_load_i8(i8* %p1) {
%r = load i8, i8* %p1 %r = load i8, i8* %p1
ret i8 %r ret i8 %r
} }
define i16 @test_load_i16(i16* %p1) { define i16 @test_load_i16(i16* %p1) {
%r = load i16, i16* %p1 %r = load i16, i16* %p1
ret i16 %r ret i16 %r
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines define float* @test_store_float(float %val, float* %p1) {
store float %val, float* %p1 store float %val, float* %p1
ret float* %p1 ret float* %p1
} }
define double* @test_store_double(double %val, double* %p1) { define double* @test_store_double(double %val, double* %p1) {
store double %val, double* %p1 store double %val, double* %p1
ret double* %p1 ret double* %p1
} }
... ...
--- ---
name: test_add_i64 name: test_add_i64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
# ALL: registers: # ALL: registers:
# ALL-NEXT: - { id: 0, class: gr64 } # ALL-NEXT: - { id: 0, class: gr64 }
▲ Show 20 Lines • Show All 682 Lines • Show Last 20 Lines