[MIR] Support Customed Register Mask and CSRs

[oren_ben_simhon]

Summary

The MIR printer dumps a string that describe the register mask of a function.
A static predefined list of register masks matches a static list of strings.

However when the register mask is not from the static predefined list, there is no descriptor string and the printer fails.
This patch adds support to custom register mask printing and dumping.

Also the list of callee saved registers (describing the registers that must be preserved for the caller) might be dynamic.
As such this data needs to be dumped and parsed back to the Machine Register Info.

[MatzeB]

Thanks for working on this!

• Printing the regmask as hexnumbers seems like a bad idea: Adding or removing registers in between would render old .mir files invalid. Even though it's unwieldy I think we should print lists of register names instead. Printing the list of preserved registers instead of the clobbered ones may also make the lists shorter.

• I only very recently learned about the thing that was called "CalleeSavedRegisters" (or UnusedPhysRegs after your patch). It is silly that we serialize this information in the first place as you can trivially recompute it after loading a mir file: Loop over all blocks, instructions, operands and call MachineRegisterInfo::addPhysRegsUsedFromRegMask on every regmask operand you find. That way we have correct information and don't have to deal with printing and parsing this information in the first place. Maybe you could change this as part of this patch?

• Browsing around I found "@todo Need to add support in MIPrinter and MIParser to represent..." in the middle of X86 code which you can remove with this.

include/llvm/CodeGen/MachineRegisterInfo.h

78–82

Unrelated and so trivial that you can just commmit this independently without review.

lib/CodeGen/MIRParser/MIParser.cpp

1676

Writing the type instead of auto is friendlier to readers (unless the type is immediately obvious, which it is not here).

1682

typo

1683

Move the declaration to where it is used to avoid the impression that it needs to hold values accross loop iterations.

lib/CodeGen/MIRPrinter.cpp

889–892

RegMask operands with a nullptr in the masks are illegal and it is perfectly reasonable not to test for that here and just crash in that case.

lib/CodeGen/MachineRegisterInfo.cpp

593

Use ArrayRef<MCPhysReg> here for increased flexibility (smallvectors are among the things that automatically convert to ArrayRefs).

597

Please use MCPhysReg instead of auto.

[oren_ben_simhon]

Implemented comments posted until 03/15 (Thank you Matthias).

[MatzeB]

LGTM, thanks.

lib/CodeGen/MIRParser/MIRParser.cpp

511–521

Oh wow, we even already had the code to compute the UsedPhysRegMask :)

include/llvm/CodeGen/MIRYamlMapping.h

struct MachineFunction {
   bool Legalized = false;
   bool RegBankSelected = false;
   bool Selected = false;
   // Register information
   bool TracksRegLiveness = false;
   std::vector<VirtualRegisterDefinition> VirtualRegisters;
   std::vector<MachineFunctionLiveIn> LiveIns;
   Optional<std::vector<FlowStringValue>> CalleeSavedRegisters;
+  Optional<std::vector<FlowStringValue>> UnusedPhysRegs;
   // TODO: Serialize the various register masks.
   // Frame information
   MachineFrameInfo FrameInfo;
   std::vector<FixedMachineStackObject> FixedStackObjects;
   std::vector<MachineStackObject> StackObjects;
   std::vector<MachineConstantPoolValue> Constants; /// Constant pool.
   MachineJumpTable JumpTableInfo;
   BlockStringValue Body;
 };
 
 template <> struct MappingTraits<MachineFunction> {
   static void mapping(IO &YamlIO, MachineFunction &MF) {
     YamlIO.mapRequired("name", MF.Name);
     YamlIO.mapOptional("alignment", MF.Alignment);
     YamlIO.mapOptional("exposesReturnsTwice", MF.ExposesReturnsTwice);
     YamlIO.mapOptional("legalized", MF.Legalized);
     YamlIO.mapOptional("regBankSelected", MF.RegBankSelected);
     YamlIO.mapOptional("selected", MF.Selected);
     YamlIO.mapOptional("tracksRegLiveness", MF.TracksRegLiveness);
     YamlIO.mapOptional("registers", MF.VirtualRegisters);
     YamlIO.mapOptional("liveins", MF.LiveIns);
     YamlIO.mapOptional("calleeSavedRegisters", MF.CalleeSavedRegisters);
+    YamlIO.mapOptional("UnusedPhysRegs", MF.UnusedPhysRegs);
     YamlIO.mapOptional("frameInfo", MF.FrameInfo);
     YamlIO.mapOptional("fixedStack", MF.FixedStackObjects);
     YamlIO.mapOptional("stack", MF.StackObjects);
     YamlIO.mapOptional("constants", MF.Constants);
     if (!YamlIO.outputting() || !MF.JumpTableInfo.Entries.empty())
       YamlIO.mapOptional("jumpTable", MF.JumpTableInfo);
     YamlIO.mapOptional("body", MF.Body);
   }
 };
 
 } // end namespace yaml
 } // end namespace llvm
 
 #endif

include/llvm/CodeGen/MachineRegisterInfo.h

private:
   /// Each element in this list contains the register class of the vreg and the
   /// start of the use/def list for the register.
   IndexedMap<std::pair<RegClassOrRegBank, MachineOperand *>,
              VirtReg2IndexFunctor>
       VRegInfo;
 
   /// The flag is true upon \p UpdatedCSRs initialization
   /// and false otherwise.
-  bool IsUpdatedCSRsInitizialied;
+  bool IsUpdatedCSRsInitialized;
 
   /// Contains the updated callee saved register list.
   /// As opposed to the static list defined in register info,
-  /// all registers that were disabled (in CalleeSaveDisableRegs)
-  /// are removed from the list.
+  /// all registers that were disabled are removed from the list.
   SmallVector<MCPhysReg, 16> UpdatedCSRs;
 
   /// RegAllocHints - This vector records register allocation hints for virtual
   /// registers. For each virtual register, it keeps a register and hint type
   /// pair making up the allocation hint. Hint type is target specific except
   /// for the value 0 which means the second value of the pair is the preferred
   /// register for allocation. For example, if the hint is <0, 1024>, it means
   /// the allocator should prefer the physical register allocated to the virtual
public:
   bool subRegLivenessEnabled() const {
     return TracksSubRegLiveness;
   }
 
   //===--------------------------------------------------------------------===//
   // Register Info
   //===--------------------------------------------------------------------===//
 
+  /// Returns true if the updated CSR list was initialized and false otherwise.
+  bool isUpdatedCSRsInitialized() const { return IsUpdatedCSRsInitialized; }
+
   /// Disables the register from the list of CSRs.
   /// I.e. the register will not appear as part of the CSR mask.
   /// \see UpdatedCalleeSavedRegs.
   void disableCalleeSavedRegister(unsigned Reg);
 
   /// Returns list of callee saved registers.
   /// The function returns the updated CSR list (after taking into account
   /// registers that are disabled from the CSR list).
   const MCPhysReg *getCalleeSavedRegs() const;
 
+  /// Sets the updated Callee Saved Registers list.
+  /// Notice that it will override ant previously disabled/saved CSRs.
+  void setCalleeSavedRegs(const SmallVectorImpl<MCPhysReg> &CSRs);
+
   // Strictly for use by MachineInstr.cpp.
   void addRegOperandToUseList(MachineOperand *MO);
 
   // Strictly for use by MachineInstr.cpp.
   void removeRegOperandFromUseList(MachineOperand *MO);
 
   // Strictly for use by MachineInstr.cpp.
   void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps);

lib/CodeGen/MIRParser/MIParser.cpp

public:
   bool parseCFIOffset(int &Offset);
   bool parseCFIRegister(unsigned &Reg);
   bool parseCFIOperand(MachineOperand &Dest);
   bool parseIRBlock(BasicBlock *&BB, const Function &F);
   bool parseBlockAddressOperand(MachineOperand &Dest);
   bool parseIntrinsicOperand(MachineOperand &Dest);
   bool parsePredicateOperand(MachineOperand &Dest);
   bool parseTargetIndexOperand(MachineOperand &Dest);
+  bool parseCustomRegisterMaskOperand(MachineOperand &Dest);
   bool parseLiveoutRegisterMaskOperand(MachineOperand &Dest);
   bool parseMachineOperand(MachineOperand &Dest,
                            Optional<unsigned> &TiedDefIdx);
   bool parseMachineOperandAndTargetFlags(MachineOperand &Dest,
                                          Optional<unsigned> &TiedDefIdx);
   bool parseOffset(int64_t &Offset);
   bool parseAlignment(unsigned &Alignment);
   bool parseOperandsOffset(MachineOperand &Op);
bool MIParser::parseTargetIndexOperand(MachineOperand &Dest) {
   if (expectAndConsume(MIToken::rparen))
     return true;
   Dest = MachineOperand::CreateTargetIndex(unsigned(Index), /*Offset=*/0);
   if (parseOperandsOffset(Dest))
     return true;
   return false;
 }
 
+bool MIParser::parseCustomRegisterMaskOperand(MachineOperand &Dest) {
+  assert(Token.stringValue() == "CustomRegMask" && "Expected a custom RegMask");
+  const auto *TRI = MF.getSubtarget().getRegisterInfo();
+  assert(TRI && "Expected target register info");
+  lex();
+  if (expectAndConsume(MIToken::lparen))
+    return true;
+
+  // Expecting a register mask as a list of hexdecimal values.
+  APInt Result;
+  uint32_t *Mask = MF.allocateRegisterMask(TRI->getNumRegs());
+  unsigned int RegMaskSize = (TRI->getNumRegs() + 31) / 32;
+  for (unsigned I = 0, E = RegMaskSize; I < E; I++) {
+    assert(Token.is(MIToken::HexLiteral) && "Expecting hexdecimal number");
+    if (getHexUint(Result))
+      return true;
+    Mask[I] = Result.getLimitedValue(uint64_t(1) << 32);
+    lex();
+    if (Token.isNot(MIToken::comma))
+      break;
+    lex();
+  }
+
+  if (expectAndConsume(MIToken::rparen))
+    return true;
+  Dest = MachineOperand::CreateRegMask(Mask);
+  return false;
+}
+
 bool MIParser::parseLiveoutRegisterMaskOperand(MachineOperand &Dest) {
   assert(Token.is(MIToken::kw_liveout));
   const auto *TRI = MF.getSubtarget().getRegisterInfo();
   assert(TRI && "Expected target register info");
   uint32_t *Mask = MF.allocateRegisterMask(TRI->getNumRegs());
   lex();
   if (expectAndConsume(MIToken::lparen))
     return true;
case MIToken::kw_intpred:
     return parsePredicateOperand(Dest);
   case MIToken::Error:
     return true;
   case MIToken::Identifier:
     if (const auto *RegMask = getRegMask(Token.stringValue())) {
       Dest = MachineOperand::CreateRegMask(RegMask);
       lex();
       break;
-    }
-    LLVM_FALLTHROUGH;
+    } else
+      return parseCustomRegisterMaskOperand(Dest);
   default:
     // FIXME: Parse the MCSymbol machine operand.
     return error("expected a machine operand");
   }
   return false;
 }
 
 bool MIParser::parseMachineOperandAndTargetFlags(
bool MIParser::getHexUint(APInt &Result) {
   assert(Token.is(MIToken::HexLiteral));
   StringRef S = Token.range();
   assert(S[0] == '0' && tolower(S[1]) == 'x');
   // This could be a floating point literal with a special prefix.
   if (!isxdigit(S[2]))
     return true;
   StringRef V = S.substr(2);
   APInt A(V.size()*4, V, 16);
-  Result = APInt(A.getActiveBits(),
+  Result = APInt(std::max(A.getActiveBits(), 1u),
                  ArrayRef<uint64_t>(A.getRawData(), A.getNumWords()));
   return false;
 }
 
 bool MIParser::parseMemoryOperandFlag(MachineMemOperand::Flags &Flags) {
   const auto OldFlags = Flags;
   switch (Token.kind()) {
   case MIToken::kw_volatile:

lib/CodeGen/MIRParser/MIRParser.cpp

if (!LiveIn.VirtualRegister.Value.empty()) {
       if (parseVirtualRegisterReference(PFS, Info, LiveIn.VirtualRegister.Value,
                                         Error))
         return error(Error, LiveIn.VirtualRegister.SourceRange);
       VReg = Info->VReg;
     }
     RegInfo.addLiveIn(Reg, VReg);
   }
 
-  // Parse the callee saved register mask.
-  BitVector CalleeSavedRegisterMask(RegInfo.getUsedPhysRegsMask().size());
-  if (!YamlMF.CalleeSavedRegisters)
-    return false;
+  // Parse unused physical registers (Registers that will
+  // not be modified by callees).
+  if (YamlMF.UnusedPhysRegs) {
+    BitVector UnusedPhysRegisterMask(RegInfo.getUsedPhysRegsMask().size());
+    for (const auto &RegSource : YamlMF.UnusedPhysRegs.getValue()) {
+      unsigned Reg = 0;
+      if (parseNamedRegisterReference(PFS, Reg, RegSource.Value, Error))
+        return error(Error, RegSource.SourceRange);
+      UnusedPhysRegisterMask[Reg] = true;
+    }
+    RegInfo.setUsedPhysRegMask(UnusedPhysRegisterMask.flip());
+  }
+
+  // Parse the callee saved registers (Registers that will
+  // be saved for the caller).
+  if (YamlMF.CalleeSavedRegisters) {
+    SmallVector<MCPhysReg, 16> CalleeSavedRegisters;
     for (const auto &RegSource : YamlMF.CalleeSavedRegisters.getValue()) {
       unsigned Reg = 0;
       if (parseNamedRegisterReference(PFS, Reg, RegSource.Value, Error))
         return error(Error, RegSource.SourceRange);
-    CalleeSavedRegisterMask[Reg] = true;
+      CalleeSavedRegisters.push_back(Reg);
     }
-  RegInfo.setUsedPhysRegMask(CalleeSavedRegisterMask.flip());
+    RegInfo.setCalleeSavedRegs(CalleeSavedRegisters);
+  }
+
   return false;
 }
 
 bool MIRParserImpl::setupRegisterInfo(const PerFunctionMIParsingState &PFS,
                                       const yaml::MachineFunction &YamlMF) {
   MachineFunction &MF = PFS.MF;
   MachineRegisterInfo &MRI = MF.getRegInfo();
   bool Error = false;
case VRegInfo::GENERIC:
       break;
     case VRegInfo::REGBANK:
       MRI.setRegBank(Reg, *Info.D.RegBank);
       break;
     }
   }
 
   // Compute MachineRegisterInfo::UsedPhysRegMask
-  if (!YamlMF.CalleeSavedRegisters) {
+  if (!YamlMF.UnusedPhysRegs) {
     for (const MachineBasicBlock &MBB : MF) {
       for (const MachineInstr &MI : MBB) {
         for (const MachineOperand &MO : MI.operands()) {
           if (!MO.isRegMask())
             continue;
           MRI.addPhysRegsUsedFromRegMask(MO.getRegMask());
         }
       }
     }
   }
 
   // FIXME: This is a temporary workaround until the reserved registers can be
   // serialized.
   MRI.freezeReservedRegs(MF);
   return Error;
 }
 
 bool MIRParserImpl::initializeFrameInfo(PerFunctionMIParsingState &PFS,

lib/CodeGen/MIRPrinter.cpp

static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
     llvm_unreachable("LLVM Module is supposed to be parsed separately");
     return "";
   }
 };
 
 } // end namespace yaml
 } // end namespace llvm
 
+static void printCustomRegMask(const uint32_t *RegMask, raw_ostream &OS,
+                               const TargetRegisterInfo *TRI) {
+  assert(RegMask && "Can't print an empty register mask");
+  OS << StringRef("CustomRegMask(");
+
+  // Printing a register mask as a list of hexdecimal values.
+  unsigned int RegMaskSize = (TRI->getNumRegs() + 31) / 32;
+  for (int I = 0, E = RegMaskSize; I < E; I++) {
+    OS << format("0x%08" PRIx32, RegMask[I]);
+    if (I + 1 < E)
+      OS << ',';
+  }
+  OS << ')';
+}
+
 static void printReg(unsigned Reg, raw_ostream &OS,
                      const TargetRegisterInfo *TRI) {
   // TODO: Print Stack Slots.
   if (!Reg)
     OS << '_';
   else if (TargetRegisterInfo::isVirtualRegister(Reg))
     OS << '%' << TargetRegisterInfo::virtReg2Index(Reg);
   else if (Reg < TRI->getNumRegs())
for (auto I = RegInfo.livein_begin(), E = RegInfo.livein_end(); I != E; ++I) {
     printReg(I->first, LiveIn.Register, TRI);
     if (I->second)
       printReg(I->second, LiveIn.VirtualRegister, TRI);
     MF.LiveIns.push_back(LiveIn);
   }
   // The used physical register mask is printed as an inverted callee saved
   // register mask.
   const BitVector &UsedPhysRegMask = RegInfo.getUsedPhysRegsMask();
-  if (UsedPhysRegMask.none())
-    return;
-  std::vector<yaml::FlowStringValue> CalleeSavedRegisters;
+  if (!UsedPhysRegMask.none()) {
+    std::vector<yaml::FlowStringValue> UnusedPhysRegs;
     for (unsigned I = 0, E = UsedPhysRegMask.size(); I != E; ++I) {
       if (!UsedPhysRegMask[I]) {
         yaml::FlowStringValue Reg;
         printReg(I, Reg, TRI);
-      CalleeSavedRegisters.push_back(Reg);
+        UnusedPhysRegs.push_back(Reg);
+      }
     }
+    MF.UnusedPhysRegs = UnusedPhysRegs;
+  }
+
+  // Prints the callee saved registers.
+  if (RegInfo.isUpdatedCSRsInitialized()) {
+    const MCPhysReg *CalleeSavedRegs = RegInfo.getCalleeSavedRegs();
+    std::vector<yaml::FlowStringValue> CalleeSavedRegisters;
+    for (const MCPhysReg *I = CalleeSavedRegs; *I; ++I) {
+      yaml::FlowStringValue Reg;
+      printReg(*I, Reg, TRI);
+      CalleeSavedRegisters.push_back(Reg);
     }
     MF.CalleeSavedRegisters = CalleeSavedRegisters;
   }
+}
 
 void MIRPrinter::convert(ModuleSlotTracker &MST,
                          yaml::MachineFrameInfo &YamlMFI,
                          const MachineFrameInfo &MFI) {
   YamlMFI.IsFrameAddressTaken = MFI.isFrameAddressTaken();
   YamlMFI.IsReturnAddressTaken = MFI.isReturnAddressTaken();
   YamlMFI.HasStackMap = MFI.hasStackMap();
   YamlMFI.HasPatchPoint = MFI.hasPatchPoint();
case MachineOperand::MO_BlockAddress:
     printIRBlockReference(*Op.getBlockAddress()->getBasicBlock());
     OS << ')';
     printOffset(Op.getOffset());
     break;
   case MachineOperand::MO_RegisterMask: {
     auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask());
     if (RegMaskInfo != RegisterMaskIds.end())
       OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();
+    else if (Op.getRegMask())
+      printCustomRegMask(Op.getRegMask(), OS, TRI);
     else
       llvm_unreachable("Can't print this machine register mask yet.");
     break;
   }
   case MachineOperand::MO_RegisterLiveOut: {
     const uint32_t *RegMask = Op.getRegLiveOut();
     OS << "liveout(";
     bool IsCommaNeeded = false;
     for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
       if (RegMask[Reg / 32] & (1U << (Reg % 32))) {

lib/CodeGen/MachineRegisterInfo.cpp

static cl::opt<bool> EnableSubRegLiveness("enable-subreg-liveness", cl::Hidden,
   cl::init(true), cl::desc("Enable subregister liveness tracking."));
 
 // Pin the vtable to this file.
 void MachineRegisterInfo::Delegate::anchor() {}
 
 MachineRegisterInfo::MachineRegisterInfo(MachineFunction *MF)
     : MF(MF), TracksSubRegLiveness(MF->getSubtarget().enableSubRegLiveness() &&
                                    EnableSubRegLiveness),
-      IsUpdatedCSRsInitizialied(false) {
+      IsUpdatedCSRsInitialized(false) {
   unsigned NumRegs = getTargetRegisterInfo()->getNumRegs();
   VRegInfo.reserve(256);
   RegAllocHints.reserve(256);
   UsedPhysRegMask.resize(NumRegs);
   PhysRegUseDefLists.reset(new MachineOperand*[NumRegs]());
 }
 
 /// setRegClass - Set the register class of the specified virtual register.

 }
 
 void MachineRegisterInfo::disableCalleeSavedRegister(unsigned Reg) {
 
   const TargetRegisterInfo *TRI = getTargetRegisterInfo();
   assert(Reg && (Reg < TRI->getNumRegs()) &&
          "Trying to disable an invalid register");
 
-  if (!IsUpdatedCSRsInitizialied) {
+  if (!IsUpdatedCSRsInitialized) {
     const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF);
     for (const MCPhysReg *I = CSR; *I; ++I)
       UpdatedCSRs.push_back(*I);
 
     // Zero value represents the end of the register list
     // (no more registers should be pushed).
     UpdatedCSRs.push_back(0);
 
-    IsUpdatedCSRsInitizialied = true;
+    IsUpdatedCSRsInitialized = true;
   }
 
   // Remove the register (and its aliases from the list).
   for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
     UpdatedCSRs.erase(std::remove(UpdatedCSRs.begin(), UpdatedCSRs.end(), *AI),
                       UpdatedCSRs.end());
 }
 
 const MCPhysReg *MachineRegisterInfo::getCalleeSavedRegs() const {
-  if (IsUpdatedCSRsInitizialied)
+  if (IsUpdatedCSRsInitialized)
     return UpdatedCSRs.data();
 
   return getTargetRegisterInfo()->getCalleeSavedRegs(MF);
 }
+
+void MachineRegisterInfo::setCalleeSavedRegs(
+    const SmallVectorImpl<MCPhysReg> &CSRs) {
+  if (IsUpdatedCSRsInitialized)
+    UpdatedCSRs.clear();
+
+  for (auto Reg : CSRs)
+    UpdatedCSRs.push_back(Reg);
+
+  // Zero value represents the end of the register list
+  // (no more registers should be pushed).
+  UpdatedCSRs.push_back(0);
+  IsUpdatedCSRsInitialized = true;
+}

test/CodeGen/MIR/Generic/dynamic-regmask.ll

+; RUN: llc -stop-after machine-sink %s -o %t.mir
+; RUN: FileCheck %s < %t.mir
+; RUN: llc %t.mir -run-pass machine-sink
+; Check that callee saved registers are printed in a format that can then be parsed.
+
+declare x86_regcallcc i32 @callee(i32 %a0, i32 %b0, i32 %c0, i32 %d0, i32 %e0)
+
+define i32 @caller(i32 %a0) nounwind {
+  %b1 = call x86_regcallcc i32 @callee(i32 %a0, i32 %a0, i32 %a0, i32 %a0, i32 %a0)
+  %b2 = add i32 %b1, %a0
+  ret i32 %b2
+}
+; CHECK:    name: caller
+; CHECK:    CALL64pcrel32 @callee, CustomRegMask(0x403001f0,0x00019030,0x00000000,0x003f0000,0x00003fc0,0x00000000,0x00000000,0x003f3f3f)
+; CHECK:    RET 0, %eax
+
+define x86_regcallcc {i32, i32, i32} @test_callee(i32 %a0, i32 %b0, i32 %c0, i32 %d0, i32 %e0) nounwind {
+  %b1 = mul i32 7, %e0
+  %b2 = udiv i32 5, %e0
+  %b3 = mul i32 7, %d0
+  %b4 = insertvalue {i32, i32, i32} undef, i32 %b1, 0
+  %b5 = insertvalue {i32, i32, i32} %b4, i32 %b2, 1
+  %b6 = insertvalue {i32, i32, i32} %b5, i32 %b3, 2
+  ret {i32, i32, i32} %b6
+}
+; CHECK: name:            test_callee
+; CHECK: calleeSavedRegisters: [ '%rbx', '%rbp', '%rsp', '%r10', '%r11', '%r12',
+; CHECK:                         '%r13', '%r14', '%r15', '%xmm8', '%xmm9', '%xmm10',
+; CHECK:                         '%xmm11', '%xmm12', '%xmm13', '%xmm14', '%xmm15' ]
+; CHECK: RET 0, %eax, %ecx, %edx

test/CodeGen/MIR/X86/used-physical-register-info.mir

bb.0.body:
     %eax = IMUL32rri8 %edi, 11, implicit-def %eflags
     RETQ %eax
 ...
 ---
 name:            foo
 liveins:
   - { reg: '%edi' }
 # CHECK: name: foo
-# CHECK: calleeSavedRegisters: [ '%bh', '%bl', '%bp', '%bpl', '%bx', '%ebp', '%ebx',
-# CHECK-NEXT:                    '%rbp', '%rbx', '%r12', '%r13', '%r14', '%r15',
-# CHECK-NEXT:                    '%r12b', '%r13b', '%r14b', '%r15b', '%r12d', '%r13d',
-# CHECK-NEXT:                    '%r14d', '%r15d', '%r12w', '%r13w', '%r14w', '%r15w' ]
-calleeSavedRegisters: [ '%bh', '%bl', '%bp', '%bpl', '%bx', '%ebp', '%ebx',
-                        '%rbp', '%rbx', '%r12', '%r13', '%r14', '%r15',
-                        '%r12b', '%r13b', '%r14b', '%r15b', '%r12d', '%r13d',
-                        '%r14d', '%r15d', '%r12w', '%r13w', '%r14w', '%r15w' ]
+# CHECK: UnusedPhysRegs: [ '%bh', '%bl', '%bp', '%bpl', '%bx', '%ebp', '%ebx',
+# CHECK-NEXT:              '%rbp', '%rbx', '%r12', '%r13', '%r14', '%r15', '%r12b',
+# CHECK-NEXT:              '%r13b', '%r14b', '%r15b', '%r12d', '%r13d', '%r14d',
+# CHECK-NEXT:              '%r15d', '%r12w', '%r13w', '%r14w', '%r15w' ]
+UnusedPhysRegs: [ '%bh', '%bl', '%bp', '%bpl', '%bx', '%ebp', '%ebx',
+                  '%rbp', '%rbx', '%r12', '%r13', '%r14', '%r15', '%r12b',
+                  '%r13b', '%r14b', '%r15b', '%r12d', '%r13d', '%r14d',
+                  '%r15d', '%r12w', '%r13w', '%r14w', '%r15w' ]
 body: |
   bb.0.entry:
     liveins: %edi
 
     PUSH64r %rax, implicit-def %rsp, implicit %rsp
     CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax
     %rdx = POP64r implicit-def %rsp, implicit %rsp
     RETQ %eax
 ...
 ---
 name:            bar
 liveins:
   - { reg: '%edi' }
 # Verify that the callee saved register can be inferred from register mask
 # machine operands:
 # CHECK: name: bar
-# CHECK: calleeSavedRegisters: [ '%bh', '%bl', '%bp', '%bpl', '%bx', '%ebp', '%ebx',
-# CHECK-NEXT:                    '%rbp', '%rbx', '%r12', '%r13', '%r14', '%r15',
-# CHECK-NEXT:                    '%r12b', '%r13b', '%r14b', '%r15b', '%r12d', '%r13d',
-# CHECK-NEXT:                    '%r14d', '%r15d', '%r12w', '%r13w', '%r14w', '%r15w' ]
+# CHECK: UnusedPhysRegs: [ '%bh', '%bl', '%bp', '%bpl', '%bx', '%ebp', '%ebx',
+# CHECK-NEXT:              '%rbp', '%rbx', '%r12', '%r13', '%r14', '%r15', '%r12b',
+# CHECK-NEXT:              '%r13b', '%r14b', '%r15b', '%r12d', '%r13d', '%r14d',
+# CHECK-NEXT:              '%r15d', '%r12w', '%r13w', '%r14w', '%r15w' ]
 body: |
   bb.0.entry:
     liveins: %edi
 
     PUSH64r %rax, implicit-def %rsp, implicit %rsp
     CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax
     %rdx = POP64r implicit-def %rsp, implicit %rsp
     RETQ %eax
 ...
 ---
 name:            empty
 liveins:
   - { reg: '%edi' }
 # Verify that the callee saved register can be empty.
 # CHECK: name: empty
-# CHECK: calleeSavedRegisters: [ ]
-calleeSavedRegisters: [ ]
+# CHECK: UnusedPhysRegs: [ ]
+UnusedPhysRegs: [ ]
 body: |
   bb.0.entry:
     liveins: %edi
 
     PUSH64r %rax, implicit-def %rsp, implicit %rsp
     CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax
     %rdx = POP64r implicit-def %rsp, implicit %rsp
     RETQ %eax
 ...