[DAGCombiner] Do various combine on usubo.

[deadalnix]

Summary

This essentially does the same transform as for SUBC.

[RKSimon]

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

2115 ↗

(On Diff #89959)

Can vectors ever use this? In which case we need to be careful of generating constants after legalization (see tryFoldToZero).

2119 ↗

(On Diff #89959)

Is it possible to add an explicit test for this?

[zvi]

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

2130 ↗

(On Diff #89959)

If i am not mistaken, we don't have a similar LLVM IR transform in InstCombine or InstSimplify.

[deadalnix]

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

2115 ↗

(On Diff #89959)

I don't think so.

2119 ↗

(On Diff #89959)

Both codegen result in a sub, the overflow flag goes into the flag register no matter what. I'm not sure what can be done. Add a usubo with a transform that work on a sub and nothing that use the flag and see the transform kicks in ?

[deadalnix]

Rebase and fix merge conflict. Also, ping ?

[RKSimon]

LGTM with one minor to check for vector types.

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

2115 ↗

(On Diff #89959)

Please can you add an early out for vectors then, just in case.

[deadalnix]

Bail in case of vector type.

[RKSimon]

LGTM - thanks.

llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

private:
     //
     SDValue visitTokenFactor(SDNode *N);
     SDValue visitMERGE_VALUES(SDNode *N);
     SDValue visitADD(SDNode *N);
     SDValue visitADDLike(SDValue N0, SDValue N1, SDNode *LocReference);
     SDValue visitSUB(SDNode *N);
     SDValue visitADDC(SDNode *N);
     SDValue visitSUBC(SDNode *N);
+    SDValue visitUSUBO(SDNode *N);
     SDValue visitADDE(SDNode *N);
     SDValue visitSUBE(SDNode *N);
     SDValue visitMUL(SDNode *N);
     SDValue useDivRem(SDNode *N);
     SDValue visitSDIV(SDNode *N);
     SDValue visitUDIV(SDNode *N);
     SDValue visitREM(SDNode *N);
     SDValue visitMULHU(SDNode *N);
SDValue DAGCombiner::visit(SDNode *N) {
   switch (N->getOpcode()) {
   default: break;
   case ISD::TokenFactor:        return visitTokenFactor(N);
   case ISD::MERGE_VALUES:       return visitMERGE_VALUES(N);
   case ISD::ADD:                return visitADD(N);
   case ISD::SUB:                return visitSUB(N);
   case ISD::ADDC:               return visitADDC(N);
   case ISD::SUBC:               return visitSUBC(N);
+  case ISD::USUBO:              return visitUSUBO(N);
   case ISD::ADDE:               return visitADDE(N);
   case ISD::SUBE:               return visitSUBE(N);
   case ISD::MUL:                return visitMUL(N);
   case ISD::SDIV:               return visitSDIV(N);
   case ISD::UDIV:               return visitUDIV(N);
   case ISD::SREM:
   case ISD::UREM:               return visitREM(N);
   case ISD::MULHU:              return visitMULHU(N);
SDValue DAGCombiner::visitSUBC(SDNode *N) {
   // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) + no borrow
   if (isAllOnesConstant(N0))
     return CombineTo(N, DAG.getNode(ISD::XOR, DL, VT, N1, N0),
                      DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));
 
   return SDValue();
 }
 
+SDValue DAGCombiner::visitUSUBO(SDNode *N) {
+  SDValue N0 = N->getOperand(0);
+  SDValue N1 = N->getOperand(1);
+  EVT VT = N0.getValueType();
+  if (VT.isVector())
+    return SDValue();
+
+  EVT CarryVT = N->getValueType(1);
+  SDLoc DL(N);
+
+  // If the flag result is dead, turn this into an SUB.
+  if (!N->hasAnyUseOfValue(1))
+    return CombineTo(N, DAG.getNode(ISD::SUB, DL, VT, N0, N1),
+                     DAG.getUNDEF(CarryVT));
+
+  // fold (usubo x, x) -> 0 + no borrow
+  if (N0 == N1)
+    return CombineTo(N, DAG.getConstant(0, DL, VT),
+                     DAG.getConstant(0, DL, CarryVT));
+
+  // fold (usubo x, 0) -> x + no borrow
+  if (isNullConstant(N1))
+    return CombineTo(N, N0, DAG.getConstant(0, DL, CarryVT));
+
+  // Canonicalize (usubo -1, x) -> ~x, i.e. (xor x, -1) + no borrow
+  if (isAllOnesConstant(N0))
+    return CombineTo(N, DAG.getNode(ISD::XOR, DL, VT, N1, N0),
+                     DAG.getConstant(0, DL, CarryVT));
+
+  return SDValue();
+}
+
 SDValue DAGCombiner::visitSUBE(SDNode *N) {
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);
   SDValue CarryIn = N->getOperand(2);
 
   // fold (sube x, y, false) -> (subc x, y)
   if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
     return DAG.getNode(ISD::SUBC, SDLoc(N), N->getVTList(), N0, N1);

llvm/trunk/test/CodeGen/X86/xaluo.ll

; KNL-NEXT:    retq
   %2 = and i64 %b, 255
   %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %1, i64 %2)
   ret {i64, i1} %t
 }
 
 define {i64, i1} @usuboovf(i64 %a, i64 %b) {
 ; SDAG-LABEL: usuboovf:
 ; SDAG:       ## BB#0:
-; SDAG-NEXT:    subq %rdi, %rdi
-; SDAG-NEXT:    sbbb %r8b, %r8b
-; SDAG-NEXT:    movq $-1, %rax
-; SDAG-NEXT:    subq %rsi, %rax
-; SDAG-NEXT:    sbbb %cl, %cl
-; SDAG-NEXT:    subq %rdi, %rax
-; SDAG-NEXT:    sbbb %dl, %dl
-; SDAG-NEXT:    orb %cl, %dl
-; SDAG-NEXT:    orb %r8b, %dl
-; SDAG-NEXT:    andb $1, %dl
+; SDAG-NEXT:    notq %rsi
+; SDAG-NEXT:    xorl %edx, %edx
+; SDAG-NEXT:    movq %rsi, %rax
 ; SDAG-NEXT:    retq
 ;
 ; FAST-LABEL: usuboovf:
 ; FAST:       ## BB#0:
-; FAST-NEXT:    subq %rdi, %rdi
-; FAST-NEXT:    sbbb %r8b, %r8b
-; FAST-NEXT:    movq $-1, %rax
-; FAST-NEXT:    subq %rsi, %rax
-; FAST-NEXT:    sbbb %cl, %cl
-; FAST-NEXT:    subq %rdi, %rax
-; FAST-NEXT:    sbbb %dl, %dl
-; FAST-NEXT:    orb %cl, %dl
-; FAST-NEXT:    orb %r8b, %dl
-; FAST-NEXT:    andb $1, %dl
+; FAST-NEXT:    notq %rsi
+; FAST-NEXT:    xorl %edx, %edx
+; FAST-NEXT:    movq %rsi, %rax
 ; FAST-NEXT:    retq
 ;
 ; KNL-LABEL: usuboovf:
 ; KNL:       ## BB#0:
-; KNL-NEXT:    subq %rdi, %rdi
-; KNL-NEXT:    sbbb %dl, %dl
-; KNL-NEXT:    movq $-1, %rax
-; KNL-NEXT:    subq %rsi, %rax
-; KNL-NEXT:    sbbb %cl, %cl
-; KNL-NEXT:    orb %dl, %cl
-; KNL-NEXT:    subq %rdi, %rax
-; KNL-NEXT:    sbbb %dl, %dl
-; KNL-NEXT:    orb %cl, %dl
+; KNL-NEXT:    notq %rsi
+; KNL-NEXT:    xorl %edx, %edx
+; KNL-NEXT:    movq %rsi, %rax
 ; KNL-NEXT:    retq
   %t0 = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %a, i64 %a)
   %v0 = extractvalue {i64, i1} %t0, 0
   %o0 = extractvalue {i64, i1} %t0, 1
   %t1 = call {i64, i1} @llvm.usub.with.overflow.i64(i64 -1, i64 %b)
   %v1 = extractvalue {i64, i1} %t1, 0
   %o1 = extractvalue {i64, i1} %t1, 1
   %oo = or i1 %o0, %o1