[ARM] Diagnose PC-writing instructions in IT blocks

[olista01]

Summary

In Thumb2, instructions which write to the PC are UNPREDICTABLE if they are in an IT block but not the last instruction in the block.

Previously, we only diagnosed this for LDM instructions, this patch extends the diagnostic to cover all of the relevant instructions.

[SjoerdMeijer]

Looks good to me.

llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

bool ARMAsmParser::validatetLDMRegList(const MCInst &Inst,
   bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC);
 
   if (!IsARPop && ListContainsSP)
     return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
                  "SP may not be in the register list");
   else if (ListContainsPC && ListContainsLR)
     return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
                  "PC and LR may not be in the register list simultaneously");
-  else if (inITBlock() && !lastInITBlock() && ListContainsPC)
-    return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
-                 "instruction must be outside of IT block or the last "
-                 "instruction in an IT block");
   return false;
 }
 
 bool ARMAsmParser::validatetSTMRegList(const MCInst &Inst,
                                        const OperandVector &Operands,
                                        unsigned ListNo) {
   const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]);
   bool HasWritebackToken = Op.isToken() && Op.getToken() == "!";
// Check for non-'al' condition codes outside of the IT block.
              Inst.getOpcode() != ARM::t2Bcc) {
     return Error(Loc, "predicated instructions must be in IT block");
   } else if (!isThumb() && !useImplicitITARM() && MCID.isPredicable() &&
              Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
                  ARMCC::AL) {
     return Warning(Loc, "predicated instructions should be in IT block");
   }
 
+  // PC-setting instructions in an IT block, but not the last instruction of
+  // the block, are UNPREDICTABLE.
+  if (inExplicitITBlock() && !lastInITBlock() && isITBlockTerminator(Inst)) {
+    return Error(Loc, "instruction must be outside of IT block or the last instruction in an IT block");
+  }
+
   const unsigned Opcode = Inst.getOpcode();
   switch (Opcode) {
   case ARM::LDRD:
   case ARM::LDRD_PRE:
   case ARM::LDRD_POST: {
     const unsigned RtReg = Inst.getOperand(0).getReg();
 
     // Rt can't be R14.
bool ARMAsmParser::isITBlockTerminator(MCInst &Inst) const {
 
   if (MCID.hasImplicitDefOfPhysReg(ARM::PC, MRI))
     return true;
 
   // Instructions with variable operand lists, which write to the variable
   // operands. We only care about Thumb instructions here, as ARM instructions
   // obviously can't be in an IT block.
   switch (Inst.getOpcode()) {
+  case ARM::tLDMIA:
   case ARM::t2LDMIA:
   case ARM::t2LDMIA_UPD:
   case ARM::t2LDMDB:
   case ARM::t2LDMDB_UPD:
     if (listContainsReg(Inst, 3, ARM::PC))
       return true;
     break;
   case ARM::tPOP:

llvm/trunk/test/MC/ARM/arm-thumb-trustzone.s

 _func:
 @ CHECK: _func
 
 
 @------------------------------------------------------------------------------
 @ SMC
 @------------------------------------------------------------------------------
         smc #0xf
-        ite eq
+        it eq
         smceq #0
 
 @ NOTZ-NOT: smc   #15
 @ NOTZ-NOT: smceq #0
 @ TZ: smc  #15                     @ encoding: [0xff,0xf7,0x00,0x80]
-@ TZ: ite  eq                      @ encoding: [0x0c,0xbf]
+@ TZ: it  eq                      @ encoding: [0x08,0xbf]
 @ TZ: smceq  #0                      @ encoding: [0xf0,0xf7,0x00,0x80]

llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s

 @ CHECK: sub.w  sp, sp, r12             @ encoding: [0xad,0xeb,0x0c,0x0d]
 @ CHECK: sub.w  sp, sp, r12             @ encoding: [0xad,0xeb,0x0c,0x0d]
 
 
 @------------------------------------------------------------------------------
 @ SVC
 @------------------------------------------------------------------------------
         svc #0
-        ite eq
+        it eq
         svceq #255
+        it ne
         swine #33
 
 @ CHECK: svc  #0                      @ encoding: [0x00,0xdf]
-@ CHECK: ite  eq                      @ encoding: [0x0c,0xbf]
+@ CHECK: it  eq                      @ encoding: [0x08,0xbf]
 @ CHECK: svceq  #255                    @ encoding: [0xff,0xdf]
+@ CHECK: it  ne                      @ encoding: [0x18,0xbf]
 @ CHECK: svcne  #33                     @ encoding: [0x21,0xdf]
 
 
 @------------------------------------------------------------------------------
 @ SXTAB
 @------------------------------------------------------------------------------
         sxtab r2, r3, r4
         sxtab r4, r5, r6, ror #0

llvm/trunk/test/MC/ARM/unpred-control-flow-in-it-block.s

+@ RUN: not llvm-mc -triple=thumbv7m--none-eabi < %s 2>&1 | FileCheck %s
+
+@ These instructions all write to the PC, so are UNPREDICTABLE if they are in
+@ an IT block, but not the last instruction in the block.
+
+  itttt eq
+  addeq pc, r0
+@ CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction must be outside of IT block or the last instruction in an IT block
+  addeq pc, sp, pc
+@ CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction must be outside of IT block or the last instruction in an IT block
+  beq.n #.+0x20
+@ CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction must be outside of IT block or the last instruction in an IT block
+  nopeq
+  itttt eq
+  beq.w #.+0x20
+@ CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction must be outside of IT block or the last instruction in an IT block
+  bleq sym
+@ CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction must be outside of IT block or the last instruction in an IT block
+  blxeq r0
+@ CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction must be outside of IT block or the last instruction in an IT block
+  nopeq
+  itttt eq
+  bxeq r0
+@ CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction must be outside of IT block or the last instruction in an IT block
+  ldmeq r0, {r8, pc}
+@ CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction must be outside of IT block or the last instruction in an IT block
+  ldmdbeq r0, {r8, pc}
+@ CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction must be outside of IT block or the last instruction in an IT block
+  nopeq
+  itttt eq
+  ldreq pc, [r0, #4]
+@ CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction must be outside of IT block or the last instruction in an IT block
+  ldreq pc, [r0, #-4]
+@ CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction must be outside of IT block or the last instruction in an IT block
+  ldreq pc, [pc, #4]
+@ CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction must be outside of IT block or the last instruction in an IT block
+  nopeq
+  itttt eq
+  ldreq pc, [r0, r1, LSL #1]
+@ CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction must be outside of IT block or the last instruction in an IT block
+  moveq pc, r0
+@ CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction must be outside of IT block or the last instruction in an IT block
+  popeq {r0, pc}
+@ CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction must be outside of IT block or the last instruction in an IT block
+  nopeq
+  itttt eq
+  popeq {r8, pc}
+@ CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction must be outside of IT block or the last instruction in an IT block
+  popeq {pc}
+@ CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction must be outside of IT block or the last instruction in an IT block
+  tbbeq [r0, r1]
+@ CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction must be outside of IT block or the last instruction in an IT block
+  nopeq
+  itt eq
+  tbheq [r0, r1, LSL #1]
+@ CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction must be outside of IT block or the last instruction in an IT block
+  nopeq