[AMDGPU] Runtime metadata fixes:

[kzhuravl]

Summary

1. Verify that runtime metadata is actually valid runtime metadata when assembling, otherwise we could accept the following when assembling, but ocl runtime will reject it:

.amdgpu_runtime_metadata
{ amd.MDVersion: [ 2, 1 ], amd.RandomUnknownKey, amd.IsaInfo:

2. Make IsaInfo optional, and always emit it.

[arsenm]

LGTM

lib/Target/AMDGPU/MCTargetDesc/AMDGPURuntimeMD.cpp

379–383 ↗

(On Diff #89716)

You don't need the llvm::'s

test/MC/AMDGPU/runtime-metadata-invalid-1.s

106–125 ↗

(On Diff #89716)

You can drop the extra comments here

[yaxunl]

LGTM. Thanks!

llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

public:
   };
 
   AMDGPUAsmParser(const MCSubtargetInfo &STI, MCAsmParser &_Parser,
                const MCInstrInfo &MII,
                const MCTargetOptions &Options)
       : MCTargetAsmParser(Options, STI), MII(MII), Parser(_Parser) {
     MCAsmParserExtension::Initialize(Parser);
 
-    if (getSTI().getFeatureBits().none()) {
+    if (getFeatureBits().none()) {
       // Set default features.
       copySTI().ToggleFeature("SOUTHERN_ISLANDS");
     }
 
-    setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
+    setAvailableFeatures(ComputeAvailableFeatures(getFeatureBits()));
 
     {
       // TODO: make those pre-defined variables read-only.
       // Currently there is none suitable machinery in the core llvm-mc for this.
       // MCSymbol::isRedefinable is intended for another purpose, and
       // AsmParser::parseDirectiveSet() cannot be specialized for specific target.
       AMDGPU::IsaInfo::IsaVersion ISA =
-          AMDGPU::IsaInfo::getIsaVersion(getSTI().getFeatureBits());
+          AMDGPU::IsaInfo::getIsaVersion(getFeatureBits());
       MCContext &Ctx = getContext();
       MCSymbol *Sym =
           Ctx.getOrCreateSymbol(Twine(".option.machine_version_major"));
       Sym->setVariableValue(MCConstantExpr::create(ISA.Major, Ctx));
       Sym = Ctx.getOrCreateSymbol(Twine(".option.machine_version_minor"));
       Sym->setVariableValue(MCConstantExpr::create(ISA.Minor, Ctx));
       Sym = Ctx.getOrCreateSymbol(Twine(".option.machine_version_stepping"));
       Sym->setVariableValue(MCConstantExpr::create(ISA.Stepping, Ctx));
bool isCI() const {
     return AMDGPU::isCI(getSTI());
   }
 
   bool isVI() const {
     return AMDGPU::isVI(getSTI());
   }
 
   bool hasInv2PiInlineImm() const {
-    return getSTI().getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm];
+    return getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm];
   }
 
   bool hasSGPR102_SGPR103() const {
     return !isVI();
   }
 
   AMDGPUTargetStreamer &getTargetStreamer() {
     MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
     return static_cast<AMDGPUTargetStreamer &>(TS);
   }
 
   const MCRegisterInfo *getMRI() const {
     // We need this const_cast because for some reason getContext() is not const
     // in MCAsmParser.
     return const_cast<AMDGPUAsmParser*>(this)->getContext().getRegisterInfo();
   }
 
   const MCInstrInfo *getMII() const {
     return &MII;
   }
 
+  const FeatureBitset &getFeatureBits() const {
+    return getSTI().getFeatureBits();
+  }
+
   void setForcedEncodingSize(unsigned Size) { ForcedEncodingSize = Size; }
   void setForcedDPP(bool ForceDPP_) { ForcedDPP = ForceDPP_; }
   void setForcedSDWA(bool ForceSDWA_) { ForcedSDWA = ForceSDWA_; }
 
   unsigned getForcedEncodingSize() const { return ForcedEncodingSize; }
   bool isForcedVOP3() const { return ForcedEncodingSize == 64; }
   bool isForcedDPP() const { return ForcedDPP; }
   bool isForcedSDWA() const { return ForcedSDWA; }
bool AMDGPUAsmParser::ParseDirectiveHSACodeObjectISA() {
   uint32_t Stepping;
   StringRef VendorName;
   StringRef ArchName;
 
   // If this directive has no arguments, then use the ISA version for the
   // targeted GPU.
   if (getLexer().is(AsmToken::EndOfStatement)) {
     AMDGPU::IsaInfo::IsaVersion ISA =
-        AMDGPU::IsaInfo::getIsaVersion(getSTI().getFeatureBits());
+        AMDGPU::IsaInfo::getIsaVersion(getFeatureBits());
     getTargetStreamer().EmitDirectiveHSACodeObjectISA(ISA.Major, ISA.Minor,
                                                       ISA.Stepping,
                                                       "AMD", "AMDGPU");
     return false;
   }
 
   if (ParseDirectiveMajorMinor(Major, Minor))
     return true;
bool AMDGPUAsmParser::ParseDirectiveRuntimeMetadata() {
 
   getLexer().setSkipSpace(true);
 
   if (getLexer().is(AsmToken::Eof) && !FoundEnd)
     return TokError("expected directive .end_amdgpu_runtime_metadata not found");
 
   MS.flush();
 
-  getTargetStreamer().EmitRuntimeMetadata(Metadata);
+  if (getTargetStreamer().EmitRuntimeMetadata(getFeatureBits(), Metadata))
+    return Error(getParser().getTok().getLoc(), "invalid runtime metadata");
 
   return false;
 }
 
 bool AMDGPUAsmParser::ParseAMDKernelCodeTValue(StringRef ID,
                                                amd_kernel_code_t &Header) {
   SmallString<40> ErrStr;
   raw_svector_ostream Err(ErrStr);
   if (!parseAmdKernelCodeField(ID, getParser(), Header, Err)) {
     return TokError(Err.str());
   }
   Lex();
   return false;
 }
 
 bool AMDGPUAsmParser::ParseDirectiveAMDKernelCodeT() {
   amd_kernel_code_t Header;
-  AMDGPU::initDefaultAMDKernelCodeT(Header, getSTI().getFeatureBits());
+  AMDGPU::initDefaultAMDKernelCodeT(Header, getFeatureBits());
 
   while (true) {
     // Lex EndOfStatement.  This is in a while loop, because lexing a comment
     // will set the current token to EndOfStatement.
     while(getLexer().is(AsmToken::EndOfStatement))
       Lex();
 
     if (getLexer().isNot(AsmToken::Identifier))
bool AMDGPUAsmParser::parseCnt(int64_t &IntVal) {
   if (getLexer().isNot(AsmToken::RParen))
     return true;
 
   Parser.Lex();
   if (getLexer().is(AsmToken::Amp) || getLexer().is(AsmToken::Comma))
     Parser.Lex();
 
   AMDGPU::IsaInfo::IsaVersion ISA =
-      AMDGPU::IsaInfo::getIsaVersion(getSTI().getFeatureBits());
+      AMDGPU::IsaInfo::getIsaVersion(getFeatureBits());
   if (CntName == "vmcnt")
     IntVal = encodeVmcnt(ISA, IntVal, CntVal);
   else if (CntName == "expcnt")
     IntVal = encodeExpcnt(ISA, IntVal, CntVal);
   else if (CntName == "lgkmcnt")
     IntVal = encodeLgkmcnt(ISA, IntVal, CntVal);
   else
     return true;
 
   return false;
 }
 
 OperandMatchResultTy
 AMDGPUAsmParser::parseSWaitCntOps(OperandVector &Operands) {
   AMDGPU::IsaInfo::IsaVersion ISA =
-      AMDGPU::IsaInfo::getIsaVersion(getSTI().getFeatureBits());
+      AMDGPU::IsaInfo::getIsaVersion(getFeatureBits());
   int64_t Waitcnt = getWaitcntBitMask(ISA);
   SMLoc S = Parser.getTok().getLoc();
 
   switch(getLexer().getKind()) {
     default: return MatchOperand_ParseFail;
     case AsmToken::Integer:
       // The operand can be an integer value.
       if (getParser().parseAbsoluteExpression(Waitcnt))

llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPURuntimeMD.h

 //===- AMDGPURuntimeMD.h - Generate runtime metadata ---------------*- C++ -*-//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file declares functions for generating runtime metadata.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPURUNTIMEMD_H
 #define LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPURUNTIMEMD_H
 
+#include "llvm/Support/ErrorOr.h"
 #include <string>
 
 namespace llvm {
 class FeatureBitset;
 class Module;
 
-// Get runtime metadata as YAML string.
+/// \returns Runtime metadata as YAML string.
 std::string getRuntimeMDYAMLString(const FeatureBitset &Features,
                                    const Module &M);
 
+/// \returns \p YAML if \p YAML is valid runtime metadata, error otherwise.
+ErrorOr<std::string> getRuntimeMDYAMLString(const FeatureBitset &Features,
+                                            StringRef YAML);
+
 }
 #endif

llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPURuntimeMD.cpp

 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Support/YAMLTraits.h"
 #include <cassert>
 #include <cstdint>
 #include <limits>
 #include <vector>
 
 using namespace llvm;
+using namespace llvm::AMDGPU::IsaInfo;
 using namespace ::AMDGPU::RuntimeMD;
 
 static cl::opt<bool>
 DumpRuntimeMD("amdgpu-dump-rtmd",
               cl::desc("Dump AMDGPU runtime metadata"));
 
 static cl::opt<bool>
 CheckRuntimeMDParser("amdgpu-check-rtmd-parser", cl::Hidden,
static void mapping(IO &YamlIO, Kernel::Metadata &K) {
     YamlIO.mapOptional(KeyName::LanguageVersion, K.LanguageVersion);
     YamlIO.mapOptional(KeyName::ReqdWorkGroupSize, K.ReqdWorkGroupSize);
     YamlIO.mapOptional(KeyName::WorkGroupSizeHint, K.WorkGroupSizeHint);
     YamlIO.mapOptional(KeyName::VecTypeHint, K.VecTypeHint, std::string());
     YamlIO.mapOptional(KeyName::KernelIndex, K.KernelIndex,
         INVALID_KERNEL_INDEX);
     YamlIO.mapOptional(KeyName::NoPartialWorkGroups, K.NoPartialWorkGroups,
         uint8_t(0));
-    YamlIO.mapRequired(KeyName::Args, K.Args);
+    YamlIO.mapOptional(KeyName::Args, K.Args);
   }
   static const bool flow = true;
 };
 
 template <> struct MappingTraits<IsaInfo::Metadata> {
   static void mapping(IO &YamlIO, IsaInfo::Metadata &I) {
     YamlIO.mapRequired(KeyName::IsaInfoWavefrontSize, I.WavefrontSize);
     YamlIO.mapRequired(KeyName::IsaInfoLocalMemorySize, I.LocalMemorySize);
YamlIO.mapRequired(KeyName::IsaInfoAddressableNumVGPRs,
         I.AddressableNumVGPRs);
   }
   static const bool flow = true;
 };
 
 template <> struct MappingTraits<Program::Metadata> {
   static void mapping(IO &YamlIO, Program::Metadata &Prog) {
     YamlIO.mapRequired(KeyName::MDVersion, Prog.MDVersionSeq);
-    YamlIO.mapRequired(KeyName::IsaInfo, Prog.IsaInfo);
+    YamlIO.mapOptional(KeyName::IsaInfo, Prog.IsaInfo);
     YamlIO.mapOptional(KeyName::PrintfInfo, Prog.PrintfInfo);
     YamlIO.mapOptional(KeyName::Kernels, Prog.Kernels);
   }
   static const bool flow = true;
 };
 
 } // end namespace yaml
 } // end namespace llvm
static Kernel::Metadata getRuntimeMDForKernel(const Function &F) {
   if (auto VTH = F.getMetadata("vec_type_hint"))
     Kernel.VecTypeHint = getOCLTypeName(cast<ValueAsMetadata>(
       VTH->getOperand(0))->getType(), mdconst::extract<ConstantInt>(
       VTH->getOperand(1))->getZExtValue());
 
   return Kernel;
 }
 
+static void getIsaInfo(const FeatureBitset &Features, IsaInfo::Metadata &IIM) {
+  IIM.WavefrontSize = getWavefrontSize(Features);
+  IIM.LocalMemorySize = getLocalMemorySize(Features);
+  IIM.EUsPerCU = getEUsPerCU(Features);
+  IIM.MaxWavesPerEU = getMaxWavesPerEU(Features);
+  IIM.MaxFlatWorkGroupSize = getMaxFlatWorkGroupSize(Features);
+  IIM.SGPRAllocGranule = getSGPRAllocGranule(Features);
+  IIM.TotalNumSGPRs = getTotalNumSGPRs(Features);
+  IIM.AddressableNumSGPRs = getAddressableNumSGPRs(Features);
+  IIM.VGPRAllocGranule = getVGPRAllocGranule(Features);
+  IIM.TotalNumVGPRs = getTotalNumVGPRs(Features);
+  IIM.AddressableNumVGPRs = getAddressableNumVGPRs(Features);
+}
+
 Program::Metadata::Metadata(const std::string &YAML) {
   yaml::Input Input(YAML);
   Input >> *this;
 }
 
 std::string Program::Metadata::toYAML() {
   std::string Text;
   raw_string_ostream Stream(Text);

 }
 
 std::string llvm::getRuntimeMDYAMLString(const FeatureBitset &Features,
                                          const Module &M) {
   Program::Metadata Prog;
   Prog.MDVersionSeq.push_back(MDVersion);
   Prog.MDVersionSeq.push_back(MDRevision);
 
-  IsaInfo::Metadata &IIM = Prog.IsaInfo;
-  IIM.WavefrontSize = AMDGPU::IsaInfo::getWavefrontSize(Features);
-  IIM.LocalMemorySize = AMDGPU::IsaInfo::getLocalMemorySize(Features);
-  IIM.EUsPerCU = AMDGPU::IsaInfo::getEUsPerCU(Features);
-  IIM.MaxWavesPerEU = AMDGPU::IsaInfo::getMaxWavesPerEU(Features);
-  IIM.MaxFlatWorkGroupSize = AMDGPU::IsaInfo::getMaxFlatWorkGroupSize(Features);
-  IIM.SGPRAllocGranule = AMDGPU::IsaInfo::getSGPRAllocGranule(Features);
-  IIM.TotalNumSGPRs = AMDGPU::IsaInfo::getTotalNumSGPRs(Features);
-  IIM.AddressableNumSGPRs = AMDGPU::IsaInfo::getAddressableNumSGPRs(Features);
-  IIM.VGPRAllocGranule = AMDGPU::IsaInfo::getVGPRAllocGranule(Features);
-  IIM.TotalNumVGPRs = AMDGPU::IsaInfo::getTotalNumVGPRs(Features);
-  IIM.AddressableNumVGPRs = AMDGPU::IsaInfo::getAddressableNumVGPRs(Features);
+  getIsaInfo(Features, Prog.IsaInfo);
 
   // Set PrintfInfo.
   if (auto MD = M.getNamedMetadata("llvm.printf.fmts")) {
     for (unsigned I = 0; I < MD->getNumOperands(); ++I) {
       auto Node = MD->getOperand(I);
       if (Node->getNumOperands() > 0)
         Prog.PrintfInfo.push_back(cast<MDString>(Node->getOperand(0))
             ->getString());
std::string llvm::getRuntimeMDYAMLString(const FeatureBitset &Features,
   if (DumpRuntimeMD)
     errs() << "AMDGPU runtime metadata:\n" << YAML << '\n';
 
   if (CheckRuntimeMDParser)
     checkRuntimeMDYAMLString(YAML);
 
   return YAML;
 }
+
+ErrorOr<std::string> llvm::getRuntimeMDYAMLString(const FeatureBitset &Features,
+                                                  StringRef YAML) {
+  Program::Metadata Prog;
+  yaml::Input Input(YAML);
+  Input >> Prog;
+
+  getIsaInfo(Features, Prog.IsaInfo);
+
+  if (Input.error())
+    return Input.error();
+  return Prog.toYAML();
+}

llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h

public:
 
   virtual void EmitAMDGPUHsaModuleScopeGlobal(StringRef GlobalName) = 0;
 
   virtual void EmitAMDGPUHsaProgramScopeGlobal(StringRef GlobalName) = 0;
 
   virtual void EmitRuntimeMetadata(const FeatureBitset &Features,
                                    const Module &M) = 0;
 
-  virtual void EmitRuntimeMetadata(StringRef Metadata) = 0;
+  /// \returns False on success, true on failure.
+  virtual bool EmitRuntimeMetadata(const FeatureBitset &Features,
+                                   StringRef Metadata) = 0;
 };
 
 class AMDGPUTargetAsmStreamer : public AMDGPUTargetStreamer {
   formatted_raw_ostream &OS;
 public:
   AMDGPUTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS);
   void EmitDirectiveHSACodeObjectVersion(uint32_t Major,
                                          uint32_t Minor) override;
 
   void EmitDirectiveHSACodeObjectISA(uint32_t Major, uint32_t Minor,
                                      uint32_t Stepping, StringRef VendorName,
                                      StringRef ArchName) override;
 
   void EmitAMDKernelCodeT(const amd_kernel_code_t &Header) override;
 
   void EmitAMDGPUSymbolType(StringRef SymbolName, unsigned Type) override;
 
   void EmitAMDGPUHsaModuleScopeGlobal(StringRef GlobalName) override;
 
   void EmitAMDGPUHsaProgramScopeGlobal(StringRef GlobalName) override;
 
   void EmitRuntimeMetadata(const FeatureBitset &Features,
                            const Module &M) override;
 
-  void EmitRuntimeMetadata(StringRef Metadata) override;
+  /// \returns False on success, true on failure.
+  bool EmitRuntimeMetadata(const FeatureBitset &Features,
+                           StringRef Metadata) override;
 };
 
 class AMDGPUTargetELFStreamer : public AMDGPUTargetStreamer {
   MCStreamer &Streamer;
 
   void EmitAMDGPUNote(const MCExpr *DescSize, AMDGPU::PT_NOTE::NoteType Type,
                       function_ref<void(MCELFStreamer &)> EmitDesc);
 
public:
 
   void EmitAMDGPUHsaModuleScopeGlobal(StringRef GlobalName) override;
 
   void EmitAMDGPUHsaProgramScopeGlobal(StringRef GlobalName) override;
 
   void EmitRuntimeMetadata(const FeatureBitset &Features,
                            const Module &M) override;
 
-  void EmitRuntimeMetadata(StringRef Metadata) override;
+  /// \returns False on success, true on failure.
+  bool EmitRuntimeMetadata(const FeatureBitset &Features,
+                           StringRef Metadata) override;
 };
 
 }
 #endif

llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp

 
 void AMDGPUTargetAsmStreamer::EmitRuntimeMetadata(const FeatureBitset &Features,
                                                   const Module &M) {
   OS << "\t.amdgpu_runtime_metadata\n";
   OS << getRuntimeMDYAMLString(Features, M);
   OS << "\n\t.end_amdgpu_runtime_metadata\n";
 }
 
-void AMDGPUTargetAsmStreamer::EmitRuntimeMetadata(StringRef Metadata) {
+bool AMDGPUTargetAsmStreamer::EmitRuntimeMetadata(const FeatureBitset &Features,
+                                                  StringRef Metadata) {
+  auto VerifiedMetadata = getRuntimeMDYAMLString(Features, Metadata);
+  if (!VerifiedMetadata)
+    return true;
+
   OS << "\t.amdgpu_runtime_metadata";
-  OS << Metadata;
+  OS << VerifiedMetadata.get();
   OS << "\t.end_amdgpu_runtime_metadata\n";
+
+  return false;
 }
 
 //===----------------------------------------------------------------------===//
 // AMDGPUTargetELFStreamer
 //===----------------------------------------------------------------------===//
 
 AMDGPUTargetELFStreamer::AMDGPUTargetELFStreamer(MCStreamer &S)
     : AMDGPUTargetStreamer(S), Streamer(S) {}
void AMDGPUTargetELFStreamer::EmitAMDGPUHsaProgramScopeGlobal(
     StringRef GlobalName) {
 
   MCSymbolELF *Symbol = cast<MCSymbolELF>(
       getStreamer().getContext().getOrCreateSymbol(GlobalName));
   Symbol->setType(ELF::STT_OBJECT);
   Symbol->setBinding(ELF::STB_GLOBAL);
 }
 
-void AMDGPUTargetELFStreamer::EmitRuntimeMetadata(StringRef Metadata) {
+bool AMDGPUTargetELFStreamer::EmitRuntimeMetadata(const FeatureBitset &Features,
+                                                  StringRef Metadata) {
+  auto VerifiedMetadata = getRuntimeMDYAMLString(Features, Metadata);
+  if (!VerifiedMetadata)
+    return true;
+
   // Create two labels to mark the beginning and end of the desc field
   // and a MCExpr to calculate the size of the desc field.
   auto &Context = getContext();
   auto *DescBegin = Context.createTempSymbol();
   auto *DescEnd = Context.createTempSymbol();
   auto *DescSZ = MCBinaryExpr::createSub(
     MCSymbolRefExpr::create(DescEnd, Context),
     MCSymbolRefExpr::create(DescBegin, Context), Context);
 
   EmitAMDGPUNote(
     DescSZ,
     PT_NOTE::NT_AMDGPU_HSA_RUNTIME_METADATA,
     [&](MCELFStreamer &OS) {
       OS.EmitLabel(DescBegin);
-      OS.EmitBytes(Metadata);
+      OS.EmitBytes(VerifiedMetadata.get());
       OS.EmitLabel(DescEnd);
     }
   );
+
+  return false;
 }
 
 void AMDGPUTargetELFStreamer::EmitRuntimeMetadata(const FeatureBitset &Features,
                                                   const Module &M) {
-  EmitRuntimeMetadata(getRuntimeMDYAMLString(Features, M));
+  EmitRuntimeMetadata(Features, getRuntimeMDYAMLString(Features, M));
 }

llvm/trunk/test/MC/AMDGPU/hsa.s

.amdgpu_runtime_metadata
         amd.Kernels: [
             { amd.KernelName: amd_kernel_code_t_test_all },
             { amd.KernelName: amd_kernel_code_t_minimal }
         ]
     }
 .end_amdgpu_runtime_metadata
 
 // ASM: .amdgpu_runtime_metadata
-// ASM:     {
-// ASM:         amd.MDVersion: [ 2, 0 ]
-// ASM:         amd.Kernels: [
-// ASM:             { amd.KernelName: amd_kernel_code_t_test_all },
-// ASM:             { amd.KernelName: amd_kernel_code_t_minimal }
-// ASM:         ]
-// ASM:     }
+// ASM:  {
+// ASM:    amd.MDVersion: [ 2, 0 ]
+// ASM:    amd.IsaInfo: { amd.IsaInfoWavefrontSize: 64, amd.IsaInfoLocalMemorySize: 65536, amd.IsaInfoEUsPerCU: 4, amd.IsaInfoMaxWavesPerEU: 10, amd.IsaInfoMaxFlatWorkGroupSize: 2048, amd.IsaInfoSGPRAllocGranule: 8, amd.IsaInfoTotalNumSGPRs: 512, amd.IsaInfoAddressableNumSGPRs: 104, amd.IsaInfoVGPRAllocGranule: 4, amd.IsaInfoTotalNumVGPRs: 256, amd.IsaInfoAddressableNumVGPRs: 256 },
+// ASM:    amd.Kernels:
+// ASM:      - { amd.KernelName: amd_kernel_code_t_test_all }
+// ASM:      - { amd.KernelName: amd_kernel_code_t_minimal }
+// ASM:  }
 // ASM: .end_amdgpu_runtime_metadata
 
 .amdgpu_hsa_kernel amd_kernel_code_t_test_all
 .amdgpu_hsa_kernel amd_kernel_code_t_minimal
 
 amd_kernel_code_t_test_all:
 ; Test all amd_kernel_code_t members with non-default values.
 .amd_kernel_code_t

llvm/trunk/test/MC/AMDGPU/metadata.s

-// RUN: llvm-mc -triple amdgcn--amdhsa -mcpu=kaveri -show-encoding %s | FileCheck %s --check-prefix=ASM
-
-.amdgpu_runtime_metadata
-    { amd.MDVersion: [ 2, 0 ], amd.PrintfInfo: [ '1:1:4:%d\n', '2:1:8:%g\n' ], amd.Kernels:
-
-    - { amd.KernelName: test_char, amd.Language: OpenCL C, amd.LanguageVersion: [ 2, 0 ], amd.Args:
-        - { amd.ArgSize: 1, amd.ArgAlign: 1, amd.ArgKind: 0, amd.ArgValueType: 1, amd.ArgTypeName: char, amd.ArgAccQual: 0 }
-        - { amd.ArgSize: 8, amd.ArgAlign: 8, amd.ArgKind: 7, amd.ArgValueType: 9 }
-        - { amd.ArgSize: 8, amd.ArgAlign: 8, amd.ArgKind: 8, amd.ArgValueType: 9 }
-        - { amd.ArgSize: 8, amd.ArgAlign: 8, amd.ArgKind: 9, amd.ArgValueType: 9 }
-        - { amd.ArgSize: 8, amd.ArgAlign: 8, amd.ArgKind: 11, amd.ArgValueType: 1, amd.ArgAddrQual: 1 } }
-
-   - { amd.KernelName: test_ushort2, amd.Language: OpenCL C, amd.LanguageVersion: [ 2, 0 ], amd.Args:
-       - { amd.ArgSize: 4, amd.ArgAlign: 4, amd.ArgKind: 0, amd.ArgValueType: 4, amd.ArgTypeName: ushort2, amd.ArgAccQual: 0 }
-       - { amd.ArgSize: 8, amd.ArgAlign: 8, amd.ArgKind: 7, amd.ArgValueType: 9 }
-       - { amd.ArgSize: 8, amd.ArgAlign: 8, amd.ArgKind: 8, amd.ArgValueType: 9 }
-       - { amd.ArgSize: 8, amd.ArgAlign: 8, amd.ArgKind: 9, amd.ArgValueType: 9 }
-       - { amd.ArgSize: 8, amd.ArgAlign: 8, amd.ArgKind: 11, amd.ArgValueType: 1, amd.ArgAddrQual: 1 } }
-   }
-.end_amdgpu_runtime_metadata
-
-// ASM: { amd.MDVersion: [ 2, 0 ], amd.PrintfInfo: [ '1:1:4:%d\n', '2:1:8:%g\n' ], amd.Kernels:
-// ASM: - { amd.KernelName: test_char, amd.Language: OpenCL C, amd.LanguageVersion: [ 2, 0 ], amd.Args:
-// ASM:     - { amd.ArgSize: 1, amd.ArgAlign: 1, amd.ArgKind: 0, amd.ArgValueType: 1, amd.ArgTypeName: char, amd.ArgAccQual: 0 }
-// ASM:     - { amd.ArgSize: 8, amd.ArgAlign: 8, amd.ArgKind: 7, amd.ArgValueType: 9 }
-// ASM:     - { amd.ArgSize: 8, amd.ArgAlign: 8, amd.ArgKind: 8, amd.ArgValueType: 9 }
-// ASM:     - { amd.ArgSize: 8, amd.ArgAlign: 8, amd.ArgKind: 9, amd.ArgValueType: 9 }
-// ASM:     - { amd.ArgSize: 8, amd.ArgAlign: 8, amd.ArgKind: 11, amd.ArgValueType: 1, amd.ArgAddrQual: 1 } }
-// ASM: - { amd.KernelName: test_ushort2, amd.Language: OpenCL C, amd.LanguageVersion: [ 2, 0 ], amd.Args:
-// ASM:    - { amd.ArgSize: 4, amd.ArgAlign: 4, amd.ArgKind: 0, amd.ArgValueType: 4, amd.ArgTypeName: ushort2, amd.ArgAccQual: 0 }
-// ASM:    - { amd.ArgSize: 8, amd.ArgAlign: 8, amd.ArgKind: 7, amd.ArgValueType: 9 }
-// ASM:    - { amd.ArgSize: 8, amd.ArgAlign: 8, amd.ArgKind: 8, amd.ArgValueType: 9 }
-// ASM:    - { amd.ArgSize: 8, amd.ArgAlign: 8, amd.ArgKind: 9, amd.ArgValueType: 9 }
-// ASM:    - { amd.ArgSize: 8, amd.ArgAlign: 8, amd.ArgKind: 11, amd.ArgValueType: 1, amd.ArgAddrQual: 1 } }
-// ASM: }

llvm/trunk/test/MC/AMDGPU/runtime-metadata-1.s

+// RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx700 -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=GFX700
+// RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx800 -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=GFX800
+// RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx900 -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=GFX900
+
+.amdgpu_runtime_metadata
+  { amd.MDVersion: [ 2, 1 ], amd.PrintfInfo: [ '1:1:4:%d\n', '2:1:8:%g\n' ], amd.Kernels:
+    - { amd.KernelName: test_char, amd.Language: OpenCL C, amd.LanguageVersion: [ 2, 0 ], amd.Args:
+        - { amd.ArgSize: 1, amd.ArgAlign: 1, amd.ArgKind: 0, amd.ArgValueType: 1, amd.ArgTypeName: char, amd.ArgAccQual: 0 }
+        - { amd.ArgSize: 8, amd.ArgAlign: 8, amd.ArgKind: 7, amd.ArgValueType: 9 }
+        - { amd.ArgSize: 8, amd.ArgAlign: 8, amd.ArgKind: 8, amd.ArgValueType: 9 }
+        - { amd.ArgSize: 8, amd.ArgAlign: 8, amd.ArgKind: 9, amd.ArgValueType: 9 }
+        - { amd.ArgSize: 8, amd.ArgAlign: 8, amd.ArgKind: 11, amd.ArgValueType: 1, amd.ArgAddrQual: 1 } }
+    - { amd.KernelName: test_ushort2, amd.Language: OpenCL C, amd.LanguageVersion: [ 2, 0 ], amd.Args:
+        - { amd.ArgSize: 4, amd.ArgAlign: 4, amd.ArgKind: 0, amd.ArgValueType: 4, amd.ArgTypeName: ushort2, amd.ArgAccQual: 0 }
+        - { amd.ArgSize: 8, amd.ArgAlign: 8, amd.ArgKind: 7, amd.ArgValueType: 9 }
+        - { amd.ArgSize: 8, amd.ArgAlign: 8, amd.ArgKind: 8, amd.ArgValueType: 9 }
+        - { amd.ArgSize: 8, amd.ArgAlign: 8, amd.ArgKind: 9, amd.ArgValueType: 9 }
+        - { amd.ArgSize: 8, amd.ArgAlign: 8, amd.ArgKind: 11, amd.ArgValueType: 1, amd.ArgAddrQual: 1 } }
+  }
+.end_amdgpu_runtime_metadata
+
+// GFX700: { amd.MDVersion: [ 2, 1 ], amd.IsaInfo: { amd.IsaInfoWavefrontSize: 64, amd.IsaInfoLocalMemorySize: 65536, amd.IsaInfoEUsPerCU: 4, amd.IsaInfoMaxWavesPerEU: 10, amd.IsaInfoMaxFlatWorkGroupSize: 2048, amd.IsaInfoSGPRAllocGranule: 8, amd.IsaInfoTotalNumSGPRs: 512, amd.IsaInfoAddressableNumSGPRs: 104, amd.IsaInfoVGPRAllocGranule: 4, amd.IsaInfoTotalNumVGPRs: 256, amd.IsaInfoAddressableNumVGPRs: 256 }, amd.PrintfInfo: [ '1:1:4:%d\n', '2:1:8:%g\n' ], amd.Kernels:
+
+// GFX800: { amd.MDVersion: [ 2, 1 ], amd.IsaInfo: { amd.IsaInfoWavefrontSize: 64, amd.IsaInfoLocalMemorySize: 65536, amd.IsaInfoEUsPerCU: 4, amd.IsaInfoMaxWavesPerEU: 10, amd.IsaInfoMaxFlatWorkGroupSize: 2048, amd.IsaInfoSGPRAllocGranule: 16, amd.IsaInfoTotalNumSGPRs: 800, amd.IsaInfoAddressableNumSGPRs: 96, amd.IsaInfoVGPRAllocGranule: 4, amd.IsaInfoTotalNumVGPRs: 256, amd.IsaInfoAddressableNumVGPRs: 256 }, amd.PrintfInfo: [ '1:1:4:%d\n', '2:1:8:%g\n' ], amd.Kernels:
+
+// GFX900: { amd.MDVersion: [ 2, 1 ], amd.IsaInfo: { amd.IsaInfoWavefrontSize: 64, amd.IsaInfoLocalMemorySize: 65536, amd.IsaInfoEUsPerCU: 4, amd.IsaInfoMaxWavesPerEU: 10, amd.IsaInfoMaxFlatWorkGroupSize: 2048, amd.IsaInfoSGPRAllocGranule: 16, amd.IsaInfoTotalNumSGPRs: 800, amd.IsaInfoAddressableNumSGPRs: 102, amd.IsaInfoVGPRAllocGranule: 4, amd.IsaInfoTotalNumVGPRs: 256, amd.IsaInfoAddressableNumVGPRs: 256 }, amd.PrintfInfo: [ '1:1:4:%d\n', '2:1:8:%g\n' ], amd.Kernels:
+
+// GCN:      - { amd.KernelName: test_char, amd.Language: OpenCL C, amd.LanguageVersion: [ 2, 0 ], amd.Args:
+// GCN-NEXT:     - { amd.ArgSize: 1, amd.ArgAlign: 1, amd.ArgKind: 0, amd.ArgValueType: 1, amd.ArgTypeName: char, amd.ArgAccQual: 0 }
+// GCN-NEXT:     - { amd.ArgSize: 8, amd.ArgAlign: 8, amd.ArgKind: 7, amd.ArgValueType: 9 }
+// GCN-NEXT:     - { amd.ArgSize: 8, amd.ArgAlign: 8, amd.ArgKind: 8, amd.ArgValueType: 9 }
+// GCN-NEXT:     - { amd.ArgSize: 8, amd.ArgAlign: 8, amd.ArgKind: 9, amd.ArgValueType: 9 }
+// GCN-NEXT:     - { amd.ArgSize: 8, amd.ArgAlign: 8, amd.ArgKind: 11, amd.ArgValueType: 1, amd.ArgAddrQual: 1 } }
+// GCN-NEXT: - { amd.KernelName: test_ushort2, amd.Language: OpenCL C, amd.LanguageVersion: [ 2, 0 ], amd.Args:
+// GCN-NEXT:     - { amd.ArgSize: 4, amd.ArgAlign: 4, amd.ArgKind: 0, amd.ArgValueType: 4, amd.ArgTypeName: ushort2, amd.ArgAccQual: 0 }
+// GCN-NEXT:     - { amd.ArgSize: 8, amd.ArgAlign: 8, amd.ArgKind: 7, amd.ArgValueType: 9 }
+// GCN-NEXT:     - { amd.ArgSize: 8, amd.ArgAlign: 8, amd.ArgKind: 8, amd.ArgValueType: 9 }
+// GCN-NEXT:     - { amd.ArgSize: 8, amd.ArgAlign: 8, amd.ArgKind: 9, amd.ArgValueType: 9 }
+// GCN-NEXT:     - { amd.ArgSize: 8, amd.ArgAlign: 8, amd.ArgKind: 11, amd.ArgValueType: 1, amd.ArgAddrQual: 1 } } }

llvm/trunk/test/MC/AMDGPU/runtime-metadata-2.s

+// RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx700 -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=GFX700
+// RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx800 -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=GFX800
+// RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx900 -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=GFX900
+
+.amdgpu_runtime_metadata
+  { amd.MDVersion: [ 2, 1 ], amd.IsaInfo: { amd.IsaInfoWavefrontSize: 64, amd.IsaInfoLocalMemorySize: 65536, amd.IsaInfoEUsPerCU: 4, amd.IsaInfoMaxWavesPerEU: 10, amd.IsaInfoMaxFlatWorkGroupSize: 2048, amd.IsaInfoSGPRAllocGranule: 8, amd.IsaInfoTotalNumSGPRs: 512, amd.IsaInfoAddressableNumSGPRs: 104, amd.IsaInfoVGPRAllocGranule: 4, amd.IsaInfoTotalNumVGPRs: 256, amd.IsaInfoAddressableNumVGPRs: 256 }, amd.PrintfInfo: [ '1:1:4:%d\n', '2:1:8:%g\n' ], amd.Kernels:
+    - { amd.KernelName: test_char, amd.Language: OpenCL C, amd.LanguageVersion: [ 2, 0 ], amd.Args:
+        - { amd.ArgSize: 1, amd.ArgAlign: 1, amd.ArgKind: 0, amd.ArgValueType: 1, amd.ArgTypeName: char, amd.ArgAccQual: 0 }
+        - { amd.ArgSize: 8, amd.ArgAlign: 8, amd.ArgKind: 7, amd.ArgValueType: 9 }
+        - { amd.ArgSize: 8, amd.ArgAlign: 8, amd.ArgKind: 8, amd.ArgValueType: 9 }
+        - { amd.ArgSize: 8, amd.ArgAlign: 8, amd.ArgKind: 9, amd.ArgValueType: 9 }
+        - { amd.ArgSize: 8, amd.ArgAlign: 8, amd.ArgKind: 11, amd.ArgValueType: 1, amd.ArgAddrQual: 1 } }
+    - { amd.KernelName: test_ushort2, amd.Language: OpenCL C, amd.LanguageVersion: [ 2, 0 ], amd.Args:
+        - { amd.ArgSize: 4, amd.ArgAlign: 4, amd.ArgKind: 0, amd.ArgValueType: 4, amd.ArgTypeName: ushort2, amd.ArgAccQual: 0 }
+        - { amd.ArgSize: 8, amd.ArgAlign: 8, amd.ArgKind: 7, amd.ArgValueType: 9 }
+        - { amd.ArgSize: 8, amd.ArgAlign: 8, amd.ArgKind: 8, amd.ArgValueType: 9 }
+        - { amd.ArgSize: 8, amd.ArgAlign: 8, amd.ArgKind: 9, amd.ArgValueType: 9 }
+        - { amd.ArgSize: 8, amd.ArgAlign: 8, amd.ArgKind: 11, amd.ArgValueType: 1, amd.ArgAddrQual: 1 } }
+  }
+.end_amdgpu_runtime_metadata
+
+// GFX700: { amd.MDVersion: [ 2, 1 ], amd.IsaInfo: { amd.IsaInfoWavefrontSize: 64, amd.IsaInfoLocalMemorySize: 65536, amd.IsaInfoEUsPerCU: 4, amd.IsaInfoMaxWavesPerEU: 10, amd.IsaInfoMaxFlatWorkGroupSize: 2048, amd.IsaInfoSGPRAllocGranule: 8, amd.IsaInfoTotalNumSGPRs: 512, amd.IsaInfoAddressableNumSGPRs: 104, amd.IsaInfoVGPRAllocGranule: 4, amd.IsaInfoTotalNumVGPRs: 256, amd.IsaInfoAddressableNumVGPRs: 256 }, amd.PrintfInfo: [ '1:1:4:%d\n', '2:1:8:%g\n' ], amd.Kernels:
+
+// GFX800: { amd.MDVersion: [ 2, 1 ], amd.IsaInfo: { amd.IsaInfoWavefrontSize: 64, amd.IsaInfoLocalMemorySize: 65536, amd.IsaInfoEUsPerCU: 4, amd.IsaInfoMaxWavesPerEU: 10, amd.IsaInfoMaxFlatWorkGroupSize: 2048, amd.IsaInfoSGPRAllocGranule: 16, amd.IsaInfoTotalNumSGPRs: 800, amd.IsaInfoAddressableNumSGPRs: 96, amd.IsaInfoVGPRAllocGranule: 4, amd.IsaInfoTotalNumVGPRs: 256, amd.IsaInfoAddressableNumVGPRs: 256 }, amd.PrintfInfo: [ '1:1:4:%d\n', '2:1:8:%g\n' ], amd.Kernels:
+
+// GFX900: { amd.MDVersion: [ 2, 1 ], amd.IsaInfo: { amd.IsaInfoWavefrontSize: 64, amd.IsaInfoLocalMemorySize: 65536, amd.IsaInfoEUsPerCU: 4, amd.IsaInfoMaxWavesPerEU: 10, amd.IsaInfoMaxFlatWorkGroupSize: 2048, amd.IsaInfoSGPRAllocGranule: 16, amd.IsaInfoTotalNumSGPRs: 800, amd.IsaInfoAddressableNumSGPRs: 102, amd.IsaInfoVGPRAllocGranule: 4, amd.IsaInfoTotalNumVGPRs: 256, amd.IsaInfoAddressableNumVGPRs: 256 }, amd.PrintfInfo: [ '1:1:4:%d\n', '2:1:8:%g\n' ], amd.Kernels:
+
+// GCN:      - { amd.KernelName: test_char, amd.Language: OpenCL C, amd.LanguageVersion: [ 2, 0 ], amd.Args:
+// GCN-NEXT:     - { amd.ArgSize: 1, amd.ArgAlign: 1, amd.ArgKind: 0, amd.ArgValueType: 1, amd.ArgTypeName: char, amd.ArgAccQual: 0 }
+// GCN-NEXT:     - { amd.ArgSize: 8, amd.ArgAlign: 8, amd.ArgKind: 7, amd.ArgValueType: 9 }
+// GCN-NEXT:     - { amd.ArgSize: 8, amd.ArgAlign: 8, amd.ArgKind: 8, amd.ArgValueType: 9 }
+// GCN-NEXT:     - { amd.ArgSize: 8, amd.ArgAlign: 8, amd.ArgKind: 9, amd.ArgValueType: 9 }
+// GCN-NEXT:     - { amd.ArgSize: 8, amd.ArgAlign: 8, amd.ArgKind: 11, amd.ArgValueType: 1, amd.ArgAddrQual: 1 } }
+// GCN-NEXT: - { amd.KernelName: test_ushort2, amd.Language: OpenCL C, amd.LanguageVersion: [ 2, 0 ], amd.Args:
+// GCN-NEXT:     - { amd.ArgSize: 4, amd.ArgAlign: 4, amd.ArgKind: 0, amd.ArgValueType: 4, amd.ArgTypeName: ushort2, amd.ArgAccQual: 0 }
+// GCN-NEXT:     - { amd.ArgSize: 8, amd.ArgAlign: 8, amd.ArgKind: 7, amd.ArgValueType: 9 }
+// GCN-NEXT:     - { amd.ArgSize: 8, amd.ArgAlign: 8, amd.ArgKind: 8, amd.ArgValueType: 9 }
+// GCN-NEXT:     - { amd.ArgSize: 8, amd.ArgAlign: 8, amd.ArgKind: 9, amd.ArgValueType: 9 }
+// GCN-NEXT:     - { amd.ArgSize: 8, amd.ArgAlign: 8, amd.ArgKind: 11, amd.ArgValueType: 1, amd.ArgAddrQual: 1 } } }

llvm/trunk/test/MC/AMDGPU/runtime-metadata-invalid-1.s

+; RUN: not llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx700 %s 2>&1 | FileCheck %s
+; RUN: not llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx700 -filetype=obj %s 2>&1 | FileCheck %s
+; RUN: not llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx800 %s 2>&1 | FileCheck %s
+; RUN: not llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx800 -filetype=obj %s 2>&1 | FileCheck %s
+; RUN: not llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx900 %s 2>&1 | FileCheck %s
+; RUN: not llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=obj %s 2>&1 | FileCheck %s
+
+; CHECK: error: unknown key 'amd.RandomUnknownKey'
+
+  .text
+  .hsa_code_object_version 2,1
+  .hsa_code_object_isa 8,0,3,"AMD","AMDGPU"
+  .amdgpu_runtime_metadata
+---
+{ amd.MDVersion: [ 2, 1 ], amd.RandomUnknownKey, amd.IsaInfo: { amd.IsaInfoWavefrontSize: 64, amd.IsaInfoLocalMemorySize: 65536, amd.IsaInfoEUsPerCU: 4, amd.IsaInfoMaxWavesPerEU: 10, amd.IsaInfoMaxFlatWorkGroupSize: 2048, amd.IsaInfoSGPRAllocGranule: 16, amd.IsaInfoTotalNumSGPRs: 800, amd.IsaInfoAddressableNumSGPRs: 102, amd.IsaInfoVGPRAllocGranule: 4, amd.IsaInfoTotalNumVGPRs: 256, amd.IsaInfoAddressableNumVGPRs: 256 }, amd.Kernels:
+  - { amd.KernelName: test, amd.Language: OpenCL C, amd.LanguageVersion: [ 1, 0 ], amd.Args:
+      - { amd.ArgSize: 8, amd.ArgAlign: 8, amd.ArgKind: 1, amd.ArgValueType: 6, amd.ArgTypeName: 'int*', amd.ArgAddrQual: 1, amd.ArgAccQual: 0 }
+      - { amd.ArgSize: 8, amd.ArgAlign: 8, amd.ArgKind: 7, amd.ArgValueType: 9 }
+      - { amd.ArgSize: 8, amd.ArgAlign: 8, amd.ArgKind: 8, amd.ArgValueType: 9 }
+      - { amd.ArgSize: 8, amd.ArgAlign: 8, amd.ArgKind: 9, amd.ArgValueType: 9 } } }
+...
+
+  .end_amdgpu_runtime_metadata
+  .globl  test
+  .p2align  8
+  .type test,@function
+  .amdgpu_hsa_kernel test
+test:                                   ; @test
+  .amd_kernel_code_t
+    amd_code_version_major = 1
+    amd_code_version_minor = 0
+    amd_machine_kind = 1
+    amd_machine_version_major = 8
+    amd_machine_version_minor = 0
+    amd_machine_version_stepping = 3
+    kernel_code_entry_byte_offset = 256
+    kernel_code_prefetch_byte_size = 0
+    max_scratch_backing_memory_byte_size = 0
+    granulated_workitem_vgpr_count = 0
+    granulated_wavefront_sgpr_count = 0
+    priority = 0
+    float_mode = 192
+    priv = 0
+    enable_dx10_clamp = 1
+    debug_mode = 0
+    enable_ieee_mode = 1
+    enable_sgpr_private_segment_wave_byte_offset = 0
+    user_sgpr_count = 6
+    enable_trap_handler = 1
+    enable_sgpr_workgroup_id_x = 1
+    enable_sgpr_workgroup_id_y = 0
+    enable_sgpr_workgroup_id_z = 0
+    enable_sgpr_workgroup_info = 0
+    enable_vgpr_workitem_id = 0
+    enable_exception_msb = 0
+    granulated_lds_size = 0
+    enable_exception = 0
+    enable_sgpr_private_segment_buffer = 1
+    enable_sgpr_dispatch_ptr = 0
+    enable_sgpr_queue_ptr = 0
+    enable_sgpr_kernarg_segment_ptr = 1
+    enable_sgpr_dispatch_id = 0
+    enable_sgpr_flat_scratch_init = 0
+    enable_sgpr_private_segment_size = 0
+    enable_sgpr_grid_workgroup_count_x = 0
+    enable_sgpr_grid_workgroup_count_y = 0
+    enable_sgpr_grid_workgroup_count_z = 0
+    enable_ordered_append_gds = 0
+    private_element_size = 1
+    is_ptr64 = 1
+    is_dynamic_callstack = 0
+    is_debug_enabled = 0
+    is_xnack_enabled = 0
+    workitem_private_segment_byte_size = 0
+    workgroup_group_segment_byte_size = 0
+    gds_segment_byte_size = 0
+    kernarg_segment_byte_size = 8
+    workgroup_fbarrier_count = 0
+    wavefront_sgpr_count = 6
+    workitem_vgpr_count = 3
+    reserved_vgpr_first = 0
+    reserved_vgpr_count = 0
+    reserved_sgpr_first = 0
+    reserved_sgpr_count = 0
+    debug_wavefront_private_segment_offset_sgpr = 0
+    debug_private_segment_buffer_sgpr = 0
+    kernarg_segment_alignment = 4
+    group_segment_alignment = 4
+    private_segment_alignment = 4
+    wavefront_size = 6
+    call_convention = -1
+    runtime_loader_kernel_symbol = 0
+  .end_amd_kernel_code_t
+; BB#0:                                 ; %entry
+  s_load_dwordx2 s[0:1], s[4:5], 0x0
+  v_mov_b32_e32 v2, 0x309
+  s_waitcnt lgkmcnt(0)
+  v_mov_b32_e32 v0, s0
+  v_mov_b32_e32 v1, s1
+  flat_store_dword v[0:1], v2
+  s_endpgm
+.Lfunc_end0:
+  .size test, .Lfunc_end0-test
+
+  .ident  ""
+  .section  ".note.GNU-stack"