This is an archive of the discontinued LLVM Phabricator instance.

Differential D29397

[DAGCombiner] Support bswap as a part of load combine patterns
ClosedPublic

Authored by apilipenko on Feb 1 2017, 7:58 AM.

Details

Reviewers
RKSimon
filcab
reames
javed.absar
hfinkel
Commits
rGd3464bf9adc2: [DAGCombiner] Support bswap as a part of load combine patterns
rL294201: [DAGCombiner] Support bswap as a part of load combine patterns

Diff Detail

Repository
rL LLVM

Event Timeline

apilipenko created this revision.Feb 1 2017, 7:58 AM
Herald added a reviewer: javed.absar. · View Herald TranscriptFeb 1 2017, 7:58 AM
rengolin added a subscriber: rengolin.Feb 1 2017, 8:30 AM
rengolin added inline comments.
test/CodeGen/ARM/load-combine-big-endian.ll
428 ↗(On Diff #86640)

I'm surprised this doesn't use REV16.

test/CodeGen/ARM/load-combine.ll
386 ↗(On Diff #86640)

Or here.

filcab added inline comments.Feb 1 2017, 9:06 AM
test/CodeGen/ARM/load-combine-big-endian.ll
428 ↗(On Diff #86640)

REV16 has Requires<[IsARM, HasV6]>,, but from the run lines, it seems that the default for "arm" is probably before v6 (I tried looking for the default, but couldn't find it).
Could that be it?

rengolin added inline comments.Feb 1 2017, 9:18 AM
test/CodeGen/ARM/load-combine-big-endian.ll
428 ↗(On Diff #86640)

Ah, good catch! REV16 is available on ARMv6+, Thumb1, 2 and ARM (and our table gen descriptions have that already), but the check lines below are only for "arm" which is "ARMv4".

This test is ok (has the CHECK-ARMv6) but the LE below has "CHECK64" which is why I got confused. :)

test/CodeGen/ARM/load-combine.ll
395 ↗(On Diff #86640)

So we just need to fix the typo here: CHECK64 -> CHECK-ARMv6

apilipenko updated this revision to Diff 87224.Feb 6 2017, 7:06 AM

Fix the type CHECK64 -> CHECK-ARMv6 in ARM load-combine.ll test case.

RKSimon edited edge metadata.Feb 6 2017, 7:26 AM

Minor nit

lib/CodeGen/SelectionDAG/DAGCombiner.cpp
4474 ↗(On Diff #87224)

Drop the braces (style)

apilipenko updated this revision to Diff 87231.Feb 6 2017, 7:49 AM
RKSimon accepted this revision.Feb 6 2017, 8:33 AM

LGTM

This revision is now accepted and ready to land.Feb 6 2017, 8:33 AM
Closed by commit rL294201: [DAGCombiner] Support bswap as a part of load combine patterns (authored by apilipenko). · Explain WhyFeb 6 2017, 9:59 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
CodeGen/
SelectionDAG/
3 lines
test/
CodeGen/
AArch64/
22 lines
23 lines
ARM/
34 lines
34 lines
X86/
32 lines

Diff 87249

llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 4,457 Lines • ▼ Show 20 Lines case ISD::ZERO_EXTEND: {
if (NarrowBitWidth % 8 != 0) if (NarrowBitWidth % 8 != 0)
return None; return None;
uint64_t NarrowByteWidth = NarrowBitWidth / 8; uint64_t NarrowByteWidth = NarrowBitWidth / 8;
return Index >= NarrowByteWidth return Index >= NarrowByteWidth
? ByteProvider::getConstantZero() ? ByteProvider::getConstantZero()
: calculateByteProvider(NarrowOp, Index, Depth + 1); : calculateByteProvider(NarrowOp, Index, Depth + 1);
} }
case ISD::BSWAP:
return calculateByteProvider(Op->getOperand(0), ByteWidth - Index - 1,
Depth + 1);
case ISD::LOAD: { case ISD::LOAD: {
auto L = cast<LoadSDNode>(Op.getNode()); auto L = cast<LoadSDNode>(Op.getNode());
// TODO: support ext loads // TODO: support ext loads
if (L->isVolatile() || L->isIndexed() || if (L->isVolatile() || L->isIndexed() ||
L->getExtensionType() != ISD::NON_EXTLOAD) L->getExtensionType() != ISD::NON_EXTLOAD)
return None; return None;
▲ Show 20 Lines • Show All 11,407 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/AArch64/load-combine-big-endian.ll

Show First 20 Lines • Show All 325 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%tmp13 = or i32 %tmp8, %tmp12 %tmp13 = or i32 %tmp8, %tmp12
%tmp14 = getelementptr inbounds i8, i8* %tmp, i32 -4 %tmp14 = getelementptr inbounds i8, i8* %tmp, i32 -4
%tmp15 = load i8, i8* %tmp14, align 4 %tmp15 = load i8, i8* %tmp14, align 4
%tmp16 = zext i8 %tmp15 to i32 %tmp16 = zext i8 %tmp15 to i32
%tmp17 = shl nuw nsw i32 %tmp16, 24 %tmp17 = shl nuw nsw i32 %tmp16, 24
%tmp18 = or i32 %tmp13, %tmp17 %tmp18 = or i32 %tmp13, %tmp17
ret i32 %tmp18 ret i32 %tmp18
} }
declare i16 @llvm.bswap.i16(i16)
; i16* p; // p is 4 byte aligned
; (i32) bswap(p[0]) | (i32) bswap(p[1] << 16)
define i32 @load_i32_by_bswap_i16(i32* %arg) {
; CHECK-LABEL: load_i32_by_bswap_i16:
; CHECK: ldr w8, [x0]
; CHECK-NEXT: rev w0, w8
; CHECK-NEXT: ret
%tmp = bitcast i32* %arg to i16*
%tmp1 = load i16, i16* %tmp, align 4
%tmp11 = call i16 @llvm.bswap.i16(i16 %tmp1)
%tmp2 = zext i16 %tmp11 to i32
%tmp3 = getelementptr inbounds i16, i16* %tmp, i32 1
%tmp4 = load i16, i16* %tmp3, align 1
%tmp41 = call i16 @llvm.bswap.i16(i16 %tmp4)
%tmp5 = zext i16 %tmp41 to i32
%tmp6 = shl nuw nsw i32 %tmp5, 16
%tmp7 = or i32 %tmp6, %tmp2
ret i32 %tmp7
}

llvm/trunk/test/CodeGen/AArch64/load-combine.ll

Show First 20 Lines • Show All 312 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%tmp13 = or i32 %tmp8, %tmp12 %tmp13 = or i32 %tmp8, %tmp12
%tmp14 = getelementptr inbounds i8, i8* %tmp, i32 -4 %tmp14 = getelementptr inbounds i8, i8* %tmp, i32 -4
%tmp15 = load i8, i8* %tmp14, align 4 %tmp15 = load i8, i8* %tmp14, align 4
%tmp16 = zext i8 %tmp15 to i32 %tmp16 = zext i8 %tmp15 to i32
%tmp17 = shl nuw nsw i32 %tmp16, 24 %tmp17 = shl nuw nsw i32 %tmp16, 24
%tmp18 = or i32 %tmp13, %tmp17 %tmp18 = or i32 %tmp13, %tmp17
ret i32 %tmp18 ret i32 %tmp18
} }
declare i16 @llvm.bswap.i16(i16)
; i16* p; // p is 4 byte aligned
; (i32) bswap(p[1]) | (i32) bswap(p[0] << 16)
define i32 @load_i32_by_bswap_i16(i32* %arg) {
; CHECK-LABEL: load_i32_by_bswap_i16:
; CHECK: ldr w8, [x0]
; CHECK-NEXT: rev w0, w8
; CHECK-NEXT: ret
%tmp = bitcast i32* %arg to i16*
%tmp1 = load i16, i16* %tmp, align 4
%tmp11 = call i16 @llvm.bswap.i16(i16 %tmp1)
%tmp2 = zext i16 %tmp11 to i32
%tmp3 = getelementptr inbounds i16, i16* %tmp, i32 1
%tmp4 = load i16, i16* %tmp3, align 1
%tmp41 = call i16 @llvm.bswap.i16(i16 %tmp4)
%tmp5 = zext i16 %tmp41 to i32
%tmp6 = shl nuw nsw i32 %tmp2, 16
%tmp7 = or i32 %tmp6, %tmp5
ret i32 %tmp7
}

llvm/trunk/test/CodeGen/ARM/load-combine-big-endian.ll

Show First 20 Lines • Show All 443 Lines • ▼ Show 20 Lines; CHECK-ARMv6-NEXT: bx lr
%tmp13 = or i32 %tmp8, %tmp12 %tmp13 = or i32 %tmp8, %tmp12
%tmp14 = getelementptr inbounds i8, i8* %tmp, i32 -4 %tmp14 = getelementptr inbounds i8, i8* %tmp, i32 -4
%tmp15 = load i8, i8* %tmp14, align 4 %tmp15 = load i8, i8* %tmp14, align 4
%tmp16 = zext i8 %tmp15 to i32 %tmp16 = zext i8 %tmp15 to i32
%tmp17 = shl nuw nsw i32 %tmp16, 24 %tmp17 = shl nuw nsw i32 %tmp16, 24
%tmp18 = or i32 %tmp13, %tmp17 %tmp18 = or i32 %tmp13, %tmp17
ret i32 %tmp18 ret i32 %tmp18
} }
declare i16 @llvm.bswap.i16(i16)
; i16* p; // p is 4 byte aligned
; (i32) bswap(p[0]) | (i32) bswap(p[1] << 16)
define i32 @load_i32_by_bswap_i16(i32* %arg) {
; CHECK-LABEL: load_i32_by_bswap_i16:
; CHECK: ldr r0, [r0]
; CHECK-NEXT: mov r1, #65280
; CHECK-NEXT: mov r2, #16711680
; CHECK-NEXT: and r1, r1, r0, lsr #8
; CHECK-NEXT: and r2, r2, r0, lsl #8
; CHECK-NEXT: orr r1, r1, r0, lsr #24
; CHECK-NEXT: orr r0, r2, r0, lsl #24
; CHECK-NEXT: orr r0, r0, r1
; CHECK-NEXT: mov pc, lr
; CHECK-ARMv6-LABEL: load_i32_by_bswap_i16:
; CHECK-ARMv6: ldr r0, [r0]
; CHECK-ARMv6-NEXT: rev r0, r0
; CHECK-ARMv6-NEXT: bx lr
%tmp = bitcast i32* %arg to i16*
%tmp1 = load i16, i16* %tmp, align 4
%tmp11 = call i16 @llvm.bswap.i16(i16 %tmp1)
%tmp2 = zext i16 %tmp11 to i32
%tmp3 = getelementptr inbounds i16, i16* %tmp, i32 1
%tmp4 = load i16, i16* %tmp3, align 1
%tmp41 = call i16 @llvm.bswap.i16(i16 %tmp4)
%tmp5 = zext i16 %tmp41 to i32
%tmp6 = shl nuw nsw i32 %tmp5, 16
%tmp7 = or i32 %tmp6, %tmp2
ret i32 %tmp7
}

llvm/trunk/test/CodeGen/ARM/load-combine.ll

Show First 20 Lines • Show All 401 Lines • ▼ Show 20 Lines; CHECK-ARMv6-NEXT: bx lr
%tmp13 = or i32 %tmp8, %tmp12 %tmp13 = or i32 %tmp8, %tmp12
%tmp14 = getelementptr inbounds i8, i8* %tmp, i32 -4 %tmp14 = getelementptr inbounds i8, i8* %tmp, i32 -4
%tmp15 = load i8, i8* %tmp14, align 4 %tmp15 = load i8, i8* %tmp14, align 4
%tmp16 = zext i8 %tmp15 to i32 %tmp16 = zext i8 %tmp15 to i32
%tmp17 = shl nuw nsw i32 %tmp16, 24 %tmp17 = shl nuw nsw i32 %tmp16, 24
%tmp18 = or i32 %tmp13, %tmp17 %tmp18 = or i32 %tmp13, %tmp17
ret i32 %tmp18 ret i32 %tmp18
} }
declare i16 @llvm.bswap.i16(i16)
; i16* p; // p is 4 byte aligned
; (i32) bswap(p[1]) | (i32) bswap(p[0] << 16)
define i32 @load_i32_by_bswap_i16(i32* %arg) {
; CHECK-LABEL: load_i32_by_bswap_i16:
; CHECK: ldr r0, [r0]
; CHECK-NEXT: mov r1, #65280
; CHECK-NEXT: mov r2, #16711680
; CHECK-NEXT: and r1, r1, r0, lsr #8
; CHECK-NEXT: and r2, r2, r0, lsl #8
; CHECK-NEXT: orr r1, r1, r0, lsr #24
; CHECK-NEXT: orr r0, r2, r0, lsl #24
; CHECK-NEXT: orr r0, r0, r1
; CHECK-NEXT: mov pc, lr
; CHECK-ARMv6-LABEL: load_i32_by_bswap_i16:
; CHECK-ARMv6: ldr r0, [r0]
; CHECK-ARMv6-NEXT: rev r0, r0
; CHECK-ARMv6-NEXT: bx lr
%tmp = bitcast i32* %arg to i16*
%tmp1 = load i16, i16* %tmp, align 4
%tmp11 = call i16 @llvm.bswap.i16(i16 %tmp1)
%tmp2 = zext i16 %tmp11 to i32
%tmp3 = getelementptr inbounds i16, i16* %tmp, i32 1
%tmp4 = load i16, i16* %tmp3, align 1
%tmp41 = call i16 @llvm.bswap.i16(i16 %tmp4)
%tmp5 = zext i16 %tmp41 to i32
%tmp6 = shl nuw nsw i32 %tmp2, 16
%tmp7 = or i32 %tmp6, %tmp5
ret i32 %tmp7
}

llvm/trunk/test/CodeGen/X86/load-combine.ll

Show First 20 Lines • Show All 863 Lines • ▼ Show 20 Linesentry:
%conv57 = zext i8 %load2 to i32 %conv57 = zext i8 %load2 to i32
%shl58 = shl i32 %conv57, 32 %shl58 = shl i32 %conv57, 32
%or59 = or i32 %or55, %shl58 %or59 = or i32 %or55, %shl58
%or74 = or i32 %or59, 0 %or74 = or i32 %or59, 0
%conv75 = sext i32 %or74 to i64 %conv75 = sext i32 %or74 to i64
store i64 %conv75, i64* %dst, align 8 store i64 %conv75, i64* %dst, align 8
ret void ret void
} }
declare i16 @llvm.bswap.i16(i16)
; i16* p;
; (i32) bswap(p[1]) | (i32) bswap(p[0] << 16)
define i32 @load_i32_by_bswap_i16(i32* %arg) {
; CHECK-LABEL: load_i32_by_bswap_i16:
; CHECK: # BB#0:
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl (%eax), %eax
; CHECK-NEXT: bswapl %eax
; CHECK-NEXT: retl
;
; CHECK64-LABEL: load_i32_by_bswap_i16:
; CHECK64: # BB#0:
; CHECK64-NEXT: movl (%rdi), %eax
; CHECK64-NEXT: bswapl %eax
; CHECK64-NEXT: retq
%tmp = bitcast i32* %arg to i16*
%tmp1 = load i16, i16* %tmp, align 4
%tmp11 = call i16 @llvm.bswap.i16(i16 %tmp1)
%tmp2 = zext i16 %tmp11 to i32
%tmp3 = getelementptr inbounds i16, i16* %tmp, i32 1
%tmp4 = load i16, i16* %tmp3, align 1
%tmp41 = call i16 @llvm.bswap.i16(i16 %tmp4)
%tmp5 = zext i16 %tmp41 to i32
%tmp6 = shl nuw nsw i32 %tmp2, 16
%tmp7 = or i32 %tmp6, %tmp5
ret i32 %tmp7
}