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[PPC] Use rldicr instruction for AND with an immediate if possible
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Authored by inouehrs on Feb 1 2017, 3:50 AM.

Details

Summary
  • generate rldicr (clrrdi) for AND with an immediate like 0xFFFFFFFFFFFF0000 (i.e. a bit sequence of ones from most significant side and all zero for reminder) on PowerPC platform; currently LLVM generates two or three instructions
  • update two unit tests affected by this change

Diff Detail

Event Timeline

inouehrs created this revision.Feb 1 2017, 3:50 AM
inouehrs updated this revision to Diff 86629.Feb 1 2017, 6:50 AM

I upload the patch with full context. Thank you for the advice.

nemanjai added inline comments.Feb 14 2017, 3:58 PM
test/CodeGen/PowerPC/i64_fp_round.ll
23

Why did this change? Is it because there are more/fewer instructions emitted for this test case that are not tested for? If this is the case, I think it makes more sense to use FileCheck variables for these registers rather than hard-coding them.

inouehrs updated this revision to Diff 88487.Feb 14 2017, 9:58 PM
inouehrs added a reviewer: hfinkel.

Thank you for the comment.
I updated i64_fp_round.ll not to use the hard-coded register number.

inouehrs marked an inline comment as done.Feb 14 2017, 10:00 PM

This patch reduces one instruction in i64_fp_round.ll and affects the register assignment.

	li 4, -2048
	and 4, 5, 4

into

	rldicr 5, 5, 0, 52
nemanjai accepted this revision.Feb 23 2017, 3:37 AM

Please add a test that intentionally triggers this transformation (i.e. the test case that motivated the patch). It doesn't necessarily have to be in a separate test case - you can just add a function to an existing test case that does this. I don't think this requires another review - you can address these on the commit.

lib/Target/PowerPC/PPCISelDAGToDAG.cpp
2717

Nit: please always make comments full sentences.

This revision is now accepted and ready to land.Feb 23 2017, 3:37 AM
inouehrs updated this revision to Diff 89614.Feb 24 2017, 12:39 AM
inouehrs edited the summary of this revision. (Show Details)
  • I updated the comment
  • I added an explicit test case in test/CodeGen/PowerPC/srl-mask.ll
This revision was automatically updated to reflect the committed changes.