[PPC] Use rldicr instruction for AND with an immediate if possible

[inouehrs]

Summary

• generate rldicr (clrrdi) for AND with an immediate like 0xFFFFFFFFFFFF0000 (i.e. a bit sequence of ones from most significant side and all zero for reminder) on PowerPC platform; currently LLVM generates two or three instructions
• update two unit tests affected by this change

[hfinkel]

Please upload the patch with full context (see http://llvm.org/docs/Phabricator.html#requesting-a-review-via-the-web-interface).

[inouehrs]

I upload the patch with full context. Thank you for the advice.

[nemanjai]

test/CodeGen/PowerPC/i64_fp_round.ll

23

Why did this change? Is it because there are more/fewer instructions emitted for this test case that are not tested for? If this is the case, I think it makes more sense to use FileCheck variables for these registers rather than hard-coding them.

[inouehrs]

Thank you for the comment.
I updated i64_fp_round.ll not to use the hard-coded register number.

[inouehrs]

This patch reduces one instruction in i64_fp_round.ll and affects the register assignment.

	li 4, -2048
	and 4, 5, 4

into

	rldicr 5, 5, 0, 52

[inouehrs]

gentle ping

[nemanjai]

Please add a test that intentionally triggers this transformation (i.e. the test case that motivated the patch). It doesn't necessarily have to be in a separate test case - you can just add a function to an existing test case that does this. I don't think this requires another review - you can address these on the commit.

lib/Target/PowerPC/PPCISelDAGToDAG.cpp

2717

Nit: please always make comments full sentences.

[inouehrs]

• I updated the comment
• I added an explicit test case in test/CodeGen/PowerPC/srl-mask.ll

lib/Target/PowerPC/PPCISelDAGToDAG.cpp

       CurDAG->SelectNodeTo(N, PPC::RLDICL, MVT::i64, Ops);
       return;
     }
+    // If this is a negated 64-bit zero-extension mask, emit clrrdi (rldicr)
+    if (isInt64Immediate(N->getOperand(1).getNode(), Imm64) &&
+        isMask_64(~Imm64)) {
+      // to opt: fold a shift as above
+      SDValue Val = N->getOperand(0);
+      MB = 63 - countTrailingOnes(~Imm64);
+      SH = 0;
+      SDValue Ops[] = { Val, getI32Imm(SH, dl), getI32Imm(MB, dl) };
+      CurDAG->SelectNodeTo(N, PPC::RLDICR, MVT::i64, Ops);
+      return;
+    }
+
     // AND X, 0 -> 0, not "rlwinm 32".
     if (isInt32Immediate(N->getOperand(1), Imm) && (Imm == 0)) {
       ReplaceUses(SDValue(N, 0), N->getOperand(1));

test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll

 ; PPC64-DAG: stxsdx 1, 0, [[ADDR_LO:[0-9]+]]
 ; PPC64-DAG: addi [[ADDR_HI]], [[SP:[0-9]+]], [[OFFSET_HI:-?[0-9]+]]
 ; PPC64-DAG: addi [[ADDR_LO]], [[SP]], [[OFFSET_LO:-?[0-9]+]]
-; PPC64-DAG: li [[MASK_REG:[0-9]+]], 1
-; PPC64: sldi [[MASK_REG]], [[MASK_REG]], 63
 ; PPC64-DAG: ld [[HI:[0-9]+]], [[OFFSET_LO]]([[SP]])
 ; PPC64-DAG: ld [[LO:[0-9]+]], [[OFFSET_HI]]([[SP]])
-; PPC64: and [[FLIP_BIT:[0-9]+]], [[HI]], [[MASK_REG]]
+; PPC64-DAG: rldicr [[FLIP_BIT:[0-9]+]], [[HI]], 0, 0
 ; PPC64-DAG: xor 3, [[HI]], [[FLIP_BIT]]
 ; PPC64-DAG: xor 4, [[LO]], [[FLIP_BIT]]
 ; PPC64: blr

 ; PPC64-P8-LABEL: test_abs:
 ; PPC64-P8-DAG: mfvsrd [[LO:[0-9]+]], 2
 ; PPC64-P8-DAG: mfvsrd [[HI:[0-9]+]], 1
-; PPC64-P8-DAG: li [[MASK_REG:[0-9]+]], 1
-; PPC64-P8-DAG: sldi [[SHIFT_REG:[0-9]+]], [[MASK_REG]], 63
-; PPC64-P8: and [[FLIP_BIT:[0-9]+]], [[HI]], [[SHIFT_REG]]
+; PPC64-P8-DAG: rldicr [[FLIP_BIT:[0-9]+]], [[HI]], 0, 0
 ; PPC64-P8-DAG: xor 3, [[HI]], [[FLIP_BIT]]
 ; PPC64-P8-DAG: xor 4, [[LO]], [[FLIP_BIT]]
 ; PPC64-P8: blr

 ; PPC64-P8-DAG: mfvsrd [[LO:[0-9]+]], 2
 ; PPC64-P8-DAG: mfvsrd [[HI:[0-9]+]], 1
 ; PPC64-P8-DAG: li [[IMM1:[0-9]+]], 1
-; PPC64-P8-DAG: sldi [[FLIP_BIT]], [[IMM1]], 63
+; PPC64-P8-DAG: sldi [[FLIP_BIT:[0-9]+]], [[IMM1]], 63
 ; PPC64-P8-NOT: BARRIER
 ; PPC64-P8-DAG: xor 3, [[HI]], [[FLIP_BIT]]
 ; PPC64-P8-DAG: xor 4, [[LO]], [[FLIP_BIT]]

 ; PPC64-LABEL: test_copysign:
 ; PPC64-DAG: stxsdx 1, 0, [[ADDR_REG:[0-9]+]]
 ; PPC64-DAG: addi [[ADDR_REG]], 1, [[OFFSET:-?[0-9]+]]
-; PPC64-DAG: li [[SIGN:[0-9]+]], 1
-; PPC64-DAG: sldi [[SIGN]], [[SIGN]], 63
 ; PPC64-DAG: li [[HI_TMP:[0-9]+]], 16399
 ; PPC64-DAG: sldi [[CST_HI:[0-9]+]], [[HI_TMP]], 48
 ; PPC64-DAG: li [[LO_TMP:[0-9]+]], 3019
 ; PPC64-DAG: sldi [[CST_LO:[0-9]+]], [[LO_TMP]], 52
 ; PPC64-NOT: BARRIER
 ; PPC64-DAG: ld [[X_HI:[0-9]+]], [[OFFSET]](1)
-; PPC64-DAG: and [[NEW_HI_TMP:[0-9]+]], [[X_HI]], [[SIGN]]
+; PPC64-DAG: rldicr [[NEW_HI_TMP:[0-9]+]], [[X_HI]], 0, 0
 ; PPC64-DAG: or 3, [[NEW_HI_TMP]], [[CST_HI]]
-; PPC64-DAG: xor 4, [[SIGN]], [[CST_LO]]
+; PPC64-DAG: xor 4, [[NEW_HI_TMP]], [[CST_LO]]
 ; PPC64: blr
 
 ; PPC64-P8-LABEL: test_copysign:
 ; PPC64-P8-DAG: mfvsrd [[X_HI:[0-9]+]], 1
-; PPC64-P8-DAG: li [[SIGN:[0-9]+]], 1
-; PPC64-P8-DAG: sldi [[SIGN]], [[SIGN]], 63
 ; PPC64-P8-DAG: li [[HI_TMP:[0-9]+]], 16399
 ; PPC64-P8-DAG: sldi [[CST_HI:[0-9]+]], [[HI_TMP]], 48
 ; PPC64-P8-DAG: li [[LO_TMP:[0-9]+]], 3019
 ; PPC64-P8-DAG: sldi [[CST_LO:[0-9]+]], [[LO_TMP]], 52
 ; PPC64-P8-NOT: BARRIER
-; PPC64-P8-DAG: and [[NEW_HI_TMP:[0-9]+]], [[X_HI]], [[SIGN]]
+; PPC64-P8-DAG: rldicr [[NEW_HI_TMP:[0-9]+]], [[X_HI]], 0, 0
 ; PPC64-P8-DAG: or 3, [[NEW_HI_TMP]], [[CST_HI]]
 ; PPC64-P8-DAG: xor 4, [[NEW_HI_TMP]], [[CST_LO]]
 ; PPC64-P8: blr

test/CodeGen/PowerPC/i64_fp_round.ll

 ; CHECK: cmpldi [[REG2]], 1
 ; CHECK: isel [[REG3:[0-9]+]], {{[0-9]+}}, 3, 1
 ; CHECK-NO-ISEL: bc 12, 1, [[TRUE:.LBB[0-9]+]]
-; CHECK-NO-ISEL: ori 11, 3, 0
+; CHECK-NO-ISEL: ori 12, 3, 0
 ; CHECK-NO-ISEL-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
 ; CHECK-NO-ISEL-NEXT: [[TRUE]]
-; CHECK-NO-ISEL-NEXT: addi 11, 4, 0
+; CHECK-NO-ISEL-NEXT: addi 12, 5, 0
 ; CHECK: std [[REG3]], -{{[0-9]+}}(1)