[AArch64] Extend redundant copy elimination pass to handle non-zero stores.

[mcrosier]

Summary

This patch extends the current functionality of the AArch64 redundant copy elimination pass to handle non-zero cases such as:

BB#0:
  cmp x0, #1
  b.eq .LBB0_1
.LBB0_1:
  orr x0, xzr, #0x1  ; <-- redundant copy; x0 known to hold #1.

This removes redundant copies from most of the SPEC200X tests. When running on Kryo, I saw a 2.7% and 1% improvement in spec2000/gap and spec2006/povray, respectively. All other testing was within noise.

Chad

[junbuml]

lib/Target/AArch64/AArch64RedundantCopyElimination.cpp

121

Is it always safe to do this directly without any check for isConditionalBranch(), Opcode, or MI.getOperand(0).isImm()?

137

If we didn't see any instruction that sets NZCV between MI and PredMBB->begin() and NZCV is live-in from PredMBB's single predecessor, then we could continue scan the single predecessor of PredMBB. Maybe different patch if it make sense.

160

At this point we know that I->getOperand(0) is zero register, so this if statement will be taken only when I->getOperand(1) is zero register. I don't see any problem when both getOperand(0) and getOperand(1) are zero register.

216–217

Please update the comment as we continue checking non-zero case.

229

Is there any case where both ZeroRegVal and KnownRegVal is true? If not, adding assert() will be good.

262–263

We could move check for ZeroRegVal above if statement in line 259.

281

The comment in MachineInstr.h mention that isMoveImmediate() return true for a move immediate (including conditional moves). I think the conditional move is not the case for AArch64, but just want to double confirm.

281

We can move KnownRegVal in line 283. It seems that both ZeroRegVal and KnownRegVal cannot be true at the same time. Then we can use if-else, instead of if-if.

[mcrosier]

lib/Target/AArch64/AArch64RedundantCopyElimination.cpp

121

Yes, I believe so. We directly check that the opcode is Bcc above, so we know MI must be a conditional branch at this point. AFAIK, the 0 operand is always the CC for a Bcc.

137

True, but I'd prefer to defer this for another day as you suggest.

160

You're correct. I'll remove accordingly.

216–217

Will do.

229

No. I'll add an assertion.

281

For AArch64, only the MOVi32imm and MOVi64imm pseudos will return true for isMoveImmediate() and these instructions are unconditionally executed.

[mcrosier]

Address Jun's comments.

[mcrosier]

lib/Target/AArch64/AArch64RedundantCopyElimination.cpp

281

I hoisted the ZeroRegVal and KnownRegVal to the outer checks, but left the code as an if-if, rather thank if-else to reduce indention. Let me know if you strongly prefer the the if-else and I'll happily

[mcrosier]

Include test case that was accidentally dropped from previous diff.

[MatzeB]

This looks good to me when the comments below are addressed.

lib/Target/AArch64/AArch64RedundantCopyElimination.cpp

84–86

Looks like you synced that with https://reviews.llvm.org/D30113, good.

105–108

Use doxygen /// comment. It would help to talk about block \p MBB instead of current block, similarily to explain some of the other parameters.

120

Is that cast to (int) here necessary?

129–130

Add a comment that this is a shortcut for a block that is empty except for the branch.

136

This slightly confused me as most loops in LLVM first initialize/declare the iteration variable then the end variable.

This could also be written as a range based for: for (MachineInstr &PredMI : make_range(std::next(MI.getReverseIterator()), PredMBB->rend()).

146–148

does the DestReg matter here? I would assume this transformation to work as well when we write to an actual register...

155

Somewhat off-topic from this specific patch and I don't expect this to be fixed here: It feels bad to scatter all those magic values like the 3 here around the targets, this function is another example where we have a lot of magic input numbers. At some point we should add some getter/accessor functions somewhere to give them a name or extend tablegen to generate some enum constants for us...

170

typo but->that

182–183

You can use DEBUG(dbgs() << "Remove redundant copy: " << *MI);

218

Can't you just have a single variable KnownVal or similar here? You can then use KnownVal == 0 instead of ZeroRegVal.

271–280

Do we really need to split this into Case 1/Case 2? There seems to be more equal code than different one so I would expect this to be better merged (with a slightly more complicated condition to check).

328

You may even delay the resizing/allocation of the bitvector to the point where it is actually used (resizing it multiple times to the same size shouldn't hurt performance).

test/CodeGen/AArch64/machine-copy-remove.mir

1

The 2>&1 is no longer necessary for .mir tests and is discouraged now as it hides abort()/assert() messages if they happen.

5–8

The IR block can be left out completely in this case the MIRParser will create the dummy functions.

14

This can be slightly simplified by leaving out the block frequencies (i.e. just successors: %bb.1, %bb.2 Similar for the other blocks.

38

Typo!
I also tend to use CHECK-LABEL: name: test1 to better match the mir output with the typo this probably matched the dummy IR function instead of the beginning of the actual test1 mir function.

[mcrosier]

lib/Target/AArch64/AArch64RedundantCopyElimination.cpp

120

It is not. Will remove.

146–148

No, this is a simplification not a requirement. I'll remove this check. I think the only necessary check is to make sure the compare doesn't clobber itself (e.g., SUBS x1, x1, 5).

155

I agree.

[mcrosier]

Address Matthias' comments as well as rebase/rework patch after r295863.

[junbuml]

LGTM

lib/Target/AArch64/AArch64RedundantCopyElimination.cpp

86

This return the compare instruction the branch is predicated upon.

211

Please remove it.

212–223

Isn't it possible to merge the "if" and "else if" block as these two block do almost the same thing ? Maybe move guaranteesZeroRegInBlock() in knownRegValInBlock() ?

[junbuml]

lib/Target/AArch64/AArch64RedundantCopyElimination.cpp

86

Please ignore this.

[mcrosier]

Address Jun's feedback. Thanks, Jun.

[gberry]

A few minor comments below. Two questions:

• can we avoid doing two backward scans of the pred block? perhaps just tracking the clobbers once
• can you add some negative tests that check that clobbers inhibit this optimization when expected?

lib/Target/AArch64/AArch64RedundantCopyElimination.cpp

56

This typedef seems unnecessary. Why not just struct RegImm?

58

This could be int32_t to save some space since SUBS can only reference 12-bit immediates (24 with lsl 12 which isn't currently handled by this change), but it probably isn't worth it since there aren't many RegImm objects.

85

Typo 'whos' -> 'whose'

152

Typo 'include' -> 'includes'

216

Perhaps invert the condition above and put the continue inside it to get rid of the 'else' here

[mcrosier]

-Address Geoff's inline comments.
-Add a few negative tests.
-Use a single ClobberReg bit vector to track clobbered registers.

While I think it's possible to only scan the predecessor instructions once, I believe it would add a fair amount of complexity. More importantly we would need to maintain a list of copies every time we scan the predecessors (even in those cases when we can't optimize the move immediate/copy, which is the common case). Regardless, I'm happy to discuss this offline and update everyone with the result of that discussion.

[gberry]

I'm convinced the two passes over PredBB makes sense.

Could you add a couple of test cases where the known register and the eliminated MOV are different register sizes? I feel like we may get into trouble in the case where we're depending on the MOVi32imm zeroing out the high 32-bits of a 64-bit value. For example:
b1:

CMP w0, 1
BCC EQ, b2

b2:

w0 = MOVi32imm 1
STORE x0 # depends on high 32-bits of w0 being zero'd by MOVi32imm

A few more questions/suggestions below.

lib/Target/AArch64/AArch64RedundantCopyElimination.cpp

62

Perhaps this could return an Optional<RegImm>, then you could get rid of the two out ref parameters?

155

I think you could get rid of lines 172 and 173 if you do the trackRegDefs before the ClobberedRegs check.

205–208

I believe this is no longer needed here.

303–304

I don't think FirstUse is being calculated correctly in the case of the non-zero immediate. E.g. if there are no COPYs to worry about, FirstUse should be the SUBS compare instruction since we want to remove the kill of the known value register in that case if it is present. Your test case test10 should show this problem, though I'm not sure why -verfiy-machineinstrs isn't catching it.

[mcrosier]

Address Geoff's latest comments.

[mcrosier]

I added the test cases you suggested (and cleaned up the others). In particular, I added the test (i.e., test 13) that has a 32 bit comparison and a move immediate that implicitly defines the upper bits. We can definitely get into trouble here. I added the necessary checks to make sure we don't remove the mov immediate in this case because that would leave the upper bits in some unknown state.

lib/Target/AArch64/AArch64RedundantCopyElimination.cpp

303–304

You are correct. I've updated the logic and test cases to make sure the kill flags are removed.

[junbuml]

lib/Target/AArch64/AArch64RedundantCopyElimination.cpp

267–268

If this is needed, it will be good to add comment why this is needed only for mov, not in Copy.

[gberry]

LGTM with a few nits

lib/Target/AArch64/AArch64RedundantCopyElimination.cpp

211

Typo 'inbetween' -> 'in between'

test/CodeGen/AArch64/machine-copy-remove.mir

408

Typo 'eliminated' -> 'eliminate'. And another before test15.

lib/Target/AArch64/AArch64RedundantCopyElimination.cpp

 //=- AArch64RedundantCopyElimination.cpp - Remove useless copy for AArch64 -=//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 // This pass removes unnecessary zero copies in BBs that are targets of
 // cbz/cbnz instructions. For instance, the copy instruction in the code below
 // can be removed because the CBZW jumps to BB#2 when W0 is zero.
 //  BB#1:
 //    CBZW %W0, <BB#2>
 //  BB#2:
 //    %W0 = COPY %WZR
-// This pass should be run after register allocation.
 //
-// FIXME: This should be extended to handle any constant other than zero. E.g.,
-//   cmp w0, #1
-//     b.eq .BB1
-//   BB1:
-//     mov w0, #1
+// Similarly, this pass also handles non-zero copies.
+//  BB#0:
+//    cmp x0, #1
+//    b.eq .LBB0_1
+//  .LBB0_1:
+//    orr x0, xzr, #0x1
+//
+// This pass should be run after register allocation.
 //
 // FIXME: This could also be extended to check the whole dominance subtree below
 // the comparison if the compile time regression is acceptable.
 //
 //===----------------------------------------------------------------------===//
 
 #include "AArch64.h"
 #include "llvm/ADT/SetVector.h"
class AArch64RedundantCopyElimination : public MachineFunctionPass {
   const TargetRegisterInfo *TRI;
 
 public:
   static char ID;
   AArch64RedundantCopyElimination() : MachineFunctionPass(ID) {
     initializeAArch64RedundantCopyEliminationPass(
         *PassRegistry::getPassRegistry());
   }
-  bool optimizeCopy(MachineBasicBlock *MBB);
+
+  void removeRedundantCopy(MachineInstr *MI, unsigned DefReg,
+                           unsigned &SmallestDef);
+  bool optimizeCopy(MachineBasicBlock *MBB, BitVector &ModifiedRegs);
   bool runOnMachineFunction(MachineFunction &MF) override;
   MachineFunctionProperties getRequiredProperties() const override {
     return MachineFunctionProperties().set(
         MachineFunctionProperties::Property::NoVRegs);
   }
   StringRef getPassName() const override {
     return "AArch64 Redundant Copy Elimination";
   }
 };
 char AArch64RedundantCopyElimination::ID = 0;
 }
 
 INITIALIZE_PASS(AArch64RedundantCopyElimination, "aarch64-copyelim",
                 "AArch64 redundant copy elimination pass", false, false)
 
 static bool guaranteesZeroRegInBlock(MachineInstr &MI, MachineBasicBlock *MBB) {
   unsigned Opc = MI.getOpcode();
   // Check if the current basic block is the target block to which the
   // CBZ/CBNZ instruction jumps when its Wt/Xt is zero.
   return ((Opc == AArch64::CBZW || Opc == AArch64::CBZX) &&
           MBB == MI.getOperand(1).getMBB()) ||
          ((Opc == AArch64::CBNZW || Opc == AArch64::CBNZX) &&
           MBB != MI.getOperand(1).getMBB());
 }
 
-bool AArch64RedundantCopyElimination::optimizeCopy(MachineBasicBlock *MBB) {
+/// Remember what registers the specified instruction modifies.
+static void trackRegDefs(const MachineInstr &MI, BitVector &ModifiedRegs,
+                         const TargetRegisterInfo *TRI) {
+  for (const MachineOperand &MO : MI.operands()) {
+    if (MO.isRegMask())
+      ModifiedRegs.setBitsNotInMask(MO.getRegMask());
+
+    if (!MO.isReg())
+      continue;
+    unsigned Reg = MO.getReg();
+    if (!Reg)
+      continue;
+    if (MO.isDef()) {
+      // WZR/XZR are not modified even when used as a destination register.
+      if (Reg != AArch64::WZR && Reg != AArch64::XZR)
+        for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
+          ModifiedRegs.set(*AI);
+    }
+  }
+}
+
+// Check if the current basic block is the target block to which a conditional
+// branch instruction jumps and whos equality comparison is against a constant.
+// If not, return false.  Otherwise, return true after setting the TargetReg
+// and known ImmVal.
+static bool knownRegValInBlock(MachineInstr &MI, MachineBasicBlock *PredMBB,
+                               MachineBasicBlock *MBB, unsigned &TargetReg,
+                               int64_t &ImmVal, BitVector &ModifiedRegs,
+                               const TargetRegisterInfo *TRI) {
+  unsigned Opc = MI.getOpcode();
+
+  // Must be a conditional branch.
+  if (Opc != AArch64::Bcc)
+    return false;
+
+  // Must be an equality check (i.e., == or !=).
+  AArch64CC::CondCode CC = (AArch64CC::CondCode)(int)MI.getOperand(0).getImm();
+  if (CC != AArch64CC::EQ && CC != AArch64CC::NE)
+    return false;
+
+  MachineBasicBlock *BrTarget = MI.getOperand(1).getMBB();
+  if ((CC == AArch64CC::EQ && BrTarget != MBB) ||
+      (CC == AArch64CC::NE && BrTarget == MBB))
+    return false;
+
+  if (MI == PredMBB->begin())
+    return false;
+
+  // Track which registers have been modified.
+  ModifiedRegs.reset();
+
+  // Finds compare instruction that sets NZCV used by conditional branch.
+  for (MachineBasicBlock::iterator B = PredMBB->begin(), I = MI; I != B;) {
+    --I;
+
+    switch (I->getOpcode()) {
+    default:
+      break;
+
+    // CMP is an alias for SUBS with a dead destination register.
+    case AArch64::SUBSWri:
+    case AArch64::SUBSXri: {
+      unsigned DestReg = I->getOperand(0).getReg();
+      if (DestReg != AArch64::WZR && DestReg != AArch64::XZR)
+        return false;
+
+      // Must not be a symbolic immediate.
+      if (!I->getOperand(2).isImm())
+        return false;
+
+      // For simplicity, give up on non-zero shifts.
+      if (I->getOperand(3).getImm())
+        return false;
+
+      // The src register must not be modified between the cmp and conditional
+      // branch.
+      if (ModifiedRegs[I->getOperand(1).getReg()])
+        return false;
+
+      // We know that the TargetReg register contains ImmVal value.
+      TargetReg = I->getOperand(1).getReg();
+      ImmVal = I->getOperand(2).getImm();
+      return true;
+    }
+    }
+
+    // Bail if we see an instruction that defines NZCV, but we don't handle.
+    if (I->definesRegister(AArch64::NZCV))
+      return false;
+
+    // Track modified registers.
+    trackRegDefs(MI, ModifiedRegs, TRI);
+  }
+  return false;
+}
+
+void AArch64RedundantCopyElimination::removeRedundantCopy(
+    MachineInstr *MI, unsigned DefReg, unsigned &SmallestDef) {
+  DEBUG(dbgs() << "Remove redundant copy : ");
+  DEBUG((MI)->print(dbgs()));
+
+  MI->eraseFromParent();
+  SmallestDef = TRI->isSubRegister(SmallestDef, DefReg) ? DefReg : SmallestDef;
+  NumCopiesRemoved++;
+}
+
+bool AArch64RedundantCopyElimination::optimizeCopy(MachineBasicBlock *MBB,
+                                                   BitVector &ModifiedRegs) {
   // Check if the current basic block has a single predecessor.
   if (MBB->pred_size() != 1)
     return false;
 
   // Check if the predecessor has two successors, implying the block ends in a
   // conditional branch.
   MachineBasicBlock *PredMBB = *MBB->pred_begin();
   if (PredMBB->succ_size() != 2)
     return false;
 
   MachineBasicBlock::iterator CompBr = PredMBB->getLastNonDebugInstr();
   if (CompBr == PredMBB->end())
     return false;
 
+  bool ZeroRegVal;
+  unsigned TargetReg;
   ++CompBr;
   do {
     --CompBr;
-    if (guaranteesZeroRegInBlock(*CompBr, MBB))
+    if ((ZeroRegVal = guaranteesZeroRegInBlock(*CompBr, MBB))) {
+      TargetReg = CompBr->getOperand(0).getReg();
       break;
+    }
   } while (CompBr != PredMBB->begin() && CompBr->isTerminator());
 
-  // We've not found a CBZ/CBNZ, time to bail out.
-  if (!guaranteesZeroRegInBlock(*CompBr, MBB))
-    return false;
+  int64_t KnownImm;
+  bool KnownRegVal = false;
+  if (!ZeroRegVal) {
+    CompBr = PredMBB->getLastNonDebugInstr();
+    KnownRegVal = knownRegValInBlock(*CompBr, PredMBB, MBB, TargetReg, KnownImm,
+                                     ModifiedRegs, TRI);
+  }
 
-  unsigned TargetReg = CompBr->getOperand(0).getReg();
-  if (!TargetReg)
+  // We've not found a CBZ/CBNZ or a non-zero compare and branch, time to bail
+  // out.
+  if (!ZeroRegVal && !KnownRegVal)
     return false;
+
   assert(TargetRegisterInfo::isPhysicalRegister(TargetReg) &&
          "Expect physical register");
+  assert(!(ZeroRegVal && KnownRegVal) &&
+         "ZeroRegVal and KnownRegVal can't both be true.");
 
   // Remember all registers aliasing with TargetReg.
   SmallSetVector<unsigned, 8> TargetRegs;
   for (MCRegAliasIterator AI(TargetReg, TRI, true); AI.isValid(); ++AI)
     TargetRegs.insert(*AI);
 
   bool Changed = false;
   MachineBasicBlock::iterator LastChange = MBB->begin();
   unsigned SmallestDef = TargetReg;
   // Remove redundant Copy instructions unless TargetReg is modified.
   for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E;) {
     MachineInstr *MI = &*I;
     ++I;
-    if (MI->isCopy() && MI->getOperand(0).isReg() &&
+
+    // Case 1:
+    //   BB#0:
+    //     cbz x0, .LBB0_2
+    //   BB#1:
+    //     ldr x0, [x1]
+    //     ret
+    //   .LBB0_2:
+    //     mov x0, wzr <-- redundant copy
+    //     ret
+    if (ZeroRegVal && MI->isCopy() && MI->getOperand(0).isReg() &&
         MI->getOperand(1).isReg()) {
 
       unsigned DefReg = MI->getOperand(0).getReg();
       unsigned SrcReg = MI->getOperand(1).getReg();
-
-      if ((SrcReg == AArch64::XZR || SrcReg == AArch64::WZR) &&
-          !MRI->isReserved(DefReg) &&
+      if (!MRI->isReserved(DefReg) &&
+          (SrcReg == AArch64::XZR || SrcReg == AArch64::WZR) &&
           (TargetReg == DefReg || TRI->isSuperRegister(DefReg, TargetReg))) {
-        DEBUG(dbgs() << "Remove redundant Copy : ");
-        DEBUG((MI)->print(dbgs()));
-
-        MI->eraseFromParent();
+        removeRedundantCopy(MI, DefReg, SmallestDef);
+        LastChange = I;
         Changed = true;
+        continue;
+      }
+    }
+    // Case 2:
+    //   BB#0:
+    //     cmp x0, #1
+    //     b.eq .LBB0_2
+    //   BB#1:
+    //     ldr x0, [x1]
+    //     ret
+    //   .LBB0_2:
+    //     orr x0, xzr, #0x1 <-- redundant mov
+    //     ret
+    if (KnownRegVal && MI->isMoveImmediate() && MI->getOperand(0).isReg() &&
+        MI->getOperand(1).isImm()) {
+
+      unsigned DefReg = MI->getOperand(0).getReg();
+      int64_t SrcImm = MI->getOperand(1).getImm();
+
+      if (!MRI->isReserved(DefReg) && SrcImm == KnownImm &&
+          (TargetReg == DefReg || TRI->isSuperRegister(DefReg, TargetReg))) {
+        removeRedundantCopy(MI, DefReg, SmallestDef);
         LastChange = I;
-        NumCopiesRemoved++;
-        SmallestDef =
-            TRI->isSubRegister(SmallestDef, DefReg) ? DefReg : SmallestDef;
+        Changed = true;
         continue;
       }
     }
 
+    // Give up if the target register's value is changed.
     if (MI->modifiesRegister(TargetReg, TRI))
       break;
   }
 
   if (!Changed)
     return false;
 
   // Otherwise, we have to fixup the use-def chain, starting with the
   // CBZ/CBNZ. Conservatively mark as much as we can live.
   CompBr->clearRegisterKills(SmallestDef, TRI);
 
   if (none_of(TargetRegs, [&](unsigned Reg) { return MBB->isLiveIn(Reg); }))
     MBB->addLiveIn(TargetReg);
 
   // Clear any kills of TargetReg between CompBr and the last removed COPY.
   for (MachineInstr &MMI : make_range(MBB->begin(), LastChange))
     MMI.clearRegisterKills(SmallestDef, TRI);
 
   return true;
 }
 
 bool AArch64RedundantCopyElimination::runOnMachineFunction(
     MachineFunction &MF) {
   if (skipFunction(*MF.getFunction()))
     return false;
   TRI = MF.getSubtarget().getRegisterInfo();
   MRI = &MF.getRegInfo();
+
+  // Resize the modified register bitfield trackers.  We do this once per
+  // function and then clear the bitfield each time we optimize a copy.
+  BitVector ModifiedRegs;
+  ModifiedRegs.resize(TRI->getNumRegs());
+
   bool Changed = false;
   for (MachineBasicBlock &MBB : MF)
-    Changed |= optimizeCopy(&MBB);
+    Changed |= optimizeCopy(&MBB, ModifiedRegs);
   return Changed;
 }
 
 FunctionPass *llvm::createAArch64RedundantCopyEliminationPass() {
   return new AArch64RedundantCopyElimination();
 }

test/CodeGen/AArch64/machine-copy-remove.mir

+# RUN: llc -mtriple=aarch64--linux-gnu -run-pass=aarch64-copyelim %s -verify-machineinstrs -o - 2>&1 | FileCheck %s
+
+# These tests make sure we can remove a redundant non-zero copy instruction.
+
+--- |
+  define void @test1() { ret void }
+  define void @test2() { ret void }
+...
+---
+name:            test1
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    successors: %bb.1(0x40000000), %bb.2(0x40000000)
+    liveins: %w0, %x1
+
+    dead %wzr = SUBSWri killed %w0, 1, 0, implicit-def %nzcv
+    Bcc 1, %bb.2, implicit killed %nzcv
+
+  bb.1:
+    successors: %bb.3(0x80000000)
+
+    %w0 = MOVi32imm 1  ; MOVi32imm is redundant base on a dominating condition.
+    B %bb.3
+
+  bb.2:
+    successors: %bb.3(0x80000000)
+    liveins: %x1
+
+    %w0 = LDRWui killed %x1, 0 :: (load 4)
+
+  bb.3:
+    liveins: %w0
+
+    RET_ReallyLR implicit %w0
+
+...
+# CHECK-LABEL: test2
+# CHECK: bb.1:
+# CHECK-NEXT: successors: %bb.3(0x80000000)
+# CHECK-NEXT: liveins: %w0
+# CHECK-NOT:  %w0 = MOVi32imm 1
+# CHECK: RET_ReallyLR
+---
+name:            test2
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    successors: %bb.1(0x40000000), %bb.2(0x40000000)
+    liveins: %x0, %x1
+
+    dead %xzr = SUBSXri killed %x0, 1, 0, implicit-def %nzcv
+    Bcc 1, %bb.2, implicit killed %nzcv
+
+  bb.1:
+    successors: %bb.3(0x80000000)
+
+    %w0 = MOVi32imm 1, implicit-def %x0  ; MOVi32imm is redundant base on a dominating condition.
+    B %bb.3
+
+  bb.2:
+    successors: %bb.3(0x80000000)
+    liveins: %x1
+
+    %x0 = LDRXui killed %x1, 0 :: (load 8)
+
+  bb.3:
+    liveins: %x0
+
+    RET_ReallyLR implicit %x0
+...
+# CHECK-LABEL: test2
+# CHECK: bb.1:
+# CHECK-NEXT: successors: %bb.3(0x80000000)
+# CHECK-NEXT: liveins: %x0
+# CHECK-NOT:  %w0 = MOVi32imm 1
+# CHECK: RET_ReallyLR