[Builtin][ARM] Add Thumb1 support for aeabi_c{f,d}cmp.S and dcmp.S

[rengolin]

Hi Weiming,

We have here the same problem as we had in the other patch: MRS/MSR is only available in ARMv6M. We'll have to find another way.

cheers,
--renato

lib/builtins/arm/aeabi_cdcmp.S

43

MSR is not available in Thumb1.

[weimingz]

using lsls to indirectly set PSR flags

[weimingz]

I run the tests under compiler-rt/test/builtins/Unit/arm

[rengolin]

Hi Weiming, this looks reasonable to me. Just use the same encoding for LSLS and feel free to commit.

Thanks!
--renato

lib/builtins/arm/aeabi_cdcmp.S

102

Use LSLS one-reg or two-reg encoding (A8.8.94 T1), but not both.

lib/builtins/CMakeLists.txt

set(arm_EABI_SOURCES
   arm/aeabi_memcmp.S
   arm/aeabi_memcpy.S
   arm/aeabi_memmove.S
   arm/aeabi_memset.S
   arm/aeabi_uidivmod.S
   arm/aeabi_uldivmod.S)
 
 set(thumb1_EABI_SOURCES
+  arm/aeabi_cdcmp.S
   arm/aeabi_cdcmpeq_check_nan.c
+  arm/aeabi_cfcmp.S
   arm/aeabi_cfcmpeq_check_nan.c
+  arm/aeabi_dcmp.S
   arm/aeabi_div0.c
   arm/aeabi_drsub.c
   arm/aeabi_fcmp.S
   arm/aeabi_frsub.c
   arm/aeabi_idivmod.S
   arm/aeabi_memcmp.S
   arm/aeabi_memcpy.S
   arm/aeabi_memset.S

lib/builtins/arm/aeabi_cdcmp.S

 //===-- aeabi_cdcmp.S - EABI cdcmp* implementation ------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is dual licensed under the MIT and the University of Illinois Open
 // Source Licenses. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
 #include "../assembly.h"
 
 #if __BYTE_ORDER__ != __ORDER_LITTLE_ENDIAN__
 #error big endian support not implemented
 #endif
 
-#define APSR_Z (1 << 30)
-#define APSR_C (1 << 29)
+#define APSR_Z_SHIFT 30
+#define APSR_C_SHIFT 29
+#define APSR_Z (1 << APSR_Z_SHIFT)
+#define APSR_C (1 << APSR_C_SHIFT)
 
 // void __aeabi_cdcmpeq(double a, double b) {
 //   if (isnan(a) || isnan(b)) {
 //     Z = 0; C = 1;
 //   } else {
 //     __aeabi_cdcmple(a, b);
 //   }
 // }
 
         .syntax unified
         .p2align 2
 DEFINE_COMPILERRT_FUNCTION(__aeabi_cdcmpeq)
         push {r0-r3, lr}
         bl __aeabi_cdcmpeq_check_nan
         cmp r0, #1
+#if __ARM_ARCH_ISA_THUMB == 1
+        beq 1f
+        // NaN has been ruled out, so __aeabi_cdcmple can't trap
+        bl __aeabi_cdcmple
+        pop {r0-r3, pc}
+1:
+        movs r0, #1
+        lsls r0, #APSR_C_SHIFT
+        msr APSR, r0
+        pop {r0-r3, pc}
+#else
         pop {r0-r3, lr}
 
         // NaN has been ruled out, so __aeabi_cdcmple can't trap
         bne __aeabi_cdcmple
 
         msr CPSR_f, #APSR_C
         JMP(lr)
+#endif
 END_COMPILERRT_FUNCTION(__aeabi_cdcmpeq)
 
 
 // void __aeabi_cdcmple(double a, double b) {
 //   if (__aeabi_dcmplt(a, b)) {
 //     Z = 0; C = 0;
 //   } else if (__aeabi_dcmpeq(a, b)) {
 //     Z = 1; C = 1;
 //   } else {
 //     Z = 0; C = 1;
 //   }
 // }
 
         .syntax unified
         .p2align 2
 DEFINE_COMPILERRT_FUNCTION(__aeabi_cdcmple)
         // Per the RTABI, this function must preserve r0-r11.
         // Save lr in the same instruction for compactness
+#if __ARM_ARCH_ISA_THUMB == 1
+        push {r0-r4, lr}
+        bl __aeabi_dcmplt
+        cmp r0, #1
+        bne 1f
+        movs r4, #0
+        b 2f
+1:
+        mov r0, sp
+        movs r4, #1
+        ldm r0, {r0-r3}
+        lsls r4, #(APSR_C_SHIFT)
+        bl __aeabi_dcmpeq
+        cmp r0, #1
+        bne 2f
+        movs r0, #1
+        lsls r0, #(APSR_Z_SHIFT)
+        orrs r4, r0
+2:
+        msr APSR, r4
+        pop {r0,r4}
+#else
         push {r0-r3, lr}
 
         bl __aeabi_dcmplt
         cmp r0, #1
         moveq ip, #0
         beq 1f
 
         ldm sp, {r0-r3}
         bl __aeabi_dcmpeq
         cmp r0, #1
         moveq ip, #(APSR_C | APSR_Z)
         movne ip, #(APSR_C)
 
 1:
         msr CPSR_f, ip
         pop {r0-r3}
+#endif
         POP_PC()
 END_COMPILERRT_FUNCTION(__aeabi_cdcmple)
 
 // int __aeabi_cdrcmple(double a, double b) {
 //   return __aeabi_cdcmple(b, a);
 // }
 
         .syntax unified

lib/builtins/arm/aeabi_cfcmp.S

 //===-- aeabi_cfcmp.S - EABI cfcmp* implementation ------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is dual licensed under the MIT and the University of Illinois Open
 // Source Licenses. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
 #include "../assembly.h"
 
 #if __BYTE_ORDER__ != __ORDER_LITTLE_ENDIAN__
 #error big endian support not implemented
 #endif
-
-#define APSR_Z (1 << 30)
-#define APSR_C (1 << 29)
+#define APSR_Z_SHIFT 30
+#define APSR_C_SHIFT 29
+#define APSR_Z (1 << APSR_Z_SHIFT)
+#define APSR_C (1 << APSR_C_SHIFT)
 
 // void __aeabi_cfcmpeq(float a, float b) {
 //   if (isnan(a) || isnan(b)) {
 //     Z = 0; C = 1;
 //   } else {
 //     __aeabi_cfcmple(a, b);
 //   }
 // }
 
         .syntax unified
         .p2align 2
 DEFINE_COMPILERRT_FUNCTION(__aeabi_cfcmpeq)
         push {r0-r3, lr}
         bl __aeabi_cfcmpeq_check_nan
         cmp r0, #1
+#if __ARM_ARCH_ISA_THUMB == 1
+        beq 1f
+
+        // NaN has been ruled out, so __aeabi_cfcmple can't trap
+        bl __aeabi_cfcmple
+        pop {r0-r3, pc}
+1:
+        movs r0, #1
+        lsls r0, #APSR_C_SHIFT
+        msr APSR, r0
+        pop {r0-r3, pc}
+#else
         pop {r0-r3, lr}
 
         // NaN has been ruled out, so __aeabi_cfcmple can't trap
         bne __aeabi_cfcmple
 
         msr CPSR_f, #APSR_C
         JMP(lr)
+#endif
 END_COMPILERRT_FUNCTION(__aeabi_cfcmpeq)
 
 
 // void __aeabi_cfcmple(float a, float b) {
 //   if (__aeabi_fcmplt(a, b)) {
 //     Z = 0; C = 0;
 //   } else if (__aeabi_fcmpeq(a, b)) {
 //     Z = 1; C = 1;
 //   } else {
 //     Z = 0; C = 1;
 //   }
 // }
 
         .syntax unified
         .p2align 2
 DEFINE_COMPILERRT_FUNCTION(__aeabi_cfcmple)
         // Per the RTABI, this function must preserve r0-r11.
         // Save lr in the same instruction for compactness
+#if __ARM_ARCH_ISA_THUMB == 1
+        push {r0-r4, lr}
+
+        bl __aeabi_fcmplt
+        cmp r0, #1
+
+        bne 1f
+        movs r4, #0
+        b 2f
+1:
+        mov r0, sp
+        movs r4, #1
+        ldm r0, {r0-r3}
+        lsls r4, #APSR_C_SHIFT
+        bl __aeabi_fcmpeq
+        cmp r0, #1
+        bne 2f
+        movs r0, #1
+        lsls r0, #APSR_Z_SHIFT
+        orrs r4, r0
+2:
+        msr APSR, r4
+        pop {r0-r4, pc}
+#else
         push {r0-r3, lr}
 
         bl __aeabi_fcmplt
         cmp r0, #1
         moveq ip, #0
         beq 1f
 
         ldm sp, {r0-r3}
         bl __aeabi_fcmpeq
         cmp r0, #1
         moveq ip, #(APSR_C | APSR_Z)
         movne ip, #(APSR_C)
 
 1:
         msr CPSR_f, ip
         pop {r0-r3}
         POP_PC()
+#endif
 END_COMPILERRT_FUNCTION(__aeabi_cfcmple)
 
 // int __aeabi_cfrcmple(float a, float b) {
 //   return __aeabi_cfcmple(b, a);
 // }
 
         .syntax unified
         .p2align 2

lib/builtins/arm/aeabi_dcmp.S

 #define DEFINE_AEABI_DCMP(cond)                            \
         .syntax unified                          SEPARATOR \
         .p2align 2                               SEPARATOR \
 DEFINE_COMPILERRT_FUNCTION(__aeabi_dcmp ## cond)           \
         push      { r4, lr }                     SEPARATOR \
         bl        SYMBOL_NAME(__ ## cond ## df2) SEPARATOR \
         cmp       r0, #0                         SEPARATOR \
         b ## cond 1f                             SEPARATOR \
-        mov       r0, #0                         SEPARATOR \
+        movs      r0, #0                         SEPARATOR \
         pop       { r4, pc }                     SEPARATOR \
 1:                                               SEPARATOR \
-        mov       r0, #1                         SEPARATOR \
+        movs      r0, #1                         SEPARATOR \
         pop       { r4, pc }                     SEPARATOR \
 END_COMPILERRT_FUNCTION(__aeabi_dcmp ## cond)
 
 DEFINE_AEABI_DCMP(eq)
 DEFINE_AEABI_DCMP(lt)
 DEFINE_AEABI_DCMP(le)
 DEFINE_AEABI_DCMP(ge)
 DEFINE_AEABI_DCMP(gt)
 
 NO_EXEC_STACK_DIRECTIVE