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Differential D28101

AMDGPU: Fold fneg into rcp
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Authored by arsenm on Dec 24 2016, 9:06 AM.

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Reviewers
• tstellarAMD
nhaehnle
escha

Diff Detail

Event Timeline

arsenm updated this revision to Diff 82450.Dec 24 2016, 9:06 AM
arsenm retitled this revision from to AMDGPU: Fold fneg into rcp.
arsenm updated this object.
arsenm added a reviewer: escha.
arsenm added a subscriber: llvm-commits.
Herald added a reviewer: • tstellarAMD. · View Herald TranscriptDec 24 2016, 9:06 AM
Herald added subscribers: tony-tye, yaxunl, nhaehnle and 2 others. · View Herald Transcript
arsenm added a child revision: D28256: AMDGPU: Skip fneg/select combine if it can fold into other.Jan 3 2017, 2:36 PM
nhaehnle added a comment.Jan 11 2017, 2:49 PM

This looks like it's missing a rebase onto the rest of the series.

arsenm updated this revision to Diff 84065.Jan 11 2017, 6:39 PM
arsenm edited edge metadata.

Rebase properly

Herald edited edge metadata. · View Herald TranscriptJan 11 2017, 6:39 PM
nhaehnle accepted this revision.Jan 12 2017, 1:17 AM
nhaehnle added a reviewer: nhaehnle.

I don't see the change that merges the FP_EXTEND / FP_ROUND cases. But the end result LGTM.

This revision is now accepted and ready to land.Jan 12 2017, 1:17 AM
arsenm closed this revision.Jan 12 2017, 9:59 AM

r291779

Revision Contents

PathSize
lib/
Target/
AMDGPU/
8 lines
test/
CodeGen/
AMDGPU/
100 lines

Diff 84065

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

Show First 20 Lines • Show All 2,807 Lines • ▼ Show 20 Lines
static bool fnegFoldsIntoOp(unsigned Opc) { static bool fnegFoldsIntoOp(unsigned Opc) {
switch (Opc) { switch (Opc) {
case ISD::FADD: case ISD::FADD:
case ISD::FSUB: case ISD::FSUB:
case ISD::FMUL: case ISD::FMUL:
case ISD::FMA: case ISD::FMA:
case ISD::FMAD: case ISD::FMAD:
case AMDGPUISD::RCP:
case AMDGPUISD::RCP_LEGACY:
return true; return true;
default: default:
return false; return false;
} }
} }
SDValue AMDGPUTargetLowering::performFNegCombine(SDNode *N, SDValue AMDGPUTargetLowering::performFNegCombine(SDNode *N,
DAGCombinerInfo &DCI) const { DAGCombinerInfo &DCI) const {
▲ Show 20 Lines • Show All 71 Lines • ▼ Show 20 Lines else
RHS = RHS.getOperand(0); RHS = RHS.getOperand(0);
SDValue Res = DAG.getNode(Opc, SL, VT, LHS, MHS, RHS); SDValue Res = DAG.getNode(Opc, SL, VT, LHS, MHS, RHS);
if (!N0.hasOneUse()) if (!N0.hasOneUse())
DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res)); DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
return Res; return Res;
} }
case ISD::FP_EXTEND: case ISD::FP_EXTEND:
case ISD::FP_ROUND: { case ISD::FP_ROUND:
case AMDGPUISD::RCP:
case AMDGPUISD::RCP_LEGACY: {
SDValue CvtSrc = N0.getOperand(0); SDValue CvtSrc = N0.getOperand(0);
if (CvtSrc.getOpcode() == ISD::FNEG) { if (CvtSrc.getOpcode() == ISD::FNEG) {
// (fneg (fp_extend (fneg x))) -> (fp_extend x) // (fneg (fp_extend (fneg x))) -> (fp_extend x)
// (fneg (fp_round (fneg x))) -> (fp_round x) // (fneg (fp_round (fneg x))) -> (fp_round x)
// (fneg (rcp (fneg x))) -> (rcp x)
return DAG.getNode(Opc, SL, VT, CvtSrc.getOperand(0)); return DAG.getNode(Opc, SL, VT, CvtSrc.getOperand(0));
} }
if (!N0.hasOneUse()) if (!N0.hasOneUse())
return SDValue(); return SDValue();
// (fneg (fp_extend x)) -> (fp_extend (fneg x)) // (fneg (fp_extend x)) -> (fp_extend (fneg x))
// (fneg (fp_round x)) -> (fp_round (fneg x)) // (fneg (fp_round x)) -> (fp_round (fneg x))
// (fneg (rcp x)) -> (rcp (fneg x))
SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc); SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc);
return DAG.getNode(Opc, SL, VT, Neg); return DAG.getNode(Opc, SL, VT, Neg);
} }
default: default:
return SDValue(); return SDValue();
} }
} }
▲ Show 20 Lines • Show All 443 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/fneg-combines.ll

Show First 20 Lines • Show All 948 Lines • ▼ Show 20 Linesdefine void @v_fneg_fp_round_multi_use_fneg_f32_to_f16(half addrspace(1)* %out, float addrspace(1)* %a.ptr, float %c) #0 {
%fpround = fptrunc float %fneg.a to half %fpround = fptrunc float %fneg.a to half
%fneg = fsub half -0.000000e+00, %fpround %fneg = fsub half -0.000000e+00, %fpround
%use1 = fmul float %fneg.a, %c %use1 = fmul float %fneg.a, %c
store volatile half %fneg, half addrspace(1)* %out.gep store volatile half %fneg, half addrspace(1)* %out.gep
store volatile float %use1, float addrspace(1)* undef store volatile float %use1, float addrspace(1)* undef
ret void ret void
} }
; --------------------------------------------------------------------------------
; rcp tests
; --------------------------------------------------------------------------------
; GCN-LABEL: {{^}}v_fneg_rcp_f32:
; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
; GCN: v_rcp_f32_e64 [[RESULT:v[0-9]+]], -[[A]]
; GCN: buffer_store_dword [[RESULT]]
define void @v_fneg_rcp_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
%out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
%a = load volatile float, float addrspace(1)* %a.gep
%rcp = call float @llvm.amdgcn.rcp.f32(float %a)
%fneg = fsub float -0.000000e+00, %rcp
store float %fneg, float addrspace(1)* %out.gep
ret void
}
; GCN-LABEL: {{^}}v_fneg_rcp_fneg_f32:
; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
; GCN: v_rcp_f32_e32 [[RESULT:v[0-9]+]], [[A]]
; GCN: buffer_store_dword [[RESULT]]
define void @v_fneg_rcp_fneg_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
%out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
%a = load volatile float, float addrspace(1)* %a.gep
%fneg.a = fsub float -0.000000e+00, %a
%rcp = call float @llvm.amdgcn.rcp.f32(float %fneg.a)
%fneg = fsub float -0.000000e+00, %rcp
store float %fneg, float addrspace(1)* %out.gep
ret void
}
; GCN-LABEL: {{^}}v_fneg_rcp_store_use_fneg_f32:
; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
; GCN-DAG: v_rcp_f32_e32 [[RESULT:v[0-9]+]], [[A]]
; GCN-DAG: v_xor_b32_e32 [[NEG_A:v[0-9]+]], 0x80000000, [[A]]
; GCN: buffer_store_dword [[RESULT]]
; GCN: buffer_store_dword [[NEG_A]]
define void @v_fneg_rcp_store_use_fneg_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
%out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
%a = load volatile float, float addrspace(1)* %a.gep
%fneg.a = fsub float -0.000000e+00, %a
%rcp = call float @llvm.amdgcn.rcp.f32(float %fneg.a)
%fneg = fsub float -0.000000e+00, %rcp
store volatile float %fneg, float addrspace(1)* %out.gep
store volatile float %fneg.a, float addrspace(1)* undef
ret void
}
; GCN-LABEL: {{^}}v_fneg_rcp_multi_use_fneg_f32:
; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
; GCN-DAG: v_rcp_f32_e32 [[RESULT:v[0-9]+]], [[A]]
; GCN-DAG: v_mul_f32_e64 [[MUL:v[0-9]+]], -[[A]], s{{[0-9]+}}
; GCN: buffer_store_dword [[RESULT]]
; GCN: buffer_store_dword [[MUL]]
define void @v_fneg_rcp_multi_use_fneg_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float %c) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
%out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
%a = load volatile float, float addrspace(1)* %a.gep
%fneg.a = fsub float -0.000000e+00, %a
%rcp = call float @llvm.amdgcn.rcp.f32(float %fneg.a)
%fneg = fsub float -0.000000e+00, %rcp
%use1 = fmul float %fneg.a, %c
store volatile float %fneg, float addrspace(1)* %out.gep
store volatile float %use1, float addrspace(1)* undef
ret void
}
; --------------------------------------------------------------------------------
; rcp_legacy tests
; --------------------------------------------------------------------------------
; GCN-LABEL: {{^}}v_fneg_rcp_legacy_f32:
; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
; GCN: v_rcp_legacy_f32_e64 [[RESULT:v[0-9]+]], -[[A]]
; GCN: buffer_store_dword [[RESULT]]
define void @v_fneg_rcp_legacy_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
%out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
%a = load volatile float, float addrspace(1)* %a.gep
%rcp = call float @llvm.amdgcn.rcp.legacy(float %a)
%fneg = fsub float -0.000000e+00, %rcp
store float %fneg, float addrspace(1)* %out.gep
ret void
}
declare i32 @llvm.amdgcn.workitem.id.x() #1 declare i32 @llvm.amdgcn.workitem.id.x() #1
declare float @llvm.fma.f32(float, float, float) #1 declare float @llvm.fma.f32(float, float, float) #1
declare float @llvm.fmuladd.f32(float, float, float) #1 declare float @llvm.fmuladd.f32(float, float, float) #1
declare float @llvm.amdgcn.rcp.f32(float) #1
declare float @llvm.amdgcn.rcp.legacy(float) #1
attributes #0 = { nounwind } attributes #0 = { nounwind }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }