AMD family 17h (znver1) enablement

[GGanesh]

Summary

This patch enables the following

1. AMD family 17h architecture using "znver1" tune flag (-march, -mcpu).
2. ISAs that are enabled for "znver1" architecture.
3. Checks ADX isa from cpuid to identify "znver1" flag when -march=native is used.
4. Enables CLZERO feature and adds the builtin macro __builtin_ia32_clzero for clzero instruction.
5. ISAs FMA4, XOP are disabled as they are dropped from amdfam17.
6. For the time being, it uses the btver2 scheduler model.
7. Test file is updated to check this flag.

This item is linked to clang review item https://reviews.llvm.org/D28018

[RKSimon]

This needs tests for the clzero intrinsic (behind a -mattr=+clzero arg for 32 and 64-bit targets as well as -mcpu=znver1), in fact it probably make sense to separate the clzero support out into a separate preliminary patch and then add -mcpu=znver1 test as part of this one?

lib/Target/X86/X86.td

802

Only one use so far - probably best to just declare it as :

def : ProcessorModel<"znver1", BtVer2Model, [

Also, add a TODO comment for a znver1 scheduler model

[craig.topper]

lib/Target/X86/X86InstrInfo.td

2456 ↗

(On Diff #82213)

The custom inserter needs to be implemented in X86ISelLowering.cpp. As Simon said, clzero should be split out of this patch.

[RKSimon]

lib/Target/X86/X86.td

797

GCC seems to think znver1 has MOVBE support - who is right?

[GGanesh]

I am preparing a patch which doesn't include the clzero feature patch.
I will submit a separate patch for clzero feature patch.

[GGanesh]

The clzero intrinsic handling and feature addition will be handled as a separate patch.
Added movbe and sse4a into ISA list of znver1.

[RKSimon]

A few minors but I don't have any major concerns.

Add znver1 tests to llvm\test\CodeGen\X86\slow-unaligned-mem.ll

lib/Target/X86/X86.td

764

Are we happy with alphabetical ordering of the feature bits? We don't seem to be consistent for this for many targets at all.

767

Remove FeatureAVX - it will be implicitly included as FeatureAVX2 is set.

777

Add znver1 to llvm\test\CodeGen\X86\lzcnt-zext-cmp.ll

791

Remove FeatureSSSE3 - it will be implicitly included as FeatureAVX2 is set.

792

Add znver1 to llvm\test\CodeGen\X86\x86-64-double-shifts-var.ll as you're testing for slow SHLD

[GGanesh]

Adding znver1 to following tests.
a. LZCNT
b. Slow SHLD
c. slow unaligned memory

Added a TODO noting down znver1 scheduler model is due.

[RKSimon]

LGTM - @craig.topper any additional comments?

[craig.topper]

LGTM

lib/Support/Host.cpp

enum ProcessorTypes {
   INTEL_X86_64,
   INTEL_NOCONA,
   INTEL_PRESCOTT,
   AMD_i486,
   AMDPENTIUM,
   AMDATHLON,
   AMDFAM14H,
   AMDFAM16H,
+  AMDFAM17H,
   CPU_TYPE_MAX
 };
 
 enum ProcessorSubtypes {
   INTEL_COREI7_NEHALEM = 1,
   INTEL_COREI7_WESTMERE,
   INTEL_COREI7_SANDYBRIDGE,
   AMDFAM10H_BARCELONA,
enum ProcessorSubtypes {
   AMDATHLON_K8SSE3,
   AMDATHLON_OPTERON,
   AMDATHLON_FX,
   AMDATHLON_64,
   AMD_BTVER1,
   AMD_BTVER2,
   AMDFAM15H_BDVER3,
   AMDFAM15H_BDVER4,
+  AMDFAM17H_ZNVER1,
   CPU_SUBTYPE_MAX
 };
 
 enum ProcessorFeatures {
   FEATURE_CMOV = 0,
   FEATURE_MMX,
   FEATURE_POPCNT,
   FEATURE_SSE,
case 22:
     *Type = AMDFAM16H;
     if (!(Features &
           (1 << FEATURE_AVX))) { // If no AVX support provide a sane fallback.
       *Subtype = AMD_BTVER1;
       break; // "btver1";
     }
     *Subtype = AMD_BTVER2;
     break; // "btver2"
+  case 23:
+    *Type = AMDFAM17H;
+    if (Features & (1 << FEATURE_ADX)) {
+      *Subtype = AMDFAM17H_ZNVER1;
+      break; // "znver1"
+    }
+    *Subtype =  AMD_BTVER1;
+    break;
   default:
     break; // "generic"
   }
 }
 
 static unsigned getAvailableFeatures(unsigned int ECX, unsigned int EDX,
                                      unsigned MaxLeaf) {
   unsigned Features = 0;
case AMDFAM16H:
       switch (Subtype) {
       case AMD_BTVER1:
         return "btver1";
       case AMD_BTVER2:
         return "btver2";
       default:
         return "amdfam16";
       }
+    case AMDFAM17H:
+      switch (Subtype) {
+      case AMD_BTVER1:
+        return "btver1";
+      case AMDFAM17H_ZNVER1:
+        return "znver1";
+      default:
+        return "amdfam17";
+      }
     default:
       return "generic";
     }
   }
   return "generic";
 }
 
 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))

lib/Target/X86/X86.td

def : Proc<"bdver4", [
   FeatureFMA,
   FeatureXSAVEOPT,
   FeatureSlowSHLD,
   FeatureFSGSBase,
   FeatureLAHFSAHF,
   FeatureMWAITX
 ]>;
 
+// Zen
+def: ProcessorModel<"znver1", BtVer2Model, [
+  FeatureADX,
+  FeatureAES,
+  FeatureAVX,
+  FeatureAVX2,
+  FeatureBMI,
+  FeatureBMI2,
+  FeatureCLFLUSHOPT,
+  FeatureCMPXCHG16B,
+  FeatureF16C,
+  FeatureFMA,
+  FeatureFSGSBase,
+  FeatureFXSR,
+  FeatureFastLZCNT,
+  FeatureLAHFSAHF,
+  FeatureLZCNT,
+  FeatureMMX,
+  FeatureMOVBE,
+  FeatureMWAITX,
+  FeaturePCLMUL,
+  FeaturePOPCNT,
+  FeaturePRFCHW,
+  FeatureRDRAND,
+  FeatureRDSEED,
+  FeatureSHA,
+  FeatureSMAP,
+  FeatureSSE4A,
+  FeatureSSSE3,
+  FeatureSlowSHLD,
+  FeatureX87,
+  FeatureXSAVE,
+  FeatureXSAVEC,
+  FeatureXSAVEOPT,
+  FeatureXSAVES]>;
+
 def : Proc<"geode",           [FeatureX87, FeatureSlowUAMem16, Feature3DNowA]>;
 
 def : Proc<"winchip-c6",      [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;
 def : Proc<"winchip2",        [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
 def : Proc<"c3",              [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
 def : Proc<"c3-2",            [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
                                FeatureSSE1, FeatureFXSR]>;
 
 // We also provide a generic 64-bit specific x86 processor model which tries to
 // be good for modern chips without enabling instruction set encodings past the
 // basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
 // modern 64-bit x86 chip, and enables features that are generally beneficial.

test/CodeGen/X86/cpus.ll

 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=amdfam10 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=barcelona 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=bdver1 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=bdver2 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=bdver3 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=bdver4 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=btver1 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=btver2 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=znver1 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty