AMDGPU: Use i16 comparison instructions

[arsenm]

Remove incorrect comment

[arsenm]

Forgot to add file

[• tstellarAMD]

LGTM.

test/CodeGen/AMDGPU/icmp.i16.ll

1–2 ↗

(On Diff #82123)

--check-prefixes=

[arsenm]

r290348

lib/Target/AMDGPU/SIISelLowering.cpp

SITargetLowering::SITargetLowering(const TargetMachine &TM,
   setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
   setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
   setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
   setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
 
   setOperationAction(ISD::SETCC, MVT::i1, Promote);
   setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
   setOperationAction(ISD::SETCC, MVT::v4i1, Expand);
+  AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
 
   setOperationAction(ISD::TRUNCATE, MVT::v2i32, Expand);
   setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
 
   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Custom);
   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Custom);
   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Custom);
if (Subtarget->has16BitInsts()) {
     setOperationAction(ISD::Constant, MVT::i16, Legal);
 
     setOperationAction(ISD::SMIN, MVT::i16, Legal);
     setOperationAction(ISD::SMAX, MVT::i16, Legal);
 
     setOperationAction(ISD::UMIN, MVT::i16, Legal);
     setOperationAction(ISD::UMAX, MVT::i16, Legal);
 
-    setOperationAction(ISD::SETCC, MVT::i16, Promote);
-    AddPromotedToType(ISD::SETCC, MVT::i16, MVT::i32);
-
     setOperationAction(ISD::SIGN_EXTEND, MVT::i16, Promote);
     AddPromotedToType(ISD::SIGN_EXTEND, MVT::i16, MVT::i32);
 
     setOperationAction(ISD::ROTR, MVT::i16, Promote);
     setOperationAction(ISD::ROTL, MVT::i16, Promote);
 
     setOperationAction(ISD::SDIV, MVT::i16, Promote);
     setOperationAction(ISD::UDIV, MVT::i16, Promote);

lib/Target/AMDGPU/VOPCInstructions.td

def _e64 : VOP3_Pseudo<opName, P,
     let isCompare = 1;
     let isCommutable = 1;
   }
 }
 
 def VOPC_I1_F16_F16 : VOPC_Profile<[Write32Bit], f16>;
 def VOPC_I1_F32_F32 : VOPC_Profile<[Write32Bit], f32>;
 def VOPC_I1_F64_F64 : VOPC_Profile<[WriteDoubleAdd], f64>;
+def VOPC_I1_I16_I16 : VOPC_Profile<[Write32Bit], i16>;
 def VOPC_I1_I32_I32 : VOPC_Profile<[Write32Bit], i32>;
 def VOPC_I1_I64_I64 : VOPC_Profile<[Write64Bit], i64>;
 
 multiclass VOPC_F16 <string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
   VOPC_Pseudos <opName, VOPC_I1_F16_F16, cond, revOp, 0>;
 
 multiclass VOPC_F32 <string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
   VOPC_Pseudos <opName, VOPC_I1_F32_F32, cond, revOp, 0>;
 
 multiclass VOPC_F64 <string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
   VOPC_Pseudos <opName, VOPC_I1_F64_F64, cond, revOp, 0>;
 
+multiclass VOPC_I16 <string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
+  VOPC_Pseudos <opName, VOPC_I1_I16_I16, cond, revOp, 0>;
+
 multiclass VOPC_I32 <string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
   VOPC_Pseudos <opName, VOPC_I1_I32_I32, cond, revOp, 0>;
 
 multiclass VOPC_I64 <string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
   VOPC_Pseudos <opName, VOPC_I1_I64_I64, cond, revOp, 0>;
 
 multiclass VOPCX_F16 <string opName, string revOp = opName> :
   VOPC_Pseudos <opName, VOPC_I1_F16_F16, COND_NULL, revOp, 1>;

 defm V_CMPSX_NGT_F64 : VOPCX_F64 <"v_cmpsx_ngt_f64", "v_cmpsx_nlt_f64">;
 defm V_CMPSX_NLE_F64 : VOPCX_F64 <"v_cmpsx_nle_f64">;
 defm V_CMPSX_NEQ_F64 : VOPCX_F64 <"v_cmpsx_neq_f64">;
 defm V_CMPSX_NLT_F64 : VOPCX_F64 <"v_cmpsx_nlt_f64">;
 defm V_CMPSX_TRU_F64 : VOPCX_F64 <"v_cmpsx_tru_f64">;
 
 } // End SubtargetPredicate = isSICI
 
-let SubtargetPredicate = isVI in {
+let SubtargetPredicate = Has16BitInsts in {
 
 defm V_CMP_F_F16    : VOPC_F16 <"v_cmp_f_f16">;
 defm V_CMP_LT_F16   : VOPC_F16 <"v_cmp_lt_f16", COND_OLT, "v_cmp_gt_f16">;
 defm V_CMP_EQ_F16   : VOPC_F16 <"v_cmp_eq_f16", COND_OEQ>;
 defm V_CMP_LE_F16   : VOPC_F16 <"v_cmp_le_f16", COND_OLE, "v_cmp_ge_f16">;
 defm V_CMP_GT_F16   : VOPC_F16 <"v_cmp_gt_f16", COND_OGT>;
 defm V_CMP_LG_F16   : VOPC_F16 <"v_cmp_lg_f16", COND_ONE>;
 defm V_CMP_GE_F16   : VOPC_F16 <"v_cmp_ge_f16", COND_OGE>;

 defm V_CMPX_NGE_F16 : VOPCX_F16 <"v_cmpx_nge_f16">;
 defm V_CMPX_NLG_F16 : VOPCX_F16 <"v_cmpx_nlg_f16">;
 defm V_CMPX_NGT_F16 : VOPCX_F16 <"v_cmpx_ngt_f16">;
 defm V_CMPX_NLE_F16 : VOPCX_F16 <"v_cmpx_nle_f16">;
 defm V_CMPX_NEQ_F16 : VOPCX_F16 <"v_cmpx_neq_f16">;
 defm V_CMPX_NLT_F16 : VOPCX_F16 <"v_cmpx_nlt_f16">;
 defm V_CMPX_TRU_F16 : VOPCX_F16 <"v_cmpx_tru_f16">;
 
+defm V_CMP_F_I16 : VOPC_I16 <"v_cmp_f_i16">;
+defm V_CMP_LT_I16 : VOPC_I16 <"v_cmp_lt_i16", COND_SLT, "v_cmp_gt_i16">;
+defm V_CMP_EQ_I16 : VOPC_I16 <"v_cmp_eq_i16">;
+defm V_CMP_LE_I16 : VOPC_I16 <"v_cmp_le_i16", COND_SLE, "v_cmp_ge_i16">;
+defm V_CMP_GT_I16 : VOPC_I16 <"v_cmp_gt_i16", COND_SGT>;
+defm V_CMP_NE_I16 : VOPC_I16 <"v_cmp_ne_i16">;
+defm V_CMP_GE_I16 : VOPC_I16 <"v_cmp_ge_i16", COND_SGE>;
+defm V_CMP_T_I16 : VOPC_I16 <"v_cmp_t_i16">;
+
+defm V_CMP_F_U16 : VOPC_I16 <"v_cmp_f_u16">;
+defm V_CMP_LT_U16 : VOPC_I16 <"v_cmp_lt_u16", COND_ULT, "v_cmp_gt_u16">;
+defm V_CMP_EQ_U16 : VOPC_I16 <"v_cmp_eq_u16", COND_EQ>;
+defm V_CMP_LE_U16 : VOPC_I16 <"v_cmp_le_u16", COND_ULE, "v_cmp_ge_u16">;
+defm V_CMP_GT_U16 : VOPC_I16 <"v_cmp_gt_u16", COND_UGT>;
+defm V_CMP_NE_U16 : VOPC_I16 <"v_cmp_ne_u16", COND_NE>;
+defm V_CMP_GE_U16 : VOPC_I16 <"v_cmp_ge_u16", COND_UGE>;
+defm V_CMP_T_U16 : VOPC_I16 <"v_cmp_t_u16">;
+
 } // End SubtargetPredicate = isVI
 
 defm V_CMP_F_I32 : VOPC_I32 <"v_cmp_f_i32">;
 defm V_CMP_LT_I32 : VOPC_I32 <"v_cmp_lt_i32", COND_SLT, "v_cmp_gt_i32">;
 defm V_CMP_EQ_I32 : VOPC_I32 <"v_cmp_eq_i32">;
 defm V_CMP_LE_I32 : VOPC_I32 <"v_cmp_le_i32", COND_SLE, "v_cmp_ge_i32">;
 defm V_CMP_GT_I32 : VOPC_I32 <"v_cmp_gt_i32", COND_SGT>;
 defm V_CMP_NE_I32 : VOPC_I32 <"v_cmp_ne_i32">;

 defm V_CMPX_NGE_F64   : VOPC_Real_vi <0x79>;
 defm V_CMPX_NLG_F64   : VOPC_Real_vi <0x7a>;
 defm V_CMPX_NGT_F64   : VOPC_Real_vi <0x7b>;
 defm V_CMPX_NLE_F64   : VOPC_Real_vi <0x7c>;
 defm V_CMPX_NEQ_F64   : VOPC_Real_vi <0x7d>;
 defm V_CMPX_NLT_F64   : VOPC_Real_vi <0x7e>;
 defm V_CMPX_TRU_F64   : VOPC_Real_vi <0x7f>;
 
+defm V_CMP_F_I16      : VOPC_Real_vi <0xa0>;
+defm V_CMP_LT_I16     : VOPC_Real_vi <0xa1>;
+defm V_CMP_EQ_I16     : VOPC_Real_vi <0xa2>;
+defm V_CMP_LE_I16     : VOPC_Real_vi <0xa3>;
+defm V_CMP_GT_I16     : VOPC_Real_vi <0xa4>;
+defm V_CMP_NE_I16     : VOPC_Real_vi <0xa5>;
+defm V_CMP_GE_I16     : VOPC_Real_vi <0xa6>;
+defm V_CMP_T_I16      : VOPC_Real_vi <0xa7>;
+
+defm V_CMP_F_U16      : VOPC_Real_vi <0xa8>;
+defm V_CMP_LT_U16     : VOPC_Real_vi <0xa9>;
+defm V_CMP_EQ_U16     : VOPC_Real_vi <0xaa>;
+defm V_CMP_LE_U16     : VOPC_Real_vi <0xab>;
+defm V_CMP_GT_U16     : VOPC_Real_vi <0xac>;
+defm V_CMP_NE_U16     : VOPC_Real_vi <0xad>;
+defm V_CMP_GE_U16     : VOPC_Real_vi <0xae>;
+defm V_CMP_T_U16      : VOPC_Real_vi <0xaf>;
+
 defm V_CMP_F_I32      : VOPC_Real_vi <0xc0>;
 defm V_CMP_LT_I32     : VOPC_Real_vi <0xc1>;
 defm V_CMP_EQ_I32     : VOPC_Real_vi <0xc2>;
 defm V_CMP_LE_I32     : VOPC_Real_vi <0xc3>;
 defm V_CMP_GT_I32     : VOPC_Real_vi <0xc4>;
 defm V_CMP_NE_I32     : VOPC_Real_vi <0xc5>;
 defm V_CMP_GE_I32     : VOPC_Real_vi <0xc6>;
 defm V_CMP_T_I32      : VOPC_Real_vi <0xc7>;

test/CodeGen/AMDGPU/fcmp.f16.ll

entry:
   %a.val = load half, half addrspace(1)* %a
   %b.val = load half, half addrspace(1)* %b
   %r.val = fcmp olt half %a.val, %b.val
   %r.val.sext = sext i1 %r.val to i32
   store i32 %r.val.sext, i32 addrspace(1)* %r
   ret void
 }
 
+; GCN-LABEL: {{^}}fcmp_f16_lt_abs:
+; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
+; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]
+
+; SI:  v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
+; SI:  v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]
+
+; SI:  v_cmp_lt_f32_e64 s{{\[[0-9]+:[0-9]+\]}}, |v[[A_F32]]|, |v[[B_F32]]|
+; VI:  v_cmp_lt_f16_e64 s{{\[[0-9]+:[0-9]+\]}}, |v[[A_F16]]|, |v[[B_F16]]|
+
+; GCN: v_cndmask_b32_e64 v[[R_I32:[0-9]+]]
+; GCN: buffer_store_dword v[[R_I32]]
+; GCN: s_endpgm
+define void @fcmp_f16_lt_abs(
+    i32 addrspace(1)* %r,
+    half addrspace(1)* %a,
+    half addrspace(1)* %b) {
+entry:
+  %a.val = load half, half addrspace(1)* %a
+  %b.val = load half, half addrspace(1)* %b
+  %a.abs = call half @llvm.fabs.f16(half %a.val)
+  %b.abs = call half @llvm.fabs.f16(half %b.val)
+  %r.val = fcmp olt half %a.abs, %b.abs
+  %r.val.sext = sext i1 %r.val to i32
+  store i32 %r.val.sext, i32 addrspace(1)* %r
+  ret void
+}
+
 ; GCN-LABEL: {{^}}fcmp_f16_eq
 ; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
 ; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]
 ; SI:  v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
 ; SI:  v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]
 ; SI:  v_cmp_eq_f32_e32 vcc, v[[A_F32]], v[[B_F32]]
 ; VI:  v_cmp_eq_f16_e32 vcc, v[[A_F16]], v[[B_F16]]
 ; GCN: v_cndmask_b32_e64 v[[R_I32:[0-9]+]]

 entry:
   %a.val = load <2 x half>, <2 x half> addrspace(1)* %a
   %b.val = load <2 x half>, <2 x half> addrspace(1)* %b
   %r.val = fcmp uge <2 x half> %a.val, %b.val
   %r.val.sext = sext <2 x i1> %r.val to <2 x i32>
   store <2 x i32> %r.val.sext, <2 x i32> addrspace(1)* %r
   ret void
 }
+
+declare half @llvm.fabs.f16(half) #1
+
+attributes #0 = { nounwind }
+attributes #1 = { nounwind readnone }

test/CodeGen/AMDGPU/setcc-opt.ll

 define void @zext_bool_icmp_ne_neg1(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
   %icmp0 = icmp ne i32 %a, %b
   %ext = zext i1 %icmp0 to i32
   %icmp1 = icmp ne i32 %ext, -1
   store i1 %icmp1, i1 addrspace(1)* %out
   ret void
 }
 
+; FIXME: VI should eliminate and
 ; FUNC-LABEL: {{^}}cmp_zext_k_i8max:
 ; SI: s_load_dword [[VALUE:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
 ; VI: s_load_dword [[VALUE:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
 ; GCN: s_movk_i32 [[K255:s[0-9]+]], 0xff
-; GCN-DAG: s_and_b32 [[B:s[0-9]+]], [[VALUE]], [[K255]]
 ; GCN-DAG: v_mov_b32_e32 [[VK255:v[0-9]+]], [[K255]]
-; GCN: v_cmp_ne_u32_e32 vcc, [[B]], [[VK255]]
+; SI-DAG: s_and_b32 [[B:s[0-9]+]], [[VALUE]], [[K255]]
+; SI: v_cmp_ne_u32_e32 vcc, [[B]], [[VK255]]
+
+; VI-DAG: v_and_b32_e32 [[B:v[0-9]+]], [[VALUE]], [[VK255]]
+; VI: v_cmp_ne_u16_e32 vcc, [[K255]], [[B]]
+
 ; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
 ; GCN: buffer_store_byte [[RESULT]]
 ; GCN: s_endpgm
 define void @cmp_zext_k_i8max(i1 addrspace(1)* %out, i8 %b) nounwind {
   %b.ext = zext i8 %b to i32
   %icmp0 = icmp ne i32 %b.ext, 255
   store i1 %icmp0, i1 addrspace(1)* %out
   ret void