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Differential D27732

[AMDGPU] Do not emit .AMDGPU.config section for amdhsa
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Authored by kzhuravl on Dec 13 2016, 2:19 PM.

Details

Reviewers
• tstellarAMD
Commits
rG67a6d5401a0d: [AMDGPU] Do not emit .AMDGPU.config section for amdhsa
rL291245: [AMDGPU] Do not emit .AMDGPU.config section for amdhsa

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rL LLVM

Event Timeline

kzhuravl updated this revision to Diff 81301.Dec 13 2016, 2:19 PM
kzhuravl retitled this revision from to [AMDGPU] Do not emit .AMDGPU.config section for amdhsa.
kzhuravl updated this object.
kzhuravl added a reviewer: • tstellarAMD.
kzhuravl added a subscriber: llvm-commits.
Herald edited edge metadata. · View Herald TranscriptDec 13 2016, 2:19 PM
Herald added subscribers: tony-tye, yaxunl, nhaehnle and 2 others. · View Herald Transcript
• tstellarAMD accepted this revision.Dec 14 2016, 7:47 AM
• tstellarAMD edited edge metadata.

LGTM.

This revision is now accepted and ready to land.Dec 14 2016, 7:47 AM
Closed by commit rL291245: [AMDGPU] Do not emit .AMDGPU.config section for amdhsa (authored by kzhuravl). · Explain WhyJan 6 2017, 9:13 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
AMDGPU/
10 lines
test/
CodeGen/
AMDGPU/
3 lines
4 lines

Diff 83373

llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

Show First 20 Lines • Show All 170 Lines • ▼ Show 20 Lines
bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) { bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
// The starting address of all shader programs must be 256 bytes aligned. // The starting address of all shader programs must be 256 bytes aligned.
MF.setAlignment(8); MF.setAlignment(8);
SetupMachineFunction(MF); SetupMachineFunction(MF);
const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
MCContext &Context = getObjFileLowering().getContext(); MCContext &Context = getObjFileLowering().getContext();
if (!STM.isAmdHsaOS()) {
MCSectionELF *ConfigSection = MCSectionELF *ConfigSection =
Context.getELFSection(".AMDGPU.config", ELF::SHT_PROGBITS, 0); Context.getELFSection(".AMDGPU.config", ELF::SHT_PROGBITS, 0);
OutStreamer->SwitchSection(ConfigSection); OutStreamer->SwitchSection(ConfigSection);
}
const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
SIProgramInfo KernelInfo; SIProgramInfo KernelInfo;
if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) { if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
getSIProgramInfo(KernelInfo, MF); getSIProgramInfo(KernelInfo, MF);
if (!STM.isAmdHsaOS()) { if (!STM.isAmdHsaOS()) {
EmitProgramInfoSI(MF, KernelInfo); EmitProgramInfoSI(MF, KernelInfo);
} }
} else { } else {
EmitProgramInfoR600(MF); EmitProgramInfoR600(MF);
▲ Show 20 Lines • Show All 634 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/AMDGPU/hsa-func.ll

Show All 24 Lines
; ELF: 0040: 50550000 ; ELF: 0040: 50550000
; ELF: Symbol { ; ELF: Symbol {
; ELF: Name: simple ; ELF: Name: simple
; ELF: Size: 288 ; ELF: Size: 288
; ELF: Type: Function (0x2) ; ELF: Type: Function (0x2)
; ELF: } ; ELF: }
; HSA: .text
; HSA: .hsa_code_object_version 2,1 ; HSA: .hsa_code_object_version 2,1
; HSA-CI: .hsa_code_object_isa 7,0,0,"AMD","AMDGPU" ; HSA-CI: .hsa_code_object_isa 7,0,0,"AMD","AMDGPU"
; HSA-VI: .hsa_code_object_isa 8,0,1,"AMD","AMDGPU" ; HSA-VI: .hsa_code_object_isa 8,0,1,"AMD","AMDGPU"
; HSA: .text
; HSA-NOT: .amdgpu_hsa_kernel simple ; HSA-NOT: .amdgpu_hsa_kernel simple
; HSA: {{^}}simple: ; HSA: {{^}}simple:
; HSA: .amd_kernel_code_t ; HSA: .amd_kernel_code_t
; HSA: enable_sgpr_private_segment_buffer = 1 ; HSA: enable_sgpr_private_segment_buffer = 1
; HSA: enable_sgpr_kernarg_segment_ptr = 1 ; HSA: enable_sgpr_kernarg_segment_ptr = 1
; HSA: .end_amd_kernel_code_t ; HSA: .end_amd_kernel_code_t
; HSA: s_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x0 ; HSA: s_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x0
Show All 15 Lines

llvm/trunk/test/CodeGen/AMDGPU/hsa.ll

Show All 28 Lines
; ELF: ) ; ELF: )
; ELF: Symbol { ; ELF: Symbol {
; ELF: Name: simple ; ELF: Name: simple
; ELF: Size: 288 ; ELF: Size: 288
; ELF: Type: AMDGPU_HSA_KERNEL (0xA) ; ELF: Type: AMDGPU_HSA_KERNEL (0xA)
; ELF: } ; ELF: }
; HSA-NOT: .AMDGPU.config
; HSA: .text
; HSA: .hsa_code_object_version 2,1 ; HSA: .hsa_code_object_version 2,1
; HSA-CI: .hsa_code_object_isa 7,0,0,"AMD","AMDGPU" ; HSA-CI: .hsa_code_object_isa 7,0,0,"AMD","AMDGPU"
; HSA-VI: .hsa_code_object_isa 8,0,1,"AMD","AMDGPU" ; HSA-VI: .hsa_code_object_isa 8,0,1,"AMD","AMDGPU"
; HSA: .text
; HSA: .amdgpu_hsa_kernel simple ; HSA: .amdgpu_hsa_kernel simple
; HSA: {{^}}simple: ; HSA: {{^}}simple:
; HSA: .amd_kernel_code_t ; HSA: .amd_kernel_code_t
; HSA: enable_sgpr_private_segment_buffer = 1 ; HSA: enable_sgpr_private_segment_buffer = 1
; HSA: enable_sgpr_kernarg_segment_ptr = 1 ; HSA: enable_sgpr_kernarg_segment_ptr = 1
; HSA: .end_amd_kernel_code_t ; HSA: .end_amd_kernel_code_t
; HSA: s_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x0 ; HSA: s_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x0
Show All 15 Lines