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Differential D27708

AMDGPU: Fix name for v_ashrrev_i16
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Authored by arsenm on Dec 13 2016, 2:44 AM.

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• tstellarAMD

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arsenm updated this revision to Diff 81206.Dec 13 2016, 2:44 AM
arsenm retitled this revision from to AMDGPU: Fix name for v_ashrrev_i16.
arsenm updated this object.
arsenm added a subscriber: llvm-commits.
Herald added a reviewer: • tstellarAMD. · View Herald TranscriptDec 13 2016, 2:44 AM
Herald added subscribers: tony-tye, yaxunl, nhaehnle and 2 others. · View Herald Transcript
• tstellarAMD accepted this revision.Dec 15 2016, 5:08 PM
• tstellarAMD edited edge metadata.

LGTM.

This revision is now accepted and ready to land.Dec 15 2016, 5:08 PM
arsenm closed this revision.Dec 16 2016, 9:50 AM

r289967

Revision Contents

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lib/
Target/
AMDGPU/
6 lines
test/
MC/
AMDGPU/
6 lines
6 lines
4 lines
Disassembler/
AMDGPU/
2 lines
2 lines

Diff 81206

lib/Target/AMDGPU/VOP2Instructions.td

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} // End let SubtargetPredicate = SICI } // End let SubtargetPredicate = SICI
let SubtargetPredicate = isVI in { let SubtargetPredicate = isVI in {
def V_MADMK_F16 : VOP2_Pseudo <"v_madmk_f16", VOP_MADMK_F16>; def V_MADMK_F16 : VOP2_Pseudo <"v_madmk_f16", VOP_MADMK_F16>;
defm V_LSHLREV_B16 : VOP2Inst <"v_lshlrev_b16", VOP_I16_I16_I16>; defm V_LSHLREV_B16 : VOP2Inst <"v_lshlrev_b16", VOP_I16_I16_I16>;
defm V_LSHRREV_B16 : VOP2Inst <"v_lshrrev_b16", VOP_I16_I16_I16>; defm V_LSHRREV_B16 : VOP2Inst <"v_lshrrev_b16", VOP_I16_I16_I16>;
defm V_ASHRREV_B16 : VOP2Inst <"v_ashrrev_b16", VOP_I16_I16_I16>; defm V_ASHRREV_I16 : VOP2Inst <"v_ashrrev_i16", VOP_I16_I16_I16>;
defm V_LDEXP_F16 : VOP2Inst <"v_ldexp_f16", VOP_F16_F16_I32, AMDGPUldexp>; defm V_LDEXP_F16 : VOP2Inst <"v_ldexp_f16", VOP_F16_F16_I32, AMDGPUldexp>;
let isCommutable = 1 in { let isCommutable = 1 in {
defm V_ADD_F16 : VOP2Inst <"v_add_f16", VOP_F16_F16_F16, fadd>; defm V_ADD_F16 : VOP2Inst <"v_add_f16", VOP_F16_F16_F16, fadd>;
defm V_SUB_F16 : VOP2Inst <"v_sub_f16", VOP_F16_F16_F16, fsub>; defm V_SUB_F16 : VOP2Inst <"v_sub_f16", VOP_F16_F16_F16, fsub>;
defm V_SUBREV_F16 : VOP2Inst <"v_subrev_f16", VOP_F16_F16_F16, null_frag, "v_sub_f16">; defm V_SUBREV_F16 : VOP2Inst <"v_subrev_f16", VOP_F16_F16_F16, null_frag, "v_sub_f16">;
defm V_MUL_F16 : VOP2Inst <"v_mul_f16", VOP_F16_F16_F16, fmul>; defm V_MUL_F16 : VOP2Inst <"v_mul_f16", VOP_F16_F16_F16, fmul>;
def V_MADAK_F16 : VOP2_Pseudo <"v_madak_f16", VOP_MADAK_F16>; def V_MADAK_F16 : VOP2_Pseudo <"v_madak_f16", VOP_MADAK_F16>;
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def : Pat < def : Pat <
(xor i16:$src0, i16:$src1), (xor i16:$src0, i16:$src1),
(V_XOR_B32_e64 $src0, $src1) (V_XOR_B32_e64 $src0, $src1)
>; >;
defm : Bits_OpsRev_i16_Pats<shl, V_LSHLREV_B16_e32>; defm : Bits_OpsRev_i16_Pats<shl, V_LSHLREV_B16_e32>;
defm : Bits_OpsRev_i16_Pats<srl, V_LSHRREV_B16_e32>; defm : Bits_OpsRev_i16_Pats<srl, V_LSHRREV_B16_e32>;
defm : Bits_OpsRev_i16_Pats<sra, V_ASHRREV_B16_e32>; defm : Bits_OpsRev_i16_Pats<sra, V_ASHRREV_I16_e32>;
def : ZExt_i16_i1_Pat<zext>; def : ZExt_i16_i1_Pat<zext>;
def : ZExt_i16_i1_Pat<anyext>; def : ZExt_i16_i1_Pat<anyext>;
def : Pat < def : Pat <
(i16 (sext i1:$src)), (i16 (sext i1:$src)),
(V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src) (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src)
>; >;
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defm V_MADMK_F16 : VOP2_Real_MADK_vi <0x24>; defm V_MADMK_F16 : VOP2_Real_MADK_vi <0x24>;
defm V_MADAK_F16 : VOP2_Real_MADK_vi <0x25>; defm V_MADAK_F16 : VOP2_Real_MADK_vi <0x25>;
defm V_ADD_U16 : VOP2_Real_e32e64_vi <0x26>; defm V_ADD_U16 : VOP2_Real_e32e64_vi <0x26>;
defm V_SUB_U16 : VOP2_Real_e32e64_vi <0x27>; defm V_SUB_U16 : VOP2_Real_e32e64_vi <0x27>;
defm V_SUBREV_U16 : VOP2_Real_e32e64_vi <0x28>; defm V_SUBREV_U16 : VOP2_Real_e32e64_vi <0x28>;
defm V_MUL_LO_U16 : VOP2_Real_e32e64_vi <0x29>; defm V_MUL_LO_U16 : VOP2_Real_e32e64_vi <0x29>;
defm V_LSHLREV_B16 : VOP2_Real_e32e64_vi <0x2a>; defm V_LSHLREV_B16 : VOP2_Real_e32e64_vi <0x2a>;
defm V_LSHRREV_B16 : VOP2_Real_e32e64_vi <0x2b>; defm V_LSHRREV_B16 : VOP2_Real_e32e64_vi <0x2b>;
defm V_ASHRREV_B16 : VOP2_Real_e32e64_vi <0x2c>; defm V_ASHRREV_I16 : VOP2_Real_e32e64_vi <0x2c>;
defm V_MAX_F16 : VOP2_Real_e32e64_vi <0x2d>; defm V_MAX_F16 : VOP2_Real_e32e64_vi <0x2d>;
defm V_MIN_F16 : VOP2_Real_e32e64_vi <0x2e>; defm V_MIN_F16 : VOP2_Real_e32e64_vi <0x2e>;
defm V_MAX_U16 : VOP2_Real_e32e64_vi <0x2f>; defm V_MAX_U16 : VOP2_Real_e32e64_vi <0x2f>;
defm V_MAX_I16 : VOP2_Real_e32e64_vi <0x30>; defm V_MAX_I16 : VOP2_Real_e32e64_vi <0x30>;
defm V_MIN_U16 : VOP2_Real_e32e64_vi <0x31>; defm V_MIN_U16 : VOP2_Real_e32e64_vi <0x31>;
defm V_MIN_I16 : VOP2_Real_e32e64_vi <0x32>; defm V_MIN_I16 : VOP2_Real_e32e64_vi <0x32>;
defm V_LDEXP_F16 : VOP2_Real_e32e64_vi <0x33>; defm V_LDEXP_F16 : VOP2_Real_e32e64_vi <0x33>;
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test/MC/AMDGPU/vop2.s

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v_lshlrev_b16_e32 v1, v2, v3 v_lshlrev_b16_e32 v1, v2, v3
// NOSICI: error: instruction not supported on this GPU // NOSICI: error: instruction not supported on this GPU
// NOSICI: v_lshrrev_b16_e32 v1, v2, v3 // NOSICI: v_lshrrev_b16_e32 v1, v2, v3
// VI: v_lshrrev_b16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x56] // VI: v_lshrrev_b16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x56]
v_lshrrev_b16_e32 v1, v2, v3 v_lshrrev_b16_e32 v1, v2, v3
// NOSICI: error: instruction not supported on this GPU // NOSICI: error: instruction not supported on this GPU
// NOSICI: v_ashrrev_b16_e32 v1, v2, v3 // NOSICI: v_ashrrev_i16_e32 v1, v2, v3
// VI: v_ashrrev_b16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x58] // VI: v_ashrrev_i16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x58]
v_ashrrev_b16_e32 v1, v2, v3 v_ashrrev_i16_e32 v1, v2, v3
// NOSICI: error: instruction not supported on this GPU // NOSICI: error: instruction not supported on this GPU
// NOSICI: v_max_f16_e32 v1, v2, v3 // NOSICI: v_max_f16_e32 v1, v2, v3
// VI: v_max_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5a] // VI: v_max_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5a]
v_max_f16_e32 v1, v2, v3 v_max_f16_e32 v1, v2, v3
// NOSICI: error: instruction not supported on this GPU // NOSICI: error: instruction not supported on this GPU
// NOSICI: v_min_f16_e32 v1, v2, v3 // NOSICI: v_min_f16_e32 v1, v2, v3
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test/MC/AMDGPU/vop3-convert.s

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v_lshlrev_b16 v1, v2, v3 v_lshlrev_b16 v1, v2, v3
// NOSICI: error: instruction not supported on this GPU // NOSICI: error: instruction not supported on this GPU
// NOSICI: v_lshrrev_b16 v1, v2, v3 // NOSICI: v_lshrrev_b16 v1, v2, v3
// VI: v_lshrrev_b16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x56] // VI: v_lshrrev_b16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x56]
v_lshrrev_b16 v1, v2, v3 v_lshrrev_b16 v1, v2, v3
// NOSICI: error: instruction not supported on this GPU // NOSICI: error: instruction not supported on this GPU
// NOSICI: v_ashrrev_b16 v1, v2, v3 // NOSICI: v_ashrrev_i16 v1, v2, v3
// VI: v_ashrrev_b16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x58] // VI: v_ashrrev_i16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x58]
v_ashrrev_b16 v1, v2, v3 v_ashrrev_i16 v1, v2, v3
// NOSICI: error: instruction not supported on this GPU // NOSICI: error: instruction not supported on this GPU
// NOSICI: v_max_f16 v1, v2, v3 // NOSICI: v_max_f16 v1, v2, v3
// VI: v_max_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5a] // VI: v_max_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5a]
v_max_f16 v1, v2, v3 v_max_f16 v1, v2, v3
// NOSICI: error: instruction not supported on this GPU // NOSICI: error: instruction not supported on this GPU
// NOSICI: v_min_f16 v1, v2, v3 // NOSICI: v_min_f16 v1, v2, v3
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test/MC/AMDGPU/vop_sdwa.s

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// VI: v_lshlrev_b16_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x54,0x02,0x06,0x05,0x02] // VI: v_lshlrev_b16_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x54,0x02,0x06,0x05,0x02]
v_lshlrev_b16 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 v_lshlrev_b16 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
// NOSICI: error: // NOSICI: error:
// VI: v_lshrrev_b16_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x56,0x02,0x06,0x05,0x02] // VI: v_lshrrev_b16_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x56,0x02,0x06,0x05,0x02]
v_lshrrev_b16 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 v_lshrrev_b16 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
// NOSICI: error: // NOSICI: error:
// VI: v_ashrrev_b16_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x58,0x02,0x06,0x05,0x02] // VI: v_ashrrev_i16_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x58,0x02,0x06,0x05,0x02]
v_ashrrev_b16 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 v_ashrrev_i16 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
// NOSICI: error: // NOSICI: error:
// VI: v_max_f16_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x5a,0x02,0x06,0x05,0x02] // VI: v_max_f16_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x5a,0x02,0x06,0x05,0x02]
v_max_f16 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 v_max_f16 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
// NOSICI: error: // NOSICI: error:
// VI: v_min_f16_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x5c,0x02,0x06,0x05,0x02] // VI: v_min_f16_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x5c,0x02,0x06,0x05,0x02]
v_min_f16 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 v_min_f16 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
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test/MC/Disassembler/AMDGPU/sdwa_vi.txt

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0xf9 0x06 0x02 0x52 0x02 0x06 0x05 0x02 0xf9 0x06 0x02 0x52 0x02 0x06 0x05 0x02
# VI: v_lshlrev_b16_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x54,0x02,0x06,0x05,0x02] # VI: v_lshlrev_b16_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x54,0x02,0x06,0x05,0x02]
0xf9 0x06 0x02 0x54 0x02 0x06 0x05 0x02 0xf9 0x06 0x02 0x54 0x02 0x06 0x05 0x02
# VI: v_lshrrev_b16_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x56,0x02,0x06,0x05,0x02] # VI: v_lshrrev_b16_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x56,0x02,0x06,0x05,0x02]
0xf9 0x06 0x02 0x56 0x02 0x06 0x05 0x02 0xf9 0x06 0x02 0x56 0x02 0x06 0x05 0x02
# VI: v_ashrrev_b16_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x58,0x02,0x06,0x05,0x02] # VI: v_ashrrev_i16_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x58,0x02,0x06,0x05,0x02]
0xf9 0x06 0x02 0x58 0x02 0x06 0x05 0x02 0xf9 0x06 0x02 0x58 0x02 0x06 0x05 0x02
# VI: v_max_f16_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x5a,0x02,0x06,0x05,0x02] # VI: v_max_f16_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x5a,0x02,0x06,0x05,0x02]
0xf9 0x06 0x02 0x5a 0x02 0x06 0x05 0x02 0xf9 0x06 0x02 0x5a 0x02 0x06 0x05 0x02
# VI: v_min_f16_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x5c,0x02,0x06,0x05,0x02] # VI: v_min_f16_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x5c,0x02,0x06,0x05,0x02]
0xf9 0x06 0x02 0x5c 0x02 0x06 0x05 0x02 0xf9 0x06 0x02 0x5c 0x02 0x06 0x05 0x02
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test/MC/Disassembler/AMDGPU/vop2_vi.txt

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0x02 0x07 0x02 0x52 0x02 0x07 0x02 0x52
# VI: v_lshlrev_b16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x54] # VI: v_lshlrev_b16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x54]
0x02 0x07 0x02 0x54 0x02 0x07 0x02 0x54
# VI: v_lshrrev_b16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x56] # VI: v_lshrrev_b16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x56]
0x02 0x07 0x02 0x56 0x02 0x07 0x02 0x56
# VI: v_ashrrev_b16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x58] # VI: v_ashrrev_i16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x58]
0x02 0x07 0x02 0x58 0x02 0x07 0x02 0x58
# VI: v_max_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5a] # VI: v_max_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5a]
0x02 0x07 0x02 0x5a 0x02 0x07 0x02 0x5a
# VI: v_min_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5c] # VI: v_min_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5c]
0x02 0x07 0x02 0x5c 0x02 0x07 0x02 0x5c
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