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[ARM] Add ARMISD::VLD1DUP to match vld1_dup more consistently
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Authored by efriedma on Dec 12 2016, 6:02 PM.

Details

Summary

Currently, there are substantial problems forming vld1_dup even if the
VDUP survives legalization. The lack of an actual node
leads to terrible results: not only can we not form post-increment vld1_dup
instructions, but we form scalar pre-increment and post-increment
loads which force the loaded value into a GPR. This patch fixes that
by combining the vdup+load into an ARMISD node before DAGCombine
messes it up.

Also includes a crash fix for vld2_dup (see testcase @vld2dupi8_postinc_variable).

Not sure who to ask to review this...

Diff Detail

Repository
rL LLVM

Event Timeline

efriedma updated this revision to Diff 81168.Dec 12 2016, 6:02 PM
efriedma retitled this revision from to [ARM] Add ARMISD::VLD1DUP to match vld1_dup more consistently.
efriedma updated this object.
efriedma added reviewers: t.p.northover, jmolloy.
efriedma set the repository for this revision to rL LLVM.
efriedma updated this revision to Diff 81296.Dec 13 2016, 1:54 PM

Minor change I forgot to include in the diff.

rengolin accepted this revision.Dec 14 2016, 2:41 AM
rengolin added a reviewer: rengolin.

Hi Eli,

Nice patch! I only have a few nits inline, but LGTM. Thanks!

--renato

lib/Target/ARM/ARMISelLowering.cpp
10697 ↗(On Diff #81296)

Maybe adding a one-line comment as to which pattern you want to combine here, as it isn't obvious.

test/CodeGen/ARM/vlddup.ll
177 ↗(On Diff #81296)

nit: clean up the "sroa" names to make it slightly more readable.

This revision is now accepted and ready to land.Dec 14 2016, 2:41 AM
This revision was automatically updated to reflect the committed changes.
efriedma reopened this revision.Dec 16 2016, 10:42 AM

Reverted in 289923.

This revision is now accepted and ready to land.Dec 16 2016, 10:42 AM
This revision was automatically updated to reflect the committed changes.