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[X86][SSE] Lower suitably sign-extended mul vXi64 using PMULDQ
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Authored by RKSimon on Dec 10 2016, 3:51 PM.

Details

Summary

PMULDQ returns the 64-bit result of the signed multiplication of the lower 32-bits of vXi64 vector inputs, we can lower with this if the sign bits stretch that far.

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Repository
rL LLVM

Event Timeline

RKSimon updated this revision to Diff 81009.Dec 10 2016, 3:51 PM
RKSimon retitled this revision from to [X86][SSE] Lower suitably sign-extended mul vXi64 using PMULDQ.
RKSimon updated this object.
RKSimon set the repository for this revision to rL LLVM.
RKSimon added a subscriber: llvm-commits.
RKSimon updated this revision to Diff 81011.Dec 10 2016, 5:13 PM

Improved AVX1 support by adding EXTRACT_SUBVECTOR support to ComputeNumSignBits

craig.topper added inline comments.Dec 11 2016, 12:03 AM
test/CodeGen/X86/vector-compare-results.ll
1884

This change seems unrelated to the multiply changes. Was it caused by the computeSignBits changes handling for extract subvector?

RKSimon added inline comments.Dec 11 2016, 3:00 AM
test/CodeGen/X86/vector-compare-results.ll
1884

Yes it's down to adding EXTRACT_SUBVECTOR support to computeSignBits

RKSimon added inline comments.Dec 11 2016, 10:19 AM
test/CodeGen/X86/vector-compare-results.ll
1884

Should I commit the EXTRACT_SUBVECTOR support first to split the diffs?

craig.topper accepted this revision.Dec 11 2016, 2:15 PM
craig.topper edited edge metadata.

LGTM. I'll let you decide whether to split it or not.

This revision is now accepted and ready to land.Dec 11 2016, 2:15 PM
This revision was automatically updated to reflect the committed changes.