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AMDGPU: Fix isTypeDesirableForOp for i16
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Authored by arsenm on Dec 8 2016, 4:49 PM.

Reviewers

• tstellarAMD

Summary

This should do nothing for targets without i16.

arsenm retitled this revision from to AMDGPU: Fix isTypeDesirableForOp for i16.

arsenm updated this object.

arsenm added a subscriber: llvm-commits.

LGTM.

This revision is now accepted and ready to land.Dec 9 2016, 8:08 AM

r289235

Path

Size

lib/

Target/

AMDGPU/

20 lines

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	bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,			bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
	Type *Ty) const {			Type *Ty) const {
	// FIXME: Could be smarter if called for vector constants.			// FIXME: Could be smarter if called for vector constants.
	return true;			return true;
	}			}

	bool SITargetLowering::isTypeDesirableForOp(unsigned Op, EVT VT) const {			bool SITargetLowering::isTypeDesirableForOp(unsigned Op, EVT VT) const {
				if (Subtarget->has16BitInsts() && VT == MVT::i16) {
				switch (Op) {
				case ISD::LOAD:
				case ISD::STORE:

	// i16 is not desirable unless it is a load or a store.			// These operations are done with 32-bit instructions anyway.
	if (VT == MVT::i16 && Op != ISD::LOAD && Op != ISD::STORE)			case ISD::AND:
				case ISD::OR:
				case ISD::XOR:
				case ISD::SELECT:
				// TODO: Extensions?
				return true;
				default:
	return false;			return false;
				}
				}

	// SimplifySetCC uses this function to determine whether or not it should			// SimplifySetCC uses this function to determine whether or not it should
	// create setcc with i1 operands. We don't have instructions for i1 setcc.			// create setcc with i1 operands. We don't have instructions for i1 setcc.
	if (VT == MVT::i1 && Op == ISD::SETCC)			if (VT == MVT::i1 && Op == ISD::SETCC)
	return false;			return false;

	return TargetLowering::isTypeDesirableForOp(Op, VT);			return TargetLowering::isTypeDesirableForOp(Op, VT);
	}			}
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