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Differential D27379

AMDGPU: Fix crash on i16 constant expression
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Authored by arsenm on Dec 2 2016, 6:16 PM.

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• tstellarAMD

Diff Detail

Event Timeline

arsenm updated this revision to Diff 80164.Dec 2 2016, 6:16 PM
arsenm retitled this revision from to AMDGPU: Fix crash on i16 constant expression.
arsenm updated this object.
arsenm added a subscriber: llvm-commits.
Herald added a reviewer: • tstellarAMD. · View Herald TranscriptDec 2 2016, 6:16 PM
Herald added subscribers: tony-tye, yaxunl, nhaehnle and 2 others. · View Herald Transcript
• tstellarAMD accepted this revision.Dec 6 2016, 3:21 PM
• tstellarAMD edited edge metadata.

LGTM.

This revision is now accepted and ready to land.Dec 6 2016, 3:21 PM
arsenm closed this revision.Dec 6 2016, 3:28 PM

r288861

Revision Contents

PathSize
lib/
Target/
AMDGPU/
5 lines
test/
CodeGen/
AMDGPU/
28 lines

Diff 80164

lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp

Show First 20 Lines • Show All 140 Lines • ▼ Show 20 Lines void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.setPreservesAll(); AU.setPreservesAll();
} }
}; };
} // End anonymous namespace } // End anonymous namespace
Value *AMDGPUCodeGenPrepare::copyFlags( Value *AMDGPUCodeGenPrepare::copyFlags(
const BinaryOperator &I, Value *V) const { const BinaryOperator &I, Value *V) const {
assert(isa<BinaryOperator>(V) && "V must be binary operation"); BinaryOperator *BinOp = dyn_cast<BinaryOperator>(V);
if (!BinOp) // Possibly constant expression.
return V;
BinaryOperator *BinOp = cast<BinaryOperator>(V);
if (isa<OverflowingBinaryOperator>(BinOp)) { if (isa<OverflowingBinaryOperator>(BinOp)) {
BinOp->setHasNoSignedWrap(I.hasNoSignedWrap()); BinOp->setHasNoSignedWrap(I.hasNoSignedWrap());
BinOp->setHasNoUnsignedWrap(I.hasNoUnsignedWrap()); BinOp->setHasNoUnsignedWrap(I.hasNoUnsignedWrap());
} else if (isa<PossiblyExactOperator>(BinOp)) } else if (isa<PossiblyExactOperator>(BinOp))
BinOp->setIsExact(I.isExact()); BinOp->setIsExact(I.isExact());
return V; return V;
} }
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test/CodeGen/AMDGPU/amdgpu-codegenprepare-i16-to-i32.ll

Show First 20 Lines • Show All 527 Lines • ▼ Show 20 Lines
; VI-NEXT: %[[R_32:[0-9]+]] = add i32 %[[A_32]], %[[B_32]] ; VI-NEXT: %[[R_32:[0-9]+]] = add i32 %[[A_32]], %[[B_32]]
; VI-NEXT: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16 ; VI-NEXT: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16
; VI-NEXT: ret i16 %[[R_16]] ; VI-NEXT: ret i16 %[[R_16]]
define i16 @add_i16(i16 %a, i16 %b) { define i16 @add_i16(i16 %a, i16 %b) {
%r = add i16 %a, %b %r = add i16 %a, %b
ret i16 %r ret i16 %r
} }
; GCN-LABEL: @constant_add_i16(
; VI: ret i16 3
define i16 @constant_add_i16() {
%r = add i16 1, 2
ret i16 %r
}
; GCN-LABEL: @constant_add_nsw_i16(
; VI: ret i16 3
define i16 @constant_add_nsw_i16() {
%r = add nsw i16 1, 2
ret i16 %r
}
; GCN-LABEL: @constant_add_nuw_i16(
; VI: ret i16 3
define i16 @constant_add_nuw_i16() {
%r = add nsw i16 1, 2
ret i16 %r
}
; GCN-LABEL: @add_nsw_i16( ; GCN-LABEL: @add_nsw_i16(
; SI: %r = add nsw i16 %a, %b ; SI: %r = add nsw i16 %a, %b
; SI-NEXT: ret i16 %r ; SI-NEXT: ret i16 %r
; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32 ; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32
; VI-NEXT: %[[B_32:[0-9]+]] = zext i16 %b to i32 ; VI-NEXT: %[[B_32:[0-9]+]] = zext i16 %b to i32
; VI-NEXT: %[[R_32:[0-9]+]] = add nsw i32 %[[A_32]], %[[B_32]] ; VI-NEXT: %[[R_32:[0-9]+]] = add nsw i32 %[[A_32]], %[[B_32]]
; VI-NEXT: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16 ; VI-NEXT: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16
; VI-NEXT: ret i16 %[[R_16]] ; VI-NEXT: ret i16 %[[R_16]]
▲ Show 20 Lines • Show All 257 Lines • ▼ Show 20 Lines
; VI-NEXT: %[[R_32:[0-9]+]] = ashr exact i32 %[[A_32]], %[[B_32]] ; VI-NEXT: %[[R_32:[0-9]+]] = ashr exact i32 %[[A_32]], %[[B_32]]
; VI-NEXT: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16 ; VI-NEXT: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16
; VI-NEXT: ret i16 %[[R_16]] ; VI-NEXT: ret i16 %[[R_16]]
define i16 @ashr_exact_i16(i16 %a, i16 %b) { define i16 @ashr_exact_i16(i16 %a, i16 %b) {
%r = ashr exact i16 %a, %b %r = ashr exact i16 %a, %b
ret i16 %r ret i16 %r
} }
; GCN-LABEL: @constant_lshr_exact_i16(
; VI: ret i16 2
define i16 @constant_lshr_exact_i16(i16 %a, i16 %b) {
%r = lshr exact i16 4, 1
ret i16 %r
}
; GCN-LABEL: @and_i16( ; GCN-LABEL: @and_i16(
; SI: %r = and i16 %a, %b ; SI: %r = and i16 %a, %b
; SI-NEXT: ret i16 %r ; SI-NEXT: ret i16 %r
; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32 ; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32
; VI-NEXT: %[[B_32:[0-9]+]] = zext i16 %b to i32 ; VI-NEXT: %[[B_32:[0-9]+]] = zext i16 %b to i32
; VI-NEXT: %[[R_32:[0-9]+]] = and i32 %[[A_32]], %[[B_32]] ; VI-NEXT: %[[R_32:[0-9]+]] = and i32 %[[A_32]], %[[B_32]]
; VI-NEXT: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16 ; VI-NEXT: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16
; VI-NEXT: ret i16 %[[R_16]] ; VI-NEXT: ret i16 %[[R_16]]
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