[PPC] Prefer direct move on power8 if load 1 or 2 bytes to VSR

[Carrot]

Summary

This patch fixes pr31144.

Power8 has MTVSRWZ but no LXSIBZX/LXSIHZX, so move 1 or 2 bytes to VSR through MTVSRWZ is much faster than store the extended value into stack and load it with LXSIWZX.

[nemanjai]

lib/Target/PowerPC/PPCISelLowering.cpp

6617 ↗

(On Diff #79836)

This is really a property of the ISA rather than the actual CPU. I think a better way of accomplishing this would be to check that the subtarget does not have "hasP9Vector()" because that's where the LXSIBZX/LXSIHZX become available. Even if that means this has to become a member function then.

[syzaara]

Looks good in terms of coding standards.

[Carrot]

ping

[nemanjai]

Other than the inline comment, I think this patch is fine but I'll let Hal have a look for the official stamp of approval.

test/CodeGen/PowerPC/pr31144.ll

14 ↗

(On Diff #79991)

This will just check that you don't have an LXSIWZX after the move. I think you don't want this instruction emitted in this test case at all. So it's probably better to use --implicit-check-not in the FileCheck invocation.

[hfinkel]

In D27287#619628, @nemanjai wrote:

Other than the inline comment, I think this patch is fine but I'll let Hal have a look for the official stamp of approval.

In that case, fine by me too.

llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h

bool canReuseLoadAddress(SDValue Op, EVT MemVT, ReuseLoadInfo &RLI,
                              ISD::LoadExtType ET = ISD::NON_EXTLOAD) const;
     void spliceIntoChain(SDValue ResChain, SDValue NewResChain,
                          SelectionDAG &DAG) const;
 
     void LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
                                 SelectionDAG &DAG, const SDLoc &dl) const;
     SDValue LowerFP_TO_INTDirectMove(SDValue Op, SelectionDAG &DAG,
                                      const SDLoc &dl) const;
+
+    bool directMoveIsProfitable(const SDValue &Op) const;
     SDValue LowerINT_TO_FPDirectMove(SDValue Op, SelectionDAG &DAG,
                                      const SDLoc &dl) const;
 
     SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
     SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
 
     bool
     IsEligibleForTailCallOptimization(SDValue Callee,

llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp

void PPCTargetLowering::spliceIntoChain(SDValue ResChain,
 
   DAG.ReplaceAllUsesOfValueWith(ResChain, TF);
   DAG.UpdateNodeOperands(TF.getNode(), ResChain, NewResChain);
 }
 
 /// \brief Analyze profitability of direct move
 /// prefer float load to int load plus direct move
 /// when there is no integer use of int load
-static bool directMoveIsProfitable(const SDValue &Op) {
+bool PPCTargetLowering::directMoveIsProfitable(const SDValue &Op) const {
   SDNode *Origin = Op.getOperand(0).getNode();
   if (Origin->getOpcode() != ISD::LOAD)
     return true;
 
+  // If there is no LXSIBZX/LXSIHZX, like Power8,
+  // prefer direct move if the memory size is 1 or 2 bytes.
+  MachineMemOperand *MMO = cast<LoadSDNode>(Origin)->getMemOperand();
+  if (!Subtarget.hasP9Vector() && MMO->getSize() <= 2)
+    return true;
+
   for (SDNode::use_iterator UI = Origin->use_begin(),
                             UE = Origin->use_end();
        UI != UE; ++UI) {
 
     // Only look at the users of the loaded value.
     if (UI.getUse().get().getResNo() != 0)
       continue;
 

llvm/trunk/test/CodeGen/PowerPC/pr31144.ll

+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=+vsx < %s | FileCheck %s --implicit-check-not lxsiwzx
+
+declare void @bar(double)
+
+define void @foo1(i8* %p) {
+entry:
+  %0 = load i8, i8* %p, align 1
+  %conv = uitofp i8 %0 to double
+  call void @bar(double %conv)
+  ret void
+
+; CHECK-LABEL: @foo1
+; CHECK:     mtvsrwz
+}
+
+define void @foo2(i16* %p) {
+entry:
+  %0 = load i16, i16* %p, align 2
+  %conv = uitofp i16 %0 to double
+  call void @bar(double %conv)
+  ret void
+
+; CHECK-LABEL: @foo2
+; CHECK:       mtvsrwz
+}
+