MCStreamer: Use "cfi" for CFI related temp labels.

[MatzeB]

Summary

Choosing a "cfi" instead of the default "tmp" makes the intend clearer in an assembly dump.
More importantly: The dumps are more stable. The temp label numbers don't move around anymore when unrelated code calls
createTempSymbol() more or less often.

Temp labels names do not influence the generated object code (just the assembly output).

This is part of an effort to productize machine module passes. The goal here is to have llvm codegen produce the same output with/without a dummy machine module pass inserted into the pipeline.

[MatzeB]

Add some more reviewers knowing debug/exception/call frame info.

[aprantl]

Seems reasonable. Does the label name have any effect outside of textual assembler?

[MatzeB]

In D27244#609906, @aprantl wrote:

Seems reasonable. Does the label name have any effect outside of textual assembler?

Nope, the generated object files are the same.

[rnk]

Why do we need to print labels for CFI at all? The labels generally aren't referenced anywhere, and they only pollute the assembly output. The assembler creates internal labels when processing .cfi_* and .seh_* directives.

[MatzeB]

In D27244#609914, @rnk wrote:

Why do we need to print labels for CFI at all? The labels generally aren't referenced anywhere, and they only pollute the assembly output. The assembler creates internal labels when processing .cfi_* and .seh_* directives.

The labels do get stored in some CurFrame/WinFrameInfo object thingies. So I assume they get used at least in some circumstances. But it would indeed be really nice to not output them if they are unused. If the assembler does something for you even better, but is that also true in the case where we stream to an object file immediately instead of the assembler?

Anyway I don't know much about these parts of the code and go with the easy renaming to "cfi" for now. I'd love to see someone removing the unnecessary labels of course ;-)

[aprantl]

If nobody else objects :-)

include/llvm/MC/MCStreamer.h

class MCStreamer {
 
   MCStreamer(const MCStreamer &) = delete;
   MCStreamer &operator=(const MCStreamer &) = delete;
 
   std::vector<MCDwarfFrameInfo> DwarfFrameInfos;
   MCDwarfFrameInfo *getCurrentDwarfFrameInfo();
   void EnsureValidDwarfFrame();
 
+  MCSymbol *EmitCFILabel();
   MCSymbol *EmitCFICommon();
 
   std::vector<WinEH::FrameInfo *> WinFrameInfos;
   WinEH::FrameInfo *CurrentWinFrameInfo;
   void EnsureValidWinFrameInfo();
 
   /// \brief Tracks an index to represent the order a symbol was emitted in.
   /// Zero means we did not emit that symbol.

lib/MC/MCStreamer.cpp

 }
 
 void MCStreamer::EmitCFIEndProcImpl(MCDwarfFrameInfo &Frame) {
   // Put a dummy non-null value in Frame.End to mark that this frame has been
   // closed.
   Frame.End = (MCSymbol *) 1;
 }
 
-MCSymbol *MCStreamer::EmitCFICommon() {
-  EnsureValidDwarfFrame();
-  MCSymbol *Label = getContext().createTempSymbol();
+MCSymbol *MCStreamer::EmitCFILabel() {
+  MCSymbol *Label = getContext().createTempSymbol("cfi", true);
   EmitLabel(Label);
   return Label;
 }
 
+MCSymbol *MCStreamer::EmitCFICommon() {
+  EnsureValidDwarfFrame();
+  return EmitCFILabel();
+}
+
 void MCStreamer::EmitCFIDefCfa(int64_t Register, int64_t Offset) {
   MCSymbol *Label = EmitCFICommon();
   MCCFIInstruction Instruction =
     MCCFIInstruction::createDefCfa(Label, Register, Offset);
   MCDwarfFrameInfo *CurFrame = getCurrentDwarfFrameInfo();
   CurFrame->Instructions.push_back(Instruction);
   CurFrame->CurrentCfaRegister = static_cast<unsigned>(Register);
 }

 
 void MCStreamer::EmitWinCFIStartProc(const MCSymbol *Symbol) {
   const MCAsmInfo *MAI = Context.getAsmInfo();
   if (!MAI->usesWindowsCFI())
     report_fatal_error(".seh_* directives are not supported on this target");
   if (CurrentWinFrameInfo && !CurrentWinFrameInfo->End)
     report_fatal_error("Starting a function before ending the previous one!");
 
-  MCSymbol *StartProc = getContext().createTempSymbol();
-  EmitLabel(StartProc);
+  MCSymbol *StartProc = EmitCFILabel();
 
   WinFrameInfos.push_back(new WinEH::FrameInfo(Symbol, StartProc));
   CurrentWinFrameInfo = WinFrameInfos.back();
   CurrentWinFrameInfo->TextSection = getCurrentSectionOnly();
 }
 
 void MCStreamer::EmitWinCFIEndProc() {
   EnsureValidWinFrameInfo();
   if (CurrentWinFrameInfo->ChainedParent)
     report_fatal_error("Not all chained regions terminated!");
 
-  MCSymbol *Label = getContext().createTempSymbol();
-  EmitLabel(Label);
+  MCSymbol *Label = EmitCFILabel();
   CurrentWinFrameInfo->End = Label;
 }
 
 void MCStreamer::EmitWinCFIStartChained() {
   EnsureValidWinFrameInfo();
 
-  MCSymbol *StartProc = getContext().createTempSymbol();
-  EmitLabel(StartProc);
+  MCSymbol *StartProc = EmitCFILabel();
 
   WinFrameInfos.push_back(new WinEH::FrameInfo(CurrentWinFrameInfo->Function,
                                                StartProc, CurrentWinFrameInfo));
   CurrentWinFrameInfo = WinFrameInfos.back();
   CurrentWinFrameInfo->TextSection = getCurrentSectionOnly();
 }
 
 void MCStreamer::EmitWinCFIEndChained() {
   EnsureValidWinFrameInfo();
   if (!CurrentWinFrameInfo->ChainedParent)
     report_fatal_error("End of a chained region outside a chained region!");
 
-  MCSymbol *Label = getContext().createTempSymbol();
-  EmitLabel(Label);
+  MCSymbol *Label = EmitCFILabel();
 
   CurrentWinFrameInfo->End = Label;
   CurrentWinFrameInfo =
       const_cast<WinEH::FrameInfo *>(CurrentWinFrameInfo->ChainedParent);
 }
 
 void MCStreamer::EmitWinEHHandler(const MCSymbol *Sym, bool Unwind,
                                   bool Except) {
return getWinCFISection(getContext(), &NextWinCFIID,
                           TextSec);
 }
 
 void MCStreamer::EmitSyntaxDirective() {}
 
 void MCStreamer::EmitWinCFIPushReg(unsigned Register) {
   EnsureValidWinFrameInfo();
 
-  MCSymbol *Label = getContext().createTempSymbol();
-  EmitLabel(Label);
+  MCSymbol *Label = EmitCFILabel();
 
   WinEH::Instruction Inst = Win64EH::Instruction::PushNonVol(Label, Register);
   CurrentWinFrameInfo->Instructions.push_back(Inst);
 }
 
 void MCStreamer::EmitWinCFISetFrame(unsigned Register, unsigned Offset) {
   EnsureValidWinFrameInfo();
   if (CurrentWinFrameInfo->LastFrameInst >= 0)
     report_fatal_error("Frame register and offset already specified!");
   if (Offset & 0x0F)
     report_fatal_error("Misaligned frame pointer offset!");
   if (Offset > 240)
     report_fatal_error("Frame offset must be less than or equal to 240!");
 
-  MCSymbol *Label = getContext().createTempSymbol();
-  EmitLabel(Label);
+  MCSymbol *Label = EmitCFILabel();
 
   WinEH::Instruction Inst =
       Win64EH::Instruction::SetFPReg(Label, Register, Offset);
   CurrentWinFrameInfo->LastFrameInst = CurrentWinFrameInfo->Instructions.size();
   CurrentWinFrameInfo->Instructions.push_back(Inst);
 }
 
 void MCStreamer::EmitWinCFIAllocStack(unsigned Size) {
   EnsureValidWinFrameInfo();
   if (Size == 0)
     report_fatal_error("Allocation size must be non-zero!");
   if (Size & 7)
     report_fatal_error("Misaligned stack allocation!");
 
-  MCSymbol *Label = getContext().createTempSymbol();
-  EmitLabel(Label);
+  MCSymbol *Label = EmitCFILabel();
 
   WinEH::Instruction Inst = Win64EH::Instruction::Alloc(Label, Size);
   CurrentWinFrameInfo->Instructions.push_back(Inst);
 }
 
 void MCStreamer::EmitWinCFISaveReg(unsigned Register, unsigned Offset) {
   EnsureValidWinFrameInfo();
   if (Offset & 7)
     report_fatal_error("Misaligned saved register offset!");
 
-  MCSymbol *Label = getContext().createTempSymbol();
-  EmitLabel(Label);
+  MCSymbol *Label = EmitCFILabel();
 
   WinEH::Instruction Inst =
       Win64EH::Instruction::SaveNonVol(Label, Register, Offset);
   CurrentWinFrameInfo->Instructions.push_back(Inst);
 }
 
 void MCStreamer::EmitWinCFISaveXMM(unsigned Register, unsigned Offset) {
   EnsureValidWinFrameInfo();
   if (Offset & 0x0F)
     report_fatal_error("Misaligned saved vector register offset!");
 
-  MCSymbol *Label = getContext().createTempSymbol();
-  EmitLabel(Label);
+  MCSymbol *Label = EmitCFILabel();
 
   WinEH::Instruction Inst =
       Win64EH::Instruction::SaveXMM(Label, Register, Offset);
   CurrentWinFrameInfo->Instructions.push_back(Inst);
 }
 
 void MCStreamer::EmitWinCFIPushFrame(bool Code) {
   EnsureValidWinFrameInfo();
   if (CurrentWinFrameInfo->Instructions.size() > 0)
     report_fatal_error("If present, PushMachFrame must be the first UOP");
 
-  MCSymbol *Label = getContext().createTempSymbol();
-  EmitLabel(Label);
+  MCSymbol *Label = EmitCFILabel();
 
   WinEH::Instruction Inst = Win64EH::Instruction::PushMachFrame(Label, Code);
   CurrentWinFrameInfo->Instructions.push_back(Inst);
 }
 
 void MCStreamer::EmitWinCFIEndProlog() {
   EnsureValidWinFrameInfo();
 
-  MCSymbol *Label = getContext().createTempSymbol();
-  EmitLabel(Label);
+  MCSymbol *Label = EmitCFILabel();
 
   CurrentWinFrameInfo->PrologEnd = Label;
 }
 
 void MCStreamer::EmitCOFFSafeSEH(MCSymbol const *Symbol) {
 }
 
 void MCStreamer::EmitCOFFSectionIndex(MCSymbol const *Symbol) {

test/CodeGen/AArch64/arm64-patchpoint-webkit_jscc.ll

 ; RUN: llc -mtriple=arm64-apple-darwin -enable-misched=0 -mcpu=cyclone < %s | FileCheck %s
 ; RUN: llc -mtriple=arm64-apple-darwin -enable-misched=0 -mcpu=cyclone -fast-isel < %s | FileCheck %s --check-prefix=FAST
 ; RUN: llc -mtriple=arm64-apple-darwin -enable-misched=0 -mcpu=cyclone -filetype=obj -o %t %s
 ; RUN: llvm-objdump -triple arm64-apple-darwin -d %t | FileCheck %s --check-prefix CHECK-ENCODING
 
 ; CHECK-ENCODING-NOT: <unknown>
 ; CHECK-ENCODING: mov x16, #281470681743360
 ; CHECK-ENCODING: movk x16, #57005, lsl #16
 ; CHECK-ENCODING: movk x16, #48879
 
 ; One argument will be passed in register, the other will be pushed on the stack.
 ; Return value in x0.
 define void @jscall_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
 entry:
 ; CHECK-LABEL: jscall_patchpoint_codegen:
-; CHECK:       Ltmp
+; CHECK:       Lcfi
 ; CHECK:       str x{{.+}}, [sp]
 ; CHECK-NEXT:  mov  x0, x{{.+}}
 ; CHECK:       Ltmp
 ; CHECK-NEXT:  mov  x16, #281470681743360
 ; CHECK:  movk  x16, #57005, lsl #16
 ; CHECK:  movk  x16, #48879
 ; CHECK-NEXT:  blr x16
 ; FAST-LABEL:  jscall_patchpoint_codegen:
-; FAST:        Ltmp
+; FAST:        Lcfi
 ; FAST:        str x{{.+}}, [sp]
 ; FAST:        Ltmp
 ; FAST-NEXT:   mov   x16, #281470681743360
 ; FAST-NEXT:   movk  x16, #57005, lsl #16
 ; FAST-NEXT:   movk  x16, #48879
 ; FAST-NEXT:   blr x16
   %resolveCall2 = inttoptr i64 281474417671919 to i8*
   %result = tail call webkit_jscc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 20, i8* %resolveCall2, i32 2, i64 %p4, i64 %p2)
   %resolveCall3 = inttoptr i64 244837814038255 to i8*
   tail call webkit_jscc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 6, i32 20, i8* %resolveCall3, i32 2, i64 %p4, i64 %result)
   ret void
 }
 
 ; Test if the arguments are properly aligned and that we don't store undef arguments.
 define i64 @jscall_patchpoint_codegen2(i64 %callee) {
 entry:
 ; CHECK-LABEL: jscall_patchpoint_codegen2:
-; CHECK:       Ltmp
+; CHECK:       Lcfi
 ; CHECK:       orr w[[REG:[0-9]+]], wzr, #0x6
 ; CHECK-NEXT:  str x[[REG]], [sp, #24]
 ; CHECK-NEXT:  orr w[[REG:[0-9]+]], wzr, #0x4
 ; CHECK-NEXT:  str w[[REG]], [sp, #16]
 ; CHECK-NEXT:  orr w[[REG:[0-9]+]], wzr, #0x2
 ; CHECK-NEXT:  str x[[REG]], [sp]
 ; CHECK:       Ltmp
 ; CHECK-NEXT:  mov  x16, #281470681743360
 ; CHECK-NEXT:  movk  x16, #57005, lsl #16
 ; CHECK-NEXT:  movk  x16, #48879
 ; CHECK-NEXT:  blr x16
 ; FAST-LABEL:  jscall_patchpoint_codegen2:
-; FAST:        Ltmp
+; FAST:        Lcfi
 ; FAST:        orr [[REG1:x[0-9]+]], xzr, #0x2
 ; FAST-NEXT:   orr [[REG2:w[0-9]+]], wzr, #0x4
 ; FAST-NEXT:   orr [[REG3:x[0-9]+]], xzr, #0x6
 ; FAST-NEXT:   str [[REG1]], [sp]
 ; FAST-NEXT:   str [[REG2]], [sp, #16]
 ; FAST-NEXT:   str [[REG3]], [sp, #24]
 ; FAST:        Ltmp
 ; FAST-NEXT:   mov  x16, #281470681743360
 ; FAST-NEXT:   movk  x16, #57005, lsl #16
 ; FAST-NEXT:   movk  x16, #48879
 ; FAST-NEXT:   blr x16
   %call = inttoptr i64 281474417671919 to i8*
   %result = call webkit_jscc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 7, i32 20, i8* %call, i32 6, i64 %callee, i64 2, i64 undef, i32 4, i32 undef, i64 6)
   ret i64 %result
 }
 
 ; Test if the arguments are properly aligned and that we don't store undef arguments.
 define i64 @jscall_patchpoint_codegen3(i64 %callee) {
 entry:
 ; CHECK-LABEL: jscall_patchpoint_codegen3:
-; CHECK:       Ltmp
+; CHECK:       Lcfi
 ; CHECK:       mov  w[[REG:[0-9]+]], #10
 ; CHECK-NEXT:  str x[[REG]], [sp, #48]
 ; CHECK-NEXT:  orr w[[REG:[0-9]+]], wzr, #0x8
 ; CHECK-NEXT:  str w[[REG]], [sp, #36]
 ; CHECK-NEXT:  orr w[[REG:[0-9]+]], wzr, #0x6
 ; CHECK-NEXT:  str x[[REG]], [sp, #24]
 ; CHECK-NEXT:  orr w[[REG:[0-9]+]], wzr, #0x4
 ; CHECK-NEXT:  str w[[REG]], [sp, #16]
 ; CHECK-NEXT:  orr w[[REG:[0-9]+]], wzr, #0x2
 ; CHECK-NEXT:  str x[[REG]], [sp]
 ; CHECK:       Ltmp
 ; CHECK-NEXT:  mov   x16, #281470681743360
 ; CHECK-NEXT:  movk  x16, #57005, lsl #16
 ; CHECK-NEXT:  movk  x16, #48879
 ; CHECK-NEXT:  blr x16
 ; FAST-LABEL:  jscall_patchpoint_codegen3:
-; FAST:        Ltmp
+; FAST:        Lcfi
 ; FAST:        orr [[REG1:x[0-9]+]], xzr, #0x2
 ; FAST-NEXT:   orr [[REG2:w[0-9]+]], wzr, #0x4
 ; FAST-NEXT:   orr [[REG3:x[0-9]+]], xzr, #0x6
 ; FAST-NEXT:   orr [[REG4:w[0-9]+]], wzr, #0x8
 ; FAST-NEXT:   mov [[REG5:x[0-9]+]], #10
 ; FAST-NEXT:   str [[REG1]], [sp]
 ; FAST-NEXT:   str [[REG2]], [sp, #16]
 ; FAST-NEXT:   str [[REG3]], [sp, #24]

test/CodeGen/X86/avg.ll

; AVX512BW-NEXT:    retq
   store <32 x i8> %8, <32 x i8>* undef, align 4
   ret void
 }
 
 define void @avg_v64i8(<64 x i8>* %a, <64 x i8>* %b) {
 ; SSE2-LABEL: avg_v64i8:
 ; SSE2:       # BB#0:
 ; SSE2-NEXT:    subq $152, %rsp
-; SSE2-NEXT:  .Ltmp0:
+; SSE2-NEXT:  .Lcfi0:
 ; SSE2-NEXT:    .cfi_def_cfa_offset 160
 ; SSE2-NEXT:    movdqa (%rdi), %xmm1
 ; SSE2-NEXT:    movdqa 16(%rdi), %xmm2
 ; SSE2-NEXT:    movdqa 32(%rdi), %xmm5
 ; SSE2-NEXT:    movdqa 48(%rdi), %xmm6
 ; SSE2-NEXT:    pxor %xmm0, %xmm0
 ; SSE2-NEXT:    pshufd {{.*#+}} xmm4 = xmm1[2,3,0,1]
 ; SSE2-NEXT:    punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]

test/CodeGen/X86/avx2-vbroadcast.ll

 ; created later, or if selection DAG cannot prove that folding the
 ; load will not create a cycle in the DAG.
 ; Those test cases exerce the latter.
 
 define void @isel_crash_16b(i8* %cV_R.addr) {
 ; X32-AVX2-LABEL: isel_crash_16b:
 ; X32-AVX2:       ## BB#0: ## %eintry
 ; X32-AVX2-NEXT:    subl $60, %esp
-; X32-AVX2-NEXT:  Ltmp0:
+; X32-AVX2-NEXT:  Lcfi0:
 ; X32-AVX2-NEXT:    .cfi_def_cfa_offset 64
 ; X32-AVX2-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-AVX2-NEXT:    vxorps %xmm0, %xmm0, %xmm0
 ; X32-AVX2-NEXT:    vmovaps %xmm0, (%esp)
 ; X32-AVX2-NEXT:    vpbroadcastb (%eax), %xmm1
 ; X32-AVX2-NEXT:    vmovaps %xmm0, {{[0-9]+}}(%esp)
 ; X32-AVX2-NEXT:    vmovdqa %xmm1, {{[0-9]+}}(%esp)
 ; X32-AVX2-NEXT:    addl $60, %esp
 ; X32-AVX2-NEXT:    retl
 ;
 ; X64-AVX2-LABEL: isel_crash_16b:
 ; X64-AVX2:       ## BB#0: ## %eintry
 ; X64-AVX2-NEXT:    vxorps %xmm0, %xmm0, %xmm0
 ; X64-AVX2-NEXT:    vmovaps %xmm0, -{{[0-9]+}}(%rsp)
 ; X64-AVX2-NEXT:    movb (%rdi), %al
 ; X64-AVX2-NEXT:    vmovd %eax, %xmm1
 ; X64-AVX2-NEXT:    vpbroadcastb %xmm1, %xmm1
 ; X64-AVX2-NEXT:    vmovaps %xmm0, -{{[0-9]+}}(%rsp)
 ; X64-AVX2-NEXT:    vmovdqa %xmm1, -{{[0-9]+}}(%rsp)
 ; X64-AVX2-NEXT:    retq
 ;
 ; X32-AVX512VL-LABEL: isel_crash_16b:
 ; X32-AVX512VL:       ## BB#0: ## %eintry
 ; X32-AVX512VL-NEXT:    subl $60, %esp
-; X32-AVX512VL-NEXT:  Ltmp0:
+; X32-AVX512VL-NEXT:  Lcfi0:
 ; X32-AVX512VL-NEXT:    .cfi_def_cfa_offset 64
 ; X32-AVX512VL-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-AVX512VL-NEXT:    vxorps %xmm0, %xmm0, %xmm0
 ; X32-AVX512VL-NEXT:    vmovaps %xmm0, (%esp)
 ; X32-AVX512VL-NEXT:    vpbroadcastb (%eax), %xmm1
 ; X32-AVX512VL-NEXT:    vmovaps %xmm0, {{[0-9]+}}(%esp)
 ; X32-AVX512VL-NEXT:    vmovdqa32 %xmm1, {{[0-9]+}}(%esp)
 ; X32-AVX512VL-NEXT:    addl $60, %esp
eintry:
   store <2 x i64> %tmp3, <2 x i64>* %__b.addr.i, align 16
   ret void
 }
 
 define void @isel_crash_32b(i8* %cV_R.addr) {
 ; X32-AVX2-LABEL: isel_crash_32b:
 ; X32-AVX2:       ## BB#0: ## %eintry
 ; X32-AVX2-NEXT:    pushl %ebp
-; X32-AVX2-NEXT:  Ltmp1:
+; X32-AVX2-NEXT:  Lcfi1:
 ; X32-AVX2-NEXT:    .cfi_def_cfa_offset 8
-; X32-AVX2-NEXT:  Ltmp2:
+; X32-AVX2-NEXT:  Lcfi2:
 ; X32-AVX2-NEXT:    .cfi_offset %ebp, -8
 ; X32-AVX2-NEXT:    movl %esp, %ebp
-; X32-AVX2-NEXT:  Ltmp3:
+; X32-AVX2-NEXT:  Lcfi3:
 ; X32-AVX2-NEXT:    .cfi_def_cfa_register %ebp
 ; X32-AVX2-NEXT:    andl $-32, %esp
 ; X32-AVX2-NEXT:    subl $128, %esp
 ; X32-AVX2-NEXT:    movl 8(%ebp), %eax
 ; X32-AVX2-NEXT:    vxorps %ymm0, %ymm0, %ymm0
 ; X32-AVX2-NEXT:    vmovaps %ymm0, (%esp)
 ; X32-AVX2-NEXT:    vpbroadcastb (%eax), %ymm1
 ; X32-AVX2-NEXT:    vmovaps %ymm0, {{[0-9]+}}(%esp)
 ; X32-AVX2-NEXT:    vmovdqa %ymm1, {{[0-9]+}}(%esp)
 ; X32-AVX2-NEXT:    movl %ebp, %esp
 ; X32-AVX2-NEXT:    popl %ebp
 ; X32-AVX2-NEXT:    vzeroupper
 ; X32-AVX2-NEXT:    retl
 ;
 ; X64-AVX2-LABEL: isel_crash_32b:
 ; X64-AVX2:       ## BB#0: ## %eintry
 ; X64-AVX2-NEXT:    pushq %rbp
-; X64-AVX2-NEXT:  Ltmp0:
+; X64-AVX2-NEXT:  Lcfi0:
 ; X64-AVX2-NEXT:    .cfi_def_cfa_offset 16
-; X64-AVX2-NEXT:  Ltmp1:
+; X64-AVX2-NEXT:  Lcfi1:
 ; X64-AVX2-NEXT:    .cfi_offset %rbp, -16
 ; X64-AVX2-NEXT:    movq %rsp, %rbp
-; X64-AVX2-NEXT:  Ltmp2:
+; X64-AVX2-NEXT:  Lcfi2:
 ; X64-AVX2-NEXT:    .cfi_def_cfa_register %rbp
 ; X64-AVX2-NEXT:    andq $-32, %rsp
 ; X64-AVX2-NEXT:    subq $128, %rsp
 ; X64-AVX2-NEXT:    vxorps %ymm0, %ymm0, %ymm0
 ; X64-AVX2-NEXT:    vmovaps %ymm0, (%rsp)
 ; X64-AVX2-NEXT:    movb (%rdi), %al
 ; X64-AVX2-NEXT:    vmovd %eax, %xmm1
 ; X64-AVX2-NEXT:    vpbroadcastb %xmm1, %ymm1
 ; X64-AVX2-NEXT:    vmovaps %ymm0, {{[0-9]+}}(%rsp)
 ; X64-AVX2-NEXT:    vmovdqa %ymm1, {{[0-9]+}}(%rsp)
 ; X64-AVX2-NEXT:    movq %rbp, %rsp
 ; X64-AVX2-NEXT:    popq %rbp
 ; X64-AVX2-NEXT:    vzeroupper
 ; X64-AVX2-NEXT:    retq
 ;
 ; X32-AVX512VL-LABEL: isel_crash_32b:
 ; X32-AVX512VL:       ## BB#0: ## %eintry
 ; X32-AVX512VL-NEXT:    pushl %ebp
-; X32-AVX512VL-NEXT:  Ltmp1:
+; X32-AVX512VL-NEXT:  Lcfi1:
 ; X32-AVX512VL-NEXT:    .cfi_def_cfa_offset 8
-; X32-AVX512VL-NEXT:  Ltmp2:
+; X32-AVX512VL-NEXT:  Lcfi2:
 ; X32-AVX512VL-NEXT:    .cfi_offset %ebp, -8
 ; X32-AVX512VL-NEXT:    movl %esp, %ebp
-; X32-AVX512VL-NEXT:  Ltmp3:
+; X32-AVX512VL-NEXT:  Lcfi3:
 ; X32-AVX512VL-NEXT:    .cfi_def_cfa_register %ebp
 ; X32-AVX512VL-NEXT:    andl $-32, %esp
 ; X32-AVX512VL-NEXT:    subl $128, %esp
 ; X32-AVX512VL-NEXT:    movl 8(%ebp), %eax
 ; X32-AVX512VL-NEXT:    vxorps %ymm0, %ymm0, %ymm0
 ; X32-AVX512VL-NEXT:    vmovaps %ymm0, (%esp)
 ; X32-AVX512VL-NEXT:    vpbroadcastb (%eax), %ymm1
 ; X32-AVX512VL-NEXT:    vmovaps %ymm0, {{[0-9]+}}(%esp)
 ; X32-AVX512VL-NEXT:    vmovdqa32 %ymm1, {{[0-9]+}}(%esp)
 ; X32-AVX512VL-NEXT:    movl %ebp, %esp
 ; X32-AVX512VL-NEXT:    popl %ebp
 ; X32-AVX512VL-NEXT:    retl
 ;
 ; X64-AVX512VL-LABEL: isel_crash_32b:
 ; X64-AVX512VL:       ## BB#0: ## %eintry
 ; X64-AVX512VL-NEXT:    pushq %rbp
-; X64-AVX512VL-NEXT:  Ltmp0:
+; X64-AVX512VL-NEXT:  Lcfi0:
 ; X64-AVX512VL-NEXT:    .cfi_def_cfa_offset 16
-; X64-AVX512VL-NEXT:  Ltmp1:
+; X64-AVX512VL-NEXT:  Lcfi1:
 ; X64-AVX512VL-NEXT:    .cfi_offset %rbp, -16
 ; X64-AVX512VL-NEXT:    movq %rsp, %rbp
-; X64-AVX512VL-NEXT:  Ltmp2:
+; X64-AVX512VL-NEXT:  Lcfi2:
 ; X64-AVX512VL-NEXT:    .cfi_def_cfa_register %rbp
 ; X64-AVX512VL-NEXT:    andq $-32, %rsp
 ; X64-AVX512VL-NEXT:    subq $128, %rsp
 ; X64-AVX512VL-NEXT:    vxorps %ymm0, %ymm0, %ymm0
 ; X64-AVX512VL-NEXT:    vmovaps %ymm0, (%rsp)
 ; X64-AVX512VL-NEXT:    movb (%rdi), %al
 ; X64-AVX512VL-NEXT:    vmovd %eax, %xmm1
 ; X64-AVX512VL-NEXT:    vpbroadcastb %xmm1, %ymm1
eintry:
   store <4 x i64> %tmp3, <4 x i64>* %__b.addr.i, align 16
   ret void
 }
 
 define void @isel_crash_8w(i16* %cV_R.addr) {
 ; X32-AVX2-LABEL: isel_crash_8w:
 ; X32-AVX2:       ## BB#0: ## %entry
 ; X32-AVX2-NEXT:    subl $60, %esp
-; X32-AVX2-NEXT:  Ltmp4:
+; X32-AVX2-NEXT:  Lcfi4:
 ; X32-AVX2-NEXT:    .cfi_def_cfa_offset 64
 ; X32-AVX2-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-AVX2-NEXT:    vxorps %xmm0, %xmm0, %xmm0
 ; X32-AVX2-NEXT:    vmovaps %xmm0, (%esp)
 ; X32-AVX2-NEXT:    vpbroadcastw (%eax), %xmm1
 ; X32-AVX2-NEXT:    vmovaps %xmm0, {{[0-9]+}}(%esp)
 ; X32-AVX2-NEXT:    vmovdqa %xmm1, {{[0-9]+}}(%esp)
 ; X32-AVX2-NEXT:    addl $60, %esp
 ; X32-AVX2-NEXT:    retl
 ;
 ; X64-AVX2-LABEL: isel_crash_8w:
 ; X64-AVX2:       ## BB#0: ## %entry
 ; X64-AVX2-NEXT:    vxorps %xmm0, %xmm0, %xmm0
 ; X64-AVX2-NEXT:    vmovaps %xmm0, -{{[0-9]+}}(%rsp)
 ; X64-AVX2-NEXT:    movw (%rdi), %ax
 ; X64-AVX2-NEXT:    vmovd %eax, %xmm1
 ; X64-AVX2-NEXT:    vpbroadcastw %xmm1, %xmm1
 ; X64-AVX2-NEXT:    vmovaps %xmm0, -{{[0-9]+}}(%rsp)
 ; X64-AVX2-NEXT:    vmovdqa %xmm1, -{{[0-9]+}}(%rsp)
 ; X64-AVX2-NEXT:    retq
 ;
 ; X32-AVX512VL-LABEL: isel_crash_8w:
 ; X32-AVX512VL:       ## BB#0: ## %entry
 ; X32-AVX512VL-NEXT:    subl $60, %esp
-; X32-AVX512VL-NEXT:  Ltmp4:
+; X32-AVX512VL-NEXT:  Lcfi4:
 ; X32-AVX512VL-NEXT:    .cfi_def_cfa_offset 64
 ; X32-AVX512VL-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-AVX512VL-NEXT:    vxorps %xmm0, %xmm0, %xmm0
 ; X32-AVX512VL-NEXT:    vmovaps %xmm0, (%esp)
 ; X32-AVX512VL-NEXT:    vpbroadcastw (%eax), %xmm1
 ; X32-AVX512VL-NEXT:    vmovaps %xmm0, {{[0-9]+}}(%esp)
 ; X32-AVX512VL-NEXT:    vmovdqa32 %xmm1, {{[0-9]+}}(%esp)
 ; X32-AVX512VL-NEXT:    addl $60, %esp
entry:
   store <2 x i64> %tmp3, <2 x i64>* %__b.addr.i, align 16
   ret void
 }
 
 define void @isel_crash_16w(i16* %cV_R.addr) {
 ; X32-AVX2-LABEL: isel_crash_16w:
 ; X32-AVX2:       ## BB#0: ## %eintry
 ; X32-AVX2-NEXT:    pushl %ebp
-; X32-AVX2-NEXT:  Ltmp5:
+; X32-AVX2-NEXT:  Lcfi5:
 ; X32-AVX2-NEXT:    .cfi_def_cfa_offset 8
-; X32-AVX2-NEXT:  Ltmp6:
+; X32-AVX2-NEXT:  Lcfi6:
 ; X32-AVX2-NEXT:    .cfi_offset %ebp, -8
 ; X32-AVX2-NEXT:    movl %esp, %ebp
-; X32-AVX2-NEXT:  Ltmp7:
+; X32-AVX2-NEXT:  Lcfi7:
 ; X32-AVX2-NEXT:    .cfi_def_cfa_register %ebp
 ; X32-AVX2-NEXT:    andl $-32, %esp
 ; X32-AVX2-NEXT:    subl $128, %esp
 ; X32-AVX2-NEXT:    movl 8(%ebp), %eax
 ; X32-AVX2-NEXT:    vxorps %ymm0, %ymm0, %ymm0
 ; X32-AVX2-NEXT:    vmovaps %ymm0, (%esp)
 ; X32-AVX2-NEXT:    vpbroadcastw (%eax), %ymm1
 ; X32-AVX2-NEXT:    vmovaps %ymm0, {{[0-9]+}}(%esp)
 ; X32-AVX2-NEXT:    vmovdqa %ymm1, {{[0-9]+}}(%esp)
 ; X32-AVX2-NEXT:    movl %ebp, %esp
 ; X32-AVX2-NEXT:    popl %ebp
 ; X32-AVX2-NEXT:    vzeroupper
 ; X32-AVX2-NEXT:    retl
 ;
 ; X64-AVX2-LABEL: isel_crash_16w:
 ; X64-AVX2:       ## BB#0: ## %eintry
 ; X64-AVX2-NEXT:    pushq %rbp
-; X64-AVX2-NEXT:  Ltmp3:
+; X64-AVX2-NEXT:  Lcfi3:
 ; X64-AVX2-NEXT:    .cfi_def_cfa_offset 16
-; X64-AVX2-NEXT:  Ltmp4:
+; X64-AVX2-NEXT:  Lcfi4:
 ; X64-AVX2-NEXT:    .cfi_offset %rbp, -16
 ; X64-AVX2-NEXT:    movq %rsp, %rbp
-; X64-AVX2-NEXT:  Ltmp5:
+; X64-AVX2-NEXT:  Lcfi5:
 ; X64-AVX2-NEXT:    .cfi_def_cfa_register %rbp
 ; X64-AVX2-NEXT:    andq $-32, %rsp
 ; X64-AVX2-NEXT:    subq $128, %rsp
 ; X64-AVX2-NEXT:    vxorps %ymm0, %ymm0, %ymm0
 ; X64-AVX2-NEXT:    vmovaps %ymm0, (%rsp)
 ; X64-AVX2-NEXT:    movw (%rdi), %ax
 ; X64-AVX2-NEXT:    vmovd %eax, %xmm1
 ; X64-AVX2-NEXT:    vpbroadcastw %xmm1, %ymm1
 ; X64-AVX2-NEXT:    vmovaps %ymm0, {{[0-9]+}}(%rsp)
 ; X64-AVX2-NEXT:    vmovdqa %ymm1, {{[0-9]+}}(%rsp)
 ; X64-AVX2-NEXT:    movq %rbp, %rsp
 ; X64-AVX2-NEXT:    popq %rbp
 ; X64-AVX2-NEXT:    vzeroupper
 ; X64-AVX2-NEXT:    retq
 ;
 ; X32-AVX512VL-LABEL: isel_crash_16w:
 ; X32-AVX512VL:       ## BB#0: ## %eintry
 ; X32-AVX512VL-NEXT:    pushl %ebp
-; X32-AVX512VL-NEXT:  Ltmp5:
+; X32-AVX512VL-NEXT:  Lcfi5:
 ; X32-AVX512VL-NEXT:    .cfi_def_cfa_offset 8
-; X32-AVX512VL-NEXT:  Ltmp6:
+; X32-AVX512VL-NEXT:  Lcfi6:
 ; X32-AVX512VL-NEXT:    .cfi_offset %ebp, -8
 ; X32-AVX512VL-NEXT:    movl %esp, %ebp
-; X32-AVX512VL-NEXT:  Ltmp7:
+; X32-AVX512VL-NEXT:  Lcfi7:
 ; X32-AVX512VL-NEXT:    .cfi_def_cfa_register %ebp
 ; X32-AVX512VL-NEXT:    andl $-32, %esp
 ; X32-AVX512VL-NEXT:    subl $128, %esp
 ; X32-AVX512VL-NEXT:    movl 8(%ebp), %eax
 ; X32-AVX512VL-NEXT:    vxorps %ymm0, %ymm0, %ymm0
 ; X32-AVX512VL-NEXT:    vmovaps %ymm0, (%esp)
 ; X32-AVX512VL-NEXT:    vpbroadcastw (%eax), %ymm1
 ; X32-AVX512VL-NEXT:    vmovaps %ymm0, {{[0-9]+}}(%esp)
 ; X32-AVX512VL-NEXT:    vmovdqa32 %ymm1, {{[0-9]+}}(%esp)
 ; X32-AVX512VL-NEXT:    movl %ebp, %esp
 ; X32-AVX512VL-NEXT:    popl %ebp
 ; X32-AVX512VL-NEXT:    retl
 ;
 ; X64-AVX512VL-LABEL: isel_crash_16w:
 ; X64-AVX512VL:       ## BB#0: ## %eintry
 ; X64-AVX512VL-NEXT:    pushq %rbp
-; X64-AVX512VL-NEXT:  Ltmp3:
+; X64-AVX512VL-NEXT:  Lcfi3:
 ; X64-AVX512VL-NEXT:    .cfi_def_cfa_offset 16
-; X64-AVX512VL-NEXT:  Ltmp4:
+; X64-AVX512VL-NEXT:  Lcfi4:
 ; X64-AVX512VL-NEXT:    .cfi_offset %rbp, -16
 ; X64-AVX512VL-NEXT:    movq %rsp, %rbp
-; X64-AVX512VL-NEXT:  Ltmp5:
+; X64-AVX512VL-NEXT:  Lcfi5:
 ; X64-AVX512VL-NEXT:    .cfi_def_cfa_register %rbp
 ; X64-AVX512VL-NEXT:    andq $-32, %rsp
 ; X64-AVX512VL-NEXT:    subq $128, %rsp
 ; X64-AVX512VL-NEXT:    vxorps %ymm0, %ymm0, %ymm0
 ; X64-AVX512VL-NEXT:    vmovaps %ymm0, (%rsp)
 ; X64-AVX512VL-NEXT:    movw (%rdi), %ax
 ; X64-AVX512VL-NEXT:    vmovd %eax, %xmm1
 ; X64-AVX512VL-NEXT:    vpbroadcastw %xmm1, %ymm1
eintry:
   store <4 x i64> %tmp3, <4 x i64>* %__b.addr.i, align 16
   ret void
 }
 
 define void @isel_crash_4d(i32* %cV_R.addr) {
 ; X32-LABEL: isel_crash_4d:
 ; X32:       ## BB#0: ## %entry
 ; X32-NEXT:    subl $60, %esp
-; X32-NEXT:  Ltmp8:
+; X32-NEXT:  Lcfi8:
 ; X32-NEXT:    .cfi_def_cfa_offset 64
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    vxorps %xmm0, %xmm0, %xmm0
 ; X32-NEXT:    vmovaps %xmm0, (%esp)
 ; X32-NEXT:    vbroadcastss (%eax), %xmm1
 ; X32-NEXT:    vmovaps %xmm0, {{[0-9]+}}(%esp)
 ; X32-NEXT:    vmovaps %xmm1, {{[0-9]+}}(%esp)
 ; X32-NEXT:    addl $60, %esp
entry:
   store <2 x i64> %tmp3, <2 x i64>* %__b.addr.i, align 16
   ret void
 }
 
 define void @isel_crash_8d(i32* %cV_R.addr) {
 ; X32-AVX2-LABEL: isel_crash_8d:
 ; X32-AVX2:       ## BB#0: ## %eintry
 ; X32-AVX2-NEXT:    pushl %ebp
-; X32-AVX2-NEXT:  Ltmp9:
+; X32-AVX2-NEXT:  Lcfi9:
 ; X32-AVX2-NEXT:    .cfi_def_cfa_offset 8
-; X32-AVX2-NEXT:  Ltmp10:
+; X32-AVX2-NEXT:  Lcfi10:
 ; X32-AVX2-NEXT:    .cfi_offset %ebp, -8
 ; X32-AVX2-NEXT:    movl %esp, %ebp
-; X32-AVX2-NEXT:  Ltmp11:
+; X32-AVX2-NEXT:  Lcfi11:
 ; X32-AVX2-NEXT:    .cfi_def_cfa_register %ebp
 ; X32-AVX2-NEXT:    andl $-32, %esp
 ; X32-AVX2-NEXT:    subl $128, %esp
 ; X32-AVX2-NEXT:    movl 8(%ebp), %eax
 ; X32-AVX2-NEXT:    vxorps %ymm0, %ymm0, %ymm0
 ; X32-AVX2-NEXT:    vmovaps %ymm0, (%esp)
 ; X32-AVX2-NEXT:    vbroadcastss (%eax), %ymm1
 ; X32-AVX2-NEXT:    vmovaps %ymm0, {{[0-9]+}}(%esp)
 ; X32-AVX2-NEXT:    vmovaps %ymm1, {{[0-9]+}}(%esp)
 ; X32-AVX2-NEXT:    movl %ebp, %esp
 ; X32-AVX2-NEXT:    popl %ebp
 ; X32-AVX2-NEXT:    vzeroupper
 ; X32-AVX2-NEXT:    retl
 ;
 ; X64-AVX2-LABEL: isel_crash_8d:
 ; X64-AVX2:       ## BB#0: ## %eintry
 ; X64-AVX2-NEXT:    pushq %rbp
-; X64-AVX2-NEXT:  Ltmp6:
+; X64-AVX2-NEXT:  Lcfi6:
 ; X64-AVX2-NEXT:    .cfi_def_cfa_offset 16
-; X64-AVX2-NEXT:  Ltmp7:
+; X64-AVX2-NEXT:  Lcfi7:
 ; X64-AVX2-NEXT:    .cfi_offset %rbp, -16
 ; X64-AVX2-NEXT:    movq %rsp, %rbp
-; X64-AVX2-NEXT:  Ltmp8:
+; X64-AVX2-NEXT:  Lcfi8:
 ; X64-AVX2-NEXT:    .cfi_def_cfa_register %rbp
 ; X64-AVX2-NEXT:    andq $-32, %rsp
 ; X64-AVX2-NEXT:    subq $128, %rsp
 ; X64-AVX2-NEXT:    vxorps %ymm0, %ymm0, %ymm0
 ; X64-AVX2-NEXT:    vmovaps %ymm0, (%rsp)
 ; X64-AVX2-NEXT:    movl (%rdi), %eax
 ; X64-AVX2-NEXT:    vmovd %eax, %xmm1
 ; X64-AVX2-NEXT:    vbroadcastss %xmm1, %ymm1
 ; X64-AVX2-NEXT:    vmovaps %ymm0, {{[0-9]+}}(%rsp)
 ; X64-AVX2-NEXT:    vmovaps %ymm1, {{[0-9]+}}(%rsp)
 ; X64-AVX2-NEXT:    movq %rbp, %rsp
 ; X64-AVX2-NEXT:    popq %rbp
 ; X64-AVX2-NEXT:    vzeroupper
 ; X64-AVX2-NEXT:    retq
 ;
 ; X32-AVX512VL-LABEL: isel_crash_8d:
 ; X32-AVX512VL:       ## BB#0: ## %eintry
 ; X32-AVX512VL-NEXT:    pushl %ebp
-; X32-AVX512VL-NEXT:  Ltmp9:
+; X32-AVX512VL-NEXT:  Lcfi9:
 ; X32-AVX512VL-NEXT:    .cfi_def_cfa_offset 8
-; X32-AVX512VL-NEXT:  Ltmp10:
+; X32-AVX512VL-NEXT:  Lcfi10:
 ; X32-AVX512VL-NEXT:    .cfi_offset %ebp, -8
 ; X32-AVX512VL-NEXT:    movl %esp, %ebp
-; X32-AVX512VL-NEXT:  Ltmp11:
+; X32-AVX512VL-NEXT:  Lcfi11:
 ; X32-AVX512VL-NEXT:    .cfi_def_cfa_register %ebp
 ; X32-AVX512VL-NEXT:    andl $-32, %esp
 ; X32-AVX512VL-NEXT:    subl $128, %esp
 ; X32-AVX512VL-NEXT:    movl 8(%ebp), %eax
 ; X32-AVX512VL-NEXT:    vxorps %ymm0, %ymm0, %ymm0
 ; X32-AVX512VL-NEXT:    vmovaps %ymm0, (%esp)
 ; X32-AVX512VL-NEXT:    vbroadcastss (%eax), %ymm1
 ; X32-AVX512VL-NEXT:    vmovaps %ymm0, {{[0-9]+}}(%esp)
 ; X32-AVX512VL-NEXT:    vmovaps %ymm1, {{[0-9]+}}(%esp)
 ; X32-AVX512VL-NEXT:    movl %ebp, %esp
 ; X32-AVX512VL-NEXT:    popl %ebp
 ; X32-AVX512VL-NEXT:    retl
 ;
 ; X64-AVX512VL-LABEL: isel_crash_8d:
 ; X64-AVX512VL:       ## BB#0: ## %eintry
 ; X64-AVX512VL-NEXT:    pushq %rbp
-; X64-AVX512VL-NEXT:  Ltmp6:
+; X64-AVX512VL-NEXT:  Lcfi6:
 ; X64-AVX512VL-NEXT:    .cfi_def_cfa_offset 16
-; X64-AVX512VL-NEXT:  Ltmp7:
+; X64-AVX512VL-NEXT:  Lcfi7:
 ; X64-AVX512VL-NEXT:    .cfi_offset %rbp, -16
 ; X64-AVX512VL-NEXT:    movq %rsp, %rbp
-; X64-AVX512VL-NEXT:  Ltmp8:
+; X64-AVX512VL-NEXT:  Lcfi8:
 ; X64-AVX512VL-NEXT:    .cfi_def_cfa_register %rbp
 ; X64-AVX512VL-NEXT:    andq $-32, %rsp
 ; X64-AVX512VL-NEXT:    subq $128, %rsp
 ; X64-AVX512VL-NEXT:    vxorps %ymm0, %ymm0, %ymm0
 ; X64-AVX512VL-NEXT:    vmovaps %ymm0, (%rsp)
 ; X64-AVX512VL-NEXT:    movl (%rdi), %eax
 ; X64-AVX512VL-NEXT:    vpbroadcastd %eax, %ymm1
 ; X64-AVX512VL-NEXT:    vmovaps %ymm0, {{[0-9]+}}(%rsp)
eintry:
   store <4 x i64> %tmp3, <4 x i64>* %__b.addr.i, align 16
   ret void
 }
 
 define void @isel_crash_2q(i64* %cV_R.addr) {
 ; X32-AVX2-LABEL: isel_crash_2q:
 ; X32-AVX2:       ## BB#0: ## %entry
 ; X32-AVX2-NEXT:    subl $60, %esp
-; X32-AVX2-NEXT:  Ltmp12:
+; X32-AVX2-NEXT:  Lcfi12:
 ; X32-AVX2-NEXT:    .cfi_def_cfa_offset 64
 ; X32-AVX2-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-AVX2-NEXT:    vxorps %xmm0, %xmm0, %xmm0
 ; X32-AVX2-NEXT:    vmovaps %xmm0, (%esp)
 ; X32-AVX2-NEXT:    movl (%eax), %ecx
 ; X32-AVX2-NEXT:    movl 4(%eax), %eax
 ; X32-AVX2-NEXT:    vmovd %ecx, %xmm1
 ; X32-AVX2-NEXT:    vpinsrd $1, %eax, %xmm1, %xmm1

 ; X64-AVX2-NEXT:    vpbroadcastq %xmm1, %xmm1
 ; X64-AVX2-NEXT:    vmovaps %xmm0, -{{[0-9]+}}(%rsp)
 ; X64-AVX2-NEXT:    vmovdqa %xmm1, -{{[0-9]+}}(%rsp)
 ; X64-AVX2-NEXT:    retq
 ;
 ; X32-AVX512VL-LABEL: isel_crash_2q:
 ; X32-AVX512VL:       ## BB#0: ## %entry
 ; X32-AVX512VL-NEXT:    subl $60, %esp
-; X32-AVX512VL-NEXT:  Ltmp12:
+; X32-AVX512VL-NEXT:  Lcfi12:
 ; X32-AVX512VL-NEXT:    .cfi_def_cfa_offset 64
 ; X32-AVX512VL-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-AVX512VL-NEXT:    vxorps %xmm0, %xmm0, %xmm0
 ; X32-AVX512VL-NEXT:    vmovaps %xmm0, (%esp)
 ; X32-AVX512VL-NEXT:    movl (%eax), %ecx
 ; X32-AVX512VL-NEXT:    movl 4(%eax), %eax
 ; X32-AVX512VL-NEXT:    vmovd %ecx, %xmm1
 ; X32-AVX512VL-NEXT:    vpinsrd $1, %eax, %xmm1, %xmm1
entry:
   store <2 x i64> %splat.splat, <2 x i64>* %__b.addr.i, align 16
   ret void
 }
 
 define void @isel_crash_4q(i64* %cV_R.addr) {
 ; X32-AVX2-LABEL: isel_crash_4q:
 ; X32-AVX2:       ## BB#0: ## %eintry
 ; X32-AVX2-NEXT:    pushl %ebp
-; X32-AVX2-NEXT:  Ltmp13:
+; X32-AVX2-NEXT:  Lcfi13:
 ; X32-AVX2-NEXT:    .cfi_def_cfa_offset 8
-; X32-AVX2-NEXT:  Ltmp14:
+; X32-AVX2-NEXT:  Lcfi14:
 ; X32-AVX2-NEXT:    .cfi_offset %ebp, -8
 ; X32-AVX2-NEXT:    movl %esp, %ebp
-; X32-AVX2-NEXT:  Ltmp15:
+; X32-AVX2-NEXT:  Lcfi15:
 ; X32-AVX2-NEXT:    .cfi_def_cfa_register %ebp
 ; X32-AVX2-NEXT:    andl $-32, %esp
 ; X32-AVX2-NEXT:    subl $128, %esp
 ; X32-AVX2-NEXT:    movl 8(%ebp), %eax
 ; X32-AVX2-NEXT:    vxorps %ymm0, %ymm0, %ymm0
 ; X32-AVX2-NEXT:    vmovaps %ymm0, (%esp)
 ; X32-AVX2-NEXT:    movl (%eax), %ecx
 ; X32-AVX2-NEXT:    movl 4(%eax), %eax
 ; X32-AVX2-NEXT:    vmovd %ecx, %xmm1
 ; X32-AVX2-NEXT:    vpinsrd $1, %eax, %xmm1, %xmm1
 ; X32-AVX2-NEXT:    vpinsrd $2, %ecx, %xmm1, %xmm1
 ; X32-AVX2-NEXT:    vpinsrd $3, %eax, %xmm1, %xmm1
 ; X32-AVX2-NEXT:    vinserti128 $1, %xmm1, %ymm1, %ymm1
 ; X32-AVX2-NEXT:    vmovaps %ymm0, {{[0-9]+}}(%esp)
 ; X32-AVX2-NEXT:    vmovdqa %ymm1, {{[0-9]+}}(%esp)
 ; X32-AVX2-NEXT:    movl %ebp, %esp
 ; X32-AVX2-NEXT:    popl %ebp
 ; X32-AVX2-NEXT:    vzeroupper
 ; X32-AVX2-NEXT:    retl
 ;
 ; X64-AVX2-LABEL: isel_crash_4q:
 ; X64-AVX2:       ## BB#0: ## %eintry
 ; X64-AVX2-NEXT:    pushq %rbp
-; X64-AVX2-NEXT:  Ltmp9:
+; X64-AVX2-NEXT:  Lcfi9:
 ; X64-AVX2-NEXT:    .cfi_def_cfa_offset 16
-; X64-AVX2-NEXT:  Ltmp10:
+; X64-AVX2-NEXT:  Lcfi10:
 ; X64-AVX2-NEXT:    .cfi_offset %rbp, -16
 ; X64-AVX2-NEXT:    movq %rsp, %rbp
-; X64-AVX2-NEXT:  Ltmp11:
+; X64-AVX2-NEXT:  Lcfi11:
 ; X64-AVX2-NEXT:    .cfi_def_cfa_register %rbp
 ; X64-AVX2-NEXT:    andq $-32, %rsp
 ; X64-AVX2-NEXT:    subq $128, %rsp
 ; X64-AVX2-NEXT:    vxorps %ymm0, %ymm0, %ymm0
 ; X64-AVX2-NEXT:    vmovaps %ymm0, (%rsp)
 ; X64-AVX2-NEXT:    movq (%rdi), %rax
 ; X64-AVX2-NEXT:    vmovq %rax, %xmm1
 ; X64-AVX2-NEXT:    vbroadcastsd %xmm1, %ymm1
 ; X64-AVX2-NEXT:    vmovaps %ymm0, {{[0-9]+}}(%rsp)
 ; X64-AVX2-NEXT:    vmovaps %ymm1, {{[0-9]+}}(%rsp)
 ; X64-AVX2-NEXT:    movq %rbp, %rsp
 ; X64-AVX2-NEXT:    popq %rbp
 ; X64-AVX2-NEXT:    vzeroupper
 ; X64-AVX2-NEXT:    retq
 ;
 ; X32-AVX512VL-LABEL: isel_crash_4q:
 ; X32-AVX512VL:       ## BB#0: ## %eintry
 ; X32-AVX512VL-NEXT:    pushl %ebp
-; X32-AVX512VL-NEXT:  Ltmp13:
+; X32-AVX512VL-NEXT:  Lcfi13:
 ; X32-AVX512VL-NEXT:    .cfi_def_cfa_offset 8
-; X32-AVX512VL-NEXT:  Ltmp14:
+; X32-AVX512VL-NEXT:  Lcfi14:
 ; X32-AVX512VL-NEXT:    .cfi_offset %ebp, -8
 ; X32-AVX512VL-NEXT:    movl %esp, %ebp
-; X32-AVX512VL-NEXT:  Ltmp15:
+; X32-AVX512VL-NEXT:  Lcfi15:
 ; X32-AVX512VL-NEXT:    .cfi_def_cfa_register %ebp
 ; X32-AVX512VL-NEXT:    andl $-32, %esp
 ; X32-AVX512VL-NEXT:    subl $128, %esp
 ; X32-AVX512VL-NEXT:    movl 8(%ebp), %eax
 ; X32-AVX512VL-NEXT:    vxorps %ymm0, %ymm0, %ymm0
 ; X32-AVX512VL-NEXT:    vmovaps %ymm0, (%esp)
 ; X32-AVX512VL-NEXT:    movl (%eax), %ecx
 ; X32-AVX512VL-NEXT:    movl 4(%eax), %eax
 ; X32-AVX512VL-NEXT:    vmovd %ecx, %xmm1
 ; X32-AVX512VL-NEXT:    vpinsrd $1, %eax, %xmm1, %xmm1
 ; X32-AVX512VL-NEXT:    vpinsrd $2, %ecx, %xmm1, %xmm1
 ; X32-AVX512VL-NEXT:    vpinsrd $3, %eax, %xmm1, %xmm1
 ; X32-AVX512VL-NEXT:    vinserti32x4 $1, %xmm1, %ymm1, %ymm1
 ; X32-AVX512VL-NEXT:    vmovaps %ymm0, {{[0-9]+}}(%esp)
 ; X32-AVX512VL-NEXT:    vmovdqa32 %ymm1, {{[0-9]+}}(%esp)
 ; X32-AVX512VL-NEXT:    movl %ebp, %esp
 ; X32-AVX512VL-NEXT:    popl %ebp
 ; X32-AVX512VL-NEXT:    retl
 ;
 ; X64-AVX512VL-LABEL: isel_crash_4q:
 ; X64-AVX512VL:       ## BB#0: ## %eintry
 ; X64-AVX512VL-NEXT:    pushq %rbp
-; X64-AVX512VL-NEXT:  Ltmp9:
+; X64-AVX512VL-NEXT:  Lcfi9:
 ; X64-AVX512VL-NEXT:    .cfi_def_cfa_offset 16
-; X64-AVX512VL-NEXT:  Ltmp10:
+; X64-AVX512VL-NEXT:  Lcfi10:
 ; X64-AVX512VL-NEXT:    .cfi_offset %rbp, -16
 ; X64-AVX512VL-NEXT:    movq %rsp, %rbp
-; X64-AVX512VL-NEXT:  Ltmp11:
+; X64-AVX512VL-NEXT:  Lcfi11:
 ; X64-AVX512VL-NEXT:    .cfi_def_cfa_register %rbp
 ; X64-AVX512VL-NEXT:    andq $-32, %rsp
 ; X64-AVX512VL-NEXT:    subq $128, %rsp
 ; X64-AVX512VL-NEXT:    vxorps %ymm0, %ymm0, %ymm0
 ; X64-AVX512VL-NEXT:    vmovaps %ymm0, (%rsp)
 ; X64-AVX512VL-NEXT:    movq (%rdi), %rax
 ; X64-AVX512VL-NEXT:    vpbroadcastq %rax, %ymm1
 ; X64-AVX512VL-NEXT:    vmovaps %ymm0, {{[0-9]+}}(%rsp)

test/CodeGen/X86/avx512-calling-conv.ll

 }
 
 declare <8 x i1> @func8xi1(<8 x i1> %a)
 
 define <8 x i32> @test5(<8 x i32>%a, <8 x i32>%b) {
 ; KNL-LABEL: test5:
 ; KNL:       ## BB#0:
 ; KNL-NEXT:    pushq %rax
-; KNL-NEXT:  Ltmp0:
+; KNL-NEXT:  Lcfi0:
 ; KNL-NEXT:    .cfi_def_cfa_offset 16
 ; KNL-NEXT:    vpcmpgtd %ymm1, %ymm0, %ymm0
 ; KNL-NEXT:    vpmovdw %zmm0, %ymm0
 ; KNL-NEXT:    ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
 ; KNL-NEXT:    callq _func8xi1
 ; KNL-NEXT:    vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
 ; KNL-NEXT:    vpslld $31, %ymm0, %ymm0
 ; KNL-NEXT:    vpsrad $31, %ymm0, %ymm0
 ; KNL-NEXT:    popq %rax
 ; KNL-NEXT:    retq
 ;
 ; SKX-LABEL: test5:
 ; SKX:       ## BB#0:
 ; SKX-NEXT:    pushq %rax
-; SKX-NEXT:  Ltmp0:
+; SKX-NEXT:  Lcfi0:
 ; SKX-NEXT:    .cfi_def_cfa_offset 16
 ; SKX-NEXT:    vpcmpgtd %ymm1, %ymm0, %k0
 ; SKX-NEXT:    vpmovm2w %k0, %xmm0
 ; SKX-NEXT:    callq _func8xi1
 ; SKX-NEXT:    vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
 ; SKX-NEXT:    vpslld $31, %ymm0, %ymm0
 ; SKX-NEXT:    vpsrad $31, %ymm0, %ymm0
 ; SKX-NEXT:    popq %rax
 ; SKX-NEXT:    retq
 ;
 ; KNL_X32-LABEL: test5:
 ; KNL_X32:       ## BB#0:
 ; KNL_X32-NEXT:    subl $12, %esp
-; KNL_X32-NEXT:  Ltmp0:
+; KNL_X32-NEXT:  Lcfi0:
 ; KNL_X32-NEXT:    .cfi_def_cfa_offset 16
 ; KNL_X32-NEXT:    vpcmpgtd %ymm1, %ymm0, %ymm0
 ; KNL_X32-NEXT:    vpmovdw %zmm0, %ymm0
 ; KNL_X32-NEXT:    ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
 ; KNL_X32-NEXT:    calll _func8xi1
 ; KNL_X32-NEXT:    vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
 ; KNL_X32-NEXT:    vpslld $31, %ymm0, %ymm0
 ; KNL_X32-NEXT:    vpsrad $31, %ymm0, %ymm0
 ; KNL_X32-NEXT:    addl $12, %esp
 ; KNL_X32-NEXT:    retl
   %cmpRes = icmp sgt <8 x i32>%a, %b
   %resi = call <8 x i1> @func8xi1(<8 x i1> %cmpRes)
   %res = sext <8 x i1>%resi to <8 x i32>
   ret <8 x i32> %res
 }
 
 declare <16 x i1> @func16xi1(<16 x i1> %a)
 
 define <16 x i32> @test6(<16 x i32>%a, <16 x i32>%b) {
 ; KNL-LABEL: test6:
 ; KNL:       ## BB#0:
 ; KNL-NEXT:    pushq %rax
-; KNL-NEXT:  Ltmp1:
+; KNL-NEXT:  Lcfi1:
 ; KNL-NEXT:    .cfi_def_cfa_offset 16
 ; KNL-NEXT:    vpcmpgtd %zmm1, %zmm0, %k1
 ; KNL-NEXT:    vpternlogd $255, %zmm0, %zmm0, %zmm0
 ; KNL-NEXT:    vmovdqa32 %zmm0, %zmm0 {%k1} {z}
 ; KNL-NEXT:    vpmovdb %zmm0, %xmm0
 ; KNL-NEXT:    callq _func16xi1
 ; KNL-NEXT:    vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
 ; KNL-NEXT:    vpslld $31, %zmm0, %zmm0
 ; KNL-NEXT:    vpsrad $31, %zmm0, %zmm0
 ; KNL-NEXT:    popq %rax
 ; KNL-NEXT:    retq
 ;
 ; SKX-LABEL: test6:
 ; SKX:       ## BB#0:
 ; SKX-NEXT:    pushq %rax
-; SKX-NEXT:  Ltmp1:
+; SKX-NEXT:  Lcfi1:
 ; SKX-NEXT:    .cfi_def_cfa_offset 16
 ; SKX-NEXT:    vpcmpgtd %zmm1, %zmm0, %k0
 ; SKX-NEXT:    vpmovm2b %k0, %xmm0
 ; SKX-NEXT:    callq _func16xi1
 ; SKX-NEXT:    vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
 ; SKX-NEXT:    vpslld $31, %zmm0, %zmm0
 ; SKX-NEXT:    vpsrad $31, %zmm0, %zmm0
 ; SKX-NEXT:    popq %rax
 ; SKX-NEXT:    retq
 ;
 ; KNL_X32-LABEL: test6:
 ; KNL_X32:       ## BB#0:
 ; KNL_X32-NEXT:    subl $12, %esp
-; KNL_X32-NEXT:  Ltmp1:
+; KNL_X32-NEXT:  Lcfi1:
 ; KNL_X32-NEXT:    .cfi_def_cfa_offset 16
 ; KNL_X32-NEXT:    vpcmpgtd %zmm1, %zmm0, %k1
 ; KNL_X32-NEXT:    vpternlogd $255, %zmm0, %zmm0, %zmm0
 ; KNL_X32-NEXT:    vmovdqa32 %zmm0, %zmm0 {%k1} {z}
 ; KNL_X32-NEXT:    vpmovdb %zmm0, %xmm0
 ; KNL_X32-NEXT:    calll _func16xi1
 ; KNL_X32-NEXT:    vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
 ; KNL_X32-NEXT:    vpslld $31, %zmm0, %zmm0
 ; KNL_X32-NEXT:    vpsrad $31, %zmm0, %zmm0
 ; KNL_X32-NEXT:    addl $12, %esp
 ; KNL_X32-NEXT:    retl
   %cmpRes = icmp sgt <16 x i32>%a, %b
   %resi = call <16 x i1> @func16xi1(<16 x i1> %cmpRes)
   %res = sext <16 x i1>%resi to <16 x i32>
   ret <16 x i32> %res
 }
 
 declare <4 x i1> @func4xi1(<4 x i1> %a)
 
 define <4 x i32> @test7(<4 x i32>%a, <4 x i32>%b) {
 ; KNL-LABEL: test7:
 ; KNL:       ## BB#0:
 ; KNL-NEXT:    pushq %rax
-; KNL-NEXT:  Ltmp2:
+; KNL-NEXT:  Lcfi2:
 ; KNL-NEXT:    .cfi_def_cfa_offset 16
 ; KNL-NEXT:    vpcmpgtd %xmm1, %xmm0, %xmm0
 ; KNL-NEXT:    callq _func4xi1
 ; KNL-NEXT:    vpslld $31, %xmm0, %xmm0
 ; KNL-NEXT:    vpsrad $31, %xmm0, %xmm0
 ; KNL-NEXT:    popq %rax
 ; KNL-NEXT:    retq
 ;
 ; SKX-LABEL: test7:
 ; SKX:       ## BB#0:
 ; SKX-NEXT:    pushq %rax
-; SKX-NEXT:  Ltmp2:
+; SKX-NEXT:  Lcfi2:
 ; SKX-NEXT:    .cfi_def_cfa_offset 16
 ; SKX-NEXT:    vpcmpgtd %xmm1, %xmm0, %k0
 ; SKX-NEXT:    vpmovm2d %k0, %xmm0
 ; SKX-NEXT:    callq _func4xi1
 ; SKX-NEXT:    vpslld $31, %xmm0, %xmm0
 ; SKX-NEXT:    vpsrad $31, %xmm0, %xmm0
 ; SKX-NEXT:    popq %rax
 ; SKX-NEXT:    retq
 ;
 ; KNL_X32-LABEL: test7:
 ; KNL_X32:       ## BB#0:
 ; KNL_X32-NEXT:    subl $12, %esp
-; KNL_X32-NEXT:  Ltmp2:
+; KNL_X32-NEXT:  Lcfi2:
 ; KNL_X32-NEXT:    .cfi_def_cfa_offset 16
 ; KNL_X32-NEXT:    vpcmpgtd %xmm1, %xmm0, %xmm0
 ; KNL_X32-NEXT:    calll _func4xi1
 ; KNL_X32-NEXT:    vpslld $31, %xmm0, %xmm0
 ; KNL_X32-NEXT:    vpsrad $31, %xmm0, %xmm0
 ; KNL_X32-NEXT:    addl $12, %esp
 ; KNL_X32-NEXT:    retl
   %cmpRes = icmp sgt <4 x i32>%a, %b
   %resi = call <4 x i1> @func4xi1(<4 x i1> %cmpRes)
   %res = sext <4 x i1>%resi to <4 x i32>
   ret <4 x i32> %res
 }
 
 define <8 x i1> @test7a(<8 x i32>%a, <8 x i32>%b) {
 ; KNL-LABEL: test7a:
 ; KNL:       ## BB#0:
 ; KNL-NEXT:    pushq %rax
-; KNL-NEXT:  Ltmp3:
+; KNL-NEXT:  Lcfi3:
 ; KNL-NEXT:    .cfi_def_cfa_offset 16
 ; KNL-NEXT:    vpcmpgtd %ymm1, %ymm0, %ymm0
 ; KNL-NEXT:    vpmovdw %zmm0, %ymm0
 ; KNL-NEXT:    ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
 ; KNL-NEXT:    callq _func8xi1
 ; KNL-NEXT:    vpmovsxwq %xmm0, %zmm0
 ; KNL-NEXT:    vpsllq $63, %zmm0, %zmm0
 ; KNL-NEXT:    movb $85, %al
 ; KNL-NEXT:    kmovw %eax, %k1
 ; KNL-NEXT:    vptestmq %zmm0, %zmm0, %k1 {%k1}
 ; KNL-NEXT:    vpternlogd $255, %zmm0, %zmm0, %zmm0
 ; KNL-NEXT:    vmovdqa64 %zmm0, %zmm0 {%k1} {z}
 ; KNL-NEXT:    vpmovqw %zmm0, %xmm0
 ; KNL-NEXT:    popq %rax
 ; KNL-NEXT:    retq
 ;
 ; SKX-LABEL: test7a:
 ; SKX:       ## BB#0:
 ; SKX-NEXT:    pushq %rax
-; SKX-NEXT:  Ltmp3:
+; SKX-NEXT:  Lcfi3:
 ; SKX-NEXT:    .cfi_def_cfa_offset 16
 ; SKX-NEXT:    vpcmpgtd %ymm1, %ymm0, %k0
 ; SKX-NEXT:    vpmovm2w %k0, %xmm0
 ; SKX-NEXT:    callq _func8xi1
 ; SKX-NEXT:    vpsllw $15, %xmm0, %xmm0
 ; SKX-NEXT:    vpmovw2m %xmm0, %k0
 ; SKX-NEXT:    movb $85, %al
 ; SKX-NEXT:    kmovb %eax, %k1
 ; SKX-NEXT:    kandb %k1, %k0, %k0
 ; SKX-NEXT:    vpmovm2w %k0, %xmm0
 ; SKX-NEXT:    popq %rax
 ; SKX-NEXT:    retq
 ;
 ; KNL_X32-LABEL: test7a:
 ; KNL_X32:       ## BB#0:
 ; KNL_X32-NEXT:    subl $12, %esp
-; KNL_X32-NEXT:  Ltmp3:
+; KNL_X32-NEXT:  Lcfi3:
 ; KNL_X32-NEXT:    .cfi_def_cfa_offset 16
 ; KNL_X32-NEXT:    vpcmpgtd %ymm1, %ymm0, %ymm0
 ; KNL_X32-NEXT:    vpmovdw %zmm0, %ymm0
 ; KNL_X32-NEXT:    ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
 ; KNL_X32-NEXT:    calll _func8xi1
 ; KNL_X32-NEXT:    vpmovsxwq %xmm0, %zmm0
 ; KNL_X32-NEXT:    vpsllq $63, %zmm0, %zmm0
 ; KNL_X32-NEXT:    movb $85, %al
; KNL_X32-NEXT:    retl
   %c = icmp sgt i32 %a, %b
   ret i1 %c
 }
 
 define i32 @test12(i32 %a1, i32 %a2, i32 %b1) {
 ; ALL_X64-LABEL: test12:
 ; ALL_X64:       ## BB#0:
 ; ALL_X64-NEXT:    pushq %rbp
-; ALL_X64-NEXT:  Ltmp4:
+; ALL_X64-NEXT:  Lcfi4:
 ; ALL_X64-NEXT:    .cfi_def_cfa_offset 16
 ; ALL_X64-NEXT:    pushq %r14
-; ALL_X64-NEXT:  Ltmp5:
+; ALL_X64-NEXT:  Lcfi5:
 ; ALL_X64-NEXT:    .cfi_def_cfa_offset 24
 ; ALL_X64-NEXT:    pushq %rbx
-; ALL_X64-NEXT:  Ltmp6:
+; ALL_X64-NEXT:  Lcfi6:
 ; ALL_X64-NEXT:    .cfi_def_cfa_offset 32
-; ALL_X64-NEXT:  Ltmp7:
+; ALL_X64-NEXT:  Lcfi7:
 ; ALL_X64-NEXT:    .cfi_offset %rbx, -32
-; ALL_X64-NEXT:  Ltmp8:
+; ALL_X64-NEXT:  Lcfi8:
 ; ALL_X64-NEXT:    .cfi_offset %r14, -24
-; ALL_X64-NEXT:  Ltmp9:
+; ALL_X64-NEXT:  Lcfi9:
 ; ALL_X64-NEXT:    .cfi_offset %rbp, -16
 ; ALL_X64-NEXT:    movl %esi, %r14d
 ; ALL_X64-NEXT:    movl %edi, %ebp
 ; ALL_X64-NEXT:    movl %edx, %esi
 ; ALL_X64-NEXT:    callq _test11
 ; ALL_X64-NEXT:    movzbl %al, %ebx
 ; ALL_X64-NEXT:    movl %ebp, %edi
 ; ALL_X64-NEXT:    movl %r14d, %esi
 ; ALL_X64-NEXT:    movl %ebx, %edx
 ; ALL_X64-NEXT:    callq _test10
 ; ALL_X64-NEXT:    xorl %ecx, %ecx
 ; ALL_X64-NEXT:    testb $1, %bl
 ; ALL_X64-NEXT:    cmovel %ecx, %eax
 ; ALL_X64-NEXT:    popq %rbx
 ; ALL_X64-NEXT:    popq %r14
 ; ALL_X64-NEXT:    popq %rbp
 ; ALL_X64-NEXT:    retq
 ;
 ; KNL_X32-LABEL: test12:
 ; KNL_X32:       ## BB#0:
 ; KNL_X32-NEXT:    pushl %ebx
-; KNL_X32-NEXT:  Ltmp4:
+; KNL_X32-NEXT:  Lcfi4:
 ; KNL_X32-NEXT:    .cfi_def_cfa_offset 8
 ; KNL_X32-NEXT:    pushl %edi
-; KNL_X32-NEXT:  Ltmp5:
+; KNL_X32-NEXT:  Lcfi5:
 ; KNL_X32-NEXT:    .cfi_def_cfa_offset 12
 ; KNL_X32-NEXT:    pushl %esi
-; KNL_X32-NEXT:  Ltmp6:
+; KNL_X32-NEXT:  Lcfi6:
 ; KNL_X32-NEXT:    .cfi_def_cfa_offset 16
 ; KNL_X32-NEXT:    subl $16, %esp
-; KNL_X32-NEXT:  Ltmp7:
+; KNL_X32-NEXT:  Lcfi7:
 ; KNL_X32-NEXT:    .cfi_def_cfa_offset 32
-; KNL_X32-NEXT:  Ltmp8:
+; KNL_X32-NEXT:  Lcfi8:
 ; KNL_X32-NEXT:    .cfi_offset %esi, -16
-; KNL_X32-NEXT:  Ltmp9:
+; KNL_X32-NEXT:  Lcfi9:
 ; KNL_X32-NEXT:    .cfi_offset %edi, -12
-; KNL_X32-NEXT:  Ltmp10:
+; KNL_X32-NEXT:  Lcfi10:
 ; KNL_X32-NEXT:    .cfi_offset %ebx, -8
 ; KNL_X32-NEXT:    movl {{[0-9]+}}(%esp), %esi
 ; KNL_X32-NEXT:    movl {{[0-9]+}}(%esp), %edi
 ; KNL_X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; KNL_X32-NEXT:    movl %eax, {{[0-9]+}}(%esp)
 ; KNL_X32-NEXT:    movl %edi, (%esp)
 ; KNL_X32-NEXT:    calll _test11
 ; KNL_X32-NEXT:    movl %eax, %ebx

test/CodeGen/X86/avx512-fsel.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -O0 -mattr=+avx512f < %s | FileCheck %s
 
 target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-apple-macosx10.11.0"
 
 define i32 @test(float %a, float %b)  {
 ; CHECK-LABEL: test:
 ; CHECK:       ## BB#0:
 ; CHECK-NEXT:    pushq %rax
-; CHECK-NEXT:  Ltmp0:
+; CHECK-NEXT:  Lcfi0:
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    movb $1, %al
 ; CHECK-NEXT:    vucomiss %xmm1, %xmm0
 ; CHECK-NEXT:    setnp %cl
 ; CHECK-NEXT:    sete %dl
 ; CHECK-NEXT:    setp %sil
 ; CHECK-NEXT:    setne %dil
 ; CHECK-NEXT:    andb %cl, %dl

test/CodeGen/X86/avx512-insert-extract.ll

; SKX-NEXT:    retq
   %r = insertelement <32 x i8> %x, i8 %y, i32 20
   ret <32 x i8> %r
 }
 
 define i32 @test_insertelement_v32i1(i32 %a, i32 %b, <32 x i32> %x , <32 x i32> %y) {
 ; KNL-LABEL: test_insertelement_v32i1:
 ; KNL:       ## BB#0:
 ; KNL-NEXT:    pushq %rbp
-; KNL-NEXT:  Ltmp0:
+; KNL-NEXT:  Lcfi0:
 ; KNL-NEXT:    .cfi_def_cfa_offset 16
-; KNL-NEXT:  Ltmp1:
+; KNL-NEXT:  Lcfi1:
 ; KNL-NEXT:    .cfi_offset %rbp, -16
 ; KNL-NEXT:    movq %rsp, %rbp
-; KNL-NEXT:  Ltmp2:
+; KNL-NEXT:  Lcfi2:
 ; KNL-NEXT:    .cfi_def_cfa_register %rbp
 ; KNL-NEXT:    andq $-32, %rsp
 ; KNL-NEXT:    subq $32, %rsp
 ; KNL-NEXT:    cmpl %esi, %edi
 ; KNL-NEXT:    vpcmpltud %zmm3, %zmm1, %k0
 ; KNL-NEXT:    kshiftlw $14, %k0, %k1
 ; KNL-NEXT:    kshiftrw $15, %k1, %k1
 ; KNL-NEXT:    kmovw %k1, %eax

test/CodeGen/X86/avx512-mask-op.ll

; SKX-NEXT:    retq
   ret <16 x i1> %c
 }
 
 define <64 x i8> @test16(i64 %x) {
 ;
 ; KNL-LABEL: test16:
 ; KNL:       ## BB#0:
 ; KNL-NEXT:    pushq %rbp
-; KNL-NEXT:  Ltmp0:
+; KNL-NEXT:  Lcfi0:
 ; KNL-NEXT:    .cfi_def_cfa_offset 16
-; KNL-NEXT:  Ltmp1:
+; KNL-NEXT:  Lcfi1:
 ; KNL-NEXT:    .cfi_offset %rbp, -16
 ; KNL-NEXT:    movq %rsp, %rbp
-; KNL-NEXT:  Ltmp2:
+; KNL-NEXT:  Lcfi2:
 ; KNL-NEXT:    .cfi_def_cfa_register %rbp
 ; KNL-NEXT:    andq $-32, %rsp
 ; KNL-NEXT:    subq $64, %rsp
 ; KNL-NEXT:    movl %edi, (%rsp)
 ; KNL-NEXT:    shrq $32, %rdi
 ; KNL-NEXT:    movl %edi, {{[0-9]+}}(%rsp)
 ; KNL-NEXT:    vpternlogd $255, %zmm0, %zmm0, %zmm0
 ; KNL-NEXT:    kmovw (%rsp), %k1
; SKX-NEXT:    retq
   ret <64 x i8>%c
 }
 
 define <64 x i8> @test17(i64 %x, i32 %y, i32 %z) {
 ;
 ; KNL-LABEL: test17:
 ; KNL:       ## BB#0:
 ; KNL-NEXT:    pushq %rbp
-; KNL-NEXT:  Ltmp3:
+; KNL-NEXT:  Lcfi3:
 ; KNL-NEXT:    .cfi_def_cfa_offset 16
-; KNL-NEXT:  Ltmp4:
+; KNL-NEXT:  Lcfi4:
 ; KNL-NEXT:    .cfi_offset %rbp, -16
 ; KNL-NEXT:    movq %rsp, %rbp
-; KNL-NEXT:  Ltmp5:
+; KNL-NEXT:  Lcfi5:
 ; KNL-NEXT:    .cfi_def_cfa_register %rbp
 ; KNL-NEXT:    andq $-32, %rsp
 ; KNL-NEXT:    subq $64, %rsp
 ; KNL-NEXT:    movl %edi, (%rsp)
 ; KNL-NEXT:    shrq $32, %rdi
 ; KNL-NEXT:    movl %edi, {{[0-9]+}}(%rsp)
 ; KNL-NEXT:    vpternlogd $255, %zmm1, %zmm1, %zmm1
 ; KNL-NEXT:    kmovw (%rsp), %k1
End:
   ret void
 }
 
 define void @ktest_2(<32 x float> %in, float * %base) {
 ;
 ; KNL-LABEL: ktest_2:
 ; KNL:       ## BB#0:
 ; KNL-NEXT:    pushq %rbp
-; KNL-NEXT:  Ltmp6:
+; KNL-NEXT:  Lcfi6:
 ; KNL-NEXT:    .cfi_def_cfa_offset 16
-; KNL-NEXT:  Ltmp7:
+; KNL-NEXT:  Lcfi7:
 ; KNL-NEXT:    .cfi_offset %rbp, -16
 ; KNL-NEXT:    movq %rsp, %rbp
-; KNL-NEXT:  Ltmp8:
+; KNL-NEXT:  Lcfi8:
 ; KNL-NEXT:    .cfi_def_cfa_register %rbp
 ; KNL-NEXT:    andq $-32, %rsp
 ; KNL-NEXT:    subq $32, %rsp
 ; KNL-NEXT:    vmovups (%rdi), %zmm2
 ; KNL-NEXT:    vmovups 64(%rdi), %zmm3
 ; KNL-NEXT:    vcmpltps %zmm1, %zmm3, %k1
 ; KNL-NEXT:    kshiftlw $14, %k1, %k0
 ; KNL-NEXT:    kshiftrw $15, %k0, %k0

 }
 
 
 define void @store_64i1(<64 x i1>* %a, <64 x i1> %v) {
 ;
 ; KNL-LABEL: store_64i1:
 ; KNL:       ## BB#0:
 ; KNL-NEXT:    pushq %rbp
-; KNL-NEXT:  Ltmp9:
+; KNL-NEXT:  Lcfi9:
 ; KNL-NEXT:    .cfi_def_cfa_offset 16
 ; KNL-NEXT:    pushq %r15
-; KNL-NEXT:  Ltmp10:
+; KNL-NEXT:  Lcfi10:
 ; KNL-NEXT:    .cfi_def_cfa_offset 24
 ; KNL-NEXT:    pushq %r14
-; KNL-NEXT:  Ltmp11:
+; KNL-NEXT:  Lcfi11:
 ; KNL-NEXT:    .cfi_def_cfa_offset 32
 ; KNL-NEXT:    pushq %r13
-; KNL-NEXT:  Ltmp12:
+; KNL-NEXT:  Lcfi12:
 ; KNL-NEXT:    .cfi_def_cfa_offset 40
 ; KNL-NEXT:    pushq %r12
-; KNL-NEXT:  Ltmp13:
+; KNL-NEXT:  Lcfi13:
 ; KNL-NEXT:    .cfi_def_cfa_offset 48
 ; KNL-NEXT:    pushq %rbx
-; KNL-NEXT:  Ltmp14:
+; KNL-NEXT:  Lcfi14:
 ; KNL-NEXT:    .cfi_def_cfa_offset 56
-; KNL-NEXT:  Ltmp15:
+; KNL-NEXT:  Lcfi15:
 ; KNL-NEXT:    .cfi_offset %rbx, -56
-; KNL-NEXT:  Ltmp16:
+; KNL-NEXT:  Lcfi16:
 ; KNL-NEXT:    .cfi_offset %r12, -48
-; KNL-NEXT:  Ltmp17:
+; KNL-NEXT:  Lcfi17:
 ; KNL-NEXT:    .cfi_offset %r13, -40
-; KNL-NEXT:  Ltmp18:
+; KNL-NEXT:  Lcfi18:
 ; KNL-NEXT:    .cfi_offset %r14, -32
-; KNL-NEXT:  Ltmp19:
+; KNL-NEXT:  Lcfi19:
 ; KNL-NEXT:    .cfi_offset %r15, -24
-; KNL-NEXT:  Ltmp20:
+; KNL-NEXT:  Lcfi20:
 ; KNL-NEXT:    .cfi_offset %rbp, -16
 ; KNL-NEXT:    vpmovsxbd %xmm0, %zmm0
 ; KNL-NEXT:    vpslld $31, %zmm0, %zmm0
 ; KNL-NEXT:    vpmovsxbd %xmm1, %zmm1
 ; KNL-NEXT:    vpslld $31, %zmm1, %zmm1
 ; KNL-NEXT:    vpmovsxbd %xmm2, %zmm2
 ; KNL-NEXT:    vpslld $31, %zmm2, %zmm2
 ; KNL-NEXT:    vpmovsxbd %xmm3, %zmm3

test/CodeGen/X86/avx512-mask-spills.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=skx | FileCheck %s --check-prefix=CHECK --check-prefix=SKX
 
 declare void @f()
 define <4 x i1> @test_4i1(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: test_4i1:
 ; CHECK:       ## BB#0:
 ; CHECK-NEXT:    pushq %rax
-; CHECK-NEXT:  Ltmp0:
+; CHECK-NEXT:  Lcfi0:
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    vpcmpnleud %xmm1, %xmm0, %k0
 ; CHECK-NEXT:    kmovw %k0, {{[0-9]+}}(%rsp) ## 2-byte Spill
 ; CHECK-NEXT:    vpcmpgtd %xmm1, %xmm0, %k0
 ; CHECK-NEXT:    kmovw %k0, {{[0-9]+}}(%rsp) ## 2-byte Spill
 ; CHECK-NEXT:    callq _f
 ; CHECK-NEXT:    kmovw {{[0-9]+}}(%rsp), %k0 ## 2-byte Reload
 ; CHECK-NEXT:    kmovw {{[0-9]+}}(%rsp), %k1 ## 2-byte Reload
 ; CHECK-NEXT:    korw %k1, %k0, %k0
 ; CHECK-NEXT:    vpmovm2d %k0, %xmm0
 ; CHECK-NEXT:    popq %rax
 ; CHECK-NEXT:    retq
 
   %cmp_res = icmp ugt <4 x i32> %a, %b
   %cmp_res2 = icmp sgt <4 x i32> %a, %b
   call void @f()
   %res = or <4 x i1> %cmp_res, %cmp_res2
   ret <4 x i1> %res
 }
 
 define <8 x i1> @test_8i1(<8 x i32> %a, <8 x i32> %b) {
 ; CHECK-LABEL: test_8i1:
 ; CHECK:       ## BB#0:
 ; CHECK-NEXT:    pushq %rax
-; CHECK-NEXT:  Ltmp1:
+; CHECK-NEXT:  Lcfi1:
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    vpcmpnleud %ymm1, %ymm0, %k0
 ; CHECK-NEXT:    kmovw %k0, {{[0-9]+}}(%rsp) ## 2-byte Spill
 ; CHECK-NEXT:    vpcmpgtd %ymm1, %ymm0, %k0
 ; CHECK-NEXT:    kmovw %k0, {{[0-9]+}}(%rsp) ## 2-byte Spill
 ; CHECK-NEXT:    callq _f
 ; CHECK-NEXT:    kmovw {{[0-9]+}}(%rsp), %k0 ## 2-byte Reload
 ; CHECK-NEXT:    kmovw {{[0-9]+}}(%rsp), %k1 ## 2-byte Reload
 ; CHECK-NEXT:    korb %k1, %k0, %k0
 ; CHECK-NEXT:    vpmovm2w %k0, %xmm0
 ; CHECK-NEXT:    popq %rax
 ; CHECK-NEXT:    retq
 
   %cmp_res = icmp ugt <8 x i32> %a, %b
   %cmp_res2 = icmp sgt <8 x i32> %a, %b
   call void @f()
   %res = or <8 x i1> %cmp_res, %cmp_res2
   ret <8 x i1> %res
 }
 
 define <16 x i1> @test_16i1(<16 x i32> %a, <16 x i32> %b) {
 ; CHECK-LABEL: test_16i1:
 ; CHECK:       ## BB#0:
 ; CHECK-NEXT:    pushq %rax
-; CHECK-NEXT:  Ltmp2:
+; CHECK-NEXT:  Lcfi2:
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    vpcmpnleud %zmm1, %zmm0, %k0
 ; CHECK-NEXT:    kmovw %k0, {{[0-9]+}}(%rsp) ## 2-byte Spill
 ; CHECK-NEXT:    vpcmpgtd %zmm1, %zmm0, %k0
 ; CHECK-NEXT:    kmovw %k0, {{[0-9]+}}(%rsp) ## 2-byte Spill
 ; CHECK-NEXT:    callq _f
 ; CHECK-NEXT:    kmovw {{[0-9]+}}(%rsp), %k0 ## 2-byte Reload
 ; CHECK-NEXT:    kmovw {{[0-9]+}}(%rsp), %k1 ## 2-byte Reload
 ; CHECK-NEXT:    korw %k1, %k0, %k0
 ; CHECK-NEXT:    vpmovm2b %k0, %xmm0
 ; CHECK-NEXT:    popq %rax
 ; CHECK-NEXT:    retq
   %cmp_res = icmp ugt <16 x i32> %a, %b
   %cmp_res2 = icmp sgt <16 x i32> %a, %b
   call void @f()
   %res = or <16 x i1> %cmp_res, %cmp_res2
   ret <16 x i1> %res
 }
 
 define <32 x i1> @test_32i1(<32 x i16> %a, <32 x i16> %b) {
 ; CHECK-LABEL: test_32i1:
 ; CHECK:       ## BB#0:
 ; CHECK-NEXT:    pushq %rax
-; CHECK-NEXT:  Ltmp3:
+; CHECK-NEXT:  Lcfi3:
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    vpcmpnleuw %zmm1, %zmm0, %k0
 ; CHECK-NEXT:    kmovd %k0, {{[0-9]+}}(%rsp) ## 4-byte Spill
 ; CHECK-NEXT:    vpcmpgtw %zmm1, %zmm0, %k0
 ; CHECK-NEXT:    kmovd %k0, (%rsp) ## 4-byte Spill
 ; CHECK-NEXT:    callq _f
 ; CHECK-NEXT:    kmovd {{[0-9]+}}(%rsp), %k0 ## 4-byte Reload
 ; CHECK-NEXT:    kmovd (%rsp), %k1 ## 4-byte Reload
 ; CHECK-NEXT:    kord %k1, %k0, %k0
 ; CHECK-NEXT:    vpmovm2b %k0, %ymm0
 ; CHECK-NEXT:    popq %rax
 ; CHECK-NEXT:    retq
   %cmp_res = icmp ugt <32 x i16> %a, %b
   %cmp_res2 = icmp sgt <32 x i16> %a, %b
   call void @f()
   %res = or <32 x i1> %cmp_res, %cmp_res2
   ret <32 x i1> %res
 }
 
 define <64 x i1> @test_64i1(<64 x i8> %a, <64 x i8> %b) {
 ; CHECK-LABEL: test_64i1:
 ; CHECK:       ## BB#0:
 ; CHECK-NEXT:    subq $24, %rsp
-; CHECK-NEXT:  Ltmp4:
+; CHECK-NEXT:  Lcfi4:
 ; CHECK-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-NEXT:    vpcmpnleub %zmm1, %zmm0, %k0
 ; CHECK-NEXT:    kmovq %k0, {{[0-9]+}}(%rsp) ## 8-byte Spill
 ; CHECK-NEXT:    vpcmpgtb %zmm1, %zmm0, %k0
 ; CHECK-NEXT:    kmovq %k0, {{[0-9]+}}(%rsp) ## 8-byte Spill
 ; CHECK-NEXT:    callq _f
 ; CHECK-NEXT:    kmovq {{[0-9]+}}(%rsp), %k0 ## 8-byte Reload
 ; CHECK-NEXT:    kmovq {{[0-9]+}}(%rsp), %k1 ## 8-byte Reload

test/CodeGen/X86/avx512-vbroadcast.ll

; ALL-NEXT:    retq
   ret <8 x i64>%res
 }
 
 declare void @func_f32(float)
 define <16 x float> @broadcast_ss_spill(float %x) {
 ; ALL-LABEL: broadcast_ss_spill:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    pushq %rax
-; ALL-NEXT:  .Ltmp0:
+; ALL-NEXT:  .Lcfi0:
 ; ALL-NEXT:    .cfi_def_cfa_offset 16
 ; ALL-NEXT:    vaddss %xmm0, %xmm0, %xmm0
 ; ALL-NEXT:    vmovss %xmm0, {{[0-9]+}}(%rsp) # 4-byte Spill
 ; ALL-NEXT:    callq func_f32
 ; ALL-NEXT:    vbroadcastss {{[0-9]+}}(%rsp), %zmm0 # 4-byte Folded Reload
 ; ALL-NEXT:    popq %rax
 ; ALL-NEXT:    retq
   %a  = fadd float %x, %x
   call void @func_f32(float %a)
   %b = insertelement <16 x float> undef, float %a, i32 0
   %c = shufflevector <16 x float> %b, <16 x float> undef, <16 x i32> zeroinitializer
   ret <16 x float> %c
 }
 
 declare void @func_f64(double)
 define <8 x double> @broadcast_sd_spill(double %x) {
 ; ALL-LABEL: broadcast_sd_spill:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    pushq %rax
-; ALL-NEXT:  .Ltmp1:
+; ALL-NEXT:  .Lcfi1:
 ; ALL-NEXT:    .cfi_def_cfa_offset 16
 ; ALL-NEXT:    vaddsd %xmm0, %xmm0, %xmm0
 ; ALL-NEXT:    vmovsd %xmm0, (%rsp) # 8-byte Spill
 ; ALL-NEXT:    callq func_f64
 ; ALL-NEXT:    vbroadcastsd (%rsp), %zmm0 # 8-byte Folded Reload
 ; ALL-NEXT:    popq %rax
 ; ALL-NEXT:    retq
   %a  = fadd double %x, %x
   call void @func_f64(double %a)
   %b = insertelement <8 x double> undef, double %a, i32 0
   %c = shufflevector <8 x double> %b, <8 x double> undef, <8 x i32> zeroinitializer
   ret <8 x double> %c
 }

test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll

 ; AVX512BW:       ## BB#0:
 ; AVX512BW-NEXT:    vpcmpeqb %zmm1, %zmm0, %k0
 ; AVX512BW-NEXT:    kmovq %k0, %rax
 ; AVX512BW-NEXT:    retq
 ;
 ; AVX512F-32-LABEL: test_pcmpeq_b:
 ; AVX512F-32:       # BB#0:
 ; AVX512F-32-NEXT:    subl $12, %esp
-; AVX512F-32-NEXT:  .Ltmp0:
+; AVX512F-32-NEXT:  .Lcfi0:
 ; AVX512F-32-NEXT:    .cfi_def_cfa_offset 16
 ; AVX512F-32-NEXT:    vpcmpeqb %zmm1, %zmm0, %k0
 ; AVX512F-32-NEXT:    kmovq %k0, (%esp)
 ; AVX512F-32-NEXT:    movl (%esp), %eax
 ; AVX512F-32-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; AVX512F-32-NEXT:    addl $12, %esp
 ; AVX512F-32-NEXT:    retl
   %res = call i64 @llvm.x86.avx512.mask.pcmpeq.b.512(<64 x i8> %a, <64 x i8> %b, i64 -1)
   ret i64 %res
 }
 
 define i64 @test_mask_pcmpeq_b(<64 x i8> %a, <64 x i8> %b, i64 %mask) {
 ; AVX512BW-LABEL: test_mask_pcmpeq_b:
 ; AVX512BW:       ## BB#0:
 ; AVX512BW-NEXT:    kmovq %rdi, %k1
 ; AVX512BW-NEXT:    vpcmpeqb %zmm1, %zmm0, %k0 {%k1}
 ; AVX512BW-NEXT:    kmovq %k0, %rax
 ; AVX512BW-NEXT:    retq
 ;
 ; AVX512F-32-LABEL: test_mask_pcmpeq_b:
 ; AVX512F-32:       # BB#0:
 ; AVX512F-32-NEXT:    subl $12, %esp
-; AVX512F-32-NEXT:  .Ltmp1:
+; AVX512F-32-NEXT:  .Lcfi1:
 ; AVX512F-32-NEXT:    .cfi_def_cfa_offset 16
 ; AVX512F-32-NEXT:    kmovq {{[0-9]+}}(%esp), %k1
 ; AVX512F-32-NEXT:    vpcmpeqb %zmm1, %zmm0, %k0 {%k1}
 ; AVX512F-32-NEXT:    kmovq %k0, (%esp)
 ; AVX512F-32-NEXT:    movl (%esp), %eax
 ; AVX512F-32-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; AVX512F-32-NEXT:    addl $12, %esp
 ; AVX512F-32-NEXT:    retl

 ; AVX512BW:       ## BB#0:
 ; AVX512BW-NEXT:    vpcmpgtb %zmm1, %zmm0, %k0
 ; AVX512BW-NEXT:    kmovq %k0, %rax
 ; AVX512BW-NEXT:    retq
 ;
 ; AVX512F-32-LABEL: test_pcmpgt_b:
 ; AVX512F-32:       # BB#0:
 ; AVX512F-32-NEXT:    subl $12, %esp
-; AVX512F-32-NEXT:  .Ltmp2:
+; AVX512F-32-NEXT:  .Lcfi2:
 ; AVX512F-32-NEXT:    .cfi_def_cfa_offset 16
 ; AVX512F-32-NEXT:    vpcmpgtb %zmm1, %zmm0, %k0
 ; AVX512F-32-NEXT:    kmovq %k0, (%esp)
 ; AVX512F-32-NEXT:    movl (%esp), %eax
 ; AVX512F-32-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; AVX512F-32-NEXT:    addl $12, %esp
 ; AVX512F-32-NEXT:    retl
   %res = call i64 @llvm.x86.avx512.mask.pcmpgt.b.512(<64 x i8> %a, <64 x i8> %b, i64 -1)
   ret i64 %res
 }
 
 define i64 @test_mask_pcmpgt_b(<64 x i8> %a, <64 x i8> %b, i64 %mask) {
 ; AVX512BW-LABEL: test_mask_pcmpgt_b:
 ; AVX512BW:       ## BB#0:
 ; AVX512BW-NEXT:    kmovq %rdi, %k1
 ; AVX512BW-NEXT:    vpcmpgtb %zmm1, %zmm0, %k0 {%k1}
 ; AVX512BW-NEXT:    kmovq %k0, %rax
 ; AVX512BW-NEXT:    retq
 ;
 ; AVX512F-32-LABEL: test_mask_pcmpgt_b:
 ; AVX512F-32:       # BB#0:
 ; AVX512F-32-NEXT:    subl $12, %esp
-; AVX512F-32-NEXT:  .Ltmp3:
+; AVX512F-32-NEXT:  .Lcfi3:
 ; AVX512F-32-NEXT:    .cfi_def_cfa_offset 16
 ; AVX512F-32-NEXT:    kmovq {{[0-9]+}}(%esp), %k1
 ; AVX512F-32-NEXT:    vpcmpgtb %zmm1, %zmm0, %k0 {%k1}
 ; AVX512F-32-NEXT:    kmovq %k0, (%esp)
 ; AVX512F-32-NEXT:    movl (%esp), %eax
 ; AVX512F-32-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; AVX512F-32-NEXT:    addl $12, %esp
 ; AVX512F-32-NEXT:    retl

test/CodeGen/X86/avx512bw-intrinsics.ll

 ; AVX512BW-NEXT:    vpcmpordb %zmm1, %zmm0, %k0
 ; AVX512BW-NEXT:    kmovq %k0, %rax
 ; AVX512BW-NEXT:    addq %rdx, %rax
 ; AVX512BW-NEXT:    retq
 ;
 ; AVX512F-32-LABEL: test_cmp_b_512:
 ; AVX512F-32:       # BB#0:
 ; AVX512F-32-NEXT:    subl $68, %esp
-; AVX512F-32-NEXT:  .Ltmp0:
+; AVX512F-32-NEXT:  .Lcfi0:
 ; AVX512F-32-NEXT:    .cfi_def_cfa_offset 72
 ; AVX512F-32-NEXT:    vpcmpeqb %zmm1, %zmm0, %k0
 ; AVX512F-32-NEXT:    kmovq %k0, {{[0-9]+}}(%esp)
 ; AVX512F-32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; AVX512F-32-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; AVX512F-32-NEXT:    vpcmpltb %zmm1, %zmm0, %k0
 ; AVX512F-32-NEXT:    kmovq %k0, {{[0-9]+}}(%esp)
 ; AVX512F-32-NEXT:    addl {{[0-9]+}}(%esp), %eax

 ; AVX512BW-NEXT:    vpcmpordb %zmm1, %zmm0, %k0 {%k1}
 ; AVX512BW-NEXT:    kmovq %k0, %rax
 ; AVX512BW-NEXT:    addq %rdx, %rax
 ; AVX512BW-NEXT:    retq
 ;
 ; AVX512F-32-LABEL: test_mask_cmp_b_512:
 ; AVX512F-32:       # BB#0:
 ; AVX512F-32-NEXT:    subl $68, %esp
-; AVX512F-32-NEXT:  .Ltmp1:
+; AVX512F-32-NEXT:  .Lcfi1:
 ; AVX512F-32-NEXT:    .cfi_def_cfa_offset 72
 ; AVX512F-32-NEXT:    kmovd {{[0-9]+}}(%esp), %k0
 ; AVX512F-32-NEXT:    kmovd {{[0-9]+}}(%esp), %k1
 ; AVX512F-32-NEXT:    kunpckdq %k0, %k1, %k1
 ; AVX512F-32-NEXT:    vpcmpeqb %zmm1, %zmm0, %k0 {%k1}
 ; AVX512F-32-NEXT:    kmovq %k0, (%esp)
 ; AVX512F-32-NEXT:    movl (%esp), %eax
 ; AVX512F-32-NEXT:    movl {{[0-9]+}}(%esp), %edx

 ; AVX512BW-NEXT:    vpcmpordub %zmm1, %zmm0, %k0
 ; AVX512BW-NEXT:    kmovq %k0, %rax
 ; AVX512BW-NEXT:    addq %rdx, %rax
 ; AVX512BW-NEXT:    retq
 ;
 ; AVX512F-32-LABEL: test_ucmp_b_512:
 ; AVX512F-32:       # BB#0:
 ; AVX512F-32-NEXT:    subl $68, %esp
-; AVX512F-32-NEXT:  .Ltmp2:
+; AVX512F-32-NEXT:  .Lcfi2:
 ; AVX512F-32-NEXT:    .cfi_def_cfa_offset 72
 ; AVX512F-32-NEXT:    vpcmpequb %zmm1, %zmm0, %k0
 ; AVX512F-32-NEXT:    kmovq %k0, {{[0-9]+}}(%esp)
 ; AVX512F-32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; AVX512F-32-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; AVX512F-32-NEXT:    vpcmpltub %zmm1, %zmm0, %k0
 ; AVX512F-32-NEXT:    kmovq %k0, {{[0-9]+}}(%esp)
 ; AVX512F-32-NEXT:    addl {{[0-9]+}}(%esp), %eax

 ; AVX512BW-NEXT:    vpcmpordub %zmm1, %zmm0, %k0 {%k1}
 ; AVX512BW-NEXT:    kmovq %k0, %rax
 ; AVX512BW-NEXT:    addq %rdx, %rax
 ; AVX512BW-NEXT:    retq
 ;
 ; AVX512F-32-LABEL: test_mask_x86_avx512_ucmp_b_512:
 ; AVX512F-32:       # BB#0:
 ; AVX512F-32-NEXT:    subl $68, %esp
-; AVX512F-32-NEXT:  .Ltmp3:
+; AVX512F-32-NEXT:  .Lcfi3:
 ; AVX512F-32-NEXT:    .cfi_def_cfa_offset 72
 ; AVX512F-32-NEXT:    kmovd {{[0-9]+}}(%esp), %k0
 ; AVX512F-32-NEXT:    kmovd {{[0-9]+}}(%esp), %k1
 ; AVX512F-32-NEXT:    kunpckdq %k0, %k1, %k1
 ; AVX512F-32-NEXT:    vpcmpequb %zmm1, %zmm0, %k0 {%k1}
 ; AVX512F-32-NEXT:    kmovq %k0, (%esp)
 ; AVX512F-32-NEXT:    movl (%esp), %eax
 ; AVX512F-32-NEXT:    movl {{[0-9]+}}(%esp), %edx

 ; AVX512BW-NEXT:    kmovq %rsi, %k1
 ; AVX512BW-NEXT:    kunpckdq %k1, %k0, %k0
 ; AVX512BW-NEXT:    kmovq %k0, %rax
 ; AVX512BW-NEXT:    retq
 ;
 ; AVX512F-32-LABEL: test_int_x86_avx512_kunpck_qd:
 ; AVX512F-32:       # BB#0:
 ; AVX512F-32-NEXT:    subl $12, %esp
-; AVX512F-32-NEXT:  .Ltmp4:
+; AVX512F-32-NEXT:  .Lcfi4:
 ; AVX512F-32-NEXT:    .cfi_def_cfa_offset 16
 ; AVX512F-32-NEXT:    kmovd {{[0-9]+}}(%esp), %k0
 ; AVX512F-32-NEXT:    kmovd {{[0-9]+}}(%esp), %k1
 ; AVX512F-32-NEXT:    kunpckdq %k0, %k1, %k0
 ; AVX512F-32-NEXT:    kmovq %k0, (%esp)
 ; AVX512F-32-NEXT:    movl (%esp), %eax
 ; AVX512F-32-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; AVX512F-32-NEXT:    addl $12, %esp

 ; AVX512BW:       ## BB#0:
 ; AVX512BW-NEXT:    vpmovb2m %zmm0, %k0
 ; AVX512BW-NEXT:    kmovq %k0, %rax
 ; AVX512BW-NEXT:    retq
 ;
 ; AVX512F-32-LABEL: test_int_x86_avx512_cvtb2mask_512:
 ; AVX512F-32:       # BB#0:
 ; AVX512F-32-NEXT:    subl $12, %esp
-; AVX512F-32-NEXT:  .Ltmp5:
+; AVX512F-32-NEXT:  .Lcfi5:
 ; AVX512F-32-NEXT:    .cfi_def_cfa_offset 16
 ; AVX512F-32-NEXT:    vpmovb2m %zmm0, %k0
 ; AVX512F-32-NEXT:    kmovq %k0, (%esp)
 ; AVX512F-32-NEXT:    movl (%esp), %eax
 ; AVX512F-32-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; AVX512F-32-NEXT:    addl $12, %esp
 ; AVX512F-32-NEXT:    retl
     %res = call i64 @llvm.x86.avx512.cvtb2mask.512(<64 x i8> %x0)

 ; AVX512BW-NEXT:    vptestmb %zmm1, %zmm0, %k0
 ; AVX512BW-NEXT:    kmovq %k0, %rax
 ; AVX512BW-NEXT:    addq %rcx, %rax
 ; AVX512BW-NEXT:    retq
 ;
 ; AVX512F-32-LABEL: test_int_x86_avx512_ptestm_b_512:
 ; AVX512F-32:       # BB#0:
 ; AVX512F-32-NEXT:    subl $20, %esp
-; AVX512F-32-NEXT:  .Ltmp6:
+; AVX512F-32-NEXT:  .Lcfi6:
 ; AVX512F-32-NEXT:    .cfi_def_cfa_offset 24
 ; AVX512F-32-NEXT:    kmovd {{[0-9]+}}(%esp), %k0
 ; AVX512F-32-NEXT:    kmovd {{[0-9]+}}(%esp), %k1
 ; AVX512F-32-NEXT:    kunpckdq %k0, %k1, %k1
 ; AVX512F-32-NEXT:    vptestmb %zmm1, %zmm0, %k0 {%k1}
 ; AVX512F-32-NEXT:    kmovq %k0, (%esp)
 ; AVX512F-32-NEXT:    vptestmb %zmm1, %zmm0, %k0
 ; AVX512F-32-NEXT:    kmovq %k0, {{[0-9]+}}(%esp)

 ; AVX512BW-NEXT:    vptestnmb %zmm1, %zmm0, %k0
 ; AVX512BW-NEXT:    kmovq %k0, %rax
 ; AVX512BW-NEXT:    addq %rcx, %rax
 ; AVX512BW-NEXT:    retq
 ;
 ; AVX512F-32-LABEL: test_int_x86_avx512_ptestnm_b_512:
 ; AVX512F-32:       # BB#0:
 ; AVX512F-32-NEXT:    subl $20, %esp
-; AVX512F-32-NEXT:  .Ltmp7:
+; AVX512F-32-NEXT:  .Lcfi7:
 ; AVX512F-32-NEXT:    .cfi_def_cfa_offset 24
 ; AVX512F-32-NEXT:    kmovd {{[0-9]+}}(%esp), %k0
 ; AVX512F-32-NEXT:    kmovd {{[0-9]+}}(%esp), %k1
 ; AVX512F-32-NEXT:    kunpckdq %k0, %k1, %k1
 ; AVX512F-32-NEXT:    vptestnmb %zmm1, %zmm0, %k0 {%k1}
 ; AVX512F-32-NEXT:    kmovq %k0, (%esp)
 ; AVX512F-32-NEXT:    vptestnmb %zmm1, %zmm0, %k0
 ; AVX512F-32-NEXT:    kmovq %k0, {{[0-9]+}}(%esp)

test/CodeGen/X86/avx512vl-intrinsics-fast-isel.ll

; X64-NEXT:    retq
   %res1 = bitcast <4 x i32> %res0 to <2 x i64>
   ret <2 x i64> %res1
 }
 
 define <2 x i64> @test_mm_mask_broadcastd_epi32(<2 x i64> %a0, i8 %a1, <2 x i64> %a2) {
 ; X32-LABEL: test_mm_mask_broadcastd_epi32:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Ltmp0:
+; X32-NEXT:  .Lcfi0:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $15, %al
 ; X32-NEXT:    movb %al, (%esp)
 ; X32-NEXT:    movzbl (%esp), %eax
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vpbroadcastd %xmm1, %xmm0 {%k1}
 ; X32-NEXT:    popl %eax
; X64-NEXT:    retq
   %res2 = bitcast <4 x i32> %res1 to <2 x i64>
   ret <2 x i64> %res2
 }
 
 define <2 x i64> @test_mm_maskz_broadcastd_epi32(i8 %a0, <2 x i64> %a1) {
 ; X32-LABEL: test_mm_maskz_broadcastd_epi32:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Ltmp1:
+; X32-NEXT:  .Lcfi1:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $15, %al
 ; X32-NEXT:    movb %al, (%esp)
 ; X32-NEXT:    movzbl (%esp), %eax
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vpbroadcastd %xmm0, %xmm0 {%k1} {z}
 ; X32-NEXT:    popl %eax
; X64-NEXT:    retq
   %res = shufflevector <2 x i64> %a0, <2 x i64> undef, <2 x i32> zeroinitializer
   ret <2 x i64> %res
 }
 
 define <2 x i64> @test_mm_mask_broadcastq_epi64(<2 x i64> %a0, i8 %a1, <2 x i64> %a2) {
 ; X32-LABEL: test_mm_mask_broadcastq_epi64:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Ltmp2:
+; X32-NEXT:  .Lcfi2:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $3, %al
 ; X32-NEXT:    movb %al, {{[0-9]+}}(%esp)
 ; X32-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vpbroadcastq %xmm1, %xmm0 {%k1}
 ; X32-NEXT:    popl %eax
; X64-NEXT:    retq
   %res1 = select <2 x i1> %arg1, <2 x i64> %res0, <2 x i64> %a0
   ret <2 x i64> %res1
 }
 
 define <2 x i64> @test_mm_maskz_broadcastq_epi64(i8 %a0, <2 x i64> %a1) {
 ; X32-LABEL: test_mm_maskz_broadcastq_epi64:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Ltmp3:
+; X32-NEXT:  .Lcfi3:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $3, %al
 ; X32-NEXT:    movb %al, {{[0-9]+}}(%esp)
 ; X32-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vpbroadcastq %xmm0, %xmm0 {%k1} {z}
 ; X32-NEXT:    popl %eax
; X64-NEXT:    retq
   %res = shufflevector <2 x i64> %a0, <2 x i64> undef, <4 x i32> zeroinitializer
   ret <4 x i64> %res
 }
 
 define <4 x i64> @test_mm256_mask_broadcastq_epi64(<4 x i64> %a0, i8 %a1, <2 x i64> %a2) {
 ; X32-LABEL: test_mm256_mask_broadcastq_epi64:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Ltmp4:
+; X32-NEXT:  .Lcfi4:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $15, %al
 ; X32-NEXT:    movb %al, (%esp)
 ; X32-NEXT:    movzbl (%esp), %eax
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vpbroadcastq %xmm1, %ymm0 {%k1}
 ; X32-NEXT:    popl %eax
; X64-NEXT:    retq
   %res1 = select <4 x i1> %arg1, <4 x i64> %res0, <4 x i64> %a0
   ret <4 x i64> %res1
 }
 
 define <4 x i64> @test_mm256_maskz_broadcastq_epi64(i8 %a0, <2 x i64> %a1) {
 ; X32-LABEL: test_mm256_maskz_broadcastq_epi64:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Ltmp5:
+; X32-NEXT:  .Lcfi5:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $15, %al
 ; X32-NEXT:    movb %al, (%esp)
 ; X32-NEXT:    movzbl (%esp), %eax
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vpbroadcastq %xmm0, %ymm0 {%k1} {z}
 ; X32-NEXT:    popl %eax
; X64-NEXT:    retq
   %res = shufflevector <2 x double> %a0, <2 x double> undef, <2 x i32> zeroinitializer
   ret <2 x double> %res
 }
 
 define <2 x double> @test_mm_mask_broadcastsd_pd(<2 x double> %a0, i8 %a1, <2 x double> %a2) {
 ; X32-LABEL: test_mm_mask_broadcastsd_pd:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Ltmp6:
+; X32-NEXT:  .Lcfi6:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $3, %al
 ; X32-NEXT:    movb %al, {{[0-9]+}}(%esp)
 ; X32-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vmovddup {{.*#+}} xmm0 {%k1} = xmm1[0,0]
 ; X32-NEXT:    popl %eax
; X64-NEXT:    retq
   %res1 = select <2 x i1> %arg1, <2 x double> %res0, <2 x double> %a0
   ret <2 x double> %res1
 }
 
 define <2 x double> @test_mm_maskz_broadcastsd_pd(i8 %a0, <2 x double> %a1) {
 ; X32-LABEL: test_mm_maskz_broadcastsd_pd:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Ltmp7:
+; X32-NEXT:  .Lcfi7:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $3, %al
 ; X32-NEXT:    movb %al, {{[0-9]+}}(%esp)
 ; X32-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vmovddup {{.*#+}} xmm0 {%k1} {z} = xmm0[0,0]
 ; X32-NEXT:    popl %eax
; X64-NEXT:    retq
   %res = shufflevector <2 x double> %a0, <2 x double> undef, <4 x i32> zeroinitializer
   ret <4 x double> %res
 }
 
 define <4 x double> @test_mm256_mask_broadcastsd_pd(<4 x double> %a0, i8 %a1, <2 x double> %a2) {
 ; X32-LABEL: test_mm256_mask_broadcastsd_pd:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Ltmp8:
+; X32-NEXT:  .Lcfi8:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $15, %al
 ; X32-NEXT:    movb %al, (%esp)
 ; X32-NEXT:    movzbl (%esp), %eax
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vbroadcastsd %xmm1, %ymm0 {%k1}
 ; X32-NEXT:    popl %eax
; X64-NEXT:    retq
   %res1 = select <4 x i1> %arg1, <4 x double> %res0, <4 x double> %a0
   ret <4 x double> %res1
 }
 
 define <4 x double> @test_mm256_maskz_broadcastsd_pd(i8 %a0, <2 x double> %a1) {
 ; X32-LABEL: test_mm256_maskz_broadcastsd_pd:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Ltmp9:
+; X32-NEXT:  .Lcfi9:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $15, %al
 ; X32-NEXT:    movb %al, (%esp)
 ; X32-NEXT:    movzbl (%esp), %eax
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vbroadcastsd %xmm0, %ymm0 {%k1} {z}
 ; X32-NEXT:    popl %eax
; X64-NEXT:    retq
   %res = shufflevector <4 x float> %a0, <4 x float> undef, <4 x i32> zeroinitializer
   ret <4 x float> %res
 }
 
 define <4 x float> @test_mm_mask_broadcastss_ps(<4 x float> %a0, i8 %a1, <4 x float> %a2) {
 ; X32-LABEL: test_mm_mask_broadcastss_ps:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Ltmp10:
+; X32-NEXT:  .Lcfi10:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $15, %al
 ; X32-NEXT:    movb %al, (%esp)
 ; X32-NEXT:    movzbl (%esp), %eax
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vbroadcastss %xmm1, %xmm0 {%k1}
 ; X32-NEXT:    popl %eax
; X64-NEXT:    retq
   %res1 = select <4 x i1> %arg1, <4 x float> %res0, <4 x float> %a0
   ret <4 x float> %res1
 }
 
 define <4 x float> @test_mm_maskz_broadcastss_ps(i8 %a0, <4 x float> %a1) {
 ; X32-LABEL: test_mm_maskz_broadcastss_ps:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Ltmp11:
+; X32-NEXT:  .Lcfi11:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $15, %al
 ; X32-NEXT:    movb %al, (%esp)
 ; X32-NEXT:    movzbl (%esp), %eax
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vbroadcastss %xmm0, %xmm0 {%k1} {z}
 ; X32-NEXT:    popl %eax
; X64-NEXT:    retq
   %res = shufflevector <2 x double> %a0, <2 x double> undef, <2 x i32> zeroinitializer
   ret <2 x double> %res
 }
 
 define <2 x double> @test_mm_mask_movddup_pd(<2 x double> %a0, i8 %a1, <2 x double> %a2) {
 ; X32-LABEL: test_mm_mask_movddup_pd:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Ltmp12:
+; X32-NEXT:  .Lcfi12:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $3, %al
 ; X32-NEXT:    movb %al, {{[0-9]+}}(%esp)
 ; X32-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vmovddup {{.*#+}} xmm0 {%k1} = xmm1[0,0]
 ; X32-NEXT:    popl %eax
; X64-NEXT:    retq
   %res1 = select <2 x i1> %arg1, <2 x double> %res0, <2 x double> %a0
   ret <2 x double> %res1
 }
 
 define <2 x double> @test_mm_maskz_movddup_pd(i8 %a0, <2 x double> %a1) {
 ; X32-LABEL: test_mm_maskz_movddup_pd:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Ltmp13:
+; X32-NEXT:  .Lcfi13:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $3, %al
 ; X32-NEXT:    movb %al, {{[0-9]+}}(%esp)
 ; X32-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vmovddup {{.*#+}} xmm0 {%k1} {z} = xmm0[0,0]
 ; X32-NEXT:    popl %eax
; X64-NEXT:    retq
   %res = shufflevector <4 x double> %a0, <4 x double> undef, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
   ret <4 x double> %res
 }
 
 define <4 x double> @test_mm256_mask_movddup_pd(<4 x double> %a0, i8 %a1, <4 x double> %a2) {
 ; X32-LABEL: test_mm256_mask_movddup_pd:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Ltmp14:
+; X32-NEXT:  .Lcfi14:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $15, %al
 ; X32-NEXT:    movb %al, (%esp)
 ; X32-NEXT:    movzbl (%esp), %eax
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vmovddup {{.*#+}} ymm0 {%k1} = ymm1[0,0,2,2]
 ; X32-NEXT:    popl %eax
; X64-NEXT:    retq
   %res1 = select <4 x i1> %arg1, <4 x double> %res0, <4 x double> %a0
   ret <4 x double> %res1
 }
 
 define <4 x double> @test_mm256_maskz_movddup_pd(i8 %a0, <4 x double> %a1) {
 ; X32-LABEL: test_mm256_maskz_movddup_pd:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Ltmp15:
+; X32-NEXT:  .Lcfi15:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $15, %al
 ; X32-NEXT:    movb %al, (%esp)
 ; X32-NEXT:    movzbl (%esp), %eax
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vmovddup {{.*#+}} ymm0 {%k1} {z} = ymm0[0,0,2,2]
 ; X32-NEXT:    popl %eax
; X64-NEXT:    retq
   %res = shufflevector <4 x float> %a0, <4 x float> undef, <4 x i32> <i32 1, i32 1, i32 3, i32 3>
   ret <4 x float> %res
 }
 
 define <4 x float> @test_mm_mask_movehdup_ps(<4 x float> %a0, i8 %a1, <4 x float> %a2) {
 ; X32-LABEL: test_mm_mask_movehdup_ps:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Ltmp16:
+; X32-NEXT:  .Lcfi16:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $15, %al
 ; X32-NEXT:    movb %al, (%esp)
 ; X32-NEXT:    movzbl (%esp), %eax
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vmovshdup {{.*#+}} xmm0 {%k1} = xmm1[1,1,3,3]
 ; X32-NEXT:    popl %eax
; X64-NEXT:    retq
   %res1 = select <4 x i1> %arg1, <4 x float> %res0, <4 x float> %a0
   ret <4 x float> %res1
 }
 
 define <4 x float> @test_mm_maskz_movehdup_ps(i8 %a0, <4 x float> %a1) {
 ; X32-LABEL: test_mm_maskz_movehdup_ps:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Ltmp17:
+; X32-NEXT:  .Lcfi17:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $15, %al
 ; X32-NEXT:    movb %al, (%esp)
 ; X32-NEXT:    movzbl (%esp), %eax
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vmovshdup {{.*#+}} xmm0 {%k1} {z} = xmm0[1,1,3,3]
 ; X32-NEXT:    popl %eax
; X64-NEXT:    retq
   %res = shufflevector <4 x float> %a0, <4 x float> undef, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
   ret <4 x float> %res
 }
 
 define <4 x float> @test_mm_mask_moveldup_ps(<4 x float> %a0, i8 %a1, <4 x float> %a2) {
 ; X32-LABEL: test_mm_mask_moveldup_ps:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Ltmp18:
+; X32-NEXT:  .Lcfi18:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $15, %al
 ; X32-NEXT:    movb %al, (%esp)
 ; X32-NEXT:    movzbl (%esp), %eax
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vmovsldup {{.*#+}} xmm0 {%k1} = xmm1[0,0,2,2]
 ; X32-NEXT:    popl %eax
; X64-NEXT:    retq
   %res1 = select <4 x i1> %arg1, <4 x float> %res0, <4 x float> %a0
   ret <4 x float> %res1
 }
 
 define <4 x float> @test_mm_maskz_moveldup_ps(i8 %a0, <4 x float> %a1) {
 ; X32-LABEL: test_mm_maskz_moveldup_ps:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Ltmp19:
+; X32-NEXT:  .Lcfi19:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $15, %al
 ; X32-NEXT:    movb %al, (%esp)
 ; X32-NEXT:    movzbl (%esp), %eax
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vmovsldup {{.*#+}} xmm0 {%k1} {z} = xmm0[0,0,2,2]
 ; X32-NEXT:    popl %eax
; X64-NEXT:    retq
   %res = shufflevector <4 x i64> %a0, <4 x i64> undef, <4 x i32> <i32 3, i32 0, i32 0, i32 0>
   ret <4 x i64> %res
 }
 
 define <4 x i64> @test_mm256_mask_permutex_epi64(<4 x i64> %a0, i8 %a1, <4 x i64> %a2) {
 ; X32-LABEL: test_mm256_mask_permutex_epi64:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Ltmp20:
+; X32-NEXT:  .Lcfi20:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $15, %al
 ; X32-NEXT:    movb %al, (%esp)
 ; X32-NEXT:    movzbl (%esp), %eax
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vpermq {{.*#+}} ymm0 {%k1} = ymm1[1,0,0,0]
 ; X32-NEXT:    popl %eax
; X64-NEXT:    retq
   %res1 = select <4 x i1> %arg1, <4 x i64> %res0, <4 x i64> %a0
   ret <4 x i64> %res1
 }
 
 define <4 x i64> @test_mm256_maskz_permutex_epi64(i8 %a0, <4 x i64> %a1) {
 ; X32-LABEL: test_mm256_maskz_permutex_epi64:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Ltmp21:
+; X32-NEXT:  .Lcfi21:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $15, %al
 ; X32-NEXT:    movb %al, (%esp)
 ; X32-NEXT:    movzbl (%esp), %eax
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vpermq {{.*#+}} ymm0 {%k1} {z} = ymm0[1,0,0,0]
 ; X32-NEXT:    popl %eax
; X64-NEXT:    retq
   %res = shufflevector <4 x double> %a0, <4 x double> undef, <4 x i32> <i32 3, i32 0, i32 0, i32 0>
   ret <4 x double> %res
 }
 
 define <4 x double> @test_mm256_mask_permutex_pd(<4 x double> %a0, i8 %a1, <4 x double> %a2) {
 ; X32-LABEL: test_mm256_mask_permutex_pd:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Ltmp22:
+; X32-NEXT:  .Lcfi22:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $15, %al
 ; X32-NEXT:    movb %al, (%esp)
 ; X32-NEXT:    movzbl (%esp), %eax
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vpermpd {{.*#+}} ymm0 {%k1} = ymm1[1,0,0,0]
 ; X32-NEXT:    popl %eax
; X64-NEXT:    retq
   %res1 = select <4 x i1> %arg1, <4 x double> %res0, <4 x double> %a0
   ret <4 x double> %res1
 }
 
 define <4 x double> @test_mm256_maskz_permutex_pd(i8 %a0, <4 x double> %a1) {
 ; X32-LABEL: test_mm256_maskz_permutex_pd:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Ltmp23:
+; X32-NEXT:  .Lcfi23:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $15, %al
 ; X32-NEXT:    movb %al, (%esp)
 ; X32-NEXT:    movzbl (%esp), %eax
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vpermpd {{.*#+}} ymm0 {%k1} {z} = ymm0[1,0,0,0]
 ; X32-NEXT:    popl %eax
; X64-NEXT:    retq
   %res = shufflevector <2 x double> %a0, <2 x double> %a1, <2 x i32> <i32 1, i32 3>
   ret <2 x double> %res
 }
 
 define <2 x double> @test_mm_mask_shuffle_pd(<2 x double> %a0, i8 %a1, <2 x double> %a2, <2 x double> %a3) {
 ; X32-LABEL: test_mm_mask_shuffle_pd:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Ltmp24:
+; X32-NEXT:  .Lcfi24:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $3, %al
 ; X32-NEXT:    movb %al, {{[0-9]+}}(%esp)
 ; X32-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vunpckhpd {{.*#+}} xmm0 {%k1} = xmm1[1],xmm2[1]
 ; X32-NEXT:    popl %eax
; X64-NEXT:    retq
   %res1 = select <2 x i1> %arg1, <2 x double> %res0, <2 x double> %a0
   ret <2 x double> %res1
 }
 
 define <2 x double> @test_mm_maskz_shuffle_pd(i8 %a0, <2 x double> %a1, <2 x double> %a2) {
 ; X32-LABEL: test_mm_maskz_shuffle_pd:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Ltmp25:
+; X32-NEXT:  .Lcfi25:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $3, %al
 ; X32-NEXT:    movb %al, {{[0-9]+}}(%esp)
 ; X32-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vunpckhpd {{.*#+}} xmm0 {%k1} {z} = xmm0[1],xmm1[1]
 ; X32-NEXT:    popl %eax
; X64-NEXT:    retq
   %res = shufflevector <4 x double> %a0, <4 x double> %a1, <4 x i32> <i32 1, i32 5, i32 2, i32 6>
   ret <4 x double> %res
 }
 
 define <4 x double> @test_mm256_mask_shuffle_pd(<4 x double> %a0, i8 %a1, <4 x double> %a2, <4 x double> %a3) {
 ; X32-LABEL: test_mm256_mask_shuffle_pd:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Ltmp26:
+; X32-NEXT:  .Lcfi26:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $15, %al
 ; X32-NEXT:    movb %al, (%esp)
 ; X32-NEXT:    movzbl (%esp), %eax
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vshufpd {{.*#+}} ymm0 {%k1} = ymm1[1],ymm2[1],ymm1[2],ymm2[2]
 ; X32-NEXT:    popl %eax
; X64-NEXT:    retq
   %res1 = select <4 x i1> %arg1, <4 x double> %res0, <4 x double> %a0
   ret <4 x double> %res1
 }
 
 define <4 x double> @test_mm256_maskz_shuffle_pd(i8 %a0, <4 x double> %a1, <4 x double> %a2) {
 ; X32-LABEL: test_mm256_maskz_shuffle_pd:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Ltmp27:
+; X32-NEXT:  .Lcfi27:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $15, %al
 ; X32-NEXT:    movb %al, (%esp)
 ; X32-NEXT:    movzbl (%esp), %eax
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vshufpd {{.*#+}} ymm0 {%k1} {z} = ymm0[1],ymm1[1],ymm0[2],ymm1[2]
 ; X32-NEXT:    popl %eax
; X64-NEXT:    retq
   %res = shufflevector <4 x float> %a0, <4 x float> %a1, <4 x i32> <i32 0, i32 1, i32 4, i32 4>
   ret <4 x float> %res
 }
 
 define <4 x float> @test_mm_mask_shuffle_ps(<4 x float> %a0, i8 %a1, <4 x float> %a2, <4 x float> %a3) {
 ; X32-LABEL: test_mm_mask_shuffle_ps:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Ltmp28:
+; X32-NEXT:  .Lcfi28:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $15, %al
 ; X32-NEXT:    movb %al, (%esp)
 ; X32-NEXT:    movzbl (%esp), %eax
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vshufps {{.*#+}} xmm0 {%k1} = xmm1[0,1],xmm2[0,0]
 ; X32-NEXT:    popl %eax
; X64-NEXT:    retq
   %res1 = select <4 x i1> %arg1, <4 x float> %res0, <4 x float> %a0
   ret <4 x float> %res1
 }
 
 define <4 x float> @test_mm_maskz_shuffle_ps(i8 %a0, <4 x float> %a1, <4 x float> %a2) {
 ; X32-LABEL: test_mm_maskz_shuffle_ps:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Ltmp29:
+; X32-NEXT:  .Lcfi29:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $15, %al
 ; X32-NEXT:    movb %al, (%esp)
 ; X32-NEXT:    movzbl (%esp), %eax
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vshufps {{.*#+}} xmm0 {%k1} {z} = xmm0[0,1],xmm1[0,0]
 ; X32-NEXT:    popl %eax

test/CodeGen/X86/avx512vl-vbroadcast.ll

 ; NOTE: Assertions have been autogenerated by update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+avx512f -mattr=+avx512vl| FileCheck %s
 
 declare void @func_f32(float)
 define <8 x float> @_256_broadcast_ss_spill(float %x) {
 ; CHECK-LABEL: _256_broadcast_ss_spill:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    pushq %rax
-; CHECK-NEXT:  .Ltmp0:
+; CHECK-NEXT:  .Lcfi0:
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    vaddss %xmm0, %xmm0, %xmm0
 ; CHECK-NEXT:    vmovss %xmm0, {{[0-9]+}}(%rsp) # 4-byte Spill
 ; CHECK-NEXT:    callq func_f32
 ; CHECK-NEXT:    vbroadcastss {{[0-9]+}}(%rsp), %ymm0 # 4-byte Folded Reload
 ; CHECK-NEXT:    popq %rax
 ; CHECK-NEXT:    retq
   %a  = fadd float %x, %x
   call void @func_f32(float %a)
   %b = insertelement <8 x float> undef, float %a, i32 0
   %c = shufflevector <8 x float> %b, <8 x float> undef, <8 x i32> zeroinitializer
   ret <8 x float> %c
 }
 
 define <4 x float> @_128_broadcast_ss_spill(float %x) {
 ; CHECK-LABEL: _128_broadcast_ss_spill:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    pushq %rax
-; CHECK-NEXT:  .Ltmp1:
+; CHECK-NEXT:  .Lcfi1:
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    vaddss %xmm0, %xmm0, %xmm0
 ; CHECK-NEXT:    vmovss %xmm0, {{[0-9]+}}(%rsp) # 4-byte Spill
 ; CHECK-NEXT:    callq func_f32
 ; CHECK-NEXT:    vbroadcastss {{[0-9]+}}(%rsp), %xmm0 # 4-byte Folded Reload
 ; CHECK-NEXT:    popq %rax
 ; CHECK-NEXT:    retq
   %a  = fadd float %x, %x
   call void @func_f32(float %a)
   %b = insertelement <4 x float> undef, float %a, i32 0
   %c = shufflevector <4 x float> %b, <4 x float> undef, <4 x i32> zeroinitializer
   ret <4 x float> %c
 }
 
 declare void @func_f64(double)
 define <4 x double> @_256_broadcast_sd_spill(double %x) {
 ; CHECK-LABEL: _256_broadcast_sd_spill:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    pushq %rax
-; CHECK-NEXT:  .Ltmp2:
+; CHECK-NEXT:  .Lcfi2:
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    vaddsd %xmm0, %xmm0, %xmm0
 ; CHECK-NEXT:    vmovsd %xmm0, (%rsp) # 8-byte Spill
 ; CHECK-NEXT:    callq func_f64
 ; CHECK-NEXT:    vbroadcastsd (%rsp), %ymm0 # 8-byte Folded Reload
 ; CHECK-NEXT:    popq %rax
 ; CHECK-NEXT:    retq
   %a  = fadd double %x, %x

test/CodeGen/X86/deopt-intrinsic-cconv.ll

 ; RUN: llc < %s | FileCheck %s
 ; RUN: llc -debug-only=stackmaps < %s 2>&1 | FileCheck --check-prefix=STACKMAPS %s
 ; REQUIRES: asserts
 
 target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-apple-macosx10.11.0"
 
 declare webkit_jscc i64  @llvm.experimental.deoptimize.i64(...)
 
 define i64 @caller_1() {
 ; CHECK-LABEL: _caller_1:
 ; CHECK-NEXT: {{.+cfi.+}}
 ; CHECK-NEXT: ##{{.+}}
 ; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: {{Ltmp[0-9]+}}:
+; CHECK-NEXT: {{Lcfi[0-9]+}}:
 ; CHECK-NEXT: {{.+cfi.+}}
 ; CHECK-NEXT: movl  $1140457472, (%rsp)     ## imm = 0x43FA0000
 ; CHECK-NEXT: movl  $42, %eax
 ; CHECK-NEXT: callq ___llvm_deoptimize
 ; CHECK-NEXT: {{Ltmp[0-9]+}}:
 
 entry:
   %v = call webkit_jscc i64(...) @llvm.experimental.deoptimize.i64(i32 42, float 500.0) [ "deopt"(i32 3) ]

test/CodeGen/X86/deopt-intrinsic.ll

 ; RUN: llc < %s | FileCheck %s
 ; RUN: llc -debug-only=stackmaps < %s 2>&1 | FileCheck --check-prefix=STACKMAPS %s
 ; REQUIRES: asserts
 
 target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-apple-macosx10.11.0"
 
 declare i32 @llvm.experimental.deoptimize.i32(...)
 declare i8  @llvm.experimental.deoptimize.i8(...)
 
 define i32 @caller_0() {
 ; CHECK-LABEL: _caller_0:
 ; CHECK-NEXT: {{.+cfi.+}}
 ; CHECK-NEXT: ##{{.+}}
 ; CHECK-NEXT: pushq   %rax
-; CHECK-NEXT: {{Ltmp[0-9]+}}:
+; CHECK-NEXT: {{Lcfi[0-9]+}}:
 ; CHECK-NEXT: {{.+cfi.+}}
 ; CHECK-NEXT: callq ___llvm_deoptimize
 ; CHECK-NEXT: {{Ltmp[0-9]+}}:
 entry:
   %v = call i32(...) @llvm.experimental.deoptimize.i32() [ "deopt"(i32 0) ]
   ret i32 %v
 }
 
 define i8 @caller_1() {
 ; CHECK-LABEL: _caller_1:
 ; CHECK-NEXT: {{.+cfi.+}}
 ; CHECK-NEXT: ##{{.+}}
 ; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: {{Ltmp[0-9]+}}:
+; CHECK-NEXT: {{Lcfi[0-9]+}}:
 ; CHECK-NEXT: {{.+cfi.+}}
 ; CHECK-NEXT: movss {{[a-zA-Z0-9_]+}}(%rip), %xmm0    ## xmm0 = mem[0],zero,zero,zero
 ; CHECK-NEXT: movl  $42, %edi
 ; CHECK-NEXT: callq ___llvm_deoptimize
 ; CHECK-NEXT: {{Ltmp[0-9]+}}:
 
 entry:
   %v = call i8(...) @llvm.experimental.deoptimize.i8(i32 42, float 500.0) [ "deopt"(i32 1) ]

test/CodeGen/X86/fast-isel-store.ll

 ; SSE32-NEXT:    addpd %xmm2, %xmm0
 ; SSE32-NEXT:    movupd %xmm0, (%rdi)
 ; SSE32-NEXT:    movupd %xmm1, 16(%rdi)
 ; SSE32-NEXT:    retq
 ;
 ; SSE64-LABEL: test_store_4xf64:
 ; SSE64:       # BB#0:
 ; SSE64-NEXT:    subl $12, %esp
-; SSE64-NEXT:  .Ltmp0:
+; SSE64-NEXT:  .Lcfi0:
 ; SSE64-NEXT:    .cfi_def_cfa_offset 16
 ; SSE64-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; SSE64-NEXT:    addpd {{[0-9]+}}(%esp), %xmm1
 ; SSE64-NEXT:    addpd %xmm2, %xmm0
 ; SSE64-NEXT:    movupd %xmm0, (%eax)
 ; SSE64-NEXT:    movupd %xmm1, 16(%eax)
 ; SSE64-NEXT:    addl $12, %esp
 ; SSE64-NEXT:    retl

 ; SSE32-NEXT:    addpd %xmm2, %xmm0
 ; SSE32-NEXT:    movapd %xmm0, (%rdi)
 ; SSE32-NEXT:    movapd %xmm1, 16(%rdi)
 ; SSE32-NEXT:    retq
 ;
 ; SSE64-LABEL: test_store_4xf64_aligned:
 ; SSE64:       # BB#0:
 ; SSE64-NEXT:    subl $12, %esp
-; SSE64-NEXT:  .Ltmp1:
+; SSE64-NEXT:  .Lcfi1:
 ; SSE64-NEXT:    .cfi_def_cfa_offset 16
 ; SSE64-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; SSE64-NEXT:    addpd {{[0-9]+}}(%esp), %xmm1
 ; SSE64-NEXT:    addpd %xmm2, %xmm0
 ; SSE64-NEXT:    movapd %xmm0, (%eax)
 ; SSE64-NEXT:    movapd %xmm1, 16(%eax)
 ; SSE64-NEXT:    addl $12, %esp
 ; SSE64-NEXT:    retl

 ; SSE32-NEXT:    movups %xmm1, 16(%rdi)
 ; SSE32-NEXT:    movups %xmm2, 32(%rdi)
 ; SSE32-NEXT:    movups %xmm3, 48(%rdi)
 ; SSE32-NEXT:    retq
 ;
 ; SSE64-LABEL: test_store_16xi32:
 ; SSE64:       # BB#0:
 ; SSE64-NEXT:    subl $12, %esp
-; SSE64-NEXT:  .Ltmp2:
+; SSE64-NEXT:  .Lcfi2:
 ; SSE64-NEXT:    .cfi_def_cfa_offset 16
 ; SSE64-NEXT:    movaps {{[0-9]+}}(%esp), %xmm3
 ; SSE64-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; SSE64-NEXT:    movups %xmm0, (%eax)
 ; SSE64-NEXT:    movups %xmm1, 16(%eax)
 ; SSE64-NEXT:    movups %xmm2, 32(%eax)
 ; SSE64-NEXT:    movups %xmm3, 48(%eax)
 ; SSE64-NEXT:    addl $12, %esp

 ; SSE32-NEXT:    movaps %xmm1, 16(%rdi)
 ; SSE32-NEXT:    movaps %xmm2, 32(%rdi)
 ; SSE32-NEXT:    movaps %xmm3, 48(%rdi)
 ; SSE32-NEXT:    retq
 ;
 ; SSE64-LABEL: test_store_16xi32_aligned:
 ; SSE64:       # BB#0:
 ; SSE64-NEXT:    subl $12, %esp
-; SSE64-NEXT:  .Ltmp3:
+; SSE64-NEXT:  .Lcfi3:
 ; SSE64-NEXT:    .cfi_def_cfa_offset 16
 ; SSE64-NEXT:    movaps {{[0-9]+}}(%esp), %xmm3
 ; SSE64-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; SSE64-NEXT:    movaps %xmm0, (%eax)
 ; SSE64-NEXT:    movaps %xmm1, 16(%eax)
 ; SSE64-NEXT:    movaps %xmm2, 32(%eax)
 ; SSE64-NEXT:    movaps %xmm3, 48(%eax)
 ; SSE64-NEXT:    addl $12, %esp

 ; SSE32-NEXT:    movups %xmm1, 16(%rdi)
 ; SSE32-NEXT:    movups %xmm2, 32(%rdi)
 ; SSE32-NEXT:    movups %xmm3, 48(%rdi)
 ; SSE32-NEXT:    retq
 ;
 ; SSE64-LABEL: test_store_16xf32:
 ; SSE64:       # BB#0:
 ; SSE64-NEXT:    subl $12, %esp
-; SSE64-NEXT:  .Ltmp4:
+; SSE64-NEXT:  .Lcfi4:
 ; SSE64-NEXT:    .cfi_def_cfa_offset 16
 ; SSE64-NEXT:    movaps {{[0-9]+}}(%esp), %xmm3
 ; SSE64-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; SSE64-NEXT:    movups %xmm0, (%eax)
 ; SSE64-NEXT:    movups %xmm1, 16(%eax)
 ; SSE64-NEXT:    movups %xmm2, 32(%eax)
 ; SSE64-NEXT:    movups %xmm3, 48(%eax)
 ; SSE64-NEXT:    addl $12, %esp

 ; SSE32-NEXT:    movaps %xmm1, 16(%rdi)
 ; SSE32-NEXT:    movaps %xmm2, 32(%rdi)
 ; SSE32-NEXT:    movaps %xmm3, 48(%rdi)
 ; SSE32-NEXT:    retq
 ;
 ; SSE64-LABEL: test_store_16xf32_aligned:
 ; SSE64:       # BB#0:
 ; SSE64-NEXT:    subl $12, %esp
-; SSE64-NEXT:  .Ltmp5:
+; SSE64-NEXT:  .Lcfi5:
 ; SSE64-NEXT:    .cfi_def_cfa_offset 16
 ; SSE64-NEXT:    movaps {{[0-9]+}}(%esp), %xmm3
 ; SSE64-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; SSE64-NEXT:    movaps %xmm0, (%eax)
 ; SSE64-NEXT:    movaps %xmm1, 16(%eax)
 ; SSE64-NEXT:    movaps %xmm2, 32(%eax)
 ; SSE64-NEXT:    movaps %xmm3, 48(%eax)
 ; SSE64-NEXT:    addl $12, %esp

 ; SSE32-NEXT:    movupd %xmm1, 16(%rdi)
 ; SSE32-NEXT:    movupd %xmm2, 32(%rdi)
 ; SSE32-NEXT:    movupd %xmm3, 48(%rdi)
 ; SSE32-NEXT:    retq
 ;
 ; SSE64-LABEL: test_store_8xf64:
 ; SSE64:       # BB#0:
 ; SSE64-NEXT:    subl $12, %esp
-; SSE64-NEXT:  .Ltmp6:
+; SSE64-NEXT:  .Lcfi6:
 ; SSE64-NEXT:    .cfi_def_cfa_offset 16
 ; SSE64-NEXT:    movapd {{[0-9]+}}(%esp), %xmm3
 ; SSE64-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; SSE64-NEXT:    addpd {{[0-9]+}}(%esp), %xmm3
 ; SSE64-NEXT:    addpd {{[0-9]+}}(%esp), %xmm2
 ; SSE64-NEXT:    addpd {{[0-9]+}}(%esp), %xmm1
 ; SSE64-NEXT:    addpd {{[0-9]+}}(%esp), %xmm0
 ; SSE64-NEXT:    movupd %xmm0, (%eax)

 ; AVXONLY32-NEXT:    vaddpd %ymm2, %ymm0, %ymm0
 ; AVXONLY32-NEXT:    vmovupd %ymm0, (%rdi)
 ; AVXONLY32-NEXT:    vmovupd %ymm1, 32(%rdi)
 ; AVXONLY32-NEXT:    retq
 ;
 ; AVXONLY64-LABEL: test_store_8xf64:
 ; AVXONLY64:       # BB#0:
 ; AVXONLY64-NEXT:    pushl %ebp
-; AVXONLY64-NEXT:  .Ltmp0:
+; AVXONLY64-NEXT:  .Lcfi0:
 ; AVXONLY64-NEXT:    .cfi_def_cfa_offset 8
-; AVXONLY64-NEXT:  .Ltmp1:
+; AVXONLY64-NEXT:  .Lcfi1:
 ; AVXONLY64-NEXT:    .cfi_offset %ebp, -8
 ; AVXONLY64-NEXT:    movl %esp, %ebp
-; AVXONLY64-NEXT:  .Ltmp2:
+; AVXONLY64-NEXT:  .Lcfi2:
 ; AVXONLY64-NEXT:    .cfi_def_cfa_register %ebp
 ; AVXONLY64-NEXT:    andl $-32, %esp
 ; AVXONLY64-NEXT:    subl $32, %esp
 ; AVXONLY64-NEXT:    movl 8(%ebp), %eax
 ; AVXONLY64-NEXT:    vaddpd 40(%ebp), %ymm1, %ymm1
 ; AVXONLY64-NEXT:    vaddpd %ymm2, %ymm0, %ymm0
 ; AVXONLY64-NEXT:    vmovupd %ymm0, (%eax)
 ; AVXONLY64-NEXT:    vmovupd %ymm1, 32(%eax)

 ; SSE32-NEXT:    movapd %xmm1, 16(%rdi)
 ; SSE32-NEXT:    movapd %xmm2, 32(%rdi)
 ; SSE32-NEXT:    movapd %xmm3, 48(%rdi)
 ; SSE32-NEXT:    retq
 ;
 ; SSE64-LABEL: test_store_8xf64_aligned:
 ; SSE64:       # BB#0:
 ; SSE64-NEXT:    subl $12, %esp
-; SSE64-NEXT:  .Ltmp7:
+; SSE64-NEXT:  .Lcfi7:
 ; SSE64-NEXT:    .cfi_def_cfa_offset 16
 ; SSE64-NEXT:    movapd {{[0-9]+}}(%esp), %xmm3
 ; SSE64-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; SSE64-NEXT:    addpd {{[0-9]+}}(%esp), %xmm3
 ; SSE64-NEXT:    addpd {{[0-9]+}}(%esp), %xmm2
 ; SSE64-NEXT:    addpd {{[0-9]+}}(%esp), %xmm1
 ; SSE64-NEXT:    addpd {{[0-9]+}}(%esp), %xmm0
 ; SSE64-NEXT:    movapd %xmm0, (%eax)

 ; AVXONLY32-NEXT:    vaddpd %ymm2, %ymm0, %ymm0
 ; AVXONLY32-NEXT:    vmovapd %ymm0, (%rdi)
 ; AVXONLY32-NEXT:    vmovapd %ymm1, 32(%rdi)
 ; AVXONLY32-NEXT:    retq
 ;
 ; AVXONLY64-LABEL: test_store_8xf64_aligned:
 ; AVXONLY64:       # BB#0:
 ; AVXONLY64-NEXT:    pushl %ebp
-; AVXONLY64-NEXT:  .Ltmp3:
+; AVXONLY64-NEXT:  .Lcfi3:
 ; AVXONLY64-NEXT:    .cfi_def_cfa_offset 8
-; AVXONLY64-NEXT:  .Ltmp4:
+; AVXONLY64-NEXT:  .Lcfi4:
 ; AVXONLY64-NEXT:    .cfi_offset %ebp, -8
 ; AVXONLY64-NEXT:    movl %esp, %ebp
-; AVXONLY64-NEXT:  .Ltmp5:
+; AVXONLY64-NEXT:  .Lcfi5:
 ; AVXONLY64-NEXT:    .cfi_def_cfa_register %ebp
 ; AVXONLY64-NEXT:    andl $-32, %esp
 ; AVXONLY64-NEXT:    subl $32, %esp
 ; AVXONLY64-NEXT:    movl 8(%ebp), %eax
 ; AVXONLY64-NEXT:    vaddpd 40(%ebp), %ymm1, %ymm1
 ; AVXONLY64-NEXT:    vaddpd %ymm2, %ymm0, %ymm0
 ; AVXONLY64-NEXT:    vmovapd %ymm0, (%eax)
 ; AVXONLY64-NEXT:    vmovapd %ymm1, 32(%eax)

test/CodeGen/X86/haddsub-2.ll

; AVX2-NEXT:    retq
   %vecinit29 = insertelement <8 x i32> %vecinit25, i32 %add28, i32 7
   ret <8 x i32> %vecinit29
 }
 
 define <16 x i16> @avx2_vphadd_w_test(<16 x i16> %a, <16 x i16> %b) {
 ; SSE3-LABEL: avx2_vphadd_w_test:
 ; SSE3:       # BB#0:
 ; SSE3-NEXT:    pushq %rbp
-; SSE3-NEXT:  .Ltmp0:
+; SSE3-NEXT:  .Lcfi0:
 ; SSE3-NEXT:    .cfi_def_cfa_offset 16
 ; SSE3-NEXT:    pushq %r15
-; SSE3-NEXT:  .Ltmp1:
+; SSE3-NEXT:  .Lcfi1:
 ; SSE3-NEXT:    .cfi_def_cfa_offset 24
 ; SSE3-NEXT:    pushq %r14
-; SSE3-NEXT:  .Ltmp2:
+; SSE3-NEXT:  .Lcfi2:
 ; SSE3-NEXT:    .cfi_def_cfa_offset 32
 ; SSE3-NEXT:    pushq %r13
-; SSE3-NEXT:  .Ltmp3:
+; SSE3-NEXT:  .Lcfi3:
 ; SSE3-NEXT:    .cfi_def_cfa_offset 40
 ; SSE3-NEXT:    pushq %r12
-; SSE3-NEXT:  .Ltmp4:
+; SSE3-NEXT:  .Lcfi4:
 ; SSE3-NEXT:    .cfi_def_cfa_offset 48
 ; SSE3-NEXT:    pushq %rbx
-; SSE3-NEXT:  .Ltmp5:
+; SSE3-NEXT:  .Lcfi5:
 ; SSE3-NEXT:    .cfi_def_cfa_offset 56
-; SSE3-NEXT:  .Ltmp6:
+; SSE3-NEXT:  .Lcfi6:
 ; SSE3-NEXT:    .cfi_offset %rbx, -56
-; SSE3-NEXT:  .Ltmp7:
+; SSE3-NEXT:  .Lcfi7:
 ; SSE3-NEXT:    .cfi_offset %r12, -48
-; SSE3-NEXT:  .Ltmp8:
+; SSE3-NEXT:  .Lcfi8:
 ; SSE3-NEXT:    .cfi_offset %r13, -40
-; SSE3-NEXT:  .Ltmp9:
+; SSE3-NEXT:  .Lcfi9:
 ; SSE3-NEXT:    .cfi_offset %r14, -32
-; SSE3-NEXT:  .Ltmp10:
+; SSE3-NEXT:  .Lcfi10:
 ; SSE3-NEXT:    .cfi_offset %r15, -24
-; SSE3-NEXT:  .Ltmp11:
+; SSE3-NEXT:  .Lcfi11:
 ; SSE3-NEXT:    .cfi_offset %rbp, -16
 ; SSE3-NEXT:    movd %xmm0, %eax
 ; SSE3-NEXT:    pextrw $1, %xmm0, %ecx
 ; SSE3-NEXT:    addl %eax, %ecx
 ; SSE3-NEXT:    movl %ecx, -{{[0-9]+}}(%rsp) # 4-byte Spill
 ; SSE3-NEXT:    pextrw $2, %xmm0, %eax
 ; SSE3-NEXT:    pextrw $3, %xmm0, %r11d
 ; SSE3-NEXT:    addl %eax, %r11d
; AVX2-NEXT:    retq
   %vecinit29 = insertelement <8 x i32> %vecinit25, i32 %add28, i32 7
   ret <8 x i32> %vecinit29
 }
 
 define <16 x i16> @avx2_hadd_w(<16 x i16> %a, <16 x i16> %b) {
 ; SSE3-LABEL: avx2_hadd_w:
 ; SSE3:       # BB#0:
 ; SSE3-NEXT:    pushq %rbp
-; SSE3-NEXT:  .Ltmp12:
+; SSE3-NEXT:  .Lcfi12:
 ; SSE3-NEXT:    .cfi_def_cfa_offset 16
 ; SSE3-NEXT:    pushq %r15
-; SSE3-NEXT:  .Ltmp13:
+; SSE3-NEXT:  .Lcfi13:
 ; SSE3-NEXT:    .cfi_def_cfa_offset 24
 ; SSE3-NEXT:    pushq %r14
-; SSE3-NEXT:  .Ltmp14:
+; SSE3-NEXT:  .Lcfi14:
 ; SSE3-NEXT:    .cfi_def_cfa_offset 32
 ; SSE3-NEXT:    pushq %r13
-; SSE3-NEXT:  .Ltmp15:
+; SSE3-NEXT:  .Lcfi15:
 ; SSE3-NEXT:    .cfi_def_cfa_offset 40
 ; SSE3-NEXT:    pushq %r12
-; SSE3-NEXT:  .Ltmp16:
+; SSE3-NEXT:  .Lcfi16:
 ; SSE3-NEXT:    .cfi_def_cfa_offset 48
 ; SSE3-NEXT:    pushq %rbx
-; SSE3-NEXT:  .Ltmp17:
+; SSE3-NEXT:  .Lcfi17:
 ; SSE3-NEXT:    .cfi_def_cfa_offset 56
-; SSE3-NEXT:  .Ltmp18:
+; SSE3-NEXT:  .Lcfi18:
 ; SSE3-NEXT:    .cfi_offset %rbx, -56
-; SSE3-NEXT:  .Ltmp19:
+; SSE3-NEXT:  .Lcfi19:
 ; SSE3-NEXT:    .cfi_offset %r12, -48
-; SSE3-NEXT:  .Ltmp20:
+; SSE3-NEXT:  .Lcfi20:
 ; SSE3-NEXT:    .cfi_offset %r13, -40
-; SSE3-NEXT:  .Ltmp21:
+; SSE3-NEXT:  .Lcfi21:
 ; SSE3-NEXT:    .cfi_offset %r14, -32
-; SSE3-NEXT:  .Ltmp22:
+; SSE3-NEXT:  .Lcfi22:
 ; SSE3-NEXT:    .cfi_offset %r15, -24
-; SSE3-NEXT:  .Ltmp23:
+; SSE3-NEXT:  .Lcfi23:
 ; SSE3-NEXT:    .cfi_offset %rbp, -16
 ; SSE3-NEXT:    movd %xmm0, %eax
 ; SSE3-NEXT:    pextrw $1, %xmm0, %ecx
 ; SSE3-NEXT:    addl %eax, %ecx
 ; SSE3-NEXT:    movl %ecx, -{{[0-9]+}}(%rsp) # 4-byte Spill
 ; SSE3-NEXT:    pextrw $2, %xmm0, %eax
 ; SSE3-NEXT:    pextrw $3, %xmm0, %r15d
 ; SSE3-NEXT:    addl %eax, %r15d

test/CodeGen/X86/legalize-shift-64.ll

; CHECK-NEXT:    retl
   ret i64 %shr
 }
 
 ; PR14668
 define <2 x i64> @test5(<2 x i64> %A, <2 x i64> %B) {
 ; CHECK-LABEL: test5:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    pushl %ebp
-; CHECK-NEXT:  .Ltmp0:
+; CHECK-NEXT:  .Lcfi0:
 ; CHECK-NEXT:    .cfi_def_cfa_offset 8
 ; CHECK-NEXT:    pushl %ebx
-; CHECK-NEXT:  .Ltmp1:
+; CHECK-NEXT:  .Lcfi1:
 ; CHECK-NEXT:    .cfi_def_cfa_offset 12
 ; CHECK-NEXT:    pushl %edi
-; CHECK-NEXT:  .Ltmp2:
+; CHECK-NEXT:  .Lcfi2:
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    pushl %esi
-; CHECK-NEXT:  .Ltmp3:
+; CHECK-NEXT:  .Lcfi3:
 ; CHECK-NEXT:    .cfi_def_cfa_offset 20
-; CHECK-NEXT:  .Ltmp4:
+; CHECK-NEXT:  .Lcfi4:
 ; CHECK-NEXT:    .cfi_offset %esi, -20
-; CHECK-NEXT:  .Ltmp5:
+; CHECK-NEXT:  .Lcfi5:
 ; CHECK-NEXT:    .cfi_offset %edi, -16
-; CHECK-NEXT:  .Ltmp6:
+; CHECK-NEXT:  .Lcfi6:
 ; CHECK-NEXT:    .cfi_offset %ebx, -12
-; CHECK-NEXT:  .Ltmp7:
+; CHECK-NEXT:  .Lcfi7:
 ; CHECK-NEXT:    .cfi_offset %ebp, -8
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    movb {{[0-9]+}}(%esp), %cl
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ebx
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %esi
 ; CHECK-NEXT:    movl %ebx, %edi
 ; CHECK-NEXT:    shll %cl, %edi
 ; CHECK-NEXT:    shldl %cl, %ebx, %esi
; CHECK-NEXT:    retl $4
   ret <2 x i64> %shl
 }
 
 ; PR16108
 define i32 @test6() {
 ; CHECK-LABEL: test6:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    pushl %ebp
-; CHECK-NEXT:  .Ltmp8:
+; CHECK-NEXT:  .Lcfi8:
 ; CHECK-NEXT:    .cfi_def_cfa_offset 8
-; CHECK-NEXT:  .Ltmp9:
+; CHECK-NEXT:  .Lcfi9:
 ; CHECK-NEXT:    .cfi_offset %ebp, -8
 ; CHECK-NEXT:    movl %esp, %ebp
-; CHECK-NEXT:  .Ltmp10:
+; CHECK-NEXT:  .Lcfi10:
 ; CHECK-NEXT:    .cfi_def_cfa_register %ebp
 ; CHECK-NEXT:    andl $-8, %esp
 ; CHECK-NEXT:    subl $16, %esp
 ; CHECK-NEXT:    movl $1, {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movl $0, {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movl $1, (%esp)
 ; CHECK-NEXT:    movl $1, %eax
 ; CHECK-NEXT:    xorl %ecx, %ecx

test/CodeGen/X86/masked_gather_scatter.ll

 ; KNL_64-NEXT:    vpgatherqq (,%zmm1), %zmm4 {%k2}
 ; KNL_64-NEXT:    vmovdqa64 %zmm3, %zmm0
 ; KNL_64-NEXT:    vmovdqa64 %zmm4, %zmm1
 ; KNL_64-NEXT:    retq
 ;
 ; KNL_32-LABEL: test_gather_16i64:
 ; KNL_32:       # BB#0:
 ; KNL_32-NEXT:    pushl %ebp
-; KNL_32-NEXT:  .Ltmp0:
+; KNL_32-NEXT:  .Lcfi0:
 ; KNL_32-NEXT:    .cfi_def_cfa_offset 8
-; KNL_32-NEXT:  .Ltmp1:
+; KNL_32-NEXT:  .Lcfi1:
 ; KNL_32-NEXT:    .cfi_offset %ebp, -8
 ; KNL_32-NEXT:    movl %esp, %ebp
-; KNL_32-NEXT:  .Ltmp2:
+; KNL_32-NEXT:  .Lcfi2:
 ; KNL_32-NEXT:    .cfi_def_cfa_register %ebp
 ; KNL_32-NEXT:    andl $-64, %esp
 ; KNL_32-NEXT:    subl $64, %esp
 ; KNL_32-NEXT:    vpmovsxbd %xmm1, %zmm1
 ; KNL_32-NEXT:    vpslld $31, %zmm1, %zmm1
 ; KNL_32-NEXT:    vptestmd %zmm1, %zmm1, %k1
 ; KNL_32-NEXT:    vmovdqa64 8(%ebp), %zmm1
 ; KNL_32-NEXT:    kshiftrw $8, %k1, %k2

 ; SKX-NEXT:    vpgatherqq (,%zmm1), %zmm4 {%k2}
 ; SKX-NEXT:    vmovdqa64 %zmm3, %zmm0
 ; SKX-NEXT:    vmovdqa64 %zmm4, %zmm1
 ; SKX-NEXT:    retq
 ;
 ; SKX_32-LABEL: test_gather_16i64:
 ; SKX_32:       # BB#0:
 ; SKX_32-NEXT:    pushl %ebp
-; SKX_32-NEXT:  .Ltmp1:
+; SKX_32-NEXT:  .Lcfi1:
 ; SKX_32-NEXT:    .cfi_def_cfa_offset 8
-; SKX_32-NEXT:  .Ltmp2:
+; SKX_32-NEXT:  .Lcfi2:
 ; SKX_32-NEXT:    .cfi_offset %ebp, -8
 ; SKX_32-NEXT:    movl %esp, %ebp
-; SKX_32-NEXT:  .Ltmp3:
+; SKX_32-NEXT:  .Lcfi3:
 ; SKX_32-NEXT:    .cfi_def_cfa_register %ebp
 ; SKX_32-NEXT:    andl $-64, %esp
 ; SKX_32-NEXT:    subl $64, %esp
 ; SKX_32-NEXT:    vpmovsxbd %xmm1, %zmm1
 ; SKX_32-NEXT:    vpslld $31, %zmm1, %zmm1
 ; SKX_32-NEXT:    vptestmd %zmm1, %zmm1, %k1
 ; SKX_32-NEXT:    vmovdqa64 8(%ebp), %zmm1
 ; SKX_32-NEXT:    kshiftrw $8, %k1, %k2

 ; KNL_64-NEXT:    vgatherqpd (,%zmm1), %zmm4 {%k2}
 ; KNL_64-NEXT:    vmovapd %zmm3, %zmm0
 ; KNL_64-NEXT:    vmovapd %zmm4, %zmm1
 ; KNL_64-NEXT:    retq
 ;
 ; KNL_32-LABEL: test_gather_16f64:
 ; KNL_32:       # BB#0:
 ; KNL_32-NEXT:    pushl %ebp
-; KNL_32-NEXT:  .Ltmp3:
+; KNL_32-NEXT:  .Lcfi3:
 ; KNL_32-NEXT:    .cfi_def_cfa_offset 8
-; KNL_32-NEXT:  .Ltmp4:
+; KNL_32-NEXT:  .Lcfi4:
 ; KNL_32-NEXT:    .cfi_offset %ebp, -8
 ; KNL_32-NEXT:    movl %esp, %ebp
-; KNL_32-NEXT:  .Ltmp5:
+; KNL_32-NEXT:  .Lcfi5:
 ; KNL_32-NEXT:    .cfi_def_cfa_register %ebp
 ; KNL_32-NEXT:    andl $-64, %esp
 ; KNL_32-NEXT:    subl $64, %esp
 ; KNL_32-NEXT:    vpmovsxbd %xmm1, %zmm1
 ; KNL_32-NEXT:    vpslld $31, %zmm1, %zmm1
 ; KNL_32-NEXT:    vptestmd %zmm1, %zmm1, %k1
 ; KNL_32-NEXT:    vmovapd 8(%ebp), %zmm1
 ; KNL_32-NEXT:    kshiftrw $8, %k1, %k2

 ; SKX-NEXT:    vgatherqpd (,%zmm1), %zmm4 {%k2}
 ; SKX-NEXT:    vmovapd %zmm3, %zmm0
 ; SKX-NEXT:    vmovapd %zmm4, %zmm1
 ; SKX-NEXT:    retq
 ;
 ; SKX_32-LABEL: test_gather_16f64:
 ; SKX_32:       # BB#0:
 ; SKX_32-NEXT:    pushl %ebp
-; SKX_32-NEXT:  .Ltmp4:
+; SKX_32-NEXT:  .Lcfi4:
 ; SKX_32-NEXT:    .cfi_def_cfa_offset 8
-; SKX_32-NEXT:  .Ltmp5:
+; SKX_32-NEXT:  .Lcfi5:
 ; SKX_32-NEXT:    .cfi_offset %ebp, -8
 ; SKX_32-NEXT:    movl %esp, %ebp
-; SKX_32-NEXT:  .Ltmp6:
+; SKX_32-NEXT:  .Lcfi6:
 ; SKX_32-NEXT:    .cfi_def_cfa_register %ebp
 ; SKX_32-NEXT:    andl $-64, %esp
 ; SKX_32-NEXT:    subl $64, %esp
 ; SKX_32-NEXT:    vpmovsxbd %xmm1, %zmm1
 ; SKX_32-NEXT:    vpslld $31, %zmm1, %zmm1
 ; SKX_32-NEXT:    vptestmd %zmm1, %zmm1, %k1
 ; SKX_32-NEXT:    vmovapd 8(%ebp), %zmm1
 ; SKX_32-NEXT:    kshiftrw $8, %k1, %k2

 ; KNL_64-NEXT:    kshiftrw $8, %k1, %k2
 ; KNL_64-NEXT:    vpscatterqq %zmm3, (,%zmm0) {%k1}
 ; KNL_64-NEXT:    vpscatterqq %zmm4, (,%zmm1) {%k2}
 ; KNL_64-NEXT:    retq
 ;
 ; KNL_32-LABEL: test_scatter_16i64:
 ; KNL_32:       # BB#0:
 ; KNL_32-NEXT:    pushl %ebp
-; KNL_32-NEXT:  .Ltmp6:
+; KNL_32-NEXT:  .Lcfi6:
 ; KNL_32-NEXT:    .cfi_def_cfa_offset 8
-; KNL_32-NEXT:  .Ltmp7:
+; KNL_32-NEXT:  .Lcfi7:
 ; KNL_32-NEXT:    .cfi_offset %ebp, -8
 ; KNL_32-NEXT:    movl %esp, %ebp
-; KNL_32-NEXT:  .Ltmp8:
+; KNL_32-NEXT:  .Lcfi8:
 ; KNL_32-NEXT:    .cfi_def_cfa_register %ebp
 ; KNL_32-NEXT:    andl $-64, %esp
 ; KNL_32-NEXT:    subl $64, %esp
 ; KNL_32-NEXT:    vpmovsxbd %xmm1, %zmm1
 ; KNL_32-NEXT:    vpslld $31, %zmm1, %zmm1
 ; KNL_32-NEXT:    vptestmd %zmm1, %zmm1, %k1
 ; KNL_32-NEXT:    vmovdqa64 8(%ebp), %zmm1
 ; KNL_32-NEXT:    kshiftrw $8, %k1, %k2

 ; SKX-NEXT:    kshiftrw $8, %k1, %k2
 ; SKX-NEXT:    vpscatterqq %zmm3, (,%zmm0) {%k1}
 ; SKX-NEXT:    vpscatterqq %zmm4, (,%zmm1) {%k2}
 ; SKX-NEXT:    retq
 ;
 ; SKX_32-LABEL: test_scatter_16i64:
 ; SKX_32:       # BB#0:
 ; SKX_32-NEXT:    pushl %ebp
-; SKX_32-NEXT:  .Ltmp7:
+; SKX_32-NEXT:  .Lcfi7:
 ; SKX_32-NEXT:    .cfi_def_cfa_offset 8
-; SKX_32-NEXT:  .Ltmp8:
+; SKX_32-NEXT:  .Lcfi8:
 ; SKX_32-NEXT:    .cfi_offset %ebp, -8
 ; SKX_32-NEXT:    movl %esp, %ebp
-; SKX_32-NEXT:  .Ltmp9:
+; SKX_32-NEXT:  .Lcfi9:
 ; SKX_32-NEXT:    .cfi_def_cfa_register %ebp
 ; SKX_32-NEXT:    andl $-64, %esp
 ; SKX_32-NEXT:    subl $64, %esp
 ; SKX_32-NEXT:    vpmovsxbd %xmm1, %zmm1
 ; SKX_32-NEXT:    vpslld $31, %zmm1, %zmm1
 ; SKX_32-NEXT:    vptestmd %zmm1, %zmm1, %k1
 ; SKX_32-NEXT:    vmovdqa64 8(%ebp), %zmm1
 ; SKX_32-NEXT:    kshiftrw $8, %k1, %k2

 ; KNL_64-NEXT:    kshiftrw $8, %k1, %k2
 ; KNL_64-NEXT:    vscatterqpd %zmm3, (,%zmm0) {%k1}
 ; KNL_64-NEXT:    vscatterqpd %zmm4, (,%zmm1) {%k2}
 ; KNL_64-NEXT:    retq
 ;
 ; KNL_32-LABEL: test_scatter_16f64:
 ; KNL_32:       # BB#0:
 ; KNL_32-NEXT:    pushl %ebp
-; KNL_32-NEXT:  .Ltmp9:
+; KNL_32-NEXT:  .Lcfi9:
 ; KNL_32-NEXT:    .cfi_def_cfa_offset 8
-; KNL_32-NEXT:  .Ltmp10:
+; KNL_32-NEXT:  .Lcfi10:
 ; KNL_32-NEXT:    .cfi_offset %ebp, -8
 ; KNL_32-NEXT:    movl %esp, %ebp
-; KNL_32-NEXT:  .Ltmp11:
+; KNL_32-NEXT:  .Lcfi11:
 ; KNL_32-NEXT:    .cfi_def_cfa_register %ebp
 ; KNL_32-NEXT:    andl $-64, %esp
 ; KNL_32-NEXT:    subl $64, %esp
 ; KNL_32-NEXT:    vpmovsxbd %xmm1, %zmm1
 ; KNL_32-NEXT:    vpslld $31, %zmm1, %zmm1
 ; KNL_32-NEXT:    vptestmd %zmm1, %zmm1, %k1
 ; KNL_32-NEXT:    vmovapd 8(%ebp), %zmm1
 ; KNL_32-NEXT:    kshiftrw $8, %k1, %k2

 ; SKX-NEXT:    kshiftrw $8, %k1, %k2
 ; SKX-NEXT:    vscatterqpd %zmm3, (,%zmm0) {%k1}
 ; SKX-NEXT:    vscatterqpd %zmm4, (,%zmm1) {%k2}
 ; SKX-NEXT:    retq
 ;
 ; SKX_32-LABEL: test_scatter_16f64:
 ; SKX_32:       # BB#0:
 ; SKX_32-NEXT:    pushl %ebp
-; SKX_32-NEXT:  .Ltmp10:
+; SKX_32-NEXT:  .Lcfi10:
 ; SKX_32-NEXT:    .cfi_def_cfa_offset 8
-; SKX_32-NEXT:  .Ltmp11:
+; SKX_32-NEXT:  .Lcfi11:
 ; SKX_32-NEXT:    .cfi_offset %ebp, -8
 ; SKX_32-NEXT:    movl %esp, %ebp
-; SKX_32-NEXT:  .Ltmp12:
+; SKX_32-NEXT:  .Lcfi12:
 ; SKX_32-NEXT:    .cfi_def_cfa_register %ebp
 ; SKX_32-NEXT:    andl $-64, %esp
 ; SKX_32-NEXT:    subl $64, %esp
 ; SKX_32-NEXT:    vpmovsxbd %xmm1, %zmm1
 ; SKX_32-NEXT:    vpslld $31, %zmm1, %zmm1
 ; SKX_32-NEXT:    vptestmd %zmm1, %zmm1, %k1
 ; SKX_32-NEXT:    vmovapd 8(%ebp), %zmm1
 ; SKX_32-NEXT:    kshiftrw $8, %k1, %k2

test/CodeGen/X86/memset-nonzero.ll

;
   %call = tail call i8* @__memset_chk(i8* %x, i32 42, i64 128, i64 -1)
   ret void
 }
 
 define void @memset_256_nonzero_bytes(i8* %x) {
 ; SSE-LABEL: memset_256_nonzero_bytes:
 ; SSE:       # BB#0:
 ; SSE-NEXT:    pushq %rax
-; SSE-NEXT:  .Ltmp0:
+; SSE-NEXT:  .Lcfi0:
 ; SSE-NEXT:    .cfi_def_cfa_offset 16
 ; SSE-NEXT:    movl $42, %esi
 ; SSE-NEXT:    movl $256, %edx # imm = 0x100
 ; SSE-NEXT:    callq memset
 ; SSE-NEXT:    popq %rax
 ; SSE-NEXT:    retq
 ;
 ; SSE2FAST-LABEL: memset_256_nonzero_bytes:

test/CodeGen/X86/merge-consecutive-loads-128.ll

 ; AVX-LABEL: merge_2i64_i64_12:
 ; AVX:       # BB#0:
 ; AVX-NEXT:    vmovups 8(%rdi), %xmm0
 ; AVX-NEXT:    retq
 ;
 ; X32-SSE1-LABEL: merge_2i64_i64_12:
 ; X32-SSE1:       # BB#0:
 ; X32-SSE1-NEXT:    pushl %edi
-; X32-SSE1-NEXT:  .Ltmp0:
+; X32-SSE1-NEXT:  .Lcfi0:
 ; X32-SSE1-NEXT:    .cfi_def_cfa_offset 8
 ; X32-SSE1-NEXT:    pushl %esi
-; X32-SSE1-NEXT:  .Ltmp1:
+; X32-SSE1-NEXT:  .Lcfi1:
 ; X32-SSE1-NEXT:    .cfi_def_cfa_offset 12
-; X32-SSE1-NEXT:  .Ltmp2:
+; X32-SSE1-NEXT:  .Lcfi2:
 ; X32-SSE1-NEXT:    .cfi_offset %esi, -12
-; X32-SSE1-NEXT:  .Ltmp3:
+; X32-SSE1-NEXT:  .Lcfi3:
 ; X32-SSE1-NEXT:    .cfi_offset %edi, -8
 ; X32-SSE1-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-SSE1-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X32-SSE1-NEXT:    movl 8(%ecx), %edx
 ; X32-SSE1-NEXT:    movl 12(%ecx), %esi
 ; X32-SSE1-NEXT:    movl 16(%ecx), %edi
 ; X32-SSE1-NEXT:    movl 20(%ecx), %ecx
 ; X32-SSE1-NEXT:    movl %ecx, 12(%eax)

 ; AVX-LABEL: merge_4i32_i32_23u5:
 ; AVX:       # BB#0:
 ; AVX-NEXT:    vmovups 8(%rdi), %xmm0
 ; AVX-NEXT:    retq
 ;
 ; X32-SSE1-LABEL: merge_4i32_i32_23u5:
 ; X32-SSE1:       # BB#0:
 ; X32-SSE1-NEXT:    pushl %esi
-; X32-SSE1-NEXT:  .Ltmp4:
+; X32-SSE1-NEXT:  .Lcfi4:
 ; X32-SSE1-NEXT:    .cfi_def_cfa_offset 8
-; X32-SSE1-NEXT:  .Ltmp5:
+; X32-SSE1-NEXT:  .Lcfi5:
 ; X32-SSE1-NEXT:    .cfi_offset %esi, -8
 ; X32-SSE1-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-SSE1-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X32-SSE1-NEXT:    movl 8(%ecx), %edx
 ; X32-SSE1-NEXT:    movl 12(%ecx), %esi
 ; X32-SSE1-NEXT:    movl 20(%ecx), %ecx
 ; X32-SSE1-NEXT:    movl %esi, 4(%eax)
 ; X32-SSE1-NEXT:    movl %edx, (%eax)

 ; AVX-LABEL: merge_8i16_i16_23u567u9:
 ; AVX:       # BB#0:
 ; AVX-NEXT:    vmovups 4(%rdi), %xmm0
 ; AVX-NEXT:    retq
 ;
 ; X32-SSE1-LABEL: merge_8i16_i16_23u567u9:
 ; X32-SSE1:       # BB#0:
 ; X32-SSE1-NEXT:    pushl %ebp
-; X32-SSE1-NEXT:  .Ltmp6:
+; X32-SSE1-NEXT:  .Lcfi6:
 ; X32-SSE1-NEXT:    .cfi_def_cfa_offset 8
 ; X32-SSE1-NEXT:    pushl %ebx
-; X32-SSE1-NEXT:  .Ltmp7:
+; X32-SSE1-NEXT:  .Lcfi7:
 ; X32-SSE1-NEXT:    .cfi_def_cfa_offset 12
 ; X32-SSE1-NEXT:    pushl %edi
-; X32-SSE1-NEXT:  .Ltmp8:
+; X32-SSE1-NEXT:  .Lcfi8:
 ; X32-SSE1-NEXT:    .cfi_def_cfa_offset 16
 ; X32-SSE1-NEXT:    pushl %esi
-; X32-SSE1-NEXT:  .Ltmp9:
+; X32-SSE1-NEXT:  .Lcfi9:
 ; X32-SSE1-NEXT:    .cfi_def_cfa_offset 20
-; X32-SSE1-NEXT:  .Ltmp10:
+; X32-SSE1-NEXT:  .Lcfi10:
 ; X32-SSE1-NEXT:    .cfi_offset %esi, -20
-; X32-SSE1-NEXT:  .Ltmp11:
+; X32-SSE1-NEXT:  .Lcfi11:
 ; X32-SSE1-NEXT:    .cfi_offset %edi, -16
-; X32-SSE1-NEXT:  .Ltmp12:
+; X32-SSE1-NEXT:  .Lcfi12:
 ; X32-SSE1-NEXT:    .cfi_offset %ebx, -12
-; X32-SSE1-NEXT:  .Ltmp13:
+; X32-SSE1-NEXT:  .Lcfi13:
 ; X32-SSE1-NEXT:    .cfi_offset %ebp, -8
 ; X32-SSE1-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-SSE1-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X32-SSE1-NEXT:    movzwl 4(%ecx), %edx
 ; X32-SSE1-NEXT:    movzwl 6(%ecx), %esi
 ; X32-SSE1-NEXT:    movzwl 10(%ecx), %edi
 ; X32-SSE1-NEXT:    movzwl 12(%ecx), %ebx
 ; X32-SSE1-NEXT:    movzwl 14(%ecx), %ebp

 ; AVX-LABEL: merge_8i16_i16_45u7zzzz:
 ; AVX:       # BB#0:
 ; AVX-NEXT:    vmovq {{.*#+}} xmm0 = mem[0],zero
 ; AVX-NEXT:    retq
 ;
 ; X32-SSE1-LABEL: merge_8i16_i16_45u7zzzz:
 ; X32-SSE1:       # BB#0:
 ; X32-SSE1-NEXT:    pushl %esi
-; X32-SSE1-NEXT:  .Ltmp14:
+; X32-SSE1-NEXT:  .Lcfi14:
 ; X32-SSE1-NEXT:    .cfi_def_cfa_offset 8
-; X32-SSE1-NEXT:  .Ltmp15:
+; X32-SSE1-NEXT:  .Lcfi15:
 ; X32-SSE1-NEXT:    .cfi_offset %esi, -8
 ; X32-SSE1-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-SSE1-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X32-SSE1-NEXT:    movzwl 8(%ecx), %edx
 ; X32-SSE1-NEXT:    movzwl 10(%ecx), %esi
 ; X32-SSE1-NEXT:    movzwl 14(%ecx), %ecx
 ; X32-SSE1-NEXT:    movw %si, 2(%eax)
 ; X32-SSE1-NEXT:    movw %dx, (%eax)

 ; AVX-LABEL: merge_16i8_i8_01u3456789ABCDuF:
 ; AVX:       # BB#0:
 ; AVX-NEXT:    vmovups (%rdi), %xmm0
 ; AVX-NEXT:    retq
 ;
 ; X32-SSE1-LABEL: merge_16i8_i8_01u3456789ABCDuF:
 ; X32-SSE1:       # BB#0:
 ; X32-SSE1-NEXT:    pushl %ebx
-; X32-SSE1-NEXT:  .Ltmp16:
+; X32-SSE1-NEXT:  .Lcfi16:
 ; X32-SSE1-NEXT:    .cfi_def_cfa_offset 8
 ; X32-SSE1-NEXT:    subl $12, %esp
-; X32-SSE1-NEXT:  .Ltmp17:
+; X32-SSE1-NEXT:  .Lcfi17:
 ; X32-SSE1-NEXT:    .cfi_def_cfa_offset 20
-; X32-SSE1-NEXT:  .Ltmp18:
+; X32-SSE1-NEXT:  .Lcfi18:
 ; X32-SSE1-NEXT:    .cfi_offset %ebx, -8
 ; X32-SSE1-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-SSE1-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X32-SSE1-NEXT:    movb (%ecx), %dl
 ; X32-SSE1-NEXT:    movb %dl, {{[0-9]+}}(%esp) # 1-byte Spill
 ; X32-SSE1-NEXT:    movb 1(%ecx), %dl
 ; X32-SSE1-NEXT:    movb %dl, {{[0-9]+}}(%esp) # 1-byte Spill
 ; X32-SSE1-NEXT:    movb 3(%ecx), %dl

 ; AVX-LABEL: merge_16i8_i8_0123uu67uuuuuzzz:
 ; AVX:       # BB#0:
 ; AVX-NEXT:    vmovq {{.*#+}} xmm0 = mem[0],zero
 ; AVX-NEXT:    retq
 ;
 ; X32-SSE1-LABEL: merge_16i8_i8_0123uu67uuuuuzzz:
 ; X32-SSE1:       # BB#0:
 ; X32-SSE1-NEXT:    pushl %ebx
-; X32-SSE1-NEXT:  .Ltmp19:
+; X32-SSE1-NEXT:  .Lcfi19:
 ; X32-SSE1-NEXT:    .cfi_def_cfa_offset 8
 ; X32-SSE1-NEXT:    pushl %eax
-; X32-SSE1-NEXT:  .Ltmp20:
+; X32-SSE1-NEXT:  .Lcfi20:
 ; X32-SSE1-NEXT:    .cfi_def_cfa_offset 12
-; X32-SSE1-NEXT:  .Ltmp21:
+; X32-SSE1-NEXT:  .Lcfi21:
 ; X32-SSE1-NEXT:    .cfi_offset %ebx, -8
 ; X32-SSE1-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-SSE1-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X32-SSE1-NEXT:    movb (%ecx), %dl
 ; X32-SSE1-NEXT:    movb %dl, {{[0-9]+}}(%esp) # 1-byte Spill
 ; X32-SSE1-NEXT:    movb 1(%ecx), %dh
 ; X32-SSE1-NEXT:    movb 2(%ecx), %bl
 ; X32-SSE1-NEXT:    movb 3(%ecx), %bh

 ; AVX-NEXT:    vmovq {{.*#+}} xmm0 = mem[0],zero
 ; AVX-NEXT:    vmovq {{.*#+}} xmm1 = mem[0],zero
 ; AVX-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
 ; AVX-NEXT:    retq
 ;
 ; X32-SSE1-LABEL: merge_2i64_i64_12_volatile:
 ; X32-SSE1:       # BB#0:
 ; X32-SSE1-NEXT:    pushl %edi
-; X32-SSE1-NEXT:  .Ltmp22:
+; X32-SSE1-NEXT:  .Lcfi22:
 ; X32-SSE1-NEXT:    .cfi_def_cfa_offset 8
 ; X32-SSE1-NEXT:    pushl %esi
-; X32-SSE1-NEXT:  .Ltmp23:
+; X32-SSE1-NEXT:  .Lcfi23:
 ; X32-SSE1-NEXT:    .cfi_def_cfa_offset 12
-; X32-SSE1-NEXT:  .Ltmp24:
+; X32-SSE1-NEXT:  .Lcfi24:
 ; X32-SSE1-NEXT:    .cfi_offset %esi, -12
-; X32-SSE1-NEXT:  .Ltmp25:
+; X32-SSE1-NEXT:  .Lcfi25:
 ; X32-SSE1-NEXT:    .cfi_offset %edi, -8
 ; X32-SSE1-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-SSE1-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X32-SSE1-NEXT:    movl 8(%ecx), %edx
 ; X32-SSE1-NEXT:    movl 12(%ecx), %esi
 ; X32-SSE1-NEXT:    movl 16(%ecx), %edi
 ; X32-SSE1-NEXT:    movl 20(%ecx), %ecx
 ; X32-SSE1-NEXT:    movl %ecx, 12(%eax)

test/CodeGen/X86/movpc32-check.ll

 !7 = !{i32 2, !"Dwarf Version", i32 4}
 !8 = !{i32 2, !"Debug Info Version", i32 3}
 !9 = !{i32 1, !"PIC Level", i32 2}
 !10 = !{!"clang version 3.8.0 (http://llvm.org/git/clang.git 3490ab8630d5643f71f1f04e46984f05b27b8d67) (http://llvm.org/git/llvm.git d2643e2ff955ed234944fe3c6b4ffc1250085843)"}
 !11 = !DILocation(line: 4, column: 3, scope: !4)
 !12 = !DILocation(line: 5, column: 1, scope: !4)
 
 ; CHECK: calll .L0$pb
-; CHECK-NEXT: .Ltmp3:
+; CHECK-NEXT: .Lcfi3:
 ; CHECK-NEXT: .cfi_adjust_cfa_offset 4
 ; CHECK-NEXT: .L0$pb:
 ; CHECK-NEXT: popl
-; CHECK-NEXT: .Ltmp4:
+; CHECK-NEXT: .Lcfi4:
 ; CHECK-NEXT: .cfi_adjust_cfa_offset -4

test/CodeGen/X86/patchpoint-webkit_jscc.ll

 ; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=corei7                             < %s | FileCheck %s
 ; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=corei7 -fast-isel -fast-isel-abort=1 < %s | FileCheck %s --check-prefix=FAST
 
 ; Test the webkit_jscc calling convention.
 ; One argument will be passed in register, the other will be pushed on the stack.
 ; Return value in $rax.
 define void @jscall_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
 entry:
 ; CHECK-LABEL: jscall_patchpoint_codegen:
-; CHECK:      Ltmp
+; CHECK:      Lcfi
 ; CHECK:      movq %r{{.+}}, (%rsp)
 ; CHECK:      movq %r{{.+}}, %rax
 ; CHECK:      Ltmp
 ; CHECK-NEXT: movabsq $-559038736, %r11
 ; CHECK-NEXT: callq *%r11
 ; CHECK:      movq %rax, (%rsp)
 ; CHECK:      callq
 ; FAST-LABEL: jscall_patchpoint_codegen:
-; FAST:       Ltmp
+; FAST:       Lcfi
 ; FAST:       movq %r{{.+}}, (%rsp)
 ; FAST:       movq %r{{.+}}, %rax
 ; FAST:       Ltmp
 ; FAST-NEXT:  movabsq $-559038736, %r11
 ; FAST-NEXT:  callq *%r11
 ; FAST:       movq %rax, (%rsp)
 ; FAST:       callq
   %resolveCall2 = inttoptr i64 -559038736 to i8*
   %result = tail call webkit_jscc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 15, i8* %resolveCall2, i32 2, i64 %p4, i64 %p2)
   %resolveCall3 = inttoptr i64 -559038737 to i8*
   tail call webkit_jscc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 6, i32 15, i8* %resolveCall3, i32 2, i64 %p4, i64 %result)
   ret void
 }
 
 ; Test if the arguments are properly aligned and that we don't store undef arguments.
 define i64 @jscall_patchpoint_codegen2(i64 %callee) {
 entry:
 ; CHECK-LABEL: jscall_patchpoint_codegen2:
-; CHECK:      Ltmp
+; CHECK:      Lcfi
 ; CHECK:      movq $6, 24(%rsp)
 ; CHECK-NEXT: movl $4, 16(%rsp)
 ; CHECK-NEXT: movq $2, (%rsp)
 ; CHECK:      Ltmp
 ; CHECK-NEXT: movabsq $-559038736, %r11
 ; CHECK-NEXT: callq *%r11
 ; FAST-LABEL: jscall_patchpoint_codegen2:
-; FAST:       Ltmp
+; FAST:       Lcfi
 ; FAST:       movq $2, (%rsp)
 ; FAST-NEXT:  movl $4, 16(%rsp)
 ; FAST-NEXT:  movq $6, 24(%rsp)
 ; FAST:       Ltmp
 ; FAST-NEXT:  movabsq $-559038736, %r11
 ; FAST-NEXT:  callq *%r11
   %call = inttoptr i64 -559038736 to i8*
   %result = call webkit_jscc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 7, i32 15, i8* %call, i32 6, i64 %callee, i64 2, i64 undef, i32 4, i32 undef, i64 6)
   ret i64 %result
 }
 
 ; Test if the arguments are properly aligned and that we don't store undef arguments.
 define i64 @jscall_patchpoint_codegen3(i64 %callee) {
 entry:
 ; CHECK-LABEL: jscall_patchpoint_codegen3:
-; CHECK:      Ltmp
+; CHECK:      Lcfi
 ; CHECK:      movq $10, 48(%rsp)
 ; CHECK-NEXT: movl  $8, 36(%rsp)
 ; CHECK-NEXT: movq  $6, 24(%rsp)
 ; CHECK-NEXT: movl  $4, 16(%rsp)
 ; CHECK-NEXT: movq  $2, (%rsp)
 ; CHECK:      Ltmp
 ; CHECK-NEXT: movabsq $-559038736, %r11
 ; CHECK-NEXT: callq *%r11
 ; FAST-LABEL: jscall_patchpoint_codegen3:
-; FAST:       Ltmp
+; FAST:       Lcfi
 ; FAST:       movq  $2, (%rsp)
 ; FAST-NEXT:  movl  $4, 16(%rsp)
 ; FAST-NEXT:  movq  $6, 24(%rsp)
 ; FAST-NEXT:  movl  $8, 36(%rsp)
 ; FAST-NEXT:  movq $10, 48(%rsp)
 ; FAST:       Ltmp
 ; FAST-NEXT:  movabsq $-559038736, %r11
 ; FAST-NEXT:  callq *%r11
   %call = inttoptr i64 -559038736 to i8*
   %result = call webkit_jscc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 7, i32 15, i8* %call, i32 10, i64 %callee, i64 2, i64 undef, i32 4, i32 undef, i64 6, i32 undef, i32 8, i32 undef, i64 10)
   ret i64 %result
 }
 
 declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
 declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)
 

test/CodeGen/X86/pr27071.ll

sw.epilog:                                        ; preds = %entry
   ret void
 }
 
 declare void @x2(i8*)
 
 attributes #0 = { optsize }
 
 ; CHECK-LABEL: x3:
-; CHECK:         addl    $_GLOBAL_OFFSET_TABLE_+(.Ltmp4-.L0$pb), %[[REG:.*]]
+; CHECK:         addl    $_GLOBAL_OFFSET_TABLE_+(.Ltmp0-.L0$pb), %[[REG:.*]]
 ; CHECK-NEXT:    leal    x1@TLSGD(,%[[REG]]), %eax
 ; CHECK-NEXT:    calll   ___tls_get_addr@PLT
 ; CHECK-NEXT:    cmpl    $92, (%eax)

test/CodeGen/X86/pr29112.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx512f | FileCheck %s
 
 declare <4 x float> @foo(<4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>)
 
 ; Due to a bug in X86RegisterInfo::getLargestLegalSuperClass this test case was trying to use XMM16 and spill it without VLX support for the necessary store instruction. We briefly implemented the spill using VEXTRACTF32X4, but the bug in getLargestLegalSuperClass has now been fixed so we no longer use XMM16.
 
 define <4 x float> @bar(<4 x float>* %a1p, <4 x float>* %a2p, <4 x float> %a3, <4 x float> %a4, <16 x float>%c1, <16 x float>%c2) {
 ; CHECK-LABEL: bar:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    subq $88, %rsp
-; CHECK-NEXT:  .Ltmp0:
+; CHECK-NEXT:  .Lcfi0:
 ; CHECK-NEXT:    .cfi_def_cfa_offset 96
 ; CHECK-NEXT:    vmovaps %xmm1, {{[0-9]+}}(%rsp) # 16-byte Spill
 ; CHECK-NEXT:    vextractf32x4 $1, %zmm3, %xmm1
 ; CHECK-NEXT:    vextractf32x4 $1, %zmm2, %xmm8
 ; CHECK-NEXT:    vinsertps {{.*#+}} xmm9 = xmm8[0],xmm1[0],xmm8[2,3]
 ; CHECK-NEXT:    vinsertps {{.*#+}} xmm0 = xmm9[0,1],xmm2[1],xmm9[3]
 ; CHECK-NEXT:    vinsertps {{.*#+}} xmm15 = xmm0[0,1,2],xmm3[1]
 ; CHECK-NEXT:    vblendps {{.*#+}} xmm4 = xmm8[0],xmm1[1],xmm8[2,3]

test/CodeGen/X86/pr30430.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx512f -O0 | FileCheck %s
 
 define <16 x float> @makefloat(float %f1, float %f2, float %f3, float %f4, float %f5, float %f6, float %f7, float %f8, float %f9, float %f10, float %f11, float %f12, float %f13, float %f14, float %f15, float %f16) #0 {
 ; CHECK-LABEL: makefloat:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    pushq %rbp
-; CHECK-NEXT:  .Ltmp0:
+; CHECK-NEXT:  .Lcfi0:
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:  .Ltmp1:
+; CHECK-NEXT:  .Lcfi1:
 ; CHECK-NEXT:    .cfi_offset %rbp, -16
 ; CHECK-NEXT:    movq %rsp, %rbp
-; CHECK-NEXT:  .Ltmp2:
+; CHECK-NEXT:  .Lcfi2:
 ; CHECK-NEXT:    .cfi_def_cfa_register %rbp
 ; CHECK-NEXT:    andq $-64, %rsp
 ; CHECK-NEXT:    subq $256, %rsp # imm = 0x100
 ; CHECK-NEXT:    vmovss {{.*#+}} xmm8 = mem[0],zero,zero,zero
 ; CHECK-NEXT:    vmovss {{.*#+}} xmm9 = mem[0],zero,zero,zero
 ; CHECK-NEXT:    vmovss {{.*#+}} xmm10 = mem[0],zero,zero,zero
 ; CHECK-NEXT:    vmovss {{.*#+}} xmm11 = mem[0],zero,zero,zero
 ; CHECK-NEXT:    vmovss {{.*#+}} xmm12 = mem[0],zero,zero,zero

test/CodeGen/X86/push-cfi.ll

 ; RUN: llc < %s -mtriple=i686-pc-linux | FileCheck %s -check-prefix=LINUX -check-prefix=CHECK
 ; RUN: llc < %s -mtriple=i686-apple-darwin | FileCheck %s -check-prefix=DARWIN -check-prefix=CHECK
 
 declare i32 @__gxx_personality_v0(...)
 declare void @good(i32 %a, i32 %b, i32 %c, i32 %d)
 declare void @large(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f)
 declare void @empty()
 
 ; When we use an invoke, we expect a .cfi_escape GNU_ARGS_SIZE
 ; with size 16 before the invocation. Without FP, we also expect
 ; .cfi_adjust_cfa_offset after each push.
 ; Darwin should not generate pushes in either circumstance.
 ; CHECK-LABEL: test1_nofp:
 ; LINUX: .cfi_escape 0x2e, 0x10
 ; LINUX-NEXT: pushl   $4
-; LINUX-NEXT: Ltmp{{[0-9]+}}:
+; LINUX-NEXT: Lcfi{{[0-9]+}}:
 ; LINUX-NEXT: .cfi_adjust_cfa_offset 4
 ; LINUX-NEXT: pushl   $3
-; LINUX-NEXT: Ltmp{{[0-9]+}}:
+; LINUX-NEXT: Lcfi{{[0-9]+}}:
 ; LINUX-NEXT: .cfi_adjust_cfa_offset 4
 ; LINUX-NEXT: pushl   $2
-; LINUX-NEXT: Ltmp{{[0-9]+}}:
+; LINUX-NEXT: Lcfi{{[0-9]+}}:
 ; LINUX-NEXT: .cfi_adjust_cfa_offset 4
 ; LINUX-NEXT: pushl   $1
-; LINUX-NEXT: Ltmp{{[0-9]+}}:
+; LINUX-NEXT: Lcfi{{[0-9]+}}:
 ; LINUX-NEXT: .cfi_adjust_cfa_offset 4
 ; LINUX-NEXT: call
 ; LINUX-NEXT: addl $16, %esp
 ; LINUX: .cfi_adjust_cfa_offset -16
 ; DARWIN-NOT: .cfi_escape
 ; DARWIN-NOT: pushl
 define void @test1_nofp() #0 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
 entry:

 }
 
 ; If the function has no handlers, we don't need to generate GNU_ARGS_SIZE,
 ; even if it has an unwind table. Without FP, we still need cfi_adjust_cfa_offset,
 ; so darwin should not generate pushes.
 ; CHECK-LABEL: test2_nofp:
 ; LINUX-NOT: .cfi_escape
 ; LINUX: pushl   $4
-; LINUX-NEXT: Ltmp{{[0-9]+}}:
+; LINUX-NEXT: Lcfi{{[0-9]+}}:
 ; LINUX-NEXT: .cfi_adjust_cfa_offset 4
 ; LINUX-NEXT: pushl   $3
-; LINUX-NEXT: Ltmp{{[0-9]+}}:
+; LINUX-NEXT: Lcfi{{[0-9]+}}:
 ; LINUX-NEXT: .cfi_adjust_cfa_offset 4
 ; LINUX-NEXT: pushl   $2
-; LINUX-NEXT: Ltmp{{[0-9]+}}:
+; LINUX-NEXT: Lcfi{{[0-9]+}}:
 ; LINUX-NEXT: .cfi_adjust_cfa_offset 4
 ; LINUX-NEXT: pushl   $1
-; LINUX-NEXT: Ltmp{{[0-9]+}}:
+; LINUX-NEXT: Lcfi{{[0-9]+}}:
 ; LINUX-NEXT: .cfi_adjust_cfa_offset 4
 ; LINUX-NEXT: call
 ; LINUX-NEXT: addl $28, %esp
 ; LINUX: .cfi_adjust_cfa_offset -16
 ; DARWIN-NOT: .cfi_escape
 ; DARWIN-NOT: pushl
 define void @test2_nofp() #0 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
 entry:
cleanup:
   ret void
 }
 
 ; If we did use pushes, we need to reset GNU_ARGS_SIZE before a call
 ; without parameters, but don't need to adjust the cfa offset
 ; CHECK-LABEL: test5_nofp:
 ; LINUX: .cfi_escape 0x2e, 0x10
 ; LINUX-NEXT: pushl   $4
-; LINUX-NEXT: Ltmp{{[0-9]+}}:
+; LINUX-NEXT: Lcfi{{[0-9]+}}:
 ; LINUX-NEXT: .cfi_adjust_cfa_offset 4
 ; LINUX-NEXT: pushl   $3
-; LINUX-NEXT: Ltmp{{[0-9]+}}:
+; LINUX-NEXT: Lcfi{{[0-9]+}}:
 ; LINUX-NEXT: .cfi_adjust_cfa_offset 4
 ; LINUX-NEXT: pushl   $2
-; LINUX-NEXT: Ltmp{{[0-9]+}}:
+; LINUX-NEXT: Lcfi{{[0-9]+}}:
 ; LINUX-NEXT: .cfi_adjust_cfa_offset 4
 ; LINUX-NEXT: pushl   $1
-; LINUX-NEXT: Ltmp{{[0-9]+}}:
+; LINUX-NEXT: Lcfi{{[0-9]+}}:
 ; LINUX-NEXT: .cfi_adjust_cfa_offset 4
 ; LINUX-NEXT: call
 ; LINUX-NEXT: addl $16, %esp
 ; LINUX: .cfi_adjust_cfa_offset -16
 ; LINUX-NOT: .cfi_adjust_cfa_offset
 ; LINUX: .cfi_escape 0x2e, 0x00
 ; LINUX-NOT: .cfi_adjust_cfa_offset
 ; LINUX: call

test/CodeGen/X86/setcc-lowering.ll

entry:
   %3 = sext <8 x i1> %2 to <8 x i16>
   ret <8 x i16> %3
 }
 
 define void @pr26232(i64 %a) {
 ; KNL-32-LABEL: pr26232:
 ; KNL-32:       # BB#0: # %for_loop599.preheader
 ; KNL-32-NEXT:    pushl %esi
-; KNL-32-NEXT:  .Ltmp0:
+; KNL-32-NEXT:  .Lcfi0:
 ; KNL-32-NEXT:    .cfi_def_cfa_offset 8
-; KNL-32-NEXT:  .Ltmp1:
+; KNL-32-NEXT:  .Lcfi1:
 ; KNL-32-NEXT:    .cfi_offset %esi, -8
 ; KNL-32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; KNL-32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; KNL-32-NEXT:    movw $-1, %dx
 ; KNL-32-NEXT:    .p2align 4, 0x90
 ; KNL-32-NEXT:  .LBB1_1: # %for_loop599
 ; KNL-32-NEXT:    # =>This Inner Loop Header: Depth=1
 ; KNL-32-NEXT:    cmpl $65536, %ecx # imm = 0x10000

test/CodeGen/X86/statepoint-allocas.ll

 ; CHECK-NEXT:   .quad 1
 
 ; Large Constants
 ; Statepoint ID only
 ; CHECK: .quad  0
 
 ; Callsites
 ; The GC one
-; CHECK: .long  .Ltmp1-test
+; CHECK: .long  .Ltmp0-test
 ; CHECK: .short 0
 ; CHECK: .short 4
 ; SmallConstant (0)
 ; CHECK: .byte  4
 ; CHECK: .byte  8
 ; CHECK: .short 0
 ; CHECK: .long  0
 ; SmallConstant (0)

 ; CHECK: .short 7
 ; CHECK: .long  0
 ; No Padding or LiveOuts
 ; CHECK: .short 0
 ; CHECK: .short 0
 ; CHECK: .p2align 3
 
 ; The Deopt one
-; CHECK: .long  .Ltmp3-test2
+; CHECK: .long  .Ltmp1-test2
 ; CHECK: .short 0
 ; CHECK: .short 4
 ; SmallConstant (0)
 ; CHECK: .byte  4
 ; CHECK: .byte  8
 ; CHECK: .short 0
 ; CHECK: .long  0
 ; SmallConstant (0)

test/CodeGen/X86/statepoint-call-lowering.ll

entry:
   ret %struct %call1
 }
 
 define i1 @test_relocate(i32 addrspace(1)* %a) gc "statepoint-example" {
 ; CHECK-LABEL: test_relocate
 ; Check that an ununsed relocate has no code-generation impact
 ; CHECK: pushq %rax
 ; CHECK: callq return_i1
-; CHECK-NEXT: .Ltmp11:
+; CHECK-NEXT: .Ltmp5:
 ; CHECK-NEXT: popq %rcx
 ; CHECK-NEXT: retq
 entry:
   %safepoint_token = tail call token (i64, i32, i1 ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_i1f(i64 0, i32 0, i1 ()* @return_i1, i32 0, i32 0, i32 0, i32 0, i32 addrspace(1)* %a)
   %call1 = call i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(token %safepoint_token,  i32 7, i32 7)
   %call2 = call zeroext i1 @llvm.experimental.gc.result.i1(token %safepoint_token)
   ret i1 %call2
 }

test/CodeGen/X86/statepoint-gctransition-call-lowering.ll

entry:
   ret float %call1
 }
 
 define i1 @test_relocate(i32 addrspace(1)* %a) gc "statepoint-example" {
 ; CHECK-LABEL: test_relocate
 ; Check that an ununsed relocate has no code-generation impact
 ; CHECK: pushq %rax
 ; CHECK: callq return_i1
-; CHECK-NEXT: .Ltmp9:
+; CHECK-NEXT: .Ltmp4:
 ; CHECK-NEXT: popq %rcx
 ; CHECK-NEXT: retq
 entry:
   %safepoint_token = tail call token (i64, i32, i1 ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_i1f(i64 0, i32 0, i1 ()* @return_i1, i32 0, i32 1, i32 0, i32 0, i32 addrspace(1)* %a)
   %call1 = call i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(token %safepoint_token, i32 7, i32 7)
   %call2 = call zeroext i1 @llvm.experimental.gc.result.i1(token %safepoint_token)
   ret i1 %call2
 }

 declare token @llvm.experimental.gc.statepoint.p0f_p0i32f(i64, i32, i32* ()*, i32, i32, ...)
 declare i32* @llvm.experimental.gc.result.p0i32(token)
 
 declare token @llvm.experimental.gc.statepoint.p0f_f32f(i64, i32, float ()*, i32, i32, ...)
 declare float @llvm.experimental.gc.result.f32(token)
 
 declare token @llvm.experimental.gc.statepoint.p0f_isVoidi32varargf(i64, i32, void (i32, ...)*, i32, i32, ...)
 
-declare i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(token, i32, i32)
+declare i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(token, i32, i32)
 

test/CodeGen/X86/statepoint-live-in.ll

 ; RUN: llc -O3 < %s | FileCheck %s
 target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-apple-macosx10.11.0"
 
 declare void @bar() #0
 declare void @baz()
 
 define void @test1(i32 %a) gc "statepoint-example" {
 entry:
 ; We expect the argument to be passed in an extra register to bar
 ; CHECK-LABEL: test1
 ; CHECK:       pushq  %rax
-; CHECK-NEXT: Ltmp0:
+; CHECK-NEXT: Lcfi0:
 ; CHECK-NEXT:  .cfi_def_cfa_offset 16
 ; CHECK-NEXT: callq _bar
   %statepoint_token1 = call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 2882400000, i32 0, void ()* @bar, i32 0, i32 2, i32 0, i32 1, i32 %a)
   ret void
 }
 
 define void @test2(i32 %a, i32 %b) gc "statepoint-example" {
 entry:

 ; Show the interaction of live-through spilling followed by live-in.
 define void @test6(i32 %a) gc "statepoint-example" {
 entry:
 ; TODO: We could have reused the previous spill slot at zero additional cost.
 ; CHECK-LABEL: test6
 ; CHECK:        movl %edi, %ebx
 ; CHECK:        movl %ebx, 12(%rsp)
 ; CHECK-NEXT:   callq _baz
-; CHECK-NEXT:  Ltmp30:
+; CHECK-NEXT:  Ltmp6:
 ; CHECK-NEXT:   callq _bar
   call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 2882400000, i32 0, void ()* @baz, i32 0, i32 0, i32 0, i32 1, i32 %a)
   call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 2882400000, i32 0, void ()* @bar, i32 0, i32 2, i32 0, i32 1, i32 %a)
   ret void
 }
 
 
-; CHECK: Ltmp1-_test1
+; CHECK: Ltmp0-_test1
 ; CHECK:      .byte 1
 ; CHECK-NEXT: .byte 4
 ; CHECK-NEXT: .short  5
 ; CHECK-NEXT: .long 0
 
-; CHECK: Ltmp7-_test2
+; CHECK: Ltmp1-_test2
 ; CHECK:      .byte 1
 ; CHECK-NEXT: .byte 4
 ; CHECK-NEXT: .short  6
 ; CHECK-NEXT: .long 0
 ; CHECK:      .byte 1
 ; CHECK-NEXT: .byte 4
 ; CHECK-NEXT: .short  3
 ; CHECK-NEXT: .long 0
-; CHECK: Ltmp8-_test2
+; CHECK: Ltmp2-_test2
 ; CHECK:      .byte 1
 ; CHECK-NEXT: .byte 4
 ; CHECK-NEXT: .short  3
 ; CHECK-NEXT: .long 0
 ; CHECK:      .byte 1
 ; CHECK-NEXT: .byte 4
 ; CHECK-NEXT: .short  6
 ; CHECK-NEXT: .long 0
 
 declare token @llvm.experimental.gc.statepoint.p0f_isVoidf(i64, i32, void ()*, i32, i32, ...)
 declare i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(token, i32, i32)
 
 
 attributes #0 = { "deopt-lowering"="live-in" }
 attributes #1 = { "deopt-lowering"="live-through" }

test/CodeGen/X86/statepoint-stackmap-format.ll

 ; test
 ;
 
 ; Statepoint ID
 ; CHECK-NEXT: .quad 0
 
 ; Callsites
 ; Constant arguments
-; CHECK-NEXT: .long .Ltmp1-test
+; CHECK-NEXT: .long .Ltmp0-test
 ; CHECK: .short 0
 ; CHECK: .short 11
 ; SmallConstant (0)
 ; CHECK: .byte  4
 ; CHECK: .byte  8
 ; CHECK: .short 0
 ; CHECK: .long  0
 ; SmallConstant (0)

 ;
 ; test_derived_arg
 
 ; Statepoint ID
 ; CHECK-NEXT: .quad 0
 
 ; Callsites
 ; Constant arguments
-; CHECK-NEXT: .long .Ltmp3-test_derived_arg
+; CHECK-NEXT: .long .Ltmp1-test_derived_arg
 ; CHECK: .short 0
 ; CHECK: .short 11
 ; SmallConstant (0)
 ; CHECK: .byte  4
 ; CHECK: .byte  8
 ; CHECK: .short 0
 ; CHECK: .long  0
 ; SmallConstant (2)

 ; CHECK: .p2align 3
 
 ; Records for the test_id function:
 
 ; The Statepoint ID:
 ; CHECK-NEXT: .quad 237
 
 ; Instruction Offset
-; CHECK-NEXT: .long .Ltmp5-test_id
+; CHECK-NEXT: .long .Ltmp2-test_id
 
 ; Reserved:
 ; CHECK: .short 0
 
 ; NumLocations:
 ; CHECK: .short 3
 
 ; StkMapRecord[0]:

test/CodeGen/X86/statepoint-vector.ll

 ; CHECK: callq  do_safepoint
 ; CHECK: pop
   %safepoint_token = call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @do_safepoint, i32 0, i32 0, i32 0, i32 1, i128 0)
   ret void
 }
 
 ; CHECK: __LLVM_StackMaps:
 
-; CHECK: .Ltmp1-test
+; CHECK: .Ltmp0-test
 ; Check for the two spill slots
 ; Stack Maps:     Loc 3: Indirect 7+0 [encoding: .byte 3, .byte 16, .short 7, .int 0]
 ; Stack Maps:     Loc 4: Indirect 7+0 [encoding: .byte 3, .byte 16, .short 7, .int 0]
 ; CHECK: .byte  3
 ; CHECK: .byte  16
 ; CHECK: .short 7
 ; CHECK: .long  0
 ; CHECK: .byte  3
 ; CHECK: .byte  16
 ; CHECK: .short 7
 ; CHECK: .long  0
 
-; CHECK: .Ltmp3-test2
+; CHECK: .Ltmp1-test2
 ; Check for the two spill slots
 ; Stack Maps:     Loc 3: Indirect 7+16  [encoding: .byte 3, .byte 16, .short 7, .int 16]
 ; Stack Maps:     Loc 4: Indirect 7+0 [encoding: .byte 3, .byte 16, .short 7, .int 0]
 ; CHECK: .byte  3
 ; CHECK: .byte  16
 ; CHECK: .short 7
 ; CHECK: .long  16
 ; CHECK: .byte  3
 ; CHECK: .byte  16
 ; CHECK: .short 7
 ; CHECK: .long  0
 
-; CHECK: .Ltmp5-test3
+; CHECK: .Ltmp2-test3
 ; Check for the four spill slots
 ; Stack Maps:     Loc 3: Indirect 7+16  [encoding: .byte 3, .byte 16, .short 7, .int 16]
 ; Stack Maps:     Loc 4: Indirect 7+16  [encoding: .byte 3, .byte 16, .short 7, .int 16]
 ; Stack Maps:     Loc 5: Indirect 7+16  [encoding: .byte 3, .byte 16, .short 7, .int 16]
 ; Stack Maps:     Loc 6: Indirect 7+0   [encoding: .byte 3, .byte 16, .short 7, .int 0]
 ; CHECK: .byte  3
 ; CHECK: .byte  16
 ; CHECK: .short 7

test/CodeGen/X86/tls-pie.ll

 
 entry:
   ret i32* @i
 }
 
 define i32 @f3() {
 ; X32-LABEL: f3:
 ; X32:      calll .L{{[0-9]+}}$pb
-; X32-NEXT: .Ltmp{{[0-9]+}}:
+; X32-NEXT: .Lcfi{{[0-9]+}}:
 ; X32-NEXT: .cfi_adjust_cfa_offset 4
 ; X32-NEXT: .L{{[0-9]+}}$pb:
 ; X32-NEXT: popl %eax
-; X32-NEXT: .Ltmp{{[0-9]+}}:
+; X32-NEXT: .Lcfi{{[0-9]+}}:
 ; X32-NEXT: .cfi_adjust_cfa_offset -4
 ; X32-NEXT: .Ltmp{{[0-9]+}}:
 ; X32-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp{{[0-9]+}}-.L{{[0-9]+}}$pb), %eax
 ; X32-NEXT: movl i2@GOTNTPOFF(%eax), %eax
 ; X32-NEXT: movl %gs:(%eax), %eax
 ; X32-NEXT: ret
 ; X64-LABEL: f3:
 ; X64:      movq i2@GOTTPOFF(%rip), %rax
 ; X64-NEXT: movl %fs:(%rax), %eax
 ; X64-NEXT: ret
 
 entry:
   %tmp1 = load i32, i32* @i2
   ret i32 %tmp1
 }
 
 define i32* @f4() {
 ; X32-LABEL: f4:
 ; X32:      calll .L{{[0-9]+}}$pb
-; X32-NEXT: .Ltmp{{[0-9]+}}:
+; X32-NEXT: .Lcfi{{[0-9]+}}:
 ; X32-NEXT: .cfi_adjust_cfa_offset 4
 ; X32-NEXT: .L{{[0-9]+}}$pb:
 ; X32-NEXT: popl %ecx
-; X32-NEXT: .Ltmp{{[0-9]+}}:
+; X32-NEXT: .Lcfi{{[0-9]+}}:
 ; X32-NEXT: .cfi_adjust_cfa_offset -4
 ; X32-NEXT: .Ltmp{{[0-9]+}}:
 ; X32-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp{{[0-9]+}}-.L{{[0-9]+}}$pb), %ecx
 ; X32-NEXT: movl %gs:0, %eax
 ; X32-NEXT: addl i2@GOTNTPOFF(%ecx), %eax
 ; X32-NEXT: ret
 ; X64-LABEL: f4:
 ; X64:      movq %fs:0, %rax

test/CodeGen/X86/tls-shrink-wrapping.ll

if.end:                                           ; preds = %if.then, %entry
   %tmp1 = phi i32 [ 0, %entry ], [ %.pre, %if.then ]
   ret i32 %tmp1
 }
 
 ; CHECK: g:                                      # @g
 ; CHECK-NEXT:         .cfi_startproc
 ; CHECK-NEXT: # BB#0:                                 # %entry
 ; CHECK-NEXT:         pushq   %rbp
-; CHECK-NEXT: .Ltmp0:
+; CHECK-NEXT: .Lcfi0:
 ; CHECK-NEXT:         .cfi_def_cfa_offset 16
-; CHECK-NEXT: .Ltmp1:
+; CHECK-NEXT: .Lcfi1:
 ; CHECK-NEXT:         .cfi_offset %rbp, -16
 ; CHECK-NEXT:         movq    %rsp, %rbp
-; CHECK-NEXT: .Ltmp2:
+; CHECK-NEXT: .Lcfi2:
 ; CHECK-NEXT:         .cfi_def_cfa_register %rbp
 ; CHECK-NEXT:         pushq   %rbx
 ; CHECK-NEXT:         pushq   %rax
-; CHECK-NEXT: .Ltmp3:
+; CHECK-NEXT: .Lcfi3:
 ; CHECK-NEXT:         .cfi_offset %rbx, -24
 ; CHECK-NEXT:         data16
 ; CHECK-NEXT:         leaq    i@TLSGD(%rip), %rdi
 
 declare void @f(...) #1
 
 attributes #0 = { nounwind uwtable "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2" "unsafe-fp-math"="false" "use-soft-float"="false" }
 attributes #1 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2" "unsafe-fp-math"="false" "use-soft-float"="false" }
 attributes #2 = { nounwind }

test/CodeGen/X86/vector-sext.ll

 ; SSE41-NEXT:    punpckhbw {{.*#+}} xmm1 = xmm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
 ; SSE41-NEXT:    psllw $15, %xmm1
 ; SSE41-NEXT:    psraw $15, %xmm1
 ; SSE41-NEXT:    retq
 ;
 ; AVX1-LABEL: load_sext_16i1_to_16i16:
 ; AVX1:       # BB#0: # %entry
 ; AVX1-NEXT:    pushq %rbp
-; AVX1-NEXT:  .Ltmp0:
+; AVX1-NEXT:  .Lcfi0:
 ; AVX1-NEXT:    .cfi_def_cfa_offset 16
 ; AVX1-NEXT:    pushq %r15
-; AVX1-NEXT:  .Ltmp1:
+; AVX1-NEXT:  .Lcfi1:
 ; AVX1-NEXT:    .cfi_def_cfa_offset 24
 ; AVX1-NEXT:    pushq %r14
-; AVX1-NEXT:  .Ltmp2:
+; AVX1-NEXT:  .Lcfi2:
 ; AVX1-NEXT:    .cfi_def_cfa_offset 32
 ; AVX1-NEXT:    pushq %r13
-; AVX1-NEXT:  .Ltmp3:
+; AVX1-NEXT:  .Lcfi3:
 ; AVX1-NEXT:    .cfi_def_cfa_offset 40
 ; AVX1-NEXT:    pushq %r12
-; AVX1-NEXT:  .Ltmp4:
+; AVX1-NEXT:  .Lcfi4:
 ; AVX1-NEXT:    .cfi_def_cfa_offset 48
 ; AVX1-NEXT:    pushq %rbx
-; AVX1-NEXT:  .Ltmp5:
+; AVX1-NEXT:  .Lcfi5:
 ; AVX1-NEXT:    .cfi_def_cfa_offset 56
-; AVX1-NEXT:  .Ltmp6:
+; AVX1-NEXT:  .Lcfi6:
 ; AVX1-NEXT:    .cfi_offset %rbx, -56
-; AVX1-NEXT:  .Ltmp7:
+; AVX1-NEXT:  .Lcfi7:
 ; AVX1-NEXT:    .cfi_offset %r12, -48
-; AVX1-NEXT:  .Ltmp8:
+; AVX1-NEXT:  .Lcfi8:
 ; AVX1-NEXT:    .cfi_offset %r13, -40
-; AVX1-NEXT:  .Ltmp9:
+; AVX1-NEXT:  .Lcfi9:
 ; AVX1-NEXT:    .cfi_offset %r14, -32
-; AVX1-NEXT:  .Ltmp10:
+; AVX1-NEXT:  .Lcfi10:
 ; AVX1-NEXT:    .cfi_offset %r15, -24
-; AVX1-NEXT:  .Ltmp11:
+; AVX1-NEXT:  .Lcfi11:
 ; AVX1-NEXT:    .cfi_offset %rbp, -16
 ; AVX1-NEXT:    movswq (%rdi), %rax
 ; AVX1-NEXT:    movq %rax, %rcx
 ; AVX1-NEXT:    shlq $55, %rcx
 ; AVX1-NEXT:    sarq $63, %rcx
 ; AVX1-NEXT:    vmovd %ecx, %xmm0
 ; AVX1-NEXT:    movq %rax, %r8
 ; AVX1-NEXT:    movq %rax, %r10

 ; AVX1-NEXT:    popq %r14
 ; AVX1-NEXT:    popq %r15
 ; AVX1-NEXT:    popq %rbp
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: load_sext_16i1_to_16i16:
 ; AVX2:       # BB#0: # %entry
 ; AVX2-NEXT:    pushq %rbp
-; AVX2-NEXT:  .Ltmp0:
+; AVX2-NEXT:  .Lcfi0:
 ; AVX2-NEXT:    .cfi_def_cfa_offset 16
 ; AVX2-NEXT:    pushq %r15
-; AVX2-NEXT:  .Ltmp1:
+; AVX2-NEXT:  .Lcfi1:
 ; AVX2-NEXT:    .cfi_def_cfa_offset 24
 ; AVX2-NEXT:    pushq %r14
-; AVX2-NEXT:  .Ltmp2:
+; AVX2-NEXT:  .Lcfi2:
 ; AVX2-NEXT:    .cfi_def_cfa_offset 32
 ; AVX2-NEXT:    pushq %r13
-; AVX2-NEXT:  .Ltmp3:
+; AVX2-NEXT:  .Lcfi3:
 ; AVX2-NEXT:    .cfi_def_cfa_offset 40
 ; AVX2-NEXT:    pushq %r12
-; AVX2-NEXT:  .Ltmp4:
+; AVX2-NEXT:  .Lcfi4:
 ; AVX2-NEXT:    .cfi_def_cfa_offset 48
 ; AVX2-NEXT:    pushq %rbx
-; AVX2-NEXT:  .Ltmp5:
+; AVX2-NEXT:  .Lcfi5:
 ; AVX2-NEXT:    .cfi_def_cfa_offset 56
-; AVX2-NEXT:  .Ltmp6:
+; AVX2-NEXT:  .Lcfi6:
 ; AVX2-NEXT:    .cfi_offset %rbx, -56
-; AVX2-NEXT:  .Ltmp7:
+; AVX2-NEXT:  .Lcfi7:
 ; AVX2-NEXT:    .cfi_offset %r12, -48
-; AVX2-NEXT:  .Ltmp8:
+; AVX2-NEXT:  .Lcfi8:
 ; AVX2-NEXT:    .cfi_offset %r13, -40
-; AVX2-NEXT:  .Ltmp9:
+; AVX2-NEXT:  .Lcfi9:
 ; AVX2-NEXT:    .cfi_offset %r14, -32
-; AVX2-NEXT:  .Ltmp10:
+; AVX2-NEXT:  .Lcfi10:
 ; AVX2-NEXT:    .cfi_offset %r15, -24
-; AVX2-NEXT:  .Ltmp11:
+; AVX2-NEXT:  .Lcfi11:
 ; AVX2-NEXT:    .cfi_offset %rbp, -16
 ; AVX2-NEXT:    movswq (%rdi), %rax
 ; AVX2-NEXT:    movq %rax, %rcx
 ; AVX2-NEXT:    shlq $55, %rcx
 ; AVX2-NEXT:    sarq $63, %rcx
 ; AVX2-NEXT:    vmovd %ecx, %xmm0
 ; AVX2-NEXT:    movq %rax, %r8
 ; AVX2-NEXT:    movq %rax, %r10

 ; AVX:       # BB#0: # %entry
 ; AVX-NEXT:    vpmovsxbw %xmm0, %xmm0
 ; AVX-NEXT:    vmovd %xmm0, %eax
 ; AVX-NEXT:    retq
 ;
 ; X32-SSE41-LABEL: sext_2i8_to_i32:
 ; X32-SSE41:       # BB#0: # %entry
 ; X32-SSE41-NEXT:    pushl %eax
-; X32-SSE41-NEXT:  .Ltmp0:
+; X32-SSE41-NEXT:  .Lcfi0:
 ; X32-SSE41-NEXT:    .cfi_def_cfa_offset 8
 ; X32-SSE41-NEXT:    pmovsxbw %xmm0, %xmm0
 ; X32-SSE41-NEXT:    movd %xmm0, %eax
 ; X32-SSE41-NEXT:    popl %ecx
 ; X32-SSE41-NEXT:    retl
 entry:
   %Shuf = shufflevector <16 x i8> %A, <16 x i8> undef, <2 x i32> <i32 0, i32 1>
   %Ex = sext <2 x i8> %Shuf to <2 x i16>

test/CodeGen/X86/vector-shuffle-mmx.ll

entry:
   store <1 x i64> %tmp10, <1 x i64>* %x
   ret void
 }
 
 define void @test1() {
 ; X32-LABEL: test1:
 ; X32:       ## BB#0: ## %entry
 ; X32-NEXT:    pushl %edi
-; X32-NEXT:  Ltmp0:
+; X32-NEXT:  Lcfi0:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    subl $16, %esp
-; X32-NEXT:  Ltmp1:
+; X32-NEXT:  Lcfi1:
 ; X32-NEXT:    .cfi_def_cfa_offset 24
-; X32-NEXT:  Ltmp2:
+; X32-NEXT:  Lcfi2:
 ; X32-NEXT:    .cfi_offset %edi, -8
 ; X32-NEXT:    xorps %xmm0, %xmm0
 ; X32-NEXT:    movlps %xmm0, (%esp)
 ; X32-NEXT:    movq (%esp), %mm0
 ; X32-NEXT:    pshuflw {{.*#+}} xmm0 = mem[0,2,2,3,4,5,6,7]
 ; X32-NEXT:    pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,6,6,7]
 ; X32-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
 ; X32-NEXT:    movq %xmm0, {{[0-9]+}}(%esp)

test/CodeGen/X86/vector-shuffle-v1.ll

; VL_BW_DQ-NEXT:    retq
   %d = bitcast <16 x i1> %c to i16
   ret i16 %d
 }
 
 define i64 @shuf64i1_zero(i64 %a) {
 ; AVX512F-LABEL: shuf64i1_zero:
 ; AVX512F:       # BB#0:
 ; AVX512F-NEXT:    pushq %rbp
-; AVX512F-NEXT:  .Ltmp0:
+; AVX512F-NEXT:  .Lcfi0:
 ; AVX512F-NEXT:    .cfi_def_cfa_offset 16
-; AVX512F-NEXT:  .Ltmp1:
+; AVX512F-NEXT:  .Lcfi1:
 ; AVX512F-NEXT:    .cfi_offset %rbp, -16
 ; AVX512F-NEXT:    movq %rsp, %rbp
-; AVX512F-NEXT:  .Ltmp2:
+; AVX512F-NEXT:  .Lcfi2:
 ; AVX512F-NEXT:    .cfi_def_cfa_register %rbp
 ; AVX512F-NEXT:    andq $-32, %rsp
 ; AVX512F-NEXT:    subq $96, %rsp
 ; AVX512F-NEXT:    movl %edi, {{[0-9]+}}(%rsp)
 ; AVX512F-NEXT:    vpternlogd $255, %zmm0, %zmm0, %zmm0
 ; AVX512F-NEXT:    kmovw {{[0-9]+}}(%rsp), %k1
 ; AVX512F-NEXT:    vmovdqa32 %zmm0, %zmm0 {%k1} {z}
 ; AVX512F-NEXT:    vpmovdb %zmm0, %xmm0

test/CodeGen/X86/win-cleanuppad.ll

 ; X86: $stateUnwindMap$nested_cleanup:
 ; X86:         .long   -1
 ; X86:         .long   "?dtor$[[cleanup_outer]]@?0?nested_cleanup@4HA"
 ; X86:         .long   0
 ; X86:         .long   "?dtor$[[cleanup_inner]]@?0?nested_cleanup@4HA"
 
 ; X64-LABEL: nested_cleanup:
 ; X64: .Lfunc_begin1:
-; X64: .Ltmp13:
+; X64: .Ltmp2:
 ; X64: movl    $1, %ecx
 ; X64: callq   f
-; X64: .Ltmp15:
+; X64: .Ltmp4:
 ; X64: movl    $2, %ecx
 ; X64: callq   f
-; X64: .Ltmp16:
+; X64: .Ltmp5:
 ; X64: callq   "??1Dtor@@QAE@XZ"
-; X64: .Ltmp17:
+; X64: .Ltmp6:
 ; X64: movl    $3, %ecx
 ; X64: callq   f
-; X64: .Ltmp18:
+; X64: .Ltmp7:
 
 ; X64: "?dtor$[[cleanup_inner:[0-9]+]]@?0?nested_cleanup@4HA":
 ; X64: LBB1_[[cleanup_inner]]: # %cleanup.inner{{$}}
 ; X64: pushq %rbp
 ; X64: leaq    {{.*}}(%rbp), %rcx
 ; X64: callq   "??1Dtor@@QAE@XZ"
 ; X64: popq %rbp
 ; X64: retq

 ; X64-NEXT: .long   -1
 ; X64-NEXT: .long   "?dtor$[[cleanup_outer]]@?0?nested_cleanup@4HA"@IMGREL
 ; X64-NEXT: .long   0
 ; X64-NEXT: .long   "?dtor$[[cleanup_inner]]@?0?nested_cleanup@4HA"@IMGREL
 
 ; X64: $ip2state$nested_cleanup:
 ; X64-NEXT: .long   .Lfunc_begin1@IMGREL
 ; X64-NEXT: .long   -1
-; X64-NEXT: .long   .Ltmp13@IMGREL
+; X64-NEXT: .long   .Ltmp2@IMGREL
 ; X64-NEXT: .long   0
-; X64-NEXT: .long   .Ltmp15@IMGREL
+; X64-NEXT: .long   .Ltmp4@IMGREL
 ; X64-NEXT: .long   1
-; X64-NEXT: .long   .Ltmp17@IMGREL
+; X64-NEXT: .long   .Ltmp6@IMGREL
 ; X64-NEXT: .long   0
-; X64-NEXT: .long   .Ltmp18@IMGREL+1
+; X64-NEXT: .long   .Ltmp7@IMGREL+1
 ; X64-NEXT: .long   -1
 
 attributes #0 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
 attributes #1 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
 attributes #2 = { nounwind }

test/CodeGen/X86/win32-pic-jumptable.ll

 ; RUN: llc < %s -relocation-model=pic | FileCheck %s
 
 ; CHECK:        calll L0$pb
-; CHECK-NEXT: Ltmp{{[0-9]+}}:
+; CHECK-NEXT: Lcfi{{[0-9]+}}:
 ; CHECK-NEXT: .cfi_adjust_cfa_offset 4
 ; CHECK-NEXT: L0$pb:
 ; CHECK-NEXT:   popl %eax
-; CHECK-NEXT: Ltmp{{[0-9]+}}:
+; CHECK-NEXT: Lcfi{{[0-9]+}}:
 ; CHECK-NEXT: .cfi_adjust_cfa_offset -4
 ; CHECK-NEXT:   addl LJTI0_0(,%ecx,4), %eax
 ; CHECK-NEXT:   jmpl *%eax
 
 ; CHECK:      LJTI0_0:
 ; CHECK-NEXT:   .long LBB0_2-L0$pb
 ; CHECK-NEXT:   .long LBB0_3-L0$pb
 ; CHECK-NEXT:   .long LBB0_4-L0$pb

test/CodeGen/XCore/epilogue_prologue.ll

entry:
   call void @f2()
   ret i32 %i
 }
 
 
 ; FP + large frame: spill FP+SR = entsp 2 + 100000
 ; CHECKFP-LABEL: f4
 ; CHECKFP: entsp 65535
-; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
+; CHECKFP-NEXT: .Lcfi{{[0-9]+}}
 ; CHECKFP-NEXT: .cfi_def_cfa_offset 262140
-; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
+; CHECKFP-NEXT: .Lcfi{{[0-9]+}}
 ; CHECKFP-NEXT: .cfi_offset 15, 0
 ; CHECKFP-NEXT: extsp 34467
-; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
+; CHECKFP-NEXT: .Lcfi{{[0-9]+}}
 ; CHECKFP-NEXT: .cfi_def_cfa_offset 400008
 ; CHECKFP-NEXT: stw r10, sp[1]
-; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
+; CHECKFP-NEXT: .Lcfi{{[0-9]+}}
 ; CHECKFP-NEXT: .cfi_offset 10, -400004
 ; CHECKFP-NEXT: ldaw r10, sp[0]
-; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
+; CHECKFP-NEXT: .Lcfi{{[0-9]+}}
 ; CHECKFP-NEXT: .cfi_def_cfa_register 10
 ; CHECKFP-NEXT: set sp, r10
 ; CHECKFP-NEXT: ldw r10, sp[1]
 ; CHECKFP-NEXT: ldaw sp, sp[65535]
 ; CHECKFP-NEXT: retsp 34467
 ;
 ; !FP + large frame: spill SR+SR = entsp 2 + 100000
 ; CHECK-LABEL: f4
 ; CHECK: entsp 65535
-; CHECK-NEXT: .Ltmp{{[0-9]+}}
+; CHECK-NEXT: .Lcfi{{[0-9]+}}
 ; CHECK-NEXT: .cfi_def_cfa_offset 262140
-; CHECK-NEXT: .Ltmp{{[0-9]+}}
+; CHECK-NEXT: .Lcfi{{[0-9]+}}
 ; CHECK-NEXT: .cfi_offset 15, 0
 ; CHECK-NEXT: extsp 34467
-; CHECK-NEXT: .Ltmp{{[0-9]+}}
+; CHECK-NEXT: .Lcfi{{[0-9]+}}
 ; CHECK-NEXT: .cfi_def_cfa_offset 400008
 ; CHECK-NEXT: ldaw sp, sp[65535]
 ; CHECK-NEXT: retsp 34467
 define void @f4() {
 entry:
   %0 = alloca [100000 x i32]
   ret void
 }
 
 
 ; FP + large frame: spill FP+SR+R4+LR = entsp 3 + 200000  + extsp 1
 ; CHECKFP: .section .cp.rodata.cst4,"aMc",@progbits,4
 ; CHECKFP-NEXT: .p2align 2
 ; CHECKFP-NEXT: .LCPI[[CNST0:[0-9_]+]]:
 ; CHECKFP-NEXT: .long 200002
 ; CHECKFP-NEXT: .LCPI[[CNST1:[0-9_]+]]:
 ; CHECKFP-NEXT: .long 200001
 ; CHECKFP-NEXT: .text
 ; CHECKFP-LABEL: f6
 ; CHECKFP: entsp 65535
-; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
+; CHECKFP-NEXT: .Lcfi{{[0-9]+}}
 ; CHECKFP-NEXT: .cfi_def_cfa_offset 262140
-; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
+; CHECKFP-NEXT: .Lcfi{{[0-9]+}}
 ; CHECKFP-NEXT: .cfi_offset 15, 0
 ; CHECKFP-NEXT: extsp 65535
-; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
+; CHECKFP-NEXT: .Lcfi{{[0-9]+}}
 ; CHECKFP-NEXT: .cfi_def_cfa_offset 524280
 ; CHECKFP-NEXT: extsp 65535
-; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
+; CHECKFP-NEXT: .Lcfi{{[0-9]+}}
 ; CHECKFP-NEXT: .cfi_def_cfa_offset 786420
 ; CHECKFP-NEXT: extsp 3398
-; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
+; CHECKFP-NEXT: .Lcfi{{[0-9]+}}
 ; CHECKFP-NEXT: .cfi_def_cfa_offset 800012
 ; CHECKFP-NEXT: stw r10, sp[1]
-; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
+; CHECKFP-NEXT: .Lcfi{{[0-9]+}}
 ; CHECKFP-NEXT: .cfi_offset 10, -800008
 ; CHECKFP-NEXT: ldaw r10, sp[0]
-; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
+; CHECKFP-NEXT: .Lcfi{{[0-9]+}}
 ; CHECKFP-NEXT: .cfi_def_cfa_register 10
 ; CHECKFP-NEXT: ldw r1, cp[.LCPI[[CNST0]]]
 ; CHECKFP-NEXT: stw [[REG:r[4-9]+]], r10[r1]
-; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
+; CHECKFP-NEXT: .Lcfi{{[0-9]+}}
 ; CHECKFP-NEXT: .cfi_offset 4, -4
 ; CHECKFP-NEXT: mov [[REG]], r0
 ; CHECKFP-NEXT: extsp 1
 ; CHECKFP-NEXT: ldaw r0, r10[2]
 ; CHECKFP-NEXT: bl f5
 ; CHECKFP-NEXT: ldaw sp, sp[1]
 ; CHECKFP-NEXT: ldw r1, cp[.LCPI3_1]
 ; CHECKFP-NEXT: ldaw r0, r10[r1]

 ; CHECK-NEXT: .p2align 2
 ; CHECK-NEXT: .LCPI[[CNST0:[0-9_]+]]:
 ; CHECK-NEXT: .long 200003
 ; CHECK-NEXT: .LCPI[[CNST1:[0-9_]+]]:
 ; CHECK-NEXT: .long 200002
 ; CHECK-NEXT: .text
 ; CHECK-LABEL: f6
 ; CHECK: entsp 65535
-; CHECK-NEXT: .Ltmp{{[0-9]+}}
+; CHECK-NEXT: .Lcfi{{[0-9]+}}
 ; CHECK-NEXT: .cfi_def_cfa_offset 262140
-; CHECK-NEXT: .Ltmp{{[0-9]+}}
+; CHECK-NEXT: .Lcfi{{[0-9]+}}
 ; CHECK-NEXT: .cfi_offset 15, 0
 ; CHECK-NEXT: extsp 65535
-; CHECK-NEXT: .Ltmp{{[0-9]+}}
+; CHECK-NEXT: .Lcfi{{[0-9]+}}
 ; CHECK-NEXT: .cfi_def_cfa_offset 524280
 ; CHECK-NEXT: extsp 65535
-; CHECK-NEXT: .Ltmp{{[0-9]+}}
+; CHECK-NEXT: .Lcfi{{[0-9]+}}
 ; CHECK-NEXT: .cfi_def_cfa_offset 786420
 ; CHECK-NEXT: extsp 3399
-; CHECK-NEXT: .Ltmp{{[0-9]+}}
+; CHECK-NEXT: .Lcfi{{[0-9]+}}
 ; CHECK-NEXT: .cfi_def_cfa_offset 800016
 ; CHECK-NEXT: ldaw r1, sp[0]
 ; CHECK-NEXT: ldw r2, cp[.LCPI[[CNST0]]]
 ; CHECK-NEXT: stw [[REG:r[4-9]+]], r1[r2]
-; CHECK-NEXT: .Ltmp{{[0-9]+}}
+; CHECK-NEXT: .Lcfi{{[0-9]+}}
 ; CHECK-NEXT: .cfi_offset 4, -4
 ; CHECK-NEXT: mov [[REG]], r0
 ; CHECK-NEXT: ldaw r0, sp[3]
 ; CHECK-NEXT: bl f5
 ; CHECK-NEXT: ldaw r0, sp[0]
 ; CHECK-NEXT: ldw r1, cp[.LCPI[[CNST1]]]
 ; CHECK-NEXT: ldaw r0, r0[r1]
 ; CHECK-NEXT: bl f5