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Differential D27057

AMDGPU: Fix adding extra implicit def of register
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Authored by arsenm on Nov 23 2016, 9:13 AM.

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• tstellarAMD

Summary

In the scalar case, there's no reason to add an additional def of the same register.

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arsenm updated this revision to Diff 79108.Nov 23 2016, 9:13 AM

arsenm retitled this revision from to AMDGPU: Fix adding extra implicit def of register.

arsenm updated this object.

arsenm added a subscriber: llvm-commits.

Herald added a reviewer: • tstellarAMD. · View Herald TranscriptNov 23 2016, 9:13 AM

Herald added subscribers: tony-tye, yaxunl, nhaehnle and 2 others. · View Herald Transcript

Also do for scalar store path

Herald edited edge metadata. · View Herald TranscriptNov 23 2016, 9:34 AM

Also for readlane

Herald edited edge metadata. · View Herald TranscriptNov 23 2016, 11:56 AM

LGTM.

This revision is now accepted and ready to land.Nov 23 2016, 12:39 PM

r287807

Revision Contents

Path

Size

lib/

Target/

AMDGPU/

SIRegisterInfo.cpp

8 lines

Diff 79108

lib/Target/AMDGPU/SIRegisterInfo.cpp

Show First 20 Lines • Show All 470 Lines • ▼ Show 20 Lines	if (i + 1 == e) {
SrcDstRegState \|= getKillRegState(IsKill);		SrcDstRegState \|= getKillRegState(IsKill);
}		}

MachinePointerInfo PInfo = BasePtrInfo.getWithOffset(EltSize * i);		MachinePointerInfo PInfo = BasePtrInfo.getWithOffset(EltSize * i);
MachineMemOperand *NewMMO		MachineMemOperand *NewMMO
= MF->getMachineMemOperand(PInfo, MMO->getFlags(),		= MF->getMachineMemOperand(PInfo, MMO->getFlags(),
EltSize, MinAlign(Align, EltSize * i));		EltSize, MinAlign(Align, EltSize * i));

BuildMI(*MBB, MI, DL, Desc)		auto MIB = BuildMI(*MBB, MI, DL, Desc)
.addReg(SubReg, getDefRegState(!IsStore))		.addReg(SubReg, getDefRegState(!IsStore))
.addReg(ScratchRsrcReg)		.addReg(ScratchRsrcReg)
.addReg(SOffset, SOffsetRegState)		.addReg(SOffset, SOffsetRegState)
.addImm(Offset)		.addImm(Offset)
.addImm(0) // glc		.addImm(0) // glc
.addImm(0) // slc		.addImm(0) // slc
.addImm(0) // tfe		.addImm(0) // tfe
.addMemOperand(NewMMO)		.addMemOperand(NewMMO);
.addReg(ValueReg, RegState::Implicit \| SrcDstRegState);
		if (NumSubRegs > 1)
		MIB.addReg(ValueReg, RegState::Implicit \| SrcDstRegState);
}		}

if (RanOutOfSGPRs) {		if (RanOutOfSGPRs) {
// Subtract the offset we added to the ScratchOffset register.		// Subtract the offset we added to the ScratchOffset register.
BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_SUB_U32), ScratchOffsetReg)		BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_SUB_U32), ScratchOffsetReg)
.addReg(ScratchOffsetReg)		.addReg(ScratchOffsetReg)
.addImm(OriginalImmOffset);		.addImm(OriginalImmOffset);
}		}
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