[ARM] Fix sema check of ARM special register names

[iid_iunknown]

Summary

This is a simple sema check patch for arguments of __builtin_arm_rsr and the related builtins, which currently do not allow special registers with indexes >7.

Some of the possible register name formats these builtins accept are:

{c}p<coprocessor>:<op1>:c<CRn>:c<CRm>:<op2>

o0:op1:CRn:CRm:op2

where op1 / op2 are integers in the range [0, 7] and CRn / CRm are integers in the range [0, 15].

The current sema check does not allow CRn > 7 and accepts op2 up to 15.

[rengolin]

Looks like an oversight. Aren't there any tests for this? Maybe there should be one.

[iid_iunknown]

Tests added.

[iid_iunknown]

Tests extended to check for more corner cases.

[iid_iunknown]

In D26464#594228, @rengolin wrote:

Looks like an oversight. Aren't there any tests for this? Maybe there should be one.

Thanks Renato!
I updated the tests to check the upper bounds for CRn/CRm/Op.

[rengolin]

LGTM. Thanks!

lib/Sema/SemaChecking.cpp

if (IsARMBuiltin) {
         ValidString &= Fields[3].startswith_lower("c");
         if (ValidString)
           Fields[3] = Fields[3].drop_front(1);
       }
     }
 
     SmallVector<int, 5> Ranges;
     if (FiveFields)
-      Ranges.append({IsAArch64Builtin ? 1 : 15, 7, 7, 15, 15});
+      Ranges.append({IsAArch64Builtin ? 1 : 15, 7, 15, 15, 7});
     else
       Ranges.append({15, 7, 15});
 
     for (unsigned i=0; i<Fields.size(); ++i) {
       int IntField;
       ValidString &= !Fields[i].getAsInteger(10, IntField);
       ValidString &= (IntField >= 0 && IntField <= Ranges[i]);
     }

test/Sema/aarch64-special-register.c

void wsrp_2(void *v) {
   __builtin_arm_wsrp("0:1:2:3:4", v);
 }
 
 void wsr64_2(unsigned long v) {
   __builtin_arm_wsr64("0:1:2:3:4", v);
 }
 
 unsigned rsr_2() {
-  return __builtin_arm_rsr("0:1:2:3:4");
+  return __builtin_arm_rsr("0:1:15:15:4");
 }
 
 void *rsrp_2() {
   return __builtin_arm_rsrp("0:1:2:3:4");
 }
 
 unsigned long rsr64_2() {
-  return __builtin_arm_rsr64("0:1:2:3:4");
+  return __builtin_arm_rsr64("0:1:15:15:4");
 }
 
 void wsr_3(unsigned v) {
   __builtin_arm_wsr("0:1:2", v); //expected-error {{invalid special register for builtin}}
 }
 
 void wsrp_3(void *v) {
   __builtin_arm_wsrp("0:1:2", v); //expected-error {{invalid special register for builtin}}
 }
 
 void wsr64_3(unsigned long v) {
   __builtin_arm_wsr64("0:1:2", v); //expected-error {{invalid special register for builtin}}
 }
 
 unsigned rsr_3() {
   return __builtin_arm_rsr("0:1:2"); //expected-error {{invalid special register for builtin}}
 }
 
+unsigned rsr_4() {
+  return __builtin_arm_rsr("0:1:2:3:8"); //expected-error {{invalid special register for builtin}}
+}
+
+unsigned rsr_5() {
+  return __builtin_arm_rsr("0:8:1:2:3"); //expected-error {{invalid special register for builtin}}
+}
+
+unsigned rsr_6() {
+  return __builtin_arm_rsr("0:1:16:16:2"); //expected-error {{invalid special register for builtin}}
+}
+
 void *rsrp_3() {
   return __builtin_arm_rsrp("0:1:2"); //expected-error {{invalid special register for builtin}}
 }
 
 unsigned long rsr64_3() {
   return __builtin_arm_rsr64("0:1:2"); //expected-error {{invalid special register for builtin}}
 }
+
+unsigned long rsr64_4() {
+  return __builtin_arm_rsr64("0:1:2:3:8"); //expected-error {{invalid special register for builtin}}
+}
+
+unsigned long rsr64_5() {
+  return __builtin_arm_rsr64("0:8:2:3:4"); //expected-error {{invalid special register for builtin}}
+}
+
+unsigned long rsr64_6() {
+  return __builtin_arm_rsr64("0:1:16:16:2"); //expected-error {{invalid special register for builtin}}
+}

test/Sema/arm-special-register.c

void wsrp_2(void *v) {
   __builtin_arm_wsrp("cp0:1:c2:c3:4", v);
 }
 
 void wsr64_2(unsigned long v) {
   __builtin_arm_wsr64("cp0:1:c2:c3:4", v); //expected-error {{invalid special register for builtin}}
 }
 
 unsigned rsr_2() {
-  return __builtin_arm_rsr("cp0:1:c2:c3:4");
+  return __builtin_arm_rsr("cp0:1:c15:c15:4");
 }
 
 void *rsrp_2() {
   return __builtin_arm_rsrp("cp0:1:c2:c3:4");
 }
 
 unsigned long rsr64_2() {
   return __builtin_arm_rsr64("cp0:1:c2:c3:4"); //expected-error {{invalid special register for builtin}}
unsigned rsr_3() {
   return __builtin_arm_rsr("cp0:1:c2"); //expected-error {{invalid special register for builtin}}
 }
 
 void *rsrp_3() {
   return __builtin_arm_rsrp("cp0:1:c2"); //expected-error {{invalid special register for builtin}}
 }
 
 unsigned long rsr64_3() {
-  return __builtin_arm_rsr64("cp0:1:c2");
+  return __builtin_arm_rsr64("cp0:1:c15");
 }
 
 unsigned rsr_4() {
   return __builtin_arm_rsr("0:1:2:3:4"); //expected-error {{invalid special register for builtin}}
 }
 
+unsigned rsr_5() {
+  return __builtin_arm_rsr("cp0:1:c2:c3:8"); //expected-error {{invalid special register for builtin}}
+}
+
+unsigned rsr_6() {
+  return __builtin_arm_rsr("cp0:8:c1:c2:3"); //expected-error {{invalid special register for builtin}}
+}
+
+unsigned rsr_7() {
+  return __builtin_arm_rsr("cp0:1:c16:c16:2"); //expected-error {{invalid special register for builtin}}
+}
+
 void *rsrp_4() {
   return __builtin_arm_rsrp("0:1:2:3:4"); //expected-error {{invalid special register for builtin}}
 }
 
 unsigned long rsr64_4() {
   return __builtin_arm_rsr64("0:1:2"); //expected-error {{invalid special register for builtin}}
 }
+
+unsigned long rsr64_5() {
+  return __builtin_arm_rsr64("cp0:8:c1"); //expected-error {{invalid special register for builtin}}
+}
+
+unsigned long rsr64_6() {
+  return __builtin_arm_rsr64("cp0:1:c16"); //expected-error {{invalid special register for builtin}}
+}