DAGCombiner: fix combine of trunc and select

[AsafBadouh]

Summary

the pattern catch the following:
// trunc (select c, a, b) -> select c, (trunc a), (trunc b)

in case select has more than one use the exist pattern will add extra select.

i16 t1 = select c, a , b
i16 t2 = srl t1, 3
i8 t3 = trunc i16 t1 to i8
-->
i8 a1 = trunc i16 a to i8
i8 b1 = trunc i16 a to i8
i8 t3 = select c, a1 , b1
i16 t1 = select c, a , b
i16 t2 = srl t1, 3

[zvi]

test/CodeGen/X86/select.ll

519 ↗

(On Diff #77345)

Can this test be reduced to a smaller example?
Please add a comment explaining what this test checks.

[AsafBadouh]

+ Sanjay
fixes pr29002
update the test case using the example in pr29002

https://llvm.org/bugs/show_bug.cgi?id=29002

[spatel]

Thanks for tracking this down!

1. Please use the regression test from:

https://llvm.org/bugs/show_bug.cgi?id=29002#c1

I think that's the minimal case. If you want to include the original test in this patch, I suppose that's ok, but I don't think it actually adds value. Zvi's example in:
https://llvm.org/bugs/show_bug.cgi?id=29002#c2
probably is interesting as it shows a different output?

2. Please use utils/update_llc_test_checks.py to auto-generate complete checks (and then remove any lines that you think are irrelevant).

[AsafBadouh]

1. update the regression tests.
2. used the utils/update_llc_test_checks.py to auto-generate complete checks.

[zvi]

Thanks, Asaf. LGTM. Please make sure you are running the tests on all targets.

llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

if (isa<ConstantSDNode>(EltNo) && isTypeLegal(NVT)) {
       SDLoc DL(N);
       return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, TrTy,
                          DAG.getBitcast(NVT, N0.getOperand(0)),
                          DAG.getConstant(Index, DL, IndexTy));
     }
   }
 
   // trunc (select c, a, b) -> select c, (trunc a), (trunc b)
-  if (N0.getOpcode() == ISD::SELECT) {
+  if (N0.getOpcode() == ISD::SELECT && N0.hasOneUse()) {
     EVT SrcVT = N0.getValueType();
     if ((!LegalOperations || TLI.isOperationLegal(ISD::SELECT, SrcVT)) &&
         TLI.isTruncateFree(SrcVT, VT)) {
       SDLoc SL(N0);
       SDValue Cond = N0.getOperand(0);
       SDValue TruncOp0 = DAG.getNode(ISD::TRUNCATE, SL, VT, N0.getOperand(1));
       SDValue TruncOp1 = DAG.getNode(ISD::TRUNCATE, SL, VT, N0.getOperand(2));
       return DAG.getNode(ISD::SELECT, SDLoc(N), VT, Cond, TruncOp0, TruncOp1);

llvm/trunk/test/CodeGen/X86/select.ll

 ; CHECK-NEXT:    retq
   %tmp1 = select i1 %cc, i32 3, i32 2
   %tmp2 = shl i32 %a, %tmp1
   ret i32 %tmp2
 }
 
 ; reproducer for pr29002
 define void @clamp_i8(i32 %src, i8* %dst) {
-; CHECK-LABEL: clamp_i8:
-; CHECK:       ## BB#0:
-; CHECK-NEXT:    cmpl $127, %edi
-; CHECK-NEXT:    movl $127, %eax
-; CHECK-NEXT:    cmovlel %edi, %eax
-; CHECK-NEXT:    movb $127, %cl
-; CHECK-NEXT:    jg LBB22_2
-; CHECK-NEXT:  ## BB#1:
-; CHECK-NEXT:    movl %edi, %ecx
-; CHECK-NEXT:  LBB22_2:
-; CHECK-NEXT:    cmpl $-128, %eax
-; CHECK-NEXT:    movb $-128, %al
-; CHECK-NEXT:    jl LBB22_4
-; CHECK-NEXT:  ## BB#3:
-; CHECK-NEXT:    movl %ecx, %eax
-; CHECK-NEXT:  LBB22_4:
-; CHECK-NEXT:    movb %al, (%rsi)
-; CHECK-NEXT:    retq
+; GENERIC-LABEL: clamp_i8:
+; GENERIC:       ## BB#0:
+; GENERIC-NEXT:    cmpl $127, %edi
+; GENERIC-NEXT:    movl $127, %eax
+; GENERIC-NEXT:    cmovlel %edi, %eax
+; GENERIC-NEXT:    cmpl $-128, %eax
+; GENERIC-NEXT:    movb $-128, %cl
+; GENERIC-NEXT:    jl LBB22_2
+; GENERIC-NEXT:  ## BB#1:
+; GENERIC-NEXT:    movl %eax, %ecx
+; GENERIC-NEXT:  LBB22_2:
+; GENERIC-NEXT:    movb %cl, (%rsi)
+; GENERIC-NEXT:    retq
+;
+; ATOM-LABEL: clamp_i8:
+; ATOM:       ## BB#0:
+; ATOM-NEXT:    cmpl $127, %edi
+; ATOM-NEXT:    movl $127, %eax
+; ATOM-NEXT:    cmovlel %edi, %eax
+; ATOM-NEXT:    movb $-128, %cl
+; ATOM-NEXT:    cmpl $-128, %eax
+; ATOM-NEXT:    jl LBB22_2
+; ATOM-NEXT:  ## BB#1:
+; ATOM-NEXT:    movl %eax, %ecx
+; ATOM-NEXT:  LBB22_2:
+; ATOM-NEXT:    movb %cl, (%rsi)
+; ATOM-NEXT:    retq
   %cmp = icmp sgt i32 %src, 127
   %sel1 = select i1 %cmp, i32 127, i32 %src
   %cmp1 = icmp slt i32 %sel1, -128
   %sel2 = select i1 %cmp1, i32 -128, i32 %sel1
   %conv = trunc i32 %sel2 to i8
   store i8 %conv, i8* %dst, align 2
   ret void
 }
 
 ; reproducer for pr29002
 define void @clamp(i32 %src, i16* %dst) {
 ; GENERIC-LABEL: clamp:
 ; GENERIC:       ## BB#0:
 ; GENERIC-NEXT:    cmpl $32767, %edi ## imm = 0x7FFF
 ; GENERIC-NEXT:    movl $32767, %eax ## imm = 0x7FFF
 ; GENERIC-NEXT:    cmovlel %edi, %eax
-; GENERIC-NEXT:    movw $32767, %cx ## imm = 0x7FFF
-; GENERIC-NEXT:    cmovlew %di, %cx
 ; GENERIC-NEXT:    cmpl $-32768, %eax ## imm = 0x8000
-; GENERIC-NEXT:    movw $-32768, %ax ## imm = 0x8000
-; GENERIC-NEXT:    cmovgew %cx, %ax
-; GENERIC-NEXT:    movw %ax, (%rsi)
+; GENERIC-NEXT:    movw $-32768, %cx ## imm = 0x8000
+; GENERIC-NEXT:    cmovgew %ax, %cx
+; GENERIC-NEXT:    movw %cx, (%rsi)
 ; GENERIC-NEXT:    retq
 ;
 ; ATOM-LABEL: clamp:
 ; ATOM:       ## BB#0:
 ; ATOM-NEXT:    cmpl $32767, %edi ## imm = 0x7FFF
 ; ATOM-NEXT:    movl $32767, %eax ## imm = 0x7FFF
-; ATOM-NEXT:    movw $32767, %cx ## imm = 0x7FFF
 ; ATOM-NEXT:    cmovlel %edi, %eax
-; ATOM-NEXT:    cmovlew %di, %cx
+; ATOM-NEXT:    movw $-32768, %cx ## imm = 0x8000
 ; ATOM-NEXT:    cmpl $-32768, %eax ## imm = 0x8000
-; ATOM-NEXT:    movw $-32768, %dx ## imm = 0x8000
-; ATOM-NEXT:    cmovgew %cx, %dx
-; ATOM-NEXT:    movw %dx, (%rsi)
+; ATOM-NEXT:    cmovgew %ax, %cx
+; ATOM-NEXT:    movw %cx, (%rsi)
 ; ATOM-NEXT:    retq
   %cmp = icmp sgt i32 %src, 32767
   %sel1 = select i1 %cmp, i32 32767, i32 %src
   %cmp1 = icmp slt i32 %sel1, -32768
   %sel2 = select i1 %cmp1, i32 -32768, i32 %sel1
   %conv = trunc i32 %sel2 to i16
   store i16 %conv, i16* %dst, align 2
   ret void