This is an archive of the discontinued LLVM Phabricator instance.

Differential D26158

Reorder the test cases in file builtins-ppc-p9vector.c
ClosedPublic

Authored by jtony on Oct 31 2016, 11:33 AM.

Details

Reviewers
lei
syzaara
kbarton
sfertile
nemanjai
• ehsan
Summary
There are some test case numbers out of order in file builtins-ppc-p9vector.c,
fix them in this changeset.

Diff Detail

Event Timeline

jtony updated this revision to Diff 76450.Oct 31 2016, 11:33 AM
jtony retitled this revision from to Reorder the test cases in file builtins-ppc-p9vector.c.
jtony updated this object.
jtony added reviewers: nemanjai, kbarton, sfertile, syzaara, • ehsan, lei.
jtony added a subscriber: llvm-commits.
nemanjai accepted this revision.Oct 31 2016, 11:40 AM
nemanjai edited edge metadata.

This is fine. LGTM. I'll commit this NFC patch now.

This revision is now accepted and ready to land.Oct 31 2016, 11:40 AM
nemanjai added a comment.Oct 31 2016, 12:12 PM

Committed revision 285623.

nemanjai closed this revision.Oct 31 2016, 12:28 PM

Revision Contents

PathSize
test/
CodeGen/
56 lines

Diff 76450

test/CodeGen/builtins-ppc-p9vector.c

Show First 20 Lines • Show All 694 Lines • ▼ Show 20 Lines
} }
vector unsigned short test54(void) { vector unsigned short test54(void) {
// CHECK-BE: @llvm.ctpop.v8i16(<8 x i16> // CHECK-BE: @llvm.ctpop.v8i16(<8 x i16>
// CHECK-BE-NEXT: ret <8 x i16> // CHECK-BE-NEXT: ret <8 x i16>
// CHECK: @llvm.ctpop.v8i16(<8 x i16> // CHECK: @llvm.ctpop.v8i16(<8 x i16>
// CHECK-NEXT: ret <8 x i16> // CHECK-NEXT: ret <8 x i16>
return vec_popcnt (vusa); return vec_popcnt (vusa);
} }
vector double test55(void) {
// CHECK-BE: @llvm.ppc.vsx.xviexpdp(<2 x i64> %{{.+}}, <2 x i64>
// CHECK-BE-NEXT: ret <2 x double>
// CHECK: @llvm.ppc.vsx.xviexpdp(<2 x i64> %{{.+}}, <2 x i64>
// CHECK-NEXT: ret <2 x double>
return vec_insert_exp (vda,vulb);
}
vector double test56(void) {
// CHECK-BE: @llvm.ppc.vsx.xviexpdp(<2 x i64> %{{.+}}, <2 x i64>
// CHECK-BE-NEXT: ret <2 x double>
// CHECK: @llvm.ppc.vsx.xviexpdp(<2 x i64> %{{.+}}, <2 x i64>
// CHECK-NEXT: ret <2 x double>
return vec_insert_exp (vula, vulb);
}
vector float test57(void) {
// CHECK-BE: @llvm.ppc.vsx.xviexpsp(<4 x i32> %{{.+}}, <4 x i32>
// CHECK-BE-NEXT: ret <4 x float>
// CHECK: @llvm.ppc.vsx.xviexpsp(<4 x i32> %{{.+}}, <4 x i32>
// CHECK-NEXT: ret <4 x float>
return vec_insert_exp (vfa,vuib);
}
vector float test58(void) {
// CHECK-BE: @llvm.ppc.vsx.xviexpsp(<4 x i32> %{{.+}}, <4 x i32>
// CHECK-BE-NEXT: ret <4 x float>
// CHECK: @llvm.ppc.vsx.xviexpsp(<4 x i32> %{{.+}}, <4 x i32>
// CHECK-NEXT: ret <4 x float>
return vec_insert_exp (vuia,vuib);
}
signed int test59(void) { signed int test59(void) {
// CHECK-BE: @llvm.ppc.altivec.vclzlsbb(<16 x i8> // CHECK-BE: @llvm.ppc.altivec.vclzlsbb(<16 x i8>
// CHECK-BE-NEXT: ret i32 // CHECK-BE-NEXT: ret i32
// CHECK-LE: @llvm.ppc.altivec.vctzlsbb(<16 x i8> // CHECK-LE: @llvm.ppc.altivec.vctzlsbb(<16 x i8>
// CHECK-LE-NEXT: ret i32 // CHECK-LE-NEXT: ret i32
return vec_cntlz_lsbb (vuca); return vec_cntlz_lsbb (vuca);
} }
signed int test60(void) { signed int test60(void) {
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
vector unsigned __int128 test68(void) { vector unsigned __int128 test68(void) {
// CHECK-BE: @llvm.ppc.altivec.vprtybq(<1 x i128> // CHECK-BE: @llvm.ppc.altivec.vprtybq(<1 x i128>
// CHECK-BE-NEXT: ret <1 x i128> // CHECK-BE-NEXT: ret <1 x i128>
// CHECK: @llvm.ppc.altivec.vprtybq(<1 x i128> // CHECK: @llvm.ppc.altivec.vprtybq(<1 x i128>
// CHECK-NEXT: ret <1 x i128> // CHECK-NEXT: ret <1 x i128>
return vec_parity_lsbb (vsi128a); return vec_parity_lsbb (vsi128a);
} }
vector double test55(void) {
// CHECK-BE: @llvm.ppc.vsx.xviexpdp(<2 x i64> %{{.+}}, <2 x i64>
// CHECK-BE-NEXT: ret <2 x double>
// CHECK: @llvm.ppc.vsx.xviexpdp(<2 x i64> %{{.+}}, <2 x i64>
// CHECK-NEXT: ret <2 x double>
return vec_insert_exp (vda,vulb);
}
vector double test56(void) {
// CHECK-BE: @llvm.ppc.vsx.xviexpdp(<2 x i64> %{{.+}}, <2 x i64>
// CHECK-BE-NEXT: ret <2 x double>
// CHECK: @llvm.ppc.vsx.xviexpdp(<2 x i64> %{{.+}}, <2 x i64>
// CHECK-NEXT: ret <2 x double>
return vec_insert_exp (vula, vulb);
}
vector float test57(void) {
// CHECK-BE: @llvm.ppc.vsx.xviexpsp(<4 x i32> %{{.+}}, <4 x i32>
// CHECK-BE-NEXT: ret <4 x float>
// CHECK: @llvm.ppc.vsx.xviexpsp(<4 x i32> %{{.+}}, <4 x i32>
// CHECK-NEXT: ret <4 x float>
return vec_insert_exp (vfa,vuib);
}
vector float test58(void) {
// CHECK-BE: @llvm.ppc.vsx.xviexpsp(<4 x i32> %{{.+}}, <4 x i32>
// CHECK-BE-NEXT: ret <4 x float>
// CHECK: @llvm.ppc.vsx.xviexpsp(<4 x i32> %{{.+}}, <4 x i32>
// CHECK-NEXT: ret <4 x float>
return vec_insert_exp (vuia,vuib);
}