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Differential D25837

[AMDGPU][mc] Fix ds_min/max[_rtn]_f32 - extra source operand removed.
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Authored by artem.tamazov on Oct 20 2016, 12:27 PM.

Details

Reviewers
• tstellarAMD
vpykhtin
Commits
rG751985a7577d: [AMDGPU][mc] Fix ds_min/max[_rtn]_f32 - extra source operand removed.
rL284825: [AMDGPU][mc] Fix ds_min/max[_rtn]_f32 - extra source operand removed.
Summary

Fixes Bug 28215. Lit tests updated.

Diff Detail

Repository
rL LLVM

Event Timeline

artem.tamazov updated this revision to Diff 75335.Oct 20 2016, 12:27 PM
artem.tamazov retitled this revision from to [AMDGPU][mc] Fix ds_min/max[_rtn]_f32 - extra source operand removed..
artem.tamazov updated this object.
artem.tamazov added a reviewer: vpykhtin.
artem.tamazov set the repository for this revision to rL LLVM.
artem.tamazov added a subscriber: Restricted Project.
Herald added a reviewer: • tstellarAMD. · View Herald TranscriptOct 20 2016, 12:27 PM
Herald added subscribers: tony-tye, yaxunl, nhaehnle and 3 others. · View Herald Transcript
vpykhtin accepted this revision.Oct 21 2016, 4:31 AM
vpykhtin edited edge metadata.

LGTM.

This revision is now accepted and ready to land.Oct 21 2016, 4:31 AM
Closed by commit rL284825: [AMDGPU][mc] Fix ds_min/max[_rtn]_f32 - extra source operand removed. (authored by artem.tamazov). · Explain WhyOct 21 2016, 7:58 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
AMDGPU/
8 lines
test/
MC/
AMDGPU/
28 lines
Disassembler/
AMDGPU/
16 lines

Diff 75429

llvm/trunk/lib/Target/AMDGPU/DSInstructions.td

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def DS_MIN_I32 : DS_1A1D_NORET<"ds_min_i32">; def DS_MIN_I32 : DS_1A1D_NORET<"ds_min_i32">;
def DS_MAX_I32 : DS_1A1D_NORET<"ds_max_i32">; def DS_MAX_I32 : DS_1A1D_NORET<"ds_max_i32">;
def DS_MIN_U32 : DS_1A1D_NORET<"ds_min_u32">; def DS_MIN_U32 : DS_1A1D_NORET<"ds_min_u32">;
def DS_MAX_U32 : DS_1A1D_NORET<"ds_max_u32">; def DS_MAX_U32 : DS_1A1D_NORET<"ds_max_u32">;
def DS_AND_B32 : DS_1A1D_NORET<"ds_and_b32">; def DS_AND_B32 : DS_1A1D_NORET<"ds_and_b32">;
def DS_OR_B32 : DS_1A1D_NORET<"ds_or_b32">; def DS_OR_B32 : DS_1A1D_NORET<"ds_or_b32">;
def DS_XOR_B32 : DS_1A1D_NORET<"ds_xor_b32">; def DS_XOR_B32 : DS_1A1D_NORET<"ds_xor_b32">;
def DS_ADD_F32 : DS_1A1D_NORET<"ds_add_f32">; def DS_ADD_F32 : DS_1A1D_NORET<"ds_add_f32">;
def DS_MIN_F32 : DS_1A1D_NORET<"ds_min_f32">;
def DS_MAX_F32 : DS_1A1D_NORET<"ds_max_f32">;
let mayLoad = 0 in { let mayLoad = 0 in {
def DS_WRITE_B8 : DS_1A1D_NORET<"ds_write_b8">; def DS_WRITE_B8 : DS_1A1D_NORET<"ds_write_b8">;
def DS_WRITE_B16 : DS_1A1D_NORET<"ds_write_b16">; def DS_WRITE_B16 : DS_1A1D_NORET<"ds_write_b16">;
def DS_WRITE_B32 : DS_1A1D_NORET<"ds_write_b32">; def DS_WRITE_B32 : DS_1A1D_NORET<"ds_write_b32">;
def DS_WRITE2_B32 : DS_1A2D_Off8_NORET<"ds_write2_b32">; def DS_WRITE2_B32 : DS_1A2D_Off8_NORET<"ds_write2_b32">;
def DS_WRITE2ST64_B32 : DS_1A2D_Off8_NORET<"ds_write2st64_b32">; def DS_WRITE2ST64_B32 : DS_1A2D_Off8_NORET<"ds_write2st64_b32">;
} }
def DS_MSKOR_B32 : DS_1A2D_NORET<"ds_mskor_b32">; def DS_MSKOR_B32 : DS_1A2D_NORET<"ds_mskor_b32">;
def DS_CMPST_B32 : DS_1A2D_NORET<"ds_cmpst_b32">; def DS_CMPST_B32 : DS_1A2D_NORET<"ds_cmpst_b32">;
def DS_CMPST_F32 : DS_1A2D_NORET<"ds_cmpst_f32">; def DS_CMPST_F32 : DS_1A2D_NORET<"ds_cmpst_f32">;
def DS_MIN_F32 : DS_1A2D_NORET<"ds_min_f32">;
def DS_MAX_F32 : DS_1A2D_NORET<"ds_max_f32">;
def DS_ADD_U64 : DS_1A1D_NORET<"ds_add_u64", VReg_64>; def DS_ADD_U64 : DS_1A1D_NORET<"ds_add_u64", VReg_64>;
def DS_SUB_U64 : DS_1A1D_NORET<"ds_sub_u64", VReg_64>; def DS_SUB_U64 : DS_1A1D_NORET<"ds_sub_u64", VReg_64>;
def DS_RSUB_U64 : DS_1A1D_NORET<"ds_rsub_u64", VReg_64>; def DS_RSUB_U64 : DS_1A1D_NORET<"ds_rsub_u64", VReg_64>;
def DS_INC_U64 : DS_1A1D_NORET<"ds_inc_u64", VReg_64>; def DS_INC_U64 : DS_1A1D_NORET<"ds_inc_u64", VReg_64>;
def DS_DEC_U64 : DS_1A1D_NORET<"ds_dec_u64", VReg_64>; def DS_DEC_U64 : DS_1A1D_NORET<"ds_dec_u64", VReg_64>;
def DS_MIN_I64 : DS_1A1D_NORET<"ds_min_i64", VReg_64>; def DS_MIN_I64 : DS_1A1D_NORET<"ds_min_i64", VReg_64>;
def DS_MAX_I64 : DS_1A1D_NORET<"ds_max_i64", VReg_64>; def DS_MAX_I64 : DS_1A1D_NORET<"ds_max_i64", VReg_64>;
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def DS_XOR_RTN_B32 : DS_1A1D_RET<"ds_xor_rtn_b32">, def DS_XOR_RTN_B32 : DS_1A1D_RET<"ds_xor_rtn_b32">,
AtomicNoRet<"ds_xor_b32", 1>; AtomicNoRet<"ds_xor_b32", 1>;
def DS_MSKOR_RTN_B32 : DS_1A2D_RET<"ds_mskor_rtn_b32">, def DS_MSKOR_RTN_B32 : DS_1A2D_RET<"ds_mskor_rtn_b32">,
AtomicNoRet<"ds_mskor_b32", 1>; AtomicNoRet<"ds_mskor_b32", 1>;
def DS_CMPST_RTN_B32 : DS_1A2D_RET <"ds_cmpst_rtn_b32">, def DS_CMPST_RTN_B32 : DS_1A2D_RET <"ds_cmpst_rtn_b32">,
AtomicNoRet<"ds_cmpst_b32", 1>; AtomicNoRet<"ds_cmpst_b32", 1>;
def DS_CMPST_RTN_F32 : DS_1A2D_RET <"ds_cmpst_rtn_f32">, def DS_CMPST_RTN_F32 : DS_1A2D_RET <"ds_cmpst_rtn_f32">,
AtomicNoRet<"ds_cmpst_f32", 1>; AtomicNoRet<"ds_cmpst_f32", 1>;
def DS_MIN_RTN_F32 : DS_1A2D_RET <"ds_min_rtn_f32">, def DS_MIN_RTN_F32 : DS_1A1D_RET <"ds_min_rtn_f32">,
AtomicNoRet<"ds_min_f32", 1>; AtomicNoRet<"ds_min_f32", 1>;
def DS_MAX_RTN_F32 : DS_1A2D_RET <"ds_max_rtn_f32">, def DS_MAX_RTN_F32 : DS_1A1D_RET <"ds_max_rtn_f32">,
AtomicNoRet<"ds_max_f32", 1>; AtomicNoRet<"ds_max_f32", 1>;
def DS_WRXCHG_RTN_B32 : DS_1A1D_RET<"ds_wrxchg_rtn_b32">, def DS_WRXCHG_RTN_B32 : DS_1A1D_RET<"ds_wrxchg_rtn_b32">,
AtomicNoRet<"", 1>; AtomicNoRet<"", 1>;
def DS_WRXCHG2_RTN_B32 : DS_1A2D_RET<"ds_wrxchg2_rtn_b32", VReg_64, VGPR_32>, def DS_WRXCHG2_RTN_B32 : DS_1A2D_RET<"ds_wrxchg2_rtn_b32", VReg_64, VGPR_32>,
AtomicNoRet<"", 1>; AtomicNoRet<"", 1>;
def DS_WRXCHG2ST64_RTN_B32 : DS_1A2D_RET<"ds_wrxchg2st64_rtn_b32", VReg_64, VGPR_32>, def DS_WRXCHG2ST64_RTN_B32 : DS_1A2D_RET<"ds_wrxchg2st64_rtn_b32", VReg_64, VGPR_32>,
AtomicNoRet<"", 1>; AtomicNoRet<"", 1>;
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llvm/trunk/test/MC/AMDGPU/ds.s

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ds_cmpst_b32 v2, v4, v6 ds_cmpst_b32 v2, v4, v6
// SICI: ds_cmpst_b32 v2, v4, v6 ; encoding: [0x00,0x00,0x40,0xd8,0x02,0x04,0x06,0x00] // SICI: ds_cmpst_b32 v2, v4, v6 ; encoding: [0x00,0x00,0x40,0xd8,0x02,0x04,0x06,0x00]
// VI: ds_cmpst_b32 v2, v4, v6 ; encoding: [0x00,0x00,0x20,0xd8,0x02,0x04,0x06,0x00] // VI: ds_cmpst_b32 v2, v4, v6 ; encoding: [0x00,0x00,0x20,0xd8,0x02,0x04,0x06,0x00]
ds_cmpst_f32 v2, v4, v6 ds_cmpst_f32 v2, v4, v6
// SICI: ds_cmpst_f32 v2, v4, v6 ; encoding: [0x00,0x00,0x44,0xd8,0x02,0x04,0x06,0x00] // SICI: ds_cmpst_f32 v2, v4, v6 ; encoding: [0x00,0x00,0x44,0xd8,0x02,0x04,0x06,0x00]
// VI: ds_cmpst_f32 v2, v4, v6 ; encoding: [0x00,0x00,0x22,0xd8,0x02,0x04,0x06,0x00] // VI: ds_cmpst_f32 v2, v4, v6 ; encoding: [0x00,0x00,0x22,0xd8,0x02,0x04,0x06,0x00]
ds_min_f32 v2, v4, v6 ds_min_f32 v2, v4
// SICI: ds_min_f32 v2, v4, v6 ; encoding: [0x00,0x00,0x48,0xd8,0x02,0x04,0x06,0x00] // SICI: ds_min_f32 v2, v4 ; encoding: [0x00,0x00,0x48,0xd8,0x02,0x04,0x00,0x00]
// VI: ds_min_f32 v2, v4, v6 ; encoding: [0x00,0x00,0x24,0xd8,0x02,0x04,0x06,0x00] // VI: ds_min_f32 v2, v4 ; encoding: [0x00,0x00,0x24,0xd8,0x02,0x04,0x00,0x00]
ds_max_f32 v2, v4, v6 ds_max_f32 v2, v4
// SICI: ds_max_f32 v2, v4, v6 ; encoding: [0x00,0x00,0x4c,0xd8,0x02,0x04,0x06,0x00] // SICI: ds_max_f32 v2, v4 ; encoding: [0x00,0x00,0x4c,0xd8,0x02,0x04,0x00,0x00]
// VI: ds_max_f32 v2, v4, v6 ; encoding: [0x00,0x00,0x26,0xd8,0x02,0x04,0x06,0x00] // VI: ds_max_f32 v2, v4 ; encoding: [0x00,0x00,0x26,0xd8,0x02,0x04,0x00,0x00]
ds_gws_init v2 gds ds_gws_init v2 gds
// SICI: ds_gws_init v2 gds ; encoding: [0x00,0x00,0x66,0xd8,0x02,0x00,0x00,0x00] // SICI: ds_gws_init v2 gds ; encoding: [0x00,0x00,0x66,0xd8,0x02,0x00,0x00,0x00]
// VI: ds_gws_init v2 gds ; encoding: [0x00,0x00,0x33,0xd8,0x02,0x00,0x00,0x00] // VI: ds_gws_init v2 gds ; encoding: [0x00,0x00,0x33,0xd8,0x02,0x00,0x00,0x00]
ds_gws_sema_v v2 gds ds_gws_sema_v v2 gds
// SICI: ds_gws_sema_v v2 gds ; encoding: [0x00,0x00,0x6a,0xd8,0x02,0x00,0x00,0x00] // SICI: ds_gws_sema_v v2 gds ; encoding: [0x00,0x00,0x6a,0xd8,0x02,0x00,0x00,0x00]
// VI: ds_gws_sema_v v2 gds ; encoding: [0x00,0x00,0x35,0xd8,0x02,0x00,0x00,0x00] // VI: ds_gws_sema_v v2 gds ; encoding: [0x00,0x00,0x35,0xd8,0x02,0x00,0x00,0x00]
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ds_cmpst_rtn_b32 v8, v2, v4, v6 ds_cmpst_rtn_b32 v8, v2, v4, v6
// SICI: ds_cmpst_rtn_b32 v8, v2, v4, v6 ; encoding: [0x00,0x00,0xc0,0xd8,0x02,0x04,0x06,0x08] // SICI: ds_cmpst_rtn_b32 v8, v2, v4, v6 ; encoding: [0x00,0x00,0xc0,0xd8,0x02,0x04,0x06,0x08]
// VI: ds_cmpst_rtn_b32 v8, v2, v4, v6 ; encoding: [0x00,0x00,0x60,0xd8,0x02,0x04,0x06,0x08] // VI: ds_cmpst_rtn_b32 v8, v2, v4, v6 ; encoding: [0x00,0x00,0x60,0xd8,0x02,0x04,0x06,0x08]
ds_cmpst_rtn_f32 v8, v2, v4, v6 ds_cmpst_rtn_f32 v8, v2, v4, v6
// SICI: ds_cmpst_rtn_f32 v8, v2, v4, v6 ; encoding: [0x00,0x00,0xc4,0xd8,0x02,0x04,0x06,0x08] // SICI: ds_cmpst_rtn_f32 v8, v2, v4, v6 ; encoding: [0x00,0x00,0xc4,0xd8,0x02,0x04,0x06,0x08]
// VI: ds_cmpst_rtn_f32 v8, v2, v4, v6 ; encoding: [0x00,0x00,0x62,0xd8,0x02,0x04,0x06,0x08] // VI: ds_cmpst_rtn_f32 v8, v2, v4, v6 ; encoding: [0x00,0x00,0x62,0xd8,0x02,0x04,0x06,0x08]
ds_min_rtn_f32 v8, v2, v4, v6 ds_min_rtn_f32 v8, v2, v4
// SICI: ds_min_rtn_f32 v8, v2, v4, v6 ; encoding: [0x00,0x00,0xc8,0xd8,0x02,0x04,0x06,0x08] // SICI: ds_min_rtn_f32 v8, v2, v4 ; encoding: [0x00,0x00,0xc8,0xd8,0x02,0x04,0x00,0x08]
// VI: ds_min_rtn_f32 v8, v2, v4, v6 ; encoding: [0x00,0x00,0x64,0xd8,0x02,0x04,0x06,0x08] // VI: ds_min_rtn_f32 v8, v2, v4 ; encoding: [0x00,0x00,0x64,0xd8,0x02,0x04,0x00,0x08]
ds_max_rtn_f32 v8, v2, v4, v6 ds_max_rtn_f32 v8, v2, v4
// SICI: ds_max_rtn_f32 v8, v2, v4, v6 ; encoding: [0x00,0x00,0xcc,0xd8,0x02,0x04,0x06,0x08] // SICI: ds_max_rtn_f32 v8, v2, v4 ; encoding: [0x00,0x00,0xcc,0xd8,0x02,0x04,0x00,0x08]
// VI: ds_max_rtn_f32 v8, v2, v4, v6 ; encoding: [0x00,0x00,0x66,0xd8,0x02,0x04,0x06,0x08] // VI: ds_max_rtn_f32 v8, v2, v4 ; encoding: [0x00,0x00,0x66,0xd8,0x02,0x04,0x00,0x08]
ds_swizzle_b32 v8, v2 ds_swizzle_b32 v8, v2
// SICI: ds_swizzle_b32 v8, v2 ; encoding: [0x00,0x00,0xd4,0xd8,0x02,0x00,0x00,0x08] // SICI: ds_swizzle_b32 v8, v2 ; encoding: [0x00,0x00,0xd4,0xd8,0x02,0x00,0x00,0x08]
// VI: ds_swizzle_b32 v8, v2 ; encoding: [0x00,0x00,0x7a,0xd8,0x02,0x00,0x00,0x08] // VI: ds_swizzle_b32 v8, v2 ; encoding: [0x00,0x00,0x7a,0xd8,0x02,0x00,0x00,0x08]
ds_read_b32 v8, v2 ds_read_b32 v8, v2
// SICI: ds_read_b32 v8, v2 ; encoding: [0x00,0x00,0xd8,0xd8,0x02,0x00,0x00,0x08] // SICI: ds_read_b32 v8, v2 ; encoding: [0x00,0x00,0xd8,0xd8,0x02,0x00,0x00,0x08]
// VI: ds_read_b32 v8, v2 ; encoding: [0x00,0x00,0x6c,0xd8,0x02,0x00,0x00,0x08] // VI: ds_read_b32 v8, v2 ; encoding: [0x00,0x00,0x6c,0xd8,0x02,0x00,0x00,0x08]
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llvm/trunk/test/MC/Disassembler/AMDGPU/ds_vi.txt

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0x00 0x00 0x1e 0xd8 0x02 0x04 0x06 0x00 0x00 0x00 0x1e 0xd8 0x02 0x04 0x06 0x00
# VI: ds_cmpst_b32 v2, v4, v6 ; encoding: [0x00,0x00,0x20,0xd8,0x02,0x04,0x06,0x00] # VI: ds_cmpst_b32 v2, v4, v6 ; encoding: [0x00,0x00,0x20,0xd8,0x02,0x04,0x06,0x00]
0x00 0x00 0x20 0xd8 0x02 0x04 0x06 0x00 0x00 0x00 0x20 0xd8 0x02 0x04 0x06 0x00
# VI: ds_cmpst_f32 v2, v4, v6 ; encoding: [0x00,0x00,0x22,0xd8,0x02,0x04,0x06,0x00] # VI: ds_cmpst_f32 v2, v4, v6 ; encoding: [0x00,0x00,0x22,0xd8,0x02,0x04,0x06,0x00]
0x00 0x00 0x22 0xd8 0x02 0x04 0x06 0x00 0x00 0x00 0x22 0xd8 0x02 0x04 0x06 0x00
# VI: ds_min_f32 v2, v4, v6 ; encoding: [0x00,0x00,0x24,0xd8,0x02,0x04,0x06,0x00] # VI: ds_min_f32 v2, v4 ; encoding: [0x00,0x00,0x24,0xd8,0x02,0x04,0x00,0x00]
0x00 0x00 0x24 0xd8 0x02 0x04 0x06 0x00 0x00 0x00 0x24 0xd8 0x02 0x04 0x00 0x00
# VI: ds_max_f32 v2, v4, v6 ; encoding: [0x00,0x00,0x26,0xd8,0x02,0x04,0x06,0x00] # VI: ds_max_f32 v2, v4 ; encoding: [0x00,0x00,0x26,0xd8,0x02,0x04,0x00,0x00]
0x00 0x00 0x26 0xd8 0x02 0x04 0x06 0x00 0x00 0x00 0x26 0xd8 0x02 0x04 0x00 0x00
# VI: ds_gws_init v2 gds ; encoding: [0x00,0x00,0x33,0xd8,0x02,0x00,0x00,0x00] # VI: ds_gws_init v2 gds ; encoding: [0x00,0x00,0x33,0xd8,0x02,0x00,0x00,0x00]
0x00 0x00 0x33 0xd8 0x02 0x00 0x00 0x00 0x00 0x00 0x33 0xd8 0x02 0x00 0x00 0x00
# VI: ds_gws_sema_v v2 gds ; encoding: [0x00,0x00,0x35,0xd8,0x02,0x00,0x00,0x00] # VI: ds_gws_sema_v v2 gds ; encoding: [0x00,0x00,0x35,0xd8,0x02,0x00,0x00,0x00]
0x00 0x00 0x35 0xd8 0x02 0x00 0x00 0x00 0x00 0x00 0x35 0xd8 0x02 0x00 0x00 0x00
# VI: ds_gws_sema_br v2 gds ; encoding: [0x00,0x00,0x37,0xd8,0x02,0x00,0x00,0x00] # VI: ds_gws_sema_br v2 gds ; encoding: [0x00,0x00,0x37,0xd8,0x02,0x00,0x00,0x00]
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0x00 0x00 0x5e 0xd8 0x02 0x04 0x06 0x08 0x00 0x00 0x5e 0xd8 0x02 0x04 0x06 0x08
# VI: ds_cmpst_rtn_b32 v8, v2, v4, v6 ; encoding: [0x00,0x00,0x60,0xd8,0x02,0x04,0x06,0x08] # VI: ds_cmpst_rtn_b32 v8, v2, v4, v6 ; encoding: [0x00,0x00,0x60,0xd8,0x02,0x04,0x06,0x08]
0x00 0x00 0x60 0xd8 0x02 0x04 0x06 0x08 0x00 0x00 0x60 0xd8 0x02 0x04 0x06 0x08
# VI: ds_cmpst_rtn_f32 v8, v2, v4, v6 ; encoding: [0x00,0x00,0x62,0xd8,0x02,0x04,0x06,0x08] # VI: ds_cmpst_rtn_f32 v8, v2, v4, v6 ; encoding: [0x00,0x00,0x62,0xd8,0x02,0x04,0x06,0x08]
0x00 0x00 0x62 0xd8 0x02 0x04 0x06 0x08 0x00 0x00 0x62 0xd8 0x02 0x04 0x06 0x08
# VI: ds_min_rtn_f32 v8, v2, v4, v6 ; encoding: [0x00,0x00,0x64,0xd8,0x02,0x04,0x06,0x08] # VI: ds_min_rtn_f32 v8, v2, v4 ; encoding: [0x00,0x00,0x64,0xd8,0x02,0x04,0x00,0x08]
0x00 0x00 0x64 0xd8 0x02 0x04 0x06 0x08 0x00 0x00 0x64 0xd8 0x02 0x04 0x00 0x08
# VI: ds_max_rtn_f32 v8, v2, v4, v6 ; encoding: [0x00,0x00,0x66,0xd8,0x02,0x04,0x06,0x08] # VI: ds_max_rtn_f32 v8, v2, v4 ; encoding: [0x00,0x00,0x66,0xd8,0x02,0x04,0x00,0x08]
0x00 0x00 0x66 0xd8 0x02 0x04 0x06 0x08 0x00 0x00 0x66 0xd8 0x02 0x04 0x00 0x08
# VI: ds_swizzle_b32 v8, v2 ; encoding: [0x00,0x00,0x7a,0xd8,0x02,0x00,0x00,0x08] # VI: ds_swizzle_b32 v8, v2 ; encoding: [0x00,0x00,0x7a,0xd8,0x02,0x00,0x00,0x08]
0x00 0x00 0x7a 0xd8 0x02 0x00 0x00 0x08 0x00 0x00 0x7a 0xd8 0x02 0x00 0x00 0x08
# VI: ds_read_b32 v8, v2 ; encoding: [0x00,0x00,0x6c,0xd8,0x02,0x00,0x00,0x08] # VI: ds_read_b32 v8, v2 ; encoding: [0x00,0x00,0x6c,0xd8,0x02,0x00,0x00,0x08]
0x00 0x00 0x6c 0xd8 0x02 0x00 0x00 0x08 0x00 0x00 0x6c 0xd8 0x02 0x00 0x00 0x08
# VI: ds_read2_b32 v[8:9], v2 ; encoding: [0x00,0x00,0x6e,0xd8,0x02,0x00,0x00,0x08] # VI: ds_read2_b32 v[8:9], v2 ; encoding: [0x00,0x00,0x6e,0xd8,0x02,0x00,0x00,0x08]
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