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AMDGPU/SI: Fix crash caused by r284267
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Authored by • tstellarAMD on Oct 19 2016, 11:45 AM.

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Reviewers

nhaehnle
arsenm

Commits

rG6c7dd980e4eb: AMDGPU/SI: Fix crash caused by r284267
rL284875: AMDGPU/SI: Fix crash caused by r284267

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Build Status

Buildable 629
Build 629: arc lint + arc unit

Event Timeline

• tstellarAMD updated this revision to Diff 75183.Oct 19 2016, 11:45 AM

• tstellarAMD retitled this revision from to AMDGPU/SI: Fix crash caused by r284267.

• tstellarAMD updated this object.

• tstellarAMD added a reviewer: arsenm.

• tstellarAMD added a subscriber: llvm-commits.

Herald added subscribers: tony-tye, yaxunl, nhaehnle and 2 others. · View Herald TranscriptOct 19 2016, 11:45 AM

LGTM, just one small comment.

test/CodeGen/AMDGPU/mul_int24.ll
150–152	Add a GCN-LABEL.

This revision is now accepted and ready to land.Oct 20 2016, 4:54 AM

Closed by commit rL284875: AMDGPU/SI: Fix crash caused by r284267 (authored by tstellar). · Explain WhyOct 21 2016, 1:34 PM

This revision was automatically updated to reflect the committed changes.

Revision Contents

Path

Size

lib/

Target/

AMDGPU/

AMDGPUISelLowering.cpp

5 lines

test/

CodeGen/

AMDGPU/

mul_int24.ll

24 lines

Diff 75183

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

Show First 20 Lines • Show All 2,625 Lines • ▼ Show 20 Lines	SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
case ISD::MULHS:		case ISD::MULHS:
return performMulhsCombine(N, DCI);		return performMulhsCombine(N, DCI);
case ISD::MULHU:		case ISD::MULHU:
return performMulhuCombine(N, DCI);		return performMulhuCombine(N, DCI);
case AMDGPUISD::MUL_I24:		case AMDGPUISD::MUL_I24:
case AMDGPUISD::MUL_U24:		case AMDGPUISD::MUL_U24:
case AMDGPUISD::MULHI_I24:		case AMDGPUISD::MULHI_I24:
case AMDGPUISD::MULHI_U24: {		case AMDGPUISD::MULHI_U24: {
simplifyI24(N, 0, DCI);		// If the first call to simplify is successfull, then N may end up being
simplifyI24(N, 1, DCI);		// deleted, so we shouldn't call simplifyI24 again.
		simplifyI24(N, 0, DCI) \|\| simplifyI24(N, 1, DCI);
return SDValue();		return SDValue();
}		}
case AMDGPUISD::MUL_LOHI_I24:		case AMDGPUISD::MUL_LOHI_I24:
case AMDGPUISD::MUL_LOHI_U24:		case AMDGPUISD::MUL_LOHI_U24:
return performMulLoHi24Combine(N, DCI);		return performMulLoHi24Combine(N, DCI);
case ISD::SELECT:		case ISD::SELECT:
return performSelectCombine(N, DCI);		return performSelectCombine(N, DCI);
case AMDGPUISD::BFE_I32:		case AMDGPUISD::BFE_I32:
▲ Show 20 Lines • Show All 328 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/mul_int24.ll

Show First 20 Lines • Show All 140 Lines • ▼ Show 20 Lines	entry:
%b_24 = ashr i33 %tmp1, 9		%b_24 = ashr i33 %tmp1, 9
%tmp2 = mul i33 %a_24, %b_24		%tmp2 = mul i33 %a_24, %b_24
%hi = lshr i33 %tmp2, 32		%hi = lshr i33 %tmp2, 32
%trunc = trunc i33 %hi to i32		%trunc = trunc i33 %hi to i32

store i32 %trunc, i32 addrspace(1)* %out		store i32 %trunc, i32 addrspace(1)* %out
ret void		ret void
}		}

		; GCN: v_mul_i32_i24_e32 v[[VAL_LO:[0-9]+]]
		; GCN: v_mov_b32_e32 v[[VAL_HI:[0-9]+]], v[[VAL_LO]]
		; GCN: buffer_store_dwordx2 v{{\[}}[[VAL_LO]]:[[VAL_HI]]{{\]}}
		nhaehnleUnsubmitted Not Done Reply Inline Actions Add a GCN-LABEL. nhaehnle: Add a GCN-LABEL.
		define void @simplify_i24_crash(<2 x i32> addrspace(1)* %out, i32 %arg0, <2 x i32> %arg1, <2 x i32> %arg2) {
		bb:
		%cmp = icmp eq i32 %arg0, 0
		br i1 %cmp, label %bb11, label %bb7

		bb11:
		%tmp14 = shufflevector <2 x i32> %arg1, <2 x i32> undef, <2 x i32> zeroinitializer
		%tmp16 = shufflevector <2 x i32> %arg2, <2 x i32> undef, <2 x i32> zeroinitializer
		%tmp17 = shl <2 x i32> %tmp14, <i32 8, i32 8>
		%tmp18 = ashr <2 x i32> %tmp17, <i32 8, i32 8>
		%tmp19 = shl <2 x i32> %tmp16, <i32 8, i32 8>
		%tmp20 = ashr <2 x i32> %tmp19, <i32 8, i32 8>
		%tmp21 = mul <2 x i32> %tmp18, %tmp20
		store <2 x i32> %tmp21, <2 x i32> addrspace(1)* %out
		br label %bb7

		bb7:
		ret void

		}
attributes #0 = { nounwind }		attributes #0 = { nounwind }