This is an archive of the discontinued LLVM Phabricator instance.

Differential D25528

AMDGPU/SI: Handle s_setreg hazard in GCNHazardRecognizer
ClosedPublic

Authored by • tstellarAMD on Oct 12 2016, 12:06 PM.

Details

Reviewers
arsenm
Commits
rG30d30824b408: AMDGPU/SI: Handle s_setreg hazard in GCNHazardRecognizer
rL285338: AMDGPU/SI: Handle s_setreg hazard in GCNHazardRecognizer

Diff Detail

Event Timeline

• tstellarAMD updated this revision to Diff 74416.Oct 12 2016, 12:06 PM
• tstellarAMD retitled this revision from to AMDGPU/SI: Handle s_setreg hazard in GCNHazardRecognizer.
• tstellarAMD updated this object.
• tstellarAMD added a reviewer: arsenm.
• tstellarAMD added a subscriber: llvm-commits.
Herald added subscribers: tony-tye, yaxunl, nhaehnle and 2 others. · View Herald TranscriptOct 12 2016, 12:06 PM
• tstellarAMD added a comment.Oct 26 2016, 7:50 AM

Ping.

nhaehnle added a comment.Oct 27 2016, 2:53 AM

One small comment, apart from that LGTM.

test/CodeGen/MIR/AMDGPU/inserted-wait-states.mir
140

GCN-NEXT?

Closed by commit rL285338: AMDGPU/SI: Handle s_setreg hazard in GCNHazardRecognizer (authored by tstellar). · Explain WhyOct 27 2016, 1:48 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
AMDGPU/
1 line
19 lines
test/
CodeGen/
MIR/
AMDGPU/
142 lines

Diff 74416

lib/Target/AMDGPU/GCNHazardRecognizer.h

Show All 40 Linesclass GCNHazardRecognizer final : public ScheduleHazardRecognizer {
int getWaitStatesSinceSetReg(function_ref<bool(MachineInstr *)> IsHazard); int getWaitStatesSinceSetReg(function_ref<bool(MachineInstr *)> IsHazard);
int checkSMEMSoftClauseHazards(MachineInstr *SMEM); int checkSMEMSoftClauseHazards(MachineInstr *SMEM);
int checkSMRDHazards(MachineInstr *SMRD); int checkSMRDHazards(MachineInstr *SMRD);
int checkVMEMHazards(MachineInstr* VMEM); int checkVMEMHazards(MachineInstr* VMEM);
int checkDPPHazards(MachineInstr *DPP); int checkDPPHazards(MachineInstr *DPP);
int checkDivFMasHazards(MachineInstr *DivFMas); int checkDivFMasHazards(MachineInstr *DivFMas);
int checkGetRegHazards(MachineInstr *GetRegInstr); int checkGetRegHazards(MachineInstr *GetRegInstr);
int checkSetRegHazards(MachineInstr *SetRegInstr);
public: public:
GCNHazardRecognizer(const MachineFunction &MF); GCNHazardRecognizer(const MachineFunction &MF);
// We can only issue one instruction per cycle. // We can only issue one instruction per cycle.
bool atIssueLimit() const override { return true; } bool atIssueLimit() const override { return true; }
void EmitInstruction(SUnit *SU) override; void EmitInstruction(SUnit *SU) override;
void EmitInstruction(MachineInstr *MI) override; void EmitInstruction(MachineInstr *MI) override;
HazardType getHazardType(SUnit *SU, int Stalls) override; HazardType getHazardType(SUnit *SU, int Stalls) override;
void EmitNoop() override; void EmitNoop() override;
Show All 9 Lines

lib/Target/AMDGPU/GCNHazardRecognizer.cpp

Show First 20 Lines • Show All 70 Lines • ▼ Show 20 Lines if (SIInstrInfo::isDPP(*MI) && checkDPPHazards(MI) > 0)
return NoopHazard; return NoopHazard;
if (isDivFMas(MI->getOpcode()) && checkDivFMasHazards(MI) > 0) if (isDivFMas(MI->getOpcode()) && checkDivFMasHazards(MI) > 0)
return NoopHazard; return NoopHazard;
if (isSGetReg(MI->getOpcode()) && checkGetRegHazards(MI) > 0) if (isSGetReg(MI->getOpcode()) && checkGetRegHazards(MI) > 0)
return NoopHazard; return NoopHazard;
if (isSSetReg(MI->getOpcode()) && checkSetRegHazards(MI) > 0)
return NoopHazard;
return NoHazard; return NoHazard;
} }
unsigned GCNHazardRecognizer::PreEmitNoops(SUnit *SU) { unsigned GCNHazardRecognizer::PreEmitNoops(SUnit *SU) {
return PreEmitNoops(SU->getInstr()); return PreEmitNoops(SU->getInstr());
} }
unsigned GCNHazardRecognizer::PreEmitNoops(MachineInstr *MI) { unsigned GCNHazardRecognizer::PreEmitNoops(MachineInstr *MI) {
if (SIInstrInfo::isSMRD(*MI)) if (SIInstrInfo::isSMRD(*MI))
return std::max(0, checkSMRDHazards(MI)); return std::max(0, checkSMRDHazards(MI));
if (SIInstrInfo::isVMEM(*MI)) if (SIInstrInfo::isVMEM(*MI))
return std::max(0, checkVMEMHazards(MI)); return std::max(0, checkVMEMHazards(MI));
if (SIInstrInfo::isDPP(*MI)) if (SIInstrInfo::isDPP(*MI))
return std::max(0, checkDPPHazards(MI)); return std::max(0, checkDPPHazards(MI));
if (isDivFMas(MI->getOpcode())) if (isDivFMas(MI->getOpcode()))
return std::max(0, checkDivFMasHazards(MI)); return std::max(0, checkDivFMasHazards(MI));
if (isSGetReg(MI->getOpcode())) if (isSGetReg(MI->getOpcode()))
return std::max(0, checkGetRegHazards(MI)); return std::max(0, checkGetRegHazards(MI));
if (isSSetReg(MI->getOpcode()))
return std::max(0, checkSetRegHazards(MI));
return 0; return 0;
} }
void GCNHazardRecognizer::EmitNoop() { void GCNHazardRecognizer::EmitNoop() {
EmittedInstrs.push_front(nullptr); EmittedInstrs.push_front(nullptr);
} }
void GCNHazardRecognizer::AdvanceCycle() { void GCNHazardRecognizer::AdvanceCycle() {
▲ Show 20 Lines • Show All 216 Lines • ▼ Show 20 Linesint GCNHazardRecognizer::checkGetRegHazards(MachineInstr *GetRegInstr) {
const int GetRegWaitStates = 2; const int GetRegWaitStates = 2;
auto IsHazardFn = [TII, HWReg] (MachineInstr *MI) { auto IsHazardFn = [TII, HWReg] (MachineInstr *MI) {
return HWReg == getHWReg(TII, *MI); return HWReg == getHWReg(TII, *MI);
}; };
int WaitStatesNeeded = getWaitStatesSinceSetReg(IsHazardFn); int WaitStatesNeeded = getWaitStatesSinceSetReg(IsHazardFn);
return GetRegWaitStates - WaitStatesNeeded; return GetRegWaitStates - WaitStatesNeeded;
} }
int GCNHazardRecognizer::checkSetRegHazards(MachineInstr *SetRegInstr) {
const SIInstrInfo *TII = ST.getInstrInfo();
unsigned HWReg = getHWReg(TII, *SetRegInstr);
const int SetRegWaitStates =
ST.getGeneration() <= AMDGPUSubtarget::SEA_ISLANDS ? 1 : 2;
auto IsHazardFn = [TII, HWReg] (MachineInstr *MI) {
return HWReg == getHWReg(TII, *MI);
};
int WaitStatesNeeded = getWaitStatesSinceSetReg(IsHazardFn);
return SetRegWaitStates - WaitStatesNeeded;
}

test/CodeGen/MIR/AMDGPU/inserted-wait-states.mir

# RUN: llc -march=amdgcn -run-pass post-RA-hazard-rec %s -o - | FileCheck %s # RUN: llc -march=amdgcn -mcpu=tahiti -run-pass post-RA-hazard-rec %s -o - | FileCheck %s -check-prefixes=GCN
# XUN: llc -march=amdgcn -mcpu=hawaii -run-pass post-RA-hazard-rec %s -o - | FileCheck %s -check-prefixes=GCN
# XUN: llc -march=amdgcn -mcpu=fiji -run-pass post-RA-hazard-rec %s -o - | FileCheck %s -check-prefixes=GCN,VI
--- | --- |
define void @div_fmas() { ret void } define void @div_fmas() { ret void }
define void @s_getreg() { ret void } define void @s_getreg() { ret void }
define void @s_setreg() { ret void }
... ...
--- ---
# CHECK-LABEL: name: div_fmas # GCN-LABEL: name: div_fmas
# CHECK-LABEL: bb.0: # GCN-LABEL: bb.0:
# CHECK: S_MOV_B64 # GCN: S_MOV_B64
# CHECK-NOT: S_NOP # GCN-NOT: S_NOP
# CHECK: V_DIV_FMAS # GCN: V_DIV_FMAS
# CHECK-LABEL: bb.1: # GCN-LABEL: bb.1:
# CHECK: V_CMP_EQ_I32 # GCN: V_CMP_EQ_I32
# CHECK: S_NOP # GCN: S_NOP
# CHECK: S_NOP # GCN: S_NOP
# CHECK: S_NOP # GCN: S_NOP
# CHECK: S_NOP # GCN: S_NOP
# CHECK: V_DIV_FMAS_F32 # GCN: V_DIV_FMAS_F32
# CHECK-LABEL: bb.2: # GCN-LABEL: bb.2:
# CHECK: V_CMP_EQ_I32 # GCN: V_CMP_EQ_I32
# CHECK: S_NOP # GCN: S_NOP
# CHECK: S_NOP # GCN: S_NOP
# CHECK: S_NOP # GCN: S_NOP
# CHECK: S_NOP # GCN: S_NOP
# CHECK: V_DIV_FMAS_F32 # GCN: V_DIV_FMAS_F32
# CHECK-LABEL: bb.3: # GCN-LABEL: bb.3:
# CHECK: V_DIV_SCALE_F32 # GCN: V_DIV_SCALE_F32
# CHECK: S_NOP # GCN: S_NOP
# CHECK: S_NOP # GCN: S_NOP
# CHECK: S_NOP # GCN: S_NOP
# CHECK: S_NOP # GCN: S_NOP
# CHECK: V_DIV_FMAS_F32 # GCN: V_DIV_FMAS_F32
name: div_fmas name: div_fmas
body: | body: |
bb.0: bb.0:
successors: %bb.1 successors: %bb.1
%vcc = S_MOV_B64 0 %vcc = S_MOV_B64 0
%vgpr0 = V_DIV_FMAS_F32 0, %vgpr1, 0, %vgpr2, 0, %vgpr3, 0, 0, implicit %vcc, implicit %exec %vgpr0 = V_DIV_FMAS_F32 0, %vgpr1, 0, %vgpr2, 0, %vgpr3, 0, 0, implicit %vcc, implicit %exec
S_BRANCH %bb.1 S_BRANCH %bb.1
Show All 14 Lines bb.3:
%vgpr4, %vcc = V_DIV_SCALE_F32 0, %vgpr1, 0, %vgpr1, 0, %vgpr3, 0, 0, implicit %exec %vgpr4, %vcc = V_DIV_SCALE_F32 0, %vgpr1, 0, %vgpr1, 0, %vgpr3, 0, 0, implicit %exec
%vgpr0 = V_DIV_FMAS_F32 0, %vgpr1, 0, %vgpr2, 0, %vgpr3, 0, 0, implicit %vcc, implicit %exec %vgpr0 = V_DIV_FMAS_F32 0, %vgpr1, 0, %vgpr2, 0, %vgpr3, 0, 0, implicit %vcc, implicit %exec
S_ENDPGM S_ENDPGM
... ...
... ...
--- ---
# CHECK-LABEL: name: s_getreg # GCN-LABEL: name: s_getreg
# CHECK-LABEL: bb.0: # GCN-LABEL: bb.0:
# CHECK: S_SETREG # GCN: S_SETREG
# CHECK: S_NOP 0 # GCN: S_NOP 0
# CHECK: S_NOP 0 # GCN: S_NOP 0
# CHECK: S_GETREG # GCN: S_GETREG
# CHECK-LABEL: bb.1: # GCN-LABEL: bb.1:
# CHECK: S_SETREG_IMM32 # GCN: S_SETREG_IMM32
# CHECK: S_NOP 0 # GCN: S_NOP 0
# CHECK: S_NOP 0 # GCN: S_NOP 0
# CHECK: S_GETREG # GCN: S_GETREG
# CHECK-LABEL: bb.2: # GCN-LABEL: bb.2:
# CHECK: S_SETREG # GCN: S_SETREG
# CHECK: S_NOP 0 # GCN: S_NOP 0
# CHECK: S_GETREG # GCN: S_GETREG
# CHECK-LABEL: bb.3: # GCN-LABEL: bb.3:
# CHECK: S_SETREG # GCN: S_SETREG
# CHECK-NEXT: S_GETREG # GCN-NEXT: S_GETREG
name: s_getreg name: s_getreg
body: | body: |
bb.0: bb.0:
successors: %bb.1 successors: %bb.1
S_SETREG_B32 %sgpr0, 1 S_SETREG_B32 %sgpr0, 1
%sgpr1 = S_GETREG_B32 1 %sgpr1 = S_GETREG_B32 1
Show All 12 Lines bb.2:
%sgpr2 = S_GETREG_B32 1 %sgpr2 = S_GETREG_B32 1
S_BRANCH %bb.3 S_BRANCH %bb.3
bb.3: bb.3:
S_SETREG_B32 %sgpr0, 0 S_SETREG_B32 %sgpr0, 0
%sgpr1 = S_GETREG_B32 1 %sgpr1 = S_GETREG_B32 1
S_ENDPGM S_ENDPGM
... ...
...
---
# GCN-LABEL: name: s_setreg
# GCN-LABEL: bb.0:
# GCN: S_SETREG
# GCN: S_NOP 0
# VI: S_NOP 0
# GCN-NEXT: S_SETREG
# GCN-LABEL: bb.1:
# GCN: S_SETREG
# GCN: S_NOP 0
# VI: S_NOP 0
# GCN-NEXT: S_SETREG
# GCN-LABEL: bb.2:
# GCN: S_SETREG
# GCN: S_SETREG
nhaehnleUnsubmitted
Not Done
ReplyInline Actions

GCN-NEXT?

nhaehnle: GCN-NEXT?
name: s_setreg
body: |
bb.0:
successors: %bb.1
S_SETREG_B32 %sgpr0, 1
S_SETREG_B32 %sgpr1, 1
S_BRANCH %bb.1
bb.1:
successors: %bb.2
S_SETREG_B32 %sgpr0, 64
S_SETREG_B32 %sgpr1, 128
S_BRANCH %bb.2
bb.2:
S_SETREG_B32 %sgpr0, 1
S_SETREG_B32 %sgpr1, 0
S_ENDPGM
...