AMDGPU: Assume spilling will occur at -O0

[arsenm]

Summary

Because everything live is spilled at the end of a
block by fast regalloc, assume this will happen and
avoid the copies of the resource descriptor.

[• tstellarAMD]

LGTM.

[arsenm]

r284119

lib/Target/AMDGPU/SIISelLowering.cpp

SDValue SITargetLowering::LowerFormalArguments(
   // Now that we've figured out where the scratch register inputs are, see if
   // should reserve the arguments and use them directly.
   bool HasStackObjects = MF.getFrameInfo().hasStackObjects();
   // Record that we know we have non-spill stack objects so we don't need to
   // check all stack objects later.
   if (HasStackObjects)
     Info->setHasNonSpillStackObjects(true);
 
+  // Everything live out of a block is spilled with fast regalloc, so it's
+  // almost certain that spilling will be required.
+  if (getTargetMachine().getOptLevel() == CodeGenOpt::None)
+    HasStackObjects = true;
+
   if (ST.isAmdCodeObjectV2()) {
-    // TODO: Assume we will spill without optimizations.
     if (HasStackObjects) {
       // If we have stack objects, we unquestionably need the private buffer
       // resource. For the Code Object V2 ABI, this will be the first 4 user
       // SGPR inputs. We can reserve those and use them directly.
 
       unsigned PrivateSegmentBufferReg = TRI->getPreloadedValue(
         MF, SIRegisterInfo::PRIVATE_SEGMENT_BUFFER);
       Info->setScratchRSrcReg(PrivateSegmentBufferReg);

test/CodeGen/AMDGPU/private-access-no-objects.ll

+; RUN: llc -O0 -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=OPTNONE %s
+
+; GCN-LABEL: {{^}}store_to_undef:
+
+; -O0 should assume spilling, so the input scratch resource descriptor
+; -should be used directly without any copies.
+
+; OPTNONE-NOT: s_mov_b32
+; OPTNONE: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[0:3], s7 offen{{$}}
+define void @store_to_undef() #0 {
+  store volatile i32 0, i32* undef
+  ret void
+}
+
+; GCN-LABEL: {{^}}store_to_inttoptr:
+define void @store_to_inttoptr() #0 {
+ store volatile i32 0, i32* inttoptr (i32 123 to i32*)
+ ret void
+}
+
+; GCN-LABEL: {{^}}load_from_undef:
+define void @load_from_undef() #0 {
+  %ld = load volatile i32, i32* undef
+  ret void
+}
+
+; GCN-LABEL: {{^}}load_from_inttoptr:
+define void @load_from_inttoptr() #0 {
+  %ld = load volatile i32, i32* inttoptr (i32 123 to i32*)
+  ret void
+}
+
+attributes #0 = { nounwind }

test/CodeGen/AMDGPU/spill-m0.ll

 ; TOVGPR: v_writelane_b32 [[SPILL_VREG:v[0-9]+]], vcc_hi, 0
 
 ; TOVMEM: v_mov_b32_e32 [[SPILL_VREG:v[0-9]+]], m0
 ; TOVMEM: buffer_store_dword [[SPILL_VREG]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} ; 4-byte Folded Spill
 ; TOVMEM: s_waitcnt vmcnt(0)
 
 ; TOSMEM: s_mov_b32 vcc_hi, m0
 ; TOSMEM-NOT: vcc_hi
-; TOSMEM: s_buffer_store_dword vcc_hi, s[84:87], s89 ; 4-byte Folded Spill
+; TOSMEM: s_buffer_store_dword vcc_hi, s[84:87], s3 ; 4-byte Folded Spill
 ; TOSMEM: s_waitcnt lgkmcnt(0)
 
 ; GCN: s_cbranch_scc1 [[ENDIF:BB[0-9]+_[0-9]+]]
 
 ; GCN: [[ENDIF]]:
 ; TOVGPR: v_readlane_b32 vcc_hi, [[SPILL_VREG]], 0
 ; TOVGPR: s_mov_b32 m0, vcc_hi
 
 ; TOVMEM: buffer_load_dword [[RELOAD_VREG:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} ; 4-byte Folded Reload
 ; TOVMEM: s_waitcnt vmcnt(0)
 ; TOVMEM: v_readfirstlane_b32 vcc_hi, [[RELOAD_VREG]]
 ; TOVMEM: s_mov_b32 m0, vcc_hi
 
-; TOSMEM: s_buffer_load_dword vcc_hi, s[84:87], s89 ; 4-byte Folded Reload
+; TOSMEM: s_buffer_load_dword vcc_hi, s[84:87], s3 ; 4-byte Folded Reload
 ; TOSMEM-NOT: vcc_hi
 ; TOSMEM: s_mov_b32 m0, vcc_hi
 
 ; GCN: s_add_i32 m0, m0, 1
 define void @spill_m0(i32 %cond, i32 addrspace(1)* %out) #0 {
 entry:
   %m0 = call i32 asm sideeffect "s_mov_b32 m0, 0", "={M0}"() #0
   %cmp0 = icmp eq i32 %cond, 0