[ARM] Fix registers clobbered by SjLj EH on soft-float targets

[olista01]

Summary

Currently, the Int_eh_sjlj_dispatchsetup intrinsic is marked as
clobbering all registers, including floating-point registers that may
not be present on the target. This is technically true, as we could get
linked against code that does use the FP registers, but that will not
actually work, as the soft-float code cannot save and restore the FP
registers. SjLj exception handling can only work correctly if either all
or none of the code is built for a target with FP registers. Therefore,
we can assume that, when Int_eh_sjlj_dispatchsetup is compiled for a
soft-float target, it is only going to be linked against other
soft-float code, and so only clobbers the general-purpose registers.
This allows us to check that no non-savable registers are clobbered when
generating the prologue/epilogue.

[t.p.northover]

Thanks Oliver. I think this looks reasonable.

llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h

public:
   /// Code Generation virtual methods...
   const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
   const MCPhysReg *
   getCalleeSavedRegsViaCopy(const MachineFunction *MF) const;
   const uint32_t *getCallPreservedMask(const MachineFunction &MF,
                                        CallingConv::ID) const override;
   const uint32_t *getNoPreservedMask() const override;
   const uint32_t *getTLSCallPreservedMask(const MachineFunction &MF) const;
+  const uint32_t *getSjLjDispatchPreservedMask(const MachineFunction &MF) const;
 
   /// getThisReturnPreservedMask - Returns a call preserved mask specific to the
   /// case that 'returned' is on an i32 first argument if the calling convention
   /// is one that can (partially) model this attribute with a preserved mask
   /// (i.e. it is a calling convention that uses the same register for the first
   /// i32 argument and an i32 return value)
   ///
   /// Should return NULL in the case that the calling convention does not have

llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp

 
 const uint32_t *
 ARMBaseRegisterInfo::getTLSCallPreservedMask(const MachineFunction &MF) const {
   assert(MF.getSubtarget<ARMSubtarget>().isTargetDarwin() &&
          "only know about special TLS call on Darwin");
   return CSR_iOS_TLSCall_RegMask;
 }
 
+const uint32_t *
+ARMBaseRegisterInfo::getSjLjDispatchPreservedMask(const MachineFunction &MF) const {
+  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
+  if (!STI.useSoftFloat() && STI.hasVFP2() && !STI.isThumb1Only())
+    return CSR_NoRegs_RegMask;
+  else
+    return CSR_FPRegs_RegMask;
+}
+
 
 const uint32_t *
 ARMBaseRegisterInfo::getThisReturnPreservedMask(const MachineFunction &MF,
                                                 CallingConv::ID CC) const {
   const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
   // This should return a register mask that is the same as that returned by
   // getCallPreservedMask but that additionally preserves the register used for
   // the first i32 argument (which must also be the register used to return a

llvm/trunk/lib/Target/ARM/ARMCallingConv.td

def RetCC_ARM_AAPCS_VFP : CallingConv<[
   CCDelegateTo<RetCC_ARM_AAPCS_Common>
 ]>;
 
 //===----------------------------------------------------------------------===//
 // Callee-saved register lists.
 //===----------------------------------------------------------------------===//
 
 def CSR_NoRegs : CalleeSavedRegs<(add)>;
+def CSR_FPRegs : CalleeSavedRegs<(add (sequence "D%u", 0, 31))>;
 
 def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4,
                                      (sequence "D%u", 15, 8))>;
 
 // The order of callee-saved registers needs to match the order we actually push
 // them in FrameLowering, because this order is what's used by
 // PrologEpilogInserter to allocate frame index slots. So when R7 is the frame
 // pointer, we use this AAPCS alternative.

llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

void ARMTargetLowering::EmitSjLjDispatchBlock(MachineInstr &MI,
 
   MachineInstrBuilder MIB;
   MIB = BuildMI(DispatchBB, dl, TII->get(ARM::Int_eh_sjlj_dispatchsetup));
 
   const ARMBaseInstrInfo *AII = static_cast<const ARMBaseInstrInfo*>(TII);
   const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
 
   // Add a register mask with no preserved registers.  This results in all
-  // registers being marked as clobbered.
-  MIB.addRegMask(RI.getNoPreservedMask());
+  // registers being marked as clobbered. This can't work if the dispatch block
+  // is in a Thumb1 function and is linked with ARM code which uses the FP
+  // registers, as there is no way to preserve the FP registers in Thumb1 mode.
+  MIB.addRegMask(RI.getSjLjDispatchPreservedMask(*MF));
 
   bool IsPositionIndependent = isPositionIndependent();
   unsigned NumLPads = LPadList.size();
   if (Subtarget->isThumb2()) {
     unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
     AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2LDRi12), NewVReg1)
                    .addFrameIndex(FI)
                    .addImm(4)

llvm/trunk/test/CodeGen/ARM/eh-dispcont.ll

-; RUN: llc -mtriple armv7-apple-ios -relocation-model=pic -o - %s | FileCheck %s -check-prefix=ARM-PIC
-; RUN: llc -mtriple armv7-apple-ios -relocation-model=static -o - %s | FileCheck %s -check-prefix=ARM-NOPIC
-; RUN: llc -mtriple armv7-apple-ios -relocation-model=dynamic-no-pic -o - %s | FileCheck %s -check-prefix=ARM-NOPIC
-; RUN: llc -mtriple thumbv6-apple-ios -relocation-model=pic -o - %s | FileCheck %s -check-prefix=THUMB1-PIC
-; RUN: llc -mtriple thumbv6-apple-ios -relocation-model=static -o - %s | FileCheck %s -check-prefix=THUMB1-NOPIC
-; RUN: llc -mtriple thumbv6-apple-ios -relocation-model=dynamic-no-pic -o - %s | FileCheck %s -check-prefix=THUMB1-NOPIC
+; RUN: llc -mtriple armv7-apple-ios -relocation-model=pic -o - %s | FileCheck %s -check-prefix=ARM-PIC -check-prefix=ARM
+; RUN: llc -mtriple armv7-apple-ios -relocation-model=static -o - %s | FileCheck %s -check-prefix=ARM-NOPIC -check-prefix=ARM
+; RUN: llc -mtriple armv7-apple-ios -relocation-model=dynamic-no-pic -o - %s | FileCheck %s -check-prefix=ARM-NOPIC -check-prefix=ARM
+; RUN: llc -mtriple thumbv6-apple-ios -relocation-model=pic -o - %s | FileCheck %s -check-prefix=THUMB1-PIC -check-prefix=THUMB1
+; RUN: llc -mtriple thumbv6-apple-ios -relocation-model=static -o - %s | FileCheck %s -check-prefix=THUMB1-NOPIC -check-prefix=THUMB1
+; RUN: llc -mtriple thumbv6-apple-ios -relocation-model=dynamic-no-pic -o - %s | FileCheck %s -check-prefix=THUMB1-NOPIC -check-prefix=THUMB1
 
 @_ZTIi = external constant i8*
 
 define i32 @main() #0 personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*) {
 entry:
   %exception = tail call i8* @__cxa_allocate_exception(i32 4) #1
   %0 = bitcast i8* %exception to i32*
   store i32 1, i32* %0, align 4

 declare void @__cxa_end_catch()
 
 declare i32 @__gxx_personality_sj0(...)
 
 attributes #0 = { ssp }
 attributes #1 = { nounwind }
 attributes #2 = { noreturn }
 
+; ARM: vst1.64
+; ARM: vst1.64
+
 ; ARM-PIC: cxa_throw
 ; ARM-PIC: trap
 ; ARM-PIC: adr [[REG1:r[0-9]+]], [[LJTI:.*]]
 ; ARM-PIC: ldr [[REG0:r[0-9]+]], [r{{[0-9]+}}, [[REG1]]]
 ; ARM-PIC: add pc, [[REG0]], [[REG1]]
 ; ARM-PIC: [[LJTI]]
 ; ARM-PIC: .data_region jt32
 ; ARM-PIC: .long [[LABEL:LBB0_[0-9]]]-[[LJTI]]
 ; ARM-PIC: .end_data_region
 ; ARM-PIC: [[LABEL]]
 
 ; ARM-NOPIC: cxa_throw
 ; ARM-NOPIC: trap
 ; ARM-NOPIC: adr [[REG1:r[0-9]+]], [[LJTI:.*]]
 ; ARM-NOPIC: ldr [[REG0:r[0-9]+]], [r{{[0-9]+}}, [[REG1]]]
 ; ARM-NOPIC: mov pc, [[REG0]]
 ; ARM-NOPIC: [[LJTI]]
 ; ARM-NOPIC: .data_region jt32
 ; ARM-NOPIC: .long [[LABEL:LBB0_[0-9]]]
 ; ARM-NOPIC: .end_data_region
 ; ARM-NOPIC: [[LABEL]]
 
+; ARM: vld1.64
+; ARM: vld1.64
+
+; On Thumb1 targets, we have no way to preserve the floating-point registers.
+; If all other code is built for Thumb1 or is built soft-float, this is not a
+; problem as the FP regs don't need saving. However, if this code is linked
+; against ARM code that uses the FP regs, they won't be restored correctly. We
+; don't support this use-case, but have no way to prevent it in the compiler.
+
+; THUMB1: push {{[^d]*$}}
+; THUMB1-NOT: vst
+
 ; THUMB1-PIC: cxa_throw
 ; THUMB1-PIC: trap
 ; THUMB1-PIC: adr [[REG1:r[0-9]+]], [[LJTI:.*]]
 ; THUMB1-PIC: adds [[REG0:r[0-9]+]], [[REG0]], [[REG1]]
 ; THUMB1-PIC: ldr [[REG0]]
 ; THUMB1-PIC: adds [[REG0]], [[REG0]], [[REG1]]
 ; THUMB1-PIC: mov pc, [[REG0]]
 ; THUMB1-PIC: [[LJTI]]
 ; THUMB1-PIC: .data_region jt32
 ; THUMB1-PIC: .long [[LABEL:LBB0_[0-9]]]-[[LJTI]]
 ; THUMB1-PIC: .end_data_region
 ; THUMB1-PIC: [[LABEL]]
 
 ; THUMB1-NOPIC: cxa_throw
 ; THUMB1-NOPIC: trap
 ; THUMB1-NOPIC: adr [[REG1:r[0-9]+]], [[LJTI:.*]]
 ; THUMB1-NOPIC: adds [[REG0:r[0-9]+]], [[REG0]], [[REG1]]
 ; THUMB1-NOPIC: ldr [[REG0]]
 ; THUMB1-NOPIC: mov pc, [[REG0]]
 ; THUMB1-NOPIC: [[LJTI]]
 ; THUMB1-NOPIC: .data_region jt32
 ; THUMB1-NOPIC: .long [[LABEL:LBB0_[0-9]]]+1
 ; THUMB1-NOPIC: .end_data_region
 ; THUMB1-NOPIC: [[LABEL]]
+
+; THUMB1-NOT: vld
+; THUMB1: pop {{[^d]*$}}