[AMDGPU] Sign extend AShr when promoting (instead of zero extending)

[kzhuravl]

Upload correct diff

[• tstellarAMD]

LGTM.

[kzhuravl]

r283130

lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp

bool AMDGPUCodeGenPrepare::isI32Ty(const Type *T) const {
   if (T->isIntegerTy(32))
     return true;
   if (!T->isVectorTy())
     return false;
   return cast<VectorType>(T)->getElementType()->isIntegerTy(32);
 }
 
 bool AMDGPUCodeGenPrepare::isSigned(const BinaryOperator &I) const {
-  return I.getOpcode() == Instruction::SDiv ||
-      I.getOpcode() == Instruction::SRem;
+  return I.getOpcode() == Instruction::AShr ||
+      I.getOpcode() == Instruction::SDiv || I.getOpcode() == Instruction::SRem;
 }
 
 bool AMDGPUCodeGenPrepare::isSigned(const SelectInst &I) const {
   return isa<ICmpInst>(I.getOperand(0)) ?
       cast<ICmpInst>(I.getOperand(0))->isSigned() : false;
 }
 
 bool AMDGPUCodeGenPrepare::promoteUniformI16OpToI32(BinaryOperator &I) const {

test/CodeGen/AMDGPU/amdgpu-codegenprepare-i16-to-i32.ll

 define i16 @lshr_exact_i16(i16 %a, i16 %b) {
   %r = lshr exact i16 %a, %b
   ret i16 %r
 }
 
 ; GCN-LABEL: @ashr_i16(
 ; SI: %r = ashr i16 %a, %b
 ; SI-NEXT: ret i16 %r
-; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32
-; VI-NEXT: %[[B_32:[0-9]+]] = zext i16 %b to i32
+; VI: %[[A_32:[0-9]+]] = sext i16 %a to i32
+; VI-NEXT: %[[B_32:[0-9]+]] = sext i16 %b to i32
 ; VI-NEXT: %[[R_32:[0-9]+]] = ashr i32 %[[A_32]], %[[B_32]]
 ; VI-NEXT: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16
 ; VI-NEXT: ret i16 %[[R_16]]
 define i16 @ashr_i16(i16 %a, i16 %b) {
   %r = ashr i16 %a, %b
   ret i16 %r
 }
 
 ; GCN-LABEL: @ashr_exact_i16(
 ; SI: %r = ashr exact i16 %a, %b
 ; SI-NEXT: ret i16 %r
-; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32
-; VI-NEXT: %[[B_32:[0-9]+]] = zext i16 %b to i32
+; VI: %[[A_32:[0-9]+]] = sext i16 %a to i32
+; VI-NEXT: %[[B_32:[0-9]+]] = sext i16 %b to i32
 ; VI-NEXT: %[[R_32:[0-9]+]] = ashr exact i32 %[[A_32]], %[[B_32]]
 ; VI-NEXT: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16
 ; VI-NEXT: ret i16 %[[R_16]]
 define i16 @ashr_exact_i16(i16 %a, i16 %b) {
   %r = ashr exact i16 %a, %b
   ret i16 %r
 }
 

 define <3 x i16> @lshr_exact_3xi16(<3 x i16> %a, <3 x i16> %b) {
   %r = lshr exact <3 x i16> %a, %b
   ret <3 x i16> %r
 }
 
 ; GCN-LABEL: @ashr_3xi16(
 ; SI: %r = ashr <3 x i16> %a, %b
 ; SI-NEXT: ret <3 x i16> %r
-; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32>
-; VI-NEXT: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32>
+; VI: %[[A_32:[0-9]+]] = sext <3 x i16> %a to <3 x i32>
+; VI-NEXT: %[[B_32:[0-9]+]] = sext <3 x i16> %b to <3 x i32>
 ; VI-NEXT: %[[R_32:[0-9]+]] = ashr <3 x i32> %[[A_32]], %[[B_32]]
 ; VI-NEXT: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16>
 ; VI-NEXT: ret <3 x i16> %[[R_16]]
 define <3 x i16> @ashr_3xi16(<3 x i16> %a, <3 x i16> %b) {
   %r = ashr <3 x i16> %a, %b
   ret <3 x i16> %r
 }
 
 ; GCN-LABEL: @ashr_exact_3xi16(
 ; SI: %r = ashr exact <3 x i16> %a, %b
 ; SI-NEXT: ret <3 x i16> %r
-; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32>
-; VI-NEXT: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32>
+; VI: %[[A_32:[0-9]+]] = sext <3 x i16> %a to <3 x i32>
+; VI-NEXT: %[[B_32:[0-9]+]] = sext <3 x i16> %b to <3 x i32>
 ; VI-NEXT: %[[R_32:[0-9]+]] = ashr exact <3 x i32> %[[A_32]], %[[B_32]]
 ; VI-NEXT: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16>
 ; VI-NEXT: ret <3 x i16> %[[R_16]]
 define <3 x i16> @ashr_exact_3xi16(<3 x i16> %a, <3 x i16> %b) {
   %r = ashr exact <3 x i16> %a, %b
   ret <3 x i16> %r
 }