[AArch64] Support 16 bit FP in inline asm register selection

[fhahn]

Summary

This patch adds support for 16 bit floating point registers to the inline asm register selection on AArch64.

Without this patch, register allocation for the example below fails.

define half @test(half %a1, half %a2) #0 {
entry:
  %0 = tail call half asm "sqrshl ${0:h}, ${1:h}, ${2:h}", "=w,w,w" (half %a1, half %a2) #1
  ret half %0
}

[fhahn]

Made a cosmetic change to the test case. It would be great if somebody could have a look.

[jmolloy]

Looks trivially correct to me. Sorry for not spotting this one fly by before.

LGTM.

[fhahn]

As I do not have commit privileges it would be great if somebody could commit this patch (already marked as ready to land). Thank you very much.

[fhahn]

Ping. This patch is accepted already and it would be great if somebody could commit it (I do not have commit privileges).

llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp

AArch64TargetLowering::getRegForInlineAsmConstraint(
     const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
   if (Constraint.size() == 1) {
     switch (Constraint[0]) {
     case 'r':
       if (VT.getSizeInBits() == 64)
         return std::make_pair(0U, &AArch64::GPR64commonRegClass);
       return std::make_pair(0U, &AArch64::GPR32commonRegClass);
     case 'w':
+      if (VT.getSizeInBits() == 16)
+        return std::make_pair(0U, &AArch64::FPR16RegClass);
       if (VT.getSizeInBits() == 32)
         return std::make_pair(0U, &AArch64::FPR32RegClass);
       if (VT.getSizeInBits() == 64)
         return std::make_pair(0U, &AArch64::FPR64RegClass);
       if (VT.getSizeInBits() == 128)
         return std::make_pair(0U, &AArch64::FPR128RegClass);
       break;
     // The instructions that this constraint is designed for can

llvm/trunk/test/CodeGen/AArch64/neon-inline-asm-16-bit-fp.ll

+; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
+
+; generated from
+; __fp16 test(__fp16 a1, __fp16 a2) {
+;    __fp16 res0;
+;    __asm__("sqrshl %h[__res], %h[__A], %h[__B]"
+;             : [__res] "=w" (res0)
+;             : [__A] "w" (a1), [__B] "w" (a2)
+;             :
+;             );
+;    return res0;
+;}
+
+; Function Attrs: nounwind readnone
+define half @test(half %a1, half %a2) #0 {
+entry:
+  ;CHECK: sqrshl {{h[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
+  %0 = tail call half asm "sqrshl ${0:h}, ${1:h}, ${2:h}", "=w,w,w" (half %a1, half %a2) #1
+  ret half %0
+}