[RFC] Inverse SQRT on ARM(do not merge)

[jojo]

Summary

Draft patch for this. As a preparation for the upcoming benchmarking,
It's ok just be able to emit.
And after that,we will give a final design.

[jojo]

update diff

[jmolloy]

Hi Jojo,

As you're updating the diff, can you confirm that you don't want review at this point?

Cheers,

James

[jojo]

Hi James,

Thanks very much!

I updated the diff as I did some tests basing on this diff. And I'm going to add comments
to the bug(bug 27107).
As I mentioned in the mail, I think this diff shouldn't be the final design for inverse sqrt
problem,but It would be ok just emitting rsqrt for upcoming benchmarking.
But even though, I'm not sure it's right. Especially I tried to support operations in f32 in
the diff.
If you could give me some advice, it would be very appreciated. : )

Regards,
Jojo

In D24911#556756, @jmolloy wrote:

Hi Jojo,

As you're updating the diff, can you confirm that you don't want review at this point?

Cheers,

James

[evandro]

Do you intend to use the VRSQRTS to perform the series steps?

lib/Target/ARM/ARMTargetMachine.cpp

33

No need to capitalize each initial.

lib/Target/ARM/ARMISelLowering.h

       VMULLs,       // ...signed
       VMULLu,       // ...unsigned
 
+      // Reciprocal estimates.
+      VRSQRTE,
+
       UMLAL,        // 64bit Unsigned Accumulate Multiply
       SMLAL,        // 64bit Signed Accumulate Multiply
       UMAAL,        // 64-bit Unsigned Accumulate Accumulate Multiply

                                        APInt &KnownOne,
                                        const SelectionDAG &DAG,
                                        unsigned Depth) const override;
-
+  SDValue getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI,
+                           unsigned &RefinementSteps,
+                           bool &UseOneConstNR) const override;
 
     bool ExpandInlineAsm(CallInst *CI) const override;
 

lib/Target/ARM/ARMISelLowering.cpp

   case ARMISD::VTBL2:         return "ARMISD::VTBL2";
   case ARMISD::VMULLs:        return "ARMISD::VMULLs";
   case ARMISD::VMULLu:        return "ARMISD::VMULLu";
+  case ARMISD::VRSQRTE:       return "ARMISD::VRSQRTE";
   case ARMISD::UMAAL:         return "ARMISD::UMAAL";
   case ARMISD::UMLAL:         return "ARMISD::UMLAL";
   case ARMISD::SMLAL:         return "ARMISD::SMLAL";

   }
 }
 
+/// getEstimate - Return the appropriate estimate DAG for either the reciprocal
+/// or the reciprocal square root.
+static SDValue getEstimate(const ARMSubtarget &ST,
+  const ARMTargetLowering::DAGCombinerInfo &DCI, unsigned Opcode,
+  const SDValue &Operand, unsigned &ExtraSteps) {
+  if (!ST.hasNEON())
+    return SDValue();
+
+  EVT VT = Operand.getValueType();
+
+  std::string RecipOp;
+  RecipOp = "sqrt";
+  RecipOp = ((VT.isVector()) ? "vec-": "") + RecipOp;
+
+ if (VT == MVT::f32 || VT == MVT::v2f32 || VT == MVT::v4f32)
+     RecipOp += "f";
+ else
+    return SDValue();
+
+  TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
+  if (!Recips.isEnabled(RecipOp))
+    return SDValue();
+
+  ExtraSteps = Recips.getRefinementSteps(RecipOp);
+  return DCI.DAG.getNode(Opcode, SDLoc(Operand), VT, Operand);
+}
+
+SDValue ARMTargetLowering::getRsqrtEstimate(SDValue Operand,
+  DAGCombinerInfo &DCI, unsigned &ExtraSteps, bool &UseOneConst) const {
+  UseOneConst = true;
+  return getEstimate(*Subtarget, DCI, ARMISD::VRSQRTE, Operand, ExtraSteps);
+}
+
 //===----------------------------------------------------------------------===//
 //                           ARM Inline Assembly Support
 //===----------------------------------------------------------------------===//

lib/Target/ARM/ARMInstrNEON.td

 def NEONvcltz     : SDNode<"ARMISD::VCLTZ", SDTARMVCMPZ>;
 def NEONvcgtu     : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
 def NEONvtst      : SDNode<"ARMISD::VTST", SDTARMVCMP>;
+def NEONfrsqrte   : SDNode<"ARMISD::VRSQRTE", SDTFPUnaryOp>;
 
 // Types for vector shift by immediates.  The "SHX" version is for long and
 // narrow operations where the source and destination vectors have different

                          v8f16, v8f16, int_arm_neon_vrsqrte>,
                 Requires<[HasNEON, HasFullFP16]>;
 
+def   : Pat<(NEONfrsqrte SPR:$Vm),
+            (EXTRACT_SUBREG (VRSQRTEfd (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$Vm, ssub_0)), ssub_0)>;
+def   : Pat<(v2f32 (NEONfrsqrte (v2f32 DPR:$Vm))),
+             (VRSQRTEfd  DPR:$Vm)>;
+def   : Pat<(v4f32 (NEONfrsqrte (v4f32 QPR:$Vm))),
+             (VRSQRTEfq  QPR:$Vm)>;
+
 //   VRSQRTS  : Vector Reciprocal Square Root Step
 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
                         IIC_VRECSD, "vrsqrts", "f32",

lib/Target/ARM/ARMTargetMachine.cpp

 using namespace llvm;
 
 static cl::opt<bool>
+EnableReciprocalSquareRoot("enable-reciprocal-square-root", cl::Hidden,
+                   cl::desc("Enable Reciprocal Square Root Optimisation"),
+                   cl::init(false));
+
+static cl::opt<bool>
 DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden,
                    cl::desc("Inhibit optimization of S->D register accesses on A15"),
                    cl::init(false));

   return *RM;
 }
 
+ // Helper function to set up the defaults for reciprocals.
+ static void initReciprocals(ARMTargetMachine& TM)
+ {
+   bool useRsqrt = EnableReciprocalSquareRoot;
+ 
+   TM.Options.Reciprocals.setDefaults("sqrtf", useRsqrt, 2);
+   TM.Options.Reciprocals.setDefaults("sqrtd", useRsqrt, 4);
+   TM.Options.Reciprocals.setDefaults("vec-sqrtf", useRsqrt, 2);
+   TM.Options.Reciprocals.setDefaults("vec-sqrtd", useRsqrt, 4);
+ }
+
 /// Create an ARM architecture model.
 ///
 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT,

                                    CodeModel::Model CM, CodeGenOpt::Level OL,
                                    bool isLittle)
     : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, isLittle) {
+  initReciprocals(*this);
   initAsmInfo();
   if (!Subtarget.hasARMOps())
     report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "