AMDGPU: Remove scheduling info from si_mask_branch

[nhaehnle]

Isn't hasNoSchedulingInfo = 0 the default setting?

[arsenm]

In D24684#545603, @nhaehnle wrote:

Isn't hasNoSchedulingInfo = 0 the default setting?

Yes, but SchedRW is inherited from PseudoInstSI as Write32

[nhaehnle]

Yes, the SchedRW part I agree with, but why the hasNoSchedulingInfo? Is there some additional interaction? FWIW, the change itself looks fine to me apart from that.

[arsenm]

In D24684#545999, @nhaehnle wrote:

Yes, the SchedRW part I agree with, but why the hasNoSchedulingInfo? Is there some additional interaction? FWIW, the change itself looks fine to me apart from that.

I thought this was supposed to produce an error when the scheduling model is supposed to be complete. I'm not sure why this isn't actually erroring without it

[arsenm]

Set bit in right direction

[nhaehnle]

LGTM

[arsenm]

r283475

lib/Target/AMDGPU/SIInstructions.td

 // replaced with exec mask operations.
 def SI_MASK_BRANCH : PseudoInstSI <
   (outs), (ins brtarget:$target)> {
   let isBranch = 0;
   let isTerminator = 1;
   let isBarrier = 0;
   let SALU = 1;
   let Uses = [EXEC];
+  let SchedRW = [];
+  let hasNoSchedulingInfo = 1;
 }
 
 let isTerminator = 1 in {
 
 def SI_IF: CFPseudoInstSI <
   (outs SReg_64:$dst), (ins SReg_64:$vcc, brtarget:$target),
   [(set i64:$dst, (int_amdgcn_if i1:$vcc, bb:$target))], 1, 1> {
   let Constraints = "";