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Differential D24499

[mips] Add rsqrt, recip for MIPS
ClosedPublic

Authored by sdardis on Sep 13 2016, 4:11 AM.

Details

Reviewers
vkalintiris
zoran.jovanovic
Summary

Add rsqrt.[ds], recip.[ds] for MIPS. Correct the microMIPS definitions for
architecture support and register usage.

Diff Detail

Event Timeline

sdardis updated this revision to Diff 71137.Sep 13 2016, 4:11 AM
sdardis retitled this revision from to [mips] Add rsqrt, recip for MIPS.
sdardis updated this object.
sdardis added reviewers: vkalintiris, zoran.jovanovic.
sdardis set the repository for this revision to rL LLVM.
sdardis added a subscriber: llvm-commits.
Herald added a subscriber: sdardis. · View Herald TranscriptSep 13 2016, 4:11 AM
vkalintiris accepted this revision.Sep 21 2016, 5:29 AM
vkalintiris edited edge metadata.

LGTM.

This revision is now accepted and ready to land.Sep 21 2016, 5:29 AM
seanbruno added a subscriber: seanbruno.Sep 26 2016, 7:03 AM
sdardis closed this revision.Sep 27 2016, 5:35 AM

Thanks, committed rL282485.

Revision Contents

PathSize
lib/
Target/
Mips/
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test/
MC/
Disassembler/
Mips/
micromips32r3/
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mips32r2/
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mips32r3/
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mips32r5/
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mips32r6/
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mips4/
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mips64/
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mips64r2/
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mips64r3/
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mips64r5/
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mips64r6/
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Mips/
micromips/
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mips32r2/
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mips32r3/
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mips32r5/
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mips32r6/
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mips4/
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mips5/
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mips64/
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mips64r2/
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mips64r3/
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mips64r5/
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mips64r6/
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Diff 71137

lib/Target/Mips/MicroMips32r6InstrInfo.td

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class CEIL_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.s", 0, 0b01101100>; class CEIL_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.s", 0, 0b01101100>;
class CEIL_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.d", 1, 0b01101100>; class CEIL_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.d", 1, 0b01101100>;
class TRUNC_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.s", 0, 0b10001100>; class TRUNC_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.s", 0, 0b10001100>;
class TRUNC_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.d", 1, 0b10001100>; class TRUNC_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.d", 1, 0b10001100>;
class TRUNC_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.s", 0, 0b10101100>; class TRUNC_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.s", 0, 0b10101100>;
class TRUNC_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.d", 1, 0b10101100>; class TRUNC_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.d", 1, 0b10101100>;
class SQRT_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.s", 0, 0b00101000>; class SQRT_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.s", 0, 0b00101000>;
class SQRT_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.d", 1, 0b00101000>; class SQRT_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.d", 1, 0b00101000>;
class RSQRT_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"rsqrt.s", 0, 0b00001000>;
class RSQRT_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"rsqrt.d", 1, 0b00001000>;
class SB_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b000110>; class SB_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b000110>;
class SBE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b100>; class SBE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b100>;
class SCE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b110>; class SCE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b110>;
class SH_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b001110>; class SH_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b001110>;
class SHE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b101>; class SHE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b101>;
class LLE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b110>; class LLE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b110>;
class LWE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b111>; class LWE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b111>;
class LW_MMR6_ENC : LOAD_WORD_FM_MMR6; class LW_MMR6_ENC : LOAD_WORD_FM_MMR6;
class LUI_MMR6_ENC : LOAD_UPPER_IMM_FM_MMR6; class LUI_MMR6_ENC : LOAD_UPPER_IMM_FM_MMR6;
class JALRC_HB_MMR6_ENC : POOL32A_JALRC_FM_MMR6<"jalrc.hb", 0b0001111100>; class JALRC_HB_MMR6_ENC : POOL32A_JALRC_FM_MMR6<"jalrc.hb", 0b0001111100>;
class RECIP_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"recip.s", 0, 0b01001000>;
class RECIP_D_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"recip.d", 1, 0b01001000>;
class RINT_S_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.s", 0>; class RINT_S_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.s", 0>;
class RINT_D_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.d", 1>; class RINT_D_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.d", 1>;
class ROUND_L_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.l.s", 0, class ROUND_L_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.l.s", 0,
0b11001100>; 0b11001100>;
class ROUND_L_D_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.l.d", 1, class ROUND_L_D_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.l.d", 1,
0b11001100>; 0b11001100>;
class ROUND_W_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.w.s", 0, class ROUND_W_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.w.s", 0,
0b11101100>; 0b11101100>;
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class TRUNC_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.s", FGR32Opnd, class TRUNC_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.s", FGR32Opnd,
FGR32Opnd, II_TRUNC>; FGR32Opnd, II_TRUNC>;
class TRUNC_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.d", FGR32Opnd, class TRUNC_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.d", FGR32Opnd,
AFGR64Opnd, II_TRUNC>; AFGR64Opnd, II_TRUNC>;
class SQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.s", FGR32Opnd, FGR32Opnd, class SQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.s", FGR32Opnd, FGR32Opnd,
II_SQRT_S, fsqrt>; II_SQRT_S, fsqrt>;
class SQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.d", AFGR64Opnd, AFGR64Opnd, class SQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.d", AFGR64Opnd, AFGR64Opnd,
II_SQRT_D, fsqrt>; II_SQRT_D, fsqrt>;
class RSQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"rsqrt.s", FGR32Opnd,
FGR32Opnd, II_TRUNC>;
class RSQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"rsqrt.d", FGR32Opnd,
AFGR64Opnd, II_TRUNC>;
class RECIP_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"recip.s", FGR32Opnd,
FGR32Opnd, II_ROUND>;
class RECIP_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"recip.d", FGR32Opnd, FGR32Opnd,
II_ROUND>;
class ROUND_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.s", FGR64Opnd, class ROUND_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.s", FGR64Opnd,
FGR32Opnd, II_ROUND>; FGR32Opnd, II_ROUND>;
class ROUND_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.d", FGR64Opnd, class ROUND_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.d", FGR64Opnd,
FGR64Opnd, II_ROUND>; FGR64Opnd, II_ROUND>;
class ROUND_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.w.s", FGR32Opnd, class ROUND_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.w.s", FGR32Opnd,
FGR32Opnd, II_ROUND>; FGR32Opnd, II_ROUND>;
class ROUND_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.w.d", FGR64Opnd, class ROUND_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.w.d", FGR64Opnd,
FGR64Opnd, II_ROUND>; FGR64Opnd, II_ROUND>;
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def TRUNC_W_S_MMR6 : StdMMR6Rel, TRUNC_W_S_MMR6_ENC, TRUNC_W_S_MMR6_DESC, def TRUNC_W_S_MMR6 : StdMMR6Rel, TRUNC_W_S_MMR6_ENC, TRUNC_W_S_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def TRUNC_W_D_MMR6 : StdMMR6Rel, TRUNC_W_D_MMR6_ENC, TRUNC_W_D_MMR6_DESC, def TRUNC_W_D_MMR6 : StdMMR6Rel, TRUNC_W_D_MMR6_ENC, TRUNC_W_D_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def SQRT_S_MMR6 : StdMMR6Rel, SQRT_S_MMR6_ENC, SQRT_S_MMR6_DESC, def SQRT_S_MMR6 : StdMMR6Rel, SQRT_S_MMR6_ENC, SQRT_S_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def SQRT_D_MMR6 : StdMMR6Rel, SQRT_D_MMR6_ENC, SQRT_D_MMR6_DESC, def SQRT_D_MMR6 : StdMMR6Rel, SQRT_D_MMR6_ENC, SQRT_D_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def RSQRT_S_MMR6 : StdMMR6Rel, RSQRT_S_MMR6_ENC, RSQRT_S_MMR6_DESC,
ISA_MICROMIPS32R6;
def RSQRT_D_MMR6 : StdMMR6Rel, RSQRT_D_MMR6_ENC, RSQRT_D_MMR6_DESC,
ISA_MICROMIPS32R6;
def SB_MMR6 : StdMMR6Rel, SB_MMR6_DESC, SB_MMR6_ENC, ISA_MICROMIPS32R6; def SB_MMR6 : StdMMR6Rel, SB_MMR6_DESC, SB_MMR6_ENC, ISA_MICROMIPS32R6;
def SBE_MMR6 : StdMMR6Rel, SBE_MMR6_DESC, SBE_MMR6_ENC, ISA_MICROMIPS32R6; def SBE_MMR6 : StdMMR6Rel, SBE_MMR6_DESC, SBE_MMR6_ENC, ISA_MICROMIPS32R6;
def SCE_MMR6 : StdMMR6Rel, SCE_MMR6_DESC, SCE_MMR6_ENC, ISA_MICROMIPS32R6; def SCE_MMR6 : StdMMR6Rel, SCE_MMR6_DESC, SCE_MMR6_ENC, ISA_MICROMIPS32R6;
def SH_MMR6 : StdMMR6Rel, SH_MMR6_DESC, SH_MMR6_ENC, ISA_MICROMIPS32R6; def SH_MMR6 : StdMMR6Rel, SH_MMR6_DESC, SH_MMR6_ENC, ISA_MICROMIPS32R6;
def SHE_MMR6 : StdMMR6Rel, SHE_MMR6_DESC, SHE_MMR6_ENC, ISA_MICROMIPS32R6; def SHE_MMR6 : StdMMR6Rel, SHE_MMR6_DESC, SHE_MMR6_ENC, ISA_MICROMIPS32R6;
def LLE_MMR6 : StdMMR6Rel, LLE_MMR6_DESC, LLE_MMR6_ENC, ISA_MICROMIPS32R6; def LLE_MMR6 : StdMMR6Rel, LLE_MMR6_DESC, LLE_MMR6_ENC, ISA_MICROMIPS32R6;
def LWE_MMR6 : StdMMR6Rel, LWE_MMR6_DESC, LWE_MMR6_ENC, ISA_MICROMIPS32R6; def LWE_MMR6 : StdMMR6Rel, LWE_MMR6_DESC, LWE_MMR6_ENC, ISA_MICROMIPS32R6;
def LW_MMR6 : StdMMR6Rel, LW_MMR6_DESC, LW_MMR6_ENC, ISA_MICROMIPS32R6; def LW_MMR6 : StdMMR6Rel, LW_MMR6_DESC, LW_MMR6_ENC, ISA_MICROMIPS32R6;
Show All 24 Linesdef SUBU16_MMR6 : StdMMR6Rel, SUBU16_MMR6_DESC, SUBU16_MMR6_ENC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def XOR16_MMR6 : StdMMR6Rel, XOR16_MMR6_DESC, XOR16_MMR6_ENC, def XOR16_MMR6 : StdMMR6Rel, XOR16_MMR6_DESC, XOR16_MMR6_ENC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def JALRC_HB_MMR6 : R6MMR6Rel, JALRC_HB_MMR6_ENC, JALRC_HB_MMR6_DESC, def JALRC_HB_MMR6 : R6MMR6Rel, JALRC_HB_MMR6_ENC, JALRC_HB_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def EXT_MMR6 : StdMMR6Rel, EXT_MMR6_ENC, EXT_MMR6_DESC, ISA_MICROMIPS32R6; def EXT_MMR6 : StdMMR6Rel, EXT_MMR6_ENC, EXT_MMR6_DESC, ISA_MICROMIPS32R6;
def INS_MMR6 : StdMMR6Rel, INS_MMR6_ENC, INS_MMR6_DESC, ISA_MICROMIPS32R6; def INS_MMR6 : StdMMR6Rel, INS_MMR6_ENC, INS_MMR6_DESC, ISA_MICROMIPS32R6;
def JALRC_MMR6 : R6MMR6Rel, JALRC_MMR6_ENC, JALRC_MMR6_DESC, ISA_MICROMIPS32R6; def JALRC_MMR6 : R6MMR6Rel, JALRC_MMR6_ENC, JALRC_MMR6_DESC, ISA_MICROMIPS32R6;
def RECIP_S_MMR6 : StdMMR6Rel, RECIP_S_MMR6_ENC, RECIP_S_MMR6_DESC,
ISA_MICROMIPS32R6;
def RECIP_D_MMR6 : StdMMR6Rel, RECIP_D_MMR6_ENC, RECIP_D_MMR6_DESC, ISA_MICROMIPS32R6;
def RINT_S_MMR6 : StdMMR6Rel, RINT_S_MMR6_ENC, RINT_S_MMR6_DESC, def RINT_S_MMR6 : StdMMR6Rel, RINT_S_MMR6_ENC, RINT_S_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def RINT_D_MMR6 : StdMMR6Rel, RINT_D_MMR6_ENC, RINT_D_MMR6_DESC, ISA_MICROMIPS32R6; def RINT_D_MMR6 : StdMMR6Rel, RINT_D_MMR6_ENC, RINT_D_MMR6_DESC, ISA_MICROMIPS32R6;
def ROUND_L_S_MMR6 : StdMMR6Rel, ROUND_L_S_MMR6_ENC, ROUND_L_S_MMR6_DESC, def ROUND_L_S_MMR6 : StdMMR6Rel, ROUND_L_S_MMR6_ENC, ROUND_L_S_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def ROUND_L_D_MMR6 : StdMMR6Rel, ROUND_L_D_MMR6_ENC, ROUND_L_D_MMR6_DESC, def ROUND_L_D_MMR6 : StdMMR6Rel, ROUND_L_D_MMR6_ENC, ROUND_L_D_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def ROUND_W_S_MMR6 : StdMMR6Rel, ROUND_W_S_MMR6_ENC, ROUND_W_S_MMR6_DESC, def ROUND_W_S_MMR6 : StdMMR6Rel, ROUND_W_S_MMR6_ENC, ROUND_W_S_MMR6_DESC,
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lib/Target/Mips/MicroMipsInstrFPU.td

Show First 20 Lines • Show All 135 Lines • ▼ Show 20 Lines def MTHC1_MM : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,
MFC1_FM_MM<0xe0>, ISA_MIPS32R2, FGR_32; MFC1_FM_MM<0xe0>, ISA_MIPS32R2, FGR_32;
def MFHC1_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>, def MFHC1_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>,
MFC1_FM_MM<0xc0>, ISA_MIPS32R2, FGR_32; MFC1_FM_MM<0xc0>, ISA_MIPS32R2, FGR_32;
let DecoderNamespace = "MicroMips" in { let DecoderNamespace = "MicroMips" in {
def CFC1_MM : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>, def CFC1_MM : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>,
MFC1_FM_MM<0x40>; MFC1_FM_MM<0x40>;
def CTC1_MM : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>, def CTC1_MM : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>,
MFC1_FM_MM<0x60>; MFC1_FM_MM<0x60>;
def RECIP_S_MM : MMRel, ABSS_FT<"recip.s", FGR32Opnd, FGR32Opnd,
II_RECIP_S>,
ROUND_W_FM_MM<0b0, 0b01001000>;
def RECIP_D_MM : MMRel, ABSS_FT<"recip.d", AFGR64Opnd, AFGR64Opnd,
II_RECIP_D>, ROUND_W_FM_MM<0b1, 0b01001000>;
def RSQRT_S_MM : MMRel, ABSS_FT<"rsqrt.s", FGR32Opnd, FGR32Opnd,
II_RECIP_S>,
ROUND_W_FM_MM<0b0, 0b00001000>;
def RSQRT_D_MM : MMRel, ABSS_FT<"rsqrt.d", AFGR64Opnd, AFGR64Opnd,
II_RECIP_D>, ROUND_W_FM_MM<0b1, 0b00001000>;
} }
let DecoderNamespace = "MicroMips", DecoderMethod = "DecodeFMemMMR2" in { let DecoderNamespace = "MicroMips", DecoderMethod = "DecodeFMemMMR2" in {
def LDC1_MM : MMRel, LW_FT<"ldc1", AFGR64Opnd, mem_mm_16, II_LDC1, load>, def LDC1_MM : MMRel, LW_FT<"ldc1", AFGR64Opnd, mem_mm_16, II_LDC1, load>,
LW_FM_MM<0x2f>, FGR_32 { LW_FM_MM<0x2f>, FGR_32 {
let BaseOpcode = "LDC132"; let BaseOpcode = "LDC132";
} }
def SDC1_MM : MMRel, SW_FT<"sdc1", AFGR64Opnd, mem_mm_16, II_SDC1, store>, def SDC1_MM : MMRel, SW_FT<"sdc1", AFGR64Opnd, mem_mm_16, II_SDC1, store>,
LW_FM_MM<0x2e>, FGR_32; LW_FM_MM<0x2e>, FGR_32;
Show All 19 Lines

lib/Target/Mips/MipsInstrFPU.td

Show First 20 Lines • Show All 278 Lines • ▼ Show 20 Lines
def CVT_W_S : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>, def CVT_W_S : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>,
ABSS_FM<0x24, 16>; ABSS_FM<0x24, 16>;
defm TRUNC_W : ROUND_M<"trunc.w.d", II_TRUNC>, ABSS_FM<0xd, 17>, ISA_MIPS2; defm TRUNC_W : ROUND_M<"trunc.w.d", II_TRUNC>, ABSS_FM<0xd, 17>, ISA_MIPS2;
defm CEIL_W : ROUND_M<"ceil.w.d", II_CEIL>, ABSS_FM<0xe, 17>, ISA_MIPS2; defm CEIL_W : ROUND_M<"ceil.w.d", II_CEIL>, ABSS_FM<0xe, 17>, ISA_MIPS2;
defm FLOOR_W : ROUND_M<"floor.w.d", II_FLOOR>, ABSS_FM<0xf, 17>, ISA_MIPS2; defm FLOOR_W : ROUND_M<"floor.w.d", II_FLOOR>, ABSS_FM<0xf, 17>, ISA_MIPS2;
defm CVT_W : ROUND_M<"cvt.w.d", II_CVT>, ABSS_FM<0x24, 17>; defm CVT_W : ROUND_M<"cvt.w.d", II_CVT>, ABSS_FM<0x24, 17>;
let AdditionalPredicates = [NotInMicroMips] in {
def RECIP_S : MMRel, ABSS_FT<"recip.s", FGR32Opnd, FGR32Opnd, II_RECIP_S>,
ABSS_FM<0b010101, 0x10>, INSN_MIPS4_32R2;
def RECIP_D : MMRel, ABSS_FT<"recip.d", FGR64Opnd, FGR64Opnd, II_RECIP_D>,
ABSS_FM<0b010101, 0x11>, INSN_MIPS4_32R2;
def RSQRT_S : MMRel, ABSS_FT<"rsqrt.s", FGR32Opnd, FGR32Opnd, II_RSQRT_S>,
ABSS_FM<0b010110, 0x10>, INSN_MIPS4_32R2;
def RSQRT_D : MMRel, ABSS_FT<"rsqrt.d", FGR64Opnd, FGR64Opnd, II_RSQRT_D>,
ABSS_FM<0b010110, 0x11>, INSN_MIPS4_32R2;
}
let DecoderNamespace = "Mips64" in { let DecoderNamespace = "Mips64" in {
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
def ROUND_L_S : ABSS_FT<"round.l.s", FGR64Opnd, FGR32Opnd, II_ROUND>, def ROUND_L_S : ABSS_FT<"round.l.s", FGR64Opnd, FGR32Opnd, II_ROUND>,
ABSS_FM<0x8, 16>, FGR_64; ABSS_FM<0x8, 16>, FGR_64;
def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64Opnd, FGR64Opnd, II_ROUND>, def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64Opnd, FGR64Opnd, II_ROUND>,
ABSS_FM<0x8, 17>, FGR_64; ABSS_FM<0x8, 17>, FGR_64;
def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64Opnd, FGR32Opnd, II_TRUNC>, def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64Opnd, FGR32Opnd, II_TRUNC>,
ABSS_FM<0x9, 16>, FGR_64; ABSS_FM<0x9, 16>, FGR_64;
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lib/Target/Mips/MipsInstrInfo.td

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// MIPS32r6 and MIPS64r6. // MIPS32r6 and MIPS64r6.
class INSN_MIPS3_32_NOT_32R6_64R6 { class INSN_MIPS3_32_NOT_32R6_64R6 {
list<Predicate> InsnPredicates = [HasMips3_32, NotMips32r6, NotMips64r6]; list<Predicate> InsnPredicates = [HasMips3_32, NotMips32r6, NotMips64r6];
} }
// The portions of MIPS-III that were also added to MIPS32 // The portions of MIPS-III that were also added to MIPS32
class INSN_MIPS3_32R2 { list<Predicate> InsnPredicates = [HasMips3_32r2]; } class INSN_MIPS3_32R2 { list<Predicate> InsnPredicates = [HasMips3_32r2]; }
// The portions of MIPS-IV that were also added to MIPS32.
class INSN_MIPS4_32 { list <Predicate> InsnPredicates = [HasMips4_32]; }
// The portions of MIPS-IV that were also added to MIPS32 but were removed in // The portions of MIPS-IV that were also added to MIPS32 but were removed in
// MIPS32r6 and MIPS64r6. // MIPS32r6 and MIPS64r6.
class INSN_MIPS4_32_NOT_32R6_64R6 { class INSN_MIPS4_32_NOT_32R6_64R6 {
list<Predicate> InsnPredicates = [HasMips4_32, NotMips32r6, NotMips64r6]; list<Predicate> InsnPredicates = [HasMips4_32, NotMips32r6, NotMips64r6];
} }
// The portions of MIPS-IV that were also added to MIPS32r2 but were removed in // The portions of MIPS-IV that were also added to MIPS32r2 but were removed in
// MIPS32r6 and MIPS64r6. // MIPS32r6 and MIPS64r6.
class INSN_MIPS4_32R2_NOT_32R6_64R6 { class INSN_MIPS4_32R2_NOT_32R6_64R6 {
list<Predicate> InsnPredicates = [HasMips4_32r2, NotMips32r6, NotMips64r6]; list<Predicate> InsnPredicates = [HasMips4_32r2, NotMips32r6, NotMips64r6];
} }
// The portions of MIPS-IV that were also added to MIPS32r2.
class INSN_MIPS4_32R2 {
list<Predicate> InsnPredicates = [HasMips4_32r2];
}
// The portions of MIPS-V that were also added to MIPS32r2 but were removed in // The portions of MIPS-V that were also added to MIPS32r2 but were removed in
// MIPS32r6 and MIPS64r6. // MIPS32r6 and MIPS64r6.
class INSN_MIPS5_32R2_NOT_32R6_64R6 { class INSN_MIPS5_32R2_NOT_32R6_64R6 {
list<Predicate> InsnPredicates = [HasMips5_32r2, NotMips32r6, NotMips64r6]; list<Predicate> InsnPredicates = [HasMips5_32r2, NotMips32r6, NotMips64r6];
} }
class ASE_CNMIPS { class ASE_CNMIPS {
list<Predicate> InsnPredicates = [HasCnMips]; list<Predicate> InsnPredicates = [HasCnMips];
▲ Show 20 Lines • Show All 2,463 Lines • Show Last 20 Lines

lib/Target/Mips/MipsSchedule.td

Show First 20 Lines • Show All 264 Lines • ▼ Show 20 Lines
def II_NMSUB_S : InstrItinClass; def II_NMSUB_S : InstrItinClass;
def II_NOR : InstrItinClass; def II_NOR : InstrItinClass;
def II_NOT : InstrItinClass; def II_NOT : InstrItinClass;
def II_OR : InstrItinClass; def II_OR : InstrItinClass;
def II_ORI : InstrItinClass; def II_ORI : InstrItinClass;
def II_POP : InstrItinClass; def II_POP : InstrItinClass;
def II_RDHWR : InstrItinClass; def II_RDHWR : InstrItinClass;
def II_RESTORE : InstrItinClass; def II_RESTORE : InstrItinClass;
def II_RECIP_S : InstrItinClass;
def II_RECIP_D : InstrItinClass;
def II_RINT_S : InstrItinClass; def II_RINT_S : InstrItinClass;
def II_RINT_D : InstrItinClass; def II_RINT_D : InstrItinClass;
def II_ROTR : InstrItinClass; def II_ROTR : InstrItinClass;
def II_ROTRV : InstrItinClass; def II_ROTRV : InstrItinClass;
def II_ROUND : InstrItinClass; def II_ROUND : InstrItinClass;
def II_RSQRT_S : InstrItinClass;
def II_RSQRT_D : InstrItinClass;
def II_SAVE : InstrItinClass; def II_SAVE : InstrItinClass;
def II_SC : InstrItinClass; def II_SC : InstrItinClass;
def II_SCD : InstrItinClass; def II_SCD : InstrItinClass;
def II_SB : InstrItinClass; def II_SB : InstrItinClass;
def II_SBE : InstrItinClass; def II_SBE : InstrItinClass;
def II_SD : InstrItinClass; def II_SD : InstrItinClass;
def II_SDC1 : InstrItinClass; def II_SDC1 : InstrItinClass;
def II_SDC2 : InstrItinClass; def II_SDC2 : InstrItinClass;
▲ Show 20 Lines • Show All 316 Lines • ▼ Show 20 Linesdef MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
InstrItinData<II_MADD_D , [InstrStage<8, [ALU]>]>, InstrItinData<II_MADD_D , [InstrStage<8, [ALU]>]>,
InstrItinData<II_MADDF_D , [InstrStage<8, [ALU]>]>, InstrItinData<II_MADDF_D , [InstrStage<8, [ALU]>]>,
InstrItinData<II_MSUB_D , [InstrStage<8, [ALU]>]>, InstrItinData<II_MSUB_D , [InstrStage<8, [ALU]>]>,
InstrItinData<II_MSUBF_D , [InstrStage<8, [ALU]>]>, InstrItinData<II_MSUBF_D , [InstrStage<8, [ALU]>]>,
InstrItinData<II_NMADD_D , [InstrStage<8, [ALU]>]>, InstrItinData<II_NMADD_D , [InstrStage<8, [ALU]>]>,
InstrItinData<II_NMSUB_D , [InstrStage<8, [ALU]>]>, InstrItinData<II_NMSUB_D , [InstrStage<8, [ALU]>]>,
InstrItinData<II_DIV_S , [InstrStage<23, [ALU]>]>, InstrItinData<II_DIV_S , [InstrStage<23, [ALU]>]>,
InstrItinData<II_DIV_D , [InstrStage<36, [ALU]>]>, InstrItinData<II_DIV_D , [InstrStage<36, [ALU]>]>,
InstrItinData<II_RECIP_D , [InstrStage<25, [ALU]>]>,
InstrItinData<II_RECIP_S , [InstrStage<13, [ALU]>]>,
InstrItinData<II_RSQRT_D , [InstrStage<29, [ALU]>]>,
InstrItinData<II_RSQRT_S , [InstrStage<14, [ALU]>]>,
InstrItinData<II_RINT_D , [InstrStage<1, [ALU]>]>, InstrItinData<II_RINT_D , [InstrStage<1, [ALU]>]>,
InstrItinData<II_RINT_S , [InstrStage<1, [ALU]>]>, InstrItinData<II_RINT_S , [InstrStage<1, [ALU]>]>,
InstrItinData<II_SQRT_S , [InstrStage<54, [ALU]>]>, InstrItinData<II_SQRT_S , [InstrStage<54, [ALU]>]>,
InstrItinData<II_SQRT_D , [InstrStage<12, [ALU]>]>, InstrItinData<II_SQRT_D , [InstrStage<12, [ALU]>]>,
InstrItinData<II_SEL_D , [InstrStage<1, [ALU]>]>, InstrItinData<II_SEL_D , [InstrStage<1, [ALU]>]>,
InstrItinData<II_SEL_S , [InstrStage<1, [ALU]>]>, InstrItinData<II_SEL_S , [InstrStage<1, [ALU]>]>,
InstrItinData<II_WSBH , [InstrStage<1, [ALU]>]>, InstrItinData<II_WSBH , [InstrStage<1, [ALU]>]>,
InstrItinData<II_LSA , [InstrStage<1, [ALU]>]>, InstrItinData<II_LSA , [InstrStage<1, [ALU]>]>,
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lib/Target/Mips/MipsScheduleGeneric.td

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// div.[ds], div.ps // div.[ds], div.ps
def : ItinRW<[GenericWriteFPUDivS], [II_DIV_S]>; def : ItinRW<[GenericWriteFPUDivS], [II_DIV_S]>;
def : ItinRW<[GenericWriteFPUDivD], [II_DIV_D]>; def : ItinRW<[GenericWriteFPUDivD], [II_DIV_D]>;
// sqrt.[ds], sqrt.ps // sqrt.[ds], sqrt.ps
def : ItinRW<[GenericWriteFPUSqrtS], [II_SQRT_S]>; def : ItinRW<[GenericWriteFPUSqrtS], [II_SQRT_S]>;
def : ItinRW<[GenericWriteFPUSqrtD], [II_SQRT_D]>; def : ItinRW<[GenericWriteFPUSqrtD], [II_SQRT_D]>;
// rsqrt.[ds], recip.[ds]
def : ItinRW<[GenericWriteFPURcpS], [II_RECIP_S, II_RSQRT_S]>;
def : ItinRW<[GenericWriteFPURcpD], [II_RECIP_D, II_RSQRT_D]>;
// MIPSR6 // MIPSR6
// ====== // ======
// //
// rint.[ds] // rint.[ds]
def : ItinRW<[GenericWriteFPUL], [II_RINT_S, II_RINT_D]>; def : ItinRW<[GenericWriteFPUL], [II_RINT_S, II_RINT_D]>;
// Load Pipe // Load Pipe
// --------- // ---------
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lib/Target/Mips/MipsScheduleP5600.td

Show First 20 Lines • Show All 442 Lines • ▼ Show 20 Lines
// sqrt.[ds], sqrt.ps // sqrt.[ds], sqrt.ps
def : ItinRW<[P5600WriteFPUSqrtS], [II_SQRT_S]>; def : ItinRW<[P5600WriteFPUSqrtS], [II_SQRT_S]>;
def : ItinRW<[P5600WriteFPUSqrtD], [II_SQRT_D]>; def : ItinRW<[P5600WriteFPUSqrtD], [II_SQRT_D]>;
// frcp.[wd], frsqrt.[wd] // frcp.[wd], frsqrt.[wd]
def : InstRW<[P5600WriteFPURsqrtD], (instregex "^FRCP_(W|D)$")>; def : InstRW<[P5600WriteFPURsqrtD], (instregex "^FRCP_(W|D)$")>;
def : InstRW<[P5600WriteFPURsqrtD], (instregex "^FRSQRT_(W|D)$")>; def : InstRW<[P5600WriteFPURsqrtD], (instregex "^FRSQRT_(W|D)$")>;
def : ItinRW<[P5600WriteFPURsqrtD], [II_RECIP_D, II_RSQRT_D]>;
def : ItinRW<[P5600WriteFPURsqrtS], [II_RECIP_S, II_RSQRT_S]>;
// fmadd.[wd], fmsubb.[wd], fdiv.[wd], fsqrt.[wd], fmul.[wd], fadd.[wd], // fmadd.[wd], fmsubb.[wd], fdiv.[wd], fsqrt.[wd], fmul.[wd], fadd.[wd],
// fsub.[wd] // fsub.[wd]
def : InstRW<[P5600WriteFPUL_MADDSUB], (instregex "^FMADD_(W|D)$")>; def : InstRW<[P5600WriteFPUL_MADDSUB], (instregex "^FMADD_(W|D)$")>;
def : InstRW<[P5600WriteFPUL_MADDSUB], (instregex "^FMSUB_(W|D)$")>; def : InstRW<[P5600WriteFPUL_MADDSUB], (instregex "^FMSUB_(W|D)$")>;
def : InstRW<[P5600WriteFPUDivS], (instregex "^FDIV_W$")>; def : InstRW<[P5600WriteFPUDivS], (instregex "^FDIV_W$")>;
def : InstRW<[P5600WriteFPUDivD], (instregex "^FDIV_D$")>; def : InstRW<[P5600WriteFPUDivD], (instregex "^FDIV_D$")>;
def : InstRW<[P5600WriteFPUSqrtS], (instregex "^FSQRT_W$")>; def : InstRW<[P5600WriteFPUSqrtS], (instregex "^FSQRT_W$")>;
def : InstRW<[P5600WriteFPUSqrtD], (instregex "^FSQRT_D$")>; def : InstRW<[P5600WriteFPUSqrtD], (instregex "^FSQRT_D$")>;
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test/MC/Disassembler/Mips/micromips32r3/valid-el.txt

Show First 20 Lines • Show All 189 Lines • ▼ Show 20 Lines
0x00 0x00 0x7c 0x8b # CHECK: syscall 0x00 0x00 0x7c 0x8b # CHECK: syscall
0x8c 0x01 0x7c 0x8b # CHECK: syscall 396 0x8c 0x01 0x7c 0x8b # CHECK: syscall 396
0xea 0xbc 0x2c 0x01 # CHECK: ldc1 $f7, 300($10) 0xea 0xbc 0x2c 0x01 # CHECK: ldc1 $f7, 300($10)
0x0a 0xbd 0x2c 0x01 # CHECK: ldc1 $f8, 300($10) 0x0a 0xbd 0x2c 0x01 # CHECK: ldc1 $f8, 300($10)
0x46 0x9c 0x04 0x00 # CHECK: lwc1 $f2, 4($6) 0x46 0x9c 0x04 0x00 # CHECK: lwc1 $f2, 4($6)
0xea 0xb8 0x40 0x00 # CHECK: sdc1 $f7, 64($10) 0xea 0xb8 0x40 0x00 # CHECK: sdc1 $f7, 64($10)
0x46 0xb8 0x04 0x00 # CHECK: sdc1 $f2, 4($6) 0x46 0xb8 0x04 0x00 # CHECK: sdc1 $f2, 4($6)
0x46 0x98 0x04 0x00 # CHECK: swc1 $f2, 4($6) 0x46 0x98 0x04 0x00 # CHECK: swc1 $f2, 4($6)
0x46,0x56,0x3b,0x52 # CHECK: recip.d $f18, $f6
0x7e,0x54,0x3b,0x12 # CHECK: recip.s $f3, $f30
0x5c,0x54,0x3b,0x42 # CHECK: rsqrt.d $f2, $f28
0x88,0x54,0x3b,0x02 # CHECK: rsqrt.s $f4, $f8

test/MC/Disassembler/Mips/micromips32r3/valid.txt

Show First 20 Lines • Show All 193 Lines • ▼ Show 20 Lines
0x9c 0x46 0x00 0x04 # CHECK: lwc1 $f2, 4($6) 0x9c 0x46 0x00 0x04 # CHECK: lwc1 $f2, 4($6)
0xb8 0x46 0x00 0x04 # CHECK: sdc1 $f2, 4($6) 0xb8 0x46 0x00 0x04 # CHECK: sdc1 $f2, 4($6)
0xb8 0xea 0x00 0x40 # CHECK: sdc1 $f7, 64($10) 0xb8 0xea 0x00 0x40 # CHECK: sdc1 $f7, 64($10)
0x98 0x46 0x00 0x04 # CHECK: swc1 $f2, 4($6) 0x98 0x46 0x00 0x04 # CHECK: swc1 $f2, 4($6)
0x54 0x22 0x10 0x3b # CHECK: cfc1 $1, $2 0x54 0x22 0x10 0x3b # CHECK: cfc1 $1, $2
0x00 0x64 0xcd 0x3c # CHECK: cfc2 $3, $4 0x00 0x64 0xcd 0x3c # CHECK: cfc2 $3, $4
0x54 0xa6 0x18 0x3b # CHECK: ctc1 $5, $6 0x54 0xa6 0x18 0x3b # CHECK: ctc1 $5, $6
0x00 0xe8 0xdd 0x3c # CHECK: ctc2 $7, $8 0x00 0xe8 0xdd 0x3c # CHECK: ctc2 $7, $8
0x56 0x46 0x52 0x3b # CHECK: recip.d $f18, $f6
0x54 0x7e 0x12 0x3b # CHECK: recip.s $f3, $f30
0x54 0x5c 0x42 0x3b # CHECK: rsqrt.d $f2, $f28
0x54 0x88 0x02 0x3b # CHECK: rsqrt.s $f4, $f8

test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-el.txt

Show First 20 Lines • Show All 129 Lines • ▼ Show 20 Lines
0x00 0x00 0x00 0x00 # CHECK: nop 0x00 0x00 0x00 0x00 # CHECK: nop
0x27 0x48 0xc7 0x00 # CHECK: nor $9, $6, $7 0x27 0x48 0xc7 0x00 # CHECK: nor $9, $6, $7
0xb9 0x87 0x1e 0x4d # CHECK: nmsub.d $f30, $f8, $f16, $f30 0xb9 0x87 0x1e 0x4d # CHECK: nmsub.d $f30, $f8, $f16, $f30
0x78 0x98 0x04 0x4f # CHECK: nmsub.s $f1, $f24, $f19, $f4 0x78 0x98 0x04 0x4f # CHECK: nmsub.s $f1, $f24, $f19, $f4
0x25 0x18 0x65 0x00 # CHECK: or $3, $3, $5 0x25 0x18 0x65 0x00 # CHECK: or $3, $3, $5
0x67 0x45 0xc9 0x34 # CHECK: ori $9, $6, 17767 0x67 0x45 0xc9 0x34 # CHECK: ori $9, $6, 17767
0xc2 0x49 0x26 0x00 # CHECK: rotr $9, $6, 7 0xc2 0x49 0x26 0x00 # CHECK: rotr $9, $6, 7
0x46 0x48 0xe6 0x00 # CHECK: rotrv $9, $6, $7 0x46 0x48 0xe6 0x00 # CHECK: rotrv $9, $6, $7
0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6
0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30
0x0c 0x73 0x20 0x46 # CHECK: round.w.d $f12, $f14 0x0c 0x73 0x20 0x46 # CHECK: round.w.d $f12, $f14
0x8c 0x39 0x00 0x46 # CHECK: round.w.s $f6, $f7 0x8c 0x39 0x00 0x46 # CHECK: round.w.s $f6, $f7
0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28
0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8
0xc6 0x23 0xa4 0xa0 # CHECK: sb $4, 9158($5) 0xc6 0x23 0xa4 0xa0 # CHECK: sb $4, 9158($5)
0x06 0x00 0xa4 0xa0 # CHECK: sb $4, 6($5) 0x06 0x00 0xa4 0xa0 # CHECK: sb $4, 6($5)
0xc6 0x23 0xe9 0xe0 # CHECK: sc $9, 9158($7) 0xc6 0x23 0xe9 0xe0 # CHECK: sc $9, 9158($7)
0xc6 0x23 0xe9 0xf4 # CHECK: sdc1 $f9, 9158($7) 0xc6 0x23 0xe9 0xf4 # CHECK: sdc1 $f9, 9158($7)
0x09 0x40 0x24 0x4f # CHECK: sdxc1 $f8, $4($25) 0x09 0x40 0x24 0x4f # CHECK: sdxc1 $f8, $4($25)
0x20 0x34 0x07 0x7c # CHECK: seb $6, $7 0x20 0x34 0x07 0x7c # CHECK: seb $6, $7
0x20 0x36 0x07 0x7c # CHECK: seh $6, $7 0x20 0x36 0x07 0x7c # CHECK: seh $6, $7
0xc6 0x23 0xa4 0xa4 # CHECK: sh $4, 9158($5) 0xc6 0x23 0xa4 0xa4 # CHECK: sh $4, 9158($5)
Show All 29 Lines

test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt

Show First 20 Lines • Show All 280 Lines • ▼ Show 20 Lines
0x46 0x3c 0x11 0x11 # CHECK: movf.d $f4, $f2, $fcc7 0x46 0x3c 0x11 0x11 # CHECK: movf.d $f4, $f2, $fcc7
0x46 0x3c 0x30 0x00 # CHECK: add.d $f0, $f6, $f28 0x46 0x3c 0x30 0x00 # CHECK: add.d $f0, $f6, $f28
0x46 0x3c 0xe0 0x3b # CHECK: c.ngl.d $f28, $f28 0x46 0x3c 0xe0 0x3b # CHECK: c.ngl.d $f28, $f28
0x46 0x3d 0x11 0x11 # CHECK: movt.d $f4, $f2, $fcc7 0x46 0x3d 0x11 0x11 # CHECK: movt.d $f4, $f2, $fcc7
0x46 0x80 0x39 0xa0 # CHECK: cvt.s.w $f6, $f7 0x46 0x80 0x39 0xa0 # CHECK: cvt.s.w $f6, $f7
0x46 0x80 0x5e 0xa1 # CHECK: cvt.d.w $f26, $f11 0x46 0x80 0x5e 0xa1 # CHECK: cvt.d.w $f26, $f11
0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14 0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14
0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15 0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15
0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18 0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
0x4c 0xa6 0x00 0x05 # CHECK: luxc1 $f0, $6($5) 0x4c 0xa6 0x00 0x05 # CHECK: luxc1 $f0, $6($5)
0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12 0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12
0x4c 0xb8 0x20 0x0d # CHECK: suxc1 $f4, $24($5) 0x4c 0xb8 0x20 0x0d # CHECK: suxc1 $f4, $24($5)
0x4d 0x1e 0x87 0xb9 # CHECK: nmsub.d $f30, $f8, $f16, $f30 0x4d 0x1e 0x87 0xb9 # CHECK: nmsub.d $f30, $f8, $f16, $f30
0x4d 0x54 0x74 0xb1 # CHECK: nmadd.d $f18, $f10, $f14, $f20 0x4d 0x54 0x74 0xb1 # CHECK: nmadd.d $f18, $f10, $f14, $f20
0x4d 0xcc 0x05 0x00 # CHECK: lwxc1 $f20, $12($14) 0x4d 0xcc 0x05 0x00 # CHECK: lwxc1 $f20, $12($14)
0x4d 0xf7 0x02 0x01 # CHECK: ldxc1 $f8, $23($15) 0x4d 0xf7 0x02 0x01 # CHECK: ldxc1 $f8, $23($15)
▲ Show 20 Lines • Show All 75 Lines • Show Last 20 Lines

test/MC/Disassembler/Mips/mips32r2/valid-xfail-mips32r2.txt

Show First 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
0x46 0xc0 0x64 0x87 # CHECK: neg.ps $f18, $f12 0x46 0xc0 0x64 0x87 # CHECK: neg.ps $f18, $f12
0x4c 0x98 0x46 0xb6 # CHECK: nmadd.ps $f26, $f4, $f8, $f24 0x4c 0x98 0x46 0xb6 # CHECK: nmadd.ps $f26, $f4, $f8, $f24
0x4d 0x90 0x71 0xbe # CHECK: nmsub.ps $f6, $f12, $f14, $f16 0x4d 0x90 0x71 0xbe # CHECK: nmsub.ps $f6, $f12, $f14, $f16
0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30 0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30
0x46 0xdc 0xd0 0x2d # CHECK: plu.ps $f0, $f26, $f28 0x46 0xdc 0xd0 0x2d # CHECK: plu.ps $f0, $f26, $f28
0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26 0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26
0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2 0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2
0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1 0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1
0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5 0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
0x46 0x20 0x03 0x08 # CHECK: round.l.d $f12, $f0 0x46 0x20 0x03 0x08 # CHECK: round.l.d $f12, $f0
0x46 0x00 0x2e 0x08 # CHECK: round.l.s $f24, $f5 0x46 0x00 0x2e 0x08 # CHECK: round.l.s $f24, $f5
0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26 0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26
0x46 0x20 0xb5 0x89 # CHECK: trunc.l.d $f22, $f22 0x46 0x20 0xb5 0x89 # CHECK: trunc.l.d $f22, $f22
0x46 0x00 0xff 0x09 # CHECK: trunc.l.s $f28, $f31 0x46 0x00 0xff 0x09 # CHECK: trunc.l.s $f28, $f31
0x41 0xcd 0x00 0x00 # CHECK: wrpgpr zero, t5 0x41 0xcd 0x00 0x00 # CHECK: wrpgpr zero, t5

test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-el.txt

Show First 20 Lines • Show All 123 Lines • ▼ Show 20 Lines
0xb1 0x74 0x54 0x4d # CHECK: nmadd.d $f18, $f10, $f14, $f20 0xb1 0x74 0x54 0x4d # CHECK: nmadd.d $f18, $f10, $f14, $f20
0x30 0xc8 0xac 0x4c # CHECK: nmadd.s $f0, $f5, $f25, $f12 0x30 0xc8 0xac 0x4c # CHECK: nmadd.s $f0, $f5, $f25, $f12
0x00 0x00 0x00 0x00 # CHECK: nop 0x00 0x00 0x00 0x00 # CHECK: nop
0x27 0x48 0xc7 0x00 # CHECK: nor $9, $6, $7 0x27 0x48 0xc7 0x00 # CHECK: nor $9, $6, $7
0xb9 0x87 0x1e 0x4d # CHECK: nmsub.d $f30, $f8, $f16, $f30 0xb9 0x87 0x1e 0x4d # CHECK: nmsub.d $f30, $f8, $f16, $f30
0x78 0x98 0x04 0x4f # CHECK: nmsub.s $f1, $f24, $f19, $f4 0x78 0x98 0x04 0x4f # CHECK: nmsub.s $f1, $f24, $f19, $f4
0x25 0x18 0x65 0x00 # CHECK: or $3, $3, $5 0x25 0x18 0x65 0x00 # CHECK: or $3, $3, $5
0x67 0x45 0xc9 0x34 # CHECK: ori $9, $6, 17767 0x67 0x45 0xc9 0x34 # CHECK: ori $9, $6, 17767
0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6
0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30
0xc2 0x49 0x26 0x00 # CHECK: rotr $9, $6, 7 0xc2 0x49 0x26 0x00 # CHECK: rotr $9, $6, 7
0x46 0x48 0xe6 0x00 # CHECK: rotrv $9, $6, $7 0x46 0x48 0xe6 0x00 # CHECK: rotrv $9, $6, $7
0x0c 0x73 0x20 0x46 # CHECK: round.w.d $f12, $f14 0x0c 0x73 0x20 0x46 # CHECK: round.w.d $f12, $f14
0x8c 0x39 0x00 0x46 # CHECK: round.w.s $f6, $f7 0x8c 0x39 0x00 0x46 # CHECK: round.w.s $f6, $f7
0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28
0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8
0xc6 0x23 0xa4 0xa0 # CHECK: sb $4, 9158($5) 0xc6 0x23 0xa4 0xa0 # CHECK: sb $4, 9158($5)
0x06 0x00 0xa4 0xa0 # CHECK: sb $4, 6($5) 0x06 0x00 0xa4 0xa0 # CHECK: sb $4, 6($5)
0xc6 0x23 0xe9 0xe0 # CHECK: sc $9, 9158($7) 0xc6 0x23 0xe9 0xe0 # CHECK: sc $9, 9158($7)
0xc6 0x23 0xe9 0xf4 # CHECK: sdc1 $f9, 9158($7) 0xc6 0x23 0xe9 0xf4 # CHECK: sdc1 $f9, 9158($7)
0x09 0x40 0x24 0x4f # CHECK: sdxc1 $f8, $4($25) 0x09 0x40 0x24 0x4f # CHECK: sdxc1 $f8, $4($25)
0x20 0x34 0x07 0x7c # CHECK: seb $6, $7 0x20 0x34 0x07 0x7c # CHECK: seb $6, $7
0x20 0x36 0x07 0x7c # CHECK: seh $6, $7 0x20 0x36 0x07 0x7c # CHECK: seh $6, $7
0xc6 0x23 0xa4 0xa4 # CHECK: sh $4, 9158($5) 0xc6 0x23 0xa4 0xa4 # CHECK: sh $4, 9158($5)
Show All 28 Lines

test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt

Show First 20 Lines • Show All 277 Lines • ▼ Show 20 Lines
0x46 0x3c 0x11 0x11 # CHECK: movf.d $f4, $f2, $fcc7 0x46 0x3c 0x11 0x11 # CHECK: movf.d $f4, $f2, $fcc7
0x46 0x3c 0x30 0x00 # CHECK: add.d $f0, $f6, $f28 0x46 0x3c 0x30 0x00 # CHECK: add.d $f0, $f6, $f28
0x46 0x3c 0xe0 0x3b # CHECK: c.ngl.d $f28, $f28 0x46 0x3c 0xe0 0x3b # CHECK: c.ngl.d $f28, $f28
0x46 0x3d 0x11 0x11 # CHECK: movt.d $f4, $f2, $fcc7 0x46 0x3d 0x11 0x11 # CHECK: movt.d $f4, $f2, $fcc7
0x46 0x80 0x39 0xa0 # CHECK: cvt.s.w $f6, $f7 0x46 0x80 0x39 0xa0 # CHECK: cvt.s.w $f6, $f7
0x46 0x80 0x5e 0xa1 # CHECK: cvt.d.w $f26, $f11 0x46 0x80 0x5e 0xa1 # CHECK: cvt.d.w $f26, $f11
0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14 0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14
0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15 0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15
0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18 0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
0x4c 0xa6 0x00 0x05 # CHECK: luxc1 $f0, $6($5) 0x4c 0xa6 0x00 0x05 # CHECK: luxc1 $f0, $6($5)
0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12 0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12
0x4c 0xb8 0x20 0x0d # CHECK: suxc1 $f4, $24($5) 0x4c 0xb8 0x20 0x0d # CHECK: suxc1 $f4, $24($5)
0x4d 0x1e 0x87 0xb9 # CHECK: nmsub.d $f30, $f8, $f16, $f30 0x4d 0x1e 0x87 0xb9 # CHECK: nmsub.d $f30, $f8, $f16, $f30
0x4d 0x54 0x74 0xb1 # CHECK: nmadd.d $f18, $f10, $f14, $f20 0x4d 0x54 0x74 0xb1 # CHECK: nmadd.d $f18, $f10, $f14, $f20
0x4d 0xcc 0x05 0x00 # CHECK: lwxc1 $f20, $12($14) 0x4d 0xcc 0x05 0x00 # CHECK: lwxc1 $f20, $12($14)
0x4d 0xf7 0x02 0x01 # CHECK: ldxc1 $f8, $23($15) 0x4d 0xf7 0x02 0x01 # CHECK: ldxc1 $f8, $23($15)
▲ Show 20 Lines • Show All 75 Lines • Show Last 20 Lines

test/MC/Disassembler/Mips/mips32r3/valid-xfail-mips32r3.txt

Show First 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
0x46 0xc0 0x64 0x87 # CHECK: neg.ps $f18, $f12 0x46 0xc0 0x64 0x87 # CHECK: neg.ps $f18, $f12
0x4c 0x98 0x46 0xb6 # CHECK: nmadd.ps $f26, $f4, $f8, $f24 0x4c 0x98 0x46 0xb6 # CHECK: nmadd.ps $f26, $f4, $f8, $f24
0x4d 0x90 0x71 0xbe # CHECK: nmsub.ps $f6, $f12, $f14, $f16 0x4d 0x90 0x71 0xbe # CHECK: nmsub.ps $f6, $f12, $f14, $f16
0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30 0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30
0x46 0xdc 0xd0 0x2d # CHECK: plu.ps $f0, $f26, $f28 0x46 0xdc 0xd0 0x2d # CHECK: plu.ps $f0, $f26, $f28
0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26 0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26
0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2 0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2
0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1 0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1
0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5 0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
0x46 0x20 0x03 0x08 # CHECK: round.l.d $f12, $f0 0x46 0x20 0x03 0x08 # CHECK: round.l.d $f12, $f0
0x46 0x00 0x2e 0x08 # CHECK: round.l.s $f24, $f5 0x46 0x00 0x2e 0x08 # CHECK: round.l.s $f24, $f5
0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26 0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26
0x46 0x20 0xb5 0x89 # CHECK: trunc.l.d $f22, $f22 0x46 0x20 0xb5 0x89 # CHECK: trunc.l.d $f22, $f22
0x46 0x00 0xff 0x09 # CHECK: trunc.l.s $f28, $f31 0x46 0x00 0xff 0x09 # CHECK: trunc.l.s $f28, $f31
0x41 0xcd 0x00 0x00 # CHECK: wrpgpr zero, t5 0x41 0xcd 0x00 0x00 # CHECK: wrpgpr zero, t5

test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-el.txt

Show First 20 Lines • Show All 125 Lines • ▼ Show 20 Lines
0x00 0x00 0x00 0x00 # CHECK: nop 0x00 0x00 0x00 0x00 # CHECK: nop
0x27 0x48 0xc7 0x00 # CHECK: nor $9, $6, $7 0x27 0x48 0xc7 0x00 # CHECK: nor $9, $6, $7
0xb9 0x87 0x1e 0x4d # CHECK: nmsub.d $f30, $f8, $f16, $f30 0xb9 0x87 0x1e 0x4d # CHECK: nmsub.d $f30, $f8, $f16, $f30
0x78 0x98 0x04 0x4f # CHECK: nmsub.s $f1, $f24, $f19, $f4 0x78 0x98 0x04 0x4f # CHECK: nmsub.s $f1, $f24, $f19, $f4
0x25 0x18 0x65 0x00 # CHECK: or $3, $3, $5 0x25 0x18 0x65 0x00 # CHECK: or $3, $3, $5
0x67 0x45 0xc9 0x34 # CHECK: ori $9, $6, 17767 0x67 0x45 0xc9 0x34 # CHECK: ori $9, $6, 17767
0xc2 0x49 0x26 0x00 # CHECK: rotr $9, $6, 7 0xc2 0x49 0x26 0x00 # CHECK: rotr $9, $6, 7
0x46 0x48 0xe6 0x00 # CHECK: rotrv $9, $6, $7 0x46 0x48 0xe6 0x00 # CHECK: rotrv $9, $6, $7
0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6
0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30
0x0c 0x73 0x20 0x46 # CHECK: round.w.d $f12, $f14 0x0c 0x73 0x20 0x46 # CHECK: round.w.d $f12, $f14
0x8c 0x39 0x00 0x46 # CHECK: round.w.s $f6, $f7 0x8c 0x39 0x00 0x46 # CHECK: round.w.s $f6, $f7
0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28
0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8
0xc6 0x23 0xa4 0xa0 # CHECK: sb $4, 9158($5) 0xc6 0x23 0xa4 0xa0 # CHECK: sb $4, 9158($5)
0x06 0x00 0xa4 0xa0 # CHECK: sb $4, 6($5) 0x06 0x00 0xa4 0xa0 # CHECK: sb $4, 6($5)
0xc6 0x23 0xe9 0xe0 # CHECK: sc $9, 9158($7) 0xc6 0x23 0xe9 0xe0 # CHECK: sc $9, 9158($7)
0xc6 0x23 0xe9 0xf4 # CHECK: sdc1 $f9, 9158($7) 0xc6 0x23 0xe9 0xf4 # CHECK: sdc1 $f9, 9158($7)
0x09 0x40 0x24 0x4f # CHECK: sdxc1 $f8, $4($25) 0x09 0x40 0x24 0x4f # CHECK: sdxc1 $f8, $4($25)
0x20 0x34 0x07 0x7c # CHECK: seb $6, $7 0x20 0x34 0x07 0x7c # CHECK: seb $6, $7
0x20 0x36 0x07 0x7c # CHECK: seh $6, $7 0x20 0x36 0x07 0x7c # CHECK: seh $6, $7
0xc6 0x23 0xa4 0xa4 # CHECK: sh $4, 9158($5) 0xc6 0x23 0xa4 0xa4 # CHECK: sh $4, 9158($5)
Show All 28 Lines

test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt

Show First 20 Lines • Show All 278 Lines • ▼ Show 20 Lines
0x46 0x3c 0x11 0x11 # CHECK: movf.d $f4, $f2, $fcc7 0x46 0x3c 0x11 0x11 # CHECK: movf.d $f4, $f2, $fcc7
0x46 0x3c 0x30 0x00 # CHECK: add.d $f0, $f6, $f28 0x46 0x3c 0x30 0x00 # CHECK: add.d $f0, $f6, $f28
0x46 0x3c 0xe0 0x3b # CHECK: c.ngl.d $f28, $f28 0x46 0x3c 0xe0 0x3b # CHECK: c.ngl.d $f28, $f28
0x46 0x3d 0x11 0x11 # CHECK: movt.d $f4, $f2, $fcc7 0x46 0x3d 0x11 0x11 # CHECK: movt.d $f4, $f2, $fcc7
0x46 0x80 0x39 0xa0 # CHECK: cvt.s.w $f6, $f7 0x46 0x80 0x39 0xa0 # CHECK: cvt.s.w $f6, $f7
0x46 0x80 0x5e 0xa1 # CHECK: cvt.d.w $f26, $f11 0x46 0x80 0x5e 0xa1 # CHECK: cvt.d.w $f26, $f11
0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14 0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14
0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15 0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15
0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18 0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
0x4c 0xa6 0x00 0x05 # CHECK: luxc1 $f0, $6($5) 0x4c 0xa6 0x00 0x05 # CHECK: luxc1 $f0, $6($5)
0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12 0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12
0x4c 0xb8 0x20 0x0d # CHECK: suxc1 $f4, $24($5) 0x4c 0xb8 0x20 0x0d # CHECK: suxc1 $f4, $24($5)
0x4d 0x1e 0x87 0xb9 # CHECK: nmsub.d $f30, $f8, $f16, $f30 0x4d 0x1e 0x87 0xb9 # CHECK: nmsub.d $f30, $f8, $f16, $f30
0x4d 0x54 0x74 0xb1 # CHECK: nmadd.d $f18, $f10, $f14, $f20 0x4d 0x54 0x74 0xb1 # CHECK: nmadd.d $f18, $f10, $f14, $f20
0x4d 0xcc 0x05 0x00 # CHECK: lwxc1 $f20, $12($14) 0x4d 0xcc 0x05 0x00 # CHECK: lwxc1 $f20, $12($14)
0x4d 0xf7 0x02 0x01 # CHECK: ldxc1 $f8, $23($15) 0x4d 0xf7 0x02 0x01 # CHECK: ldxc1 $f8, $23($15)
▲ Show 20 Lines • Show All 75 Lines • Show Last 20 Lines

test/MC/Disassembler/Mips/mips32r5/valid-xfail-mips32r5.txt

Show First 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
0x46 0xc0 0x64 0x87 # CHECK: neg.ps $f18, $f12 0x46 0xc0 0x64 0x87 # CHECK: neg.ps $f18, $f12
0x4c 0x98 0x46 0xb6 # CHECK: nmadd.ps $f26, $f4, $f8, $f24 0x4c 0x98 0x46 0xb6 # CHECK: nmadd.ps $f26, $f4, $f8, $f24
0x4d 0x90 0x71 0xbe # CHECK: nmsub.ps $f6, $f12, $f14, $f16 0x4d 0x90 0x71 0xbe # CHECK: nmsub.ps $f6, $f12, $f14, $f16
0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30 0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30
0x46 0xdc 0xd0 0x2d # CHECK: plu.ps $f0, $f26, $f28 0x46 0xdc 0xd0 0x2d # CHECK: plu.ps $f0, $f26, $f28
0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26 0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26
0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2 0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2
0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1 0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1
0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5 0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
0x46 0x20 0x03 0x08 # CHECK: round.l.d $f12, $f0 0x46 0x20 0x03 0x08 # CHECK: round.l.d $f12, $f0
0x46 0x00 0x2e 0x08 # CHECK: round.l.s $f24, $f5 0x46 0x00 0x2e 0x08 # CHECK: round.l.s $f24, $f5
0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26 0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26
0x46 0x20 0xb5 0x89 # CHECK: trunc.l.d $f22, $f22 0x46 0x20 0xb5 0x89 # CHECK: trunc.l.d $f22, $f22
0x46 0x00 0xff 0x09 # CHECK: trunc.l.s $f28, $f31 0x46 0x00 0xff 0x09 # CHECK: trunc.l.s $f28, $f31
0x41 0xcd 0x00 0x00 # CHECK: wrpgpr zero, t5 0x41 0xcd 0x00 0x00 # CHECK: wrpgpr zero, t5

test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt

Show First 20 Lines • Show All 119 Lines • ▼ Show 20 Lines
0x1f 0x10 0x24 0x46 # CHECK: maxa.d $f0, $f2, $f4 0x1f 0x10 0x24 0x46 # CHECK: maxa.d $f0, $f2, $f4
0x1e 0x10 0x04 0x46 # CHECK: mina.s $f0, $f2, $f4 0x1e 0x10 0x04 0x46 # CHECK: mina.s $f0, $f2, $f4
0x1e 0x10 0x24 0x46 # CHECK: mina.d $f0, $f2, $f4 0x1e 0x10 0x24 0x46 # CHECK: mina.d $f0, $f2, $f4
0x04 0x00 0x42 0x34 # CHECK: ori $2, $2, 4 0x04 0x00 0x42 0x34 # CHECK: ori $2, $2, 4
0x14 0x10 0x04 0x46 # CHECK: seleqz.s $f0, $f2, $f4 0x14 0x10 0x04 0x46 # CHECK: seleqz.s $f0, $f2, $f4
0x14 0x10 0x24 0x46 # CHECK: seleqz.d $f0, $f2, $f4 0x14 0x10 0x24 0x46 # CHECK: seleqz.d $f0, $f2, $f4
0x17 0x10 0x04 0x46 # CHECK: selnez.s $f0, $f2, $f4 0x17 0x10 0x04 0x46 # CHECK: selnez.s $f0, $f2, $f4
0x17 0x10 0x24 0x46 # CHECK: selnez.d $f0, $f2, $f4 0x17 0x10 0x24 0x46 # CHECK: selnez.d $f0, $f2, $f4
0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6
0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30
0x9a 0x20 0x00 0x46 # CHECK: rint.s $f2, $f4 0x9a 0x20 0x00 0x46 # CHECK: rint.s $f2, $f4
0x9a 0x20 0x20 0x46 # CHECK: rint.d $f2, $f4 0x9a 0x20 0x20 0x46 # CHECK: rint.d $f2, $f4
0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28
0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8
0x9b 0x20 0x00 0x46 # CHECK: class.s $f2, $f4 0x9b 0x20 0x00 0x46 # CHECK: class.s $f2, $f4
0x9b 0x20 0x20 0x46 # CHECK: class.d $f2, $f4 0x9b 0x20 0x20 0x46 # CHECK: class.d $f2, $f4
0x09 0x04 0x80 0x00 # CHECK: jr.hb $4 0x09 0x04 0x80 0x00 # CHECK: jr.hb $4
0x00 0x00 0x1b 0xd8 # CHECK: jrc $27 0x00 0x00 0x1b 0xd8 # CHECK: jrc $27
0x09 0xfc 0x80 0x00 # CHECK: jalr.hb $4 0x09 0xfc 0x80 0x00 # CHECK: jalr.hb $4
0x09 0x24 0xa0 0x00 # CHECK: jalr.hb $4, $5 0x09 0x24 0xa0 0x00 # CHECK: jalr.hb $4, $5
0x00 0x00 0x19 0xf8 # CHECK: jalrc $25 0x00 0x00 0x19 0xf8 # CHECK: jalrc $25
0xb6 0xb3 0x42 0x7e # CHECK: ll $2, -153($18) 0xb6 0xb3 0x42 0x7e # CHECK: ll $2, -153($18)
Show All 28 Lines

test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt

Show First 20 Lines • Show All 128 Lines • ▼ Show 20 Lines
0x46 0xa4 0x18 0x88 # CHECK: cmp.saf.d $f2, $f3, $f4 0x46 0xa4 0x18 0x88 # CHECK: cmp.saf.d $f2, $f3, $f4
0x46 0xa4 0x18 0x89 # CHECK: cmp.sun.d $f2, $f3, $f4 0x46 0xa4 0x18 0x89 # CHECK: cmp.sun.d $f2, $f3, $f4
0x46 0xa4 0x18 0x8a # CHECK: cmp.seq.d $f2, $f3, $f4 0x46 0xa4 0x18 0x8a # CHECK: cmp.seq.d $f2, $f3, $f4
0x46 0xa4 0x18 0x8b # CHECK: cmp.sueq.d $f2, $f3, $f4 0x46 0xa4 0x18 0x8b # CHECK: cmp.sueq.d $f2, $f3, $f4
0x46 0xa4 0x18 0x8c # CHECK: cmp.slt.d $f2, $f3, $f4 0x46 0xa4 0x18 0x8c # CHECK: cmp.slt.d $f2, $f3, $f4
0x46 0xa4 0x18 0x8d # CHECK: cmp.sult.d $f2, $f3, $f4 0x46 0xa4 0x18 0x8d # CHECK: cmp.sult.d $f2, $f3, $f4
0x46 0xa4 0x18 0x8e # CHECK: cmp.sle.d $f2, $f3, $f4 0x46 0xa4 0x18 0x8e # CHECK: cmp.sle.d $f2, $f3, $f4
0x46 0xa4 0x18 0x8f # CHECK: cmp.sule.d $f2, $f3, $f4 0x46 0xa4 0x18 0x8f # CHECK: cmp.sule.d $f2, $f3, $f4
0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
0x42 0x00 0x00 0x58 # CHECK: eretnc 0x42 0x00 0x00 0x58 # CHECK: eretnc
# FIXME: The encode/decode functions are not inverses of each other. # FIXME: The encode/decode functions are not inverses of each other.
# The immediate should be 8 but the disassembler currently emits 12 # The immediate should be 8 but the disassembler currently emits 12
0x49 0x20 0x00 0x02 # CHECK: bc2eqz $0, 12 0x49 0x20 0x00 0x02 # CHECK: bc2eqz $0, 12
# FIXME: The encode/decode functions are not inverses of each other. # FIXME: The encode/decode functions are not inverses of each other.
# The immediate should be 8 but the disassembler currently emits 12 # The immediate should be 8 but the disassembler currently emits 12
0x49 0x3f 0x00 0x02 # CHECK: bc2eqz $31, 12 0x49 0x3f 0x00 0x02 # CHECK: bc2eqz $31, 12
0x49 0x52 0x34 0xb7 # CHECK: lwc2 $18, -841($6) 0x49 0x52 0x34 0xb7 # CHECK: lwc2 $18, -841($6)
▲ Show 20 Lines • Show All 47 Lines • Show Last 20 Lines

test/MC/Disassembler/Mips/mips4/valid-mips4-el.txt

Show First 20 Lines • Show All 149 Lines • ▼ Show 20 Lines
0x23 0x10 0x02 0x00 # CHECK: negu $2, $2 0x23 0x10 0x02 0x00 # CHECK: negu $2, $2
0x23 0x10 0x03 0x00 # CHECK: negu $2, $3 0x23 0x10 0x03 0x00 # CHECK: negu $2, $3
0x87 0x96 0x20 0x46 # CHECK: neg.d $f26, $f18 0x87 0x96 0x20 0x46 # CHECK: neg.d $f26, $f18
0x47 0x78 0x00 0x46 # CHECK: neg.s $f1, $f15 0x47 0x78 0x00 0x46 # CHECK: neg.s $f1, $f15
0x00 0x00 0x00 0x00 # CHECK: nop 0x00 0x00 0x00 0x00 # CHECK: nop
0x27 0x38 0x07 0x00 # CHECK: nor $7, $zero, $7 0x27 0x38 0x07 0x00 # CHECK: nor $7, $zero, $7
0x25 0x60 0x1d 0x02 # CHECK: or $12, $16, $sp 0x25 0x60 0x1d 0x02 # CHECK: or $12, $16, $sp
0x04 0x00 0x42 0x34 # CHECK: ori $2, $2, 4 0x04 0x00 0x42 0x34 # CHECK: ori $2, $2, 4
0x08 0x00 0xa1 0xcc # CHECK: pref 1, 8($5) 0x08 0x00 0xa1 0xcc # CHECK: pref 1, 8($5)
0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6
0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30
0x08 0x0b 0x20 0x46 # CHECK: round.l.d $f12, $f1 0x08 0x0b 0x20 0x46 # CHECK: round.l.d $f12, $f1
0x48 0x2e 0x00 0x46 # CHECK: round.l.s $f25, $f5 0x48 0x2e 0x00 0x46 # CHECK: round.l.s $f25, $f5
0x8c 0x21 0x20 0x46 # CHECK: round.w.d $f6, $f4 0x8c 0x21 0x20 0x46 # CHECK: round.w.d $f6, $f4
0xcc 0xe6 0x00 0x46 # CHECK: round.w.s $f27, $f28 0xcc 0xe6 0x00 0x46 # CHECK: round.w.s $f27, $f28
0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28
0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8
0x6f 0xb2 0xd6 0xa1 # CHECK: sb $22, -19857($14) 0x6f 0xb2 0xd6 0xa1 # CHECK: sb $22, -19857($14)
0xd8 0x49 0x6f 0xe2 # CHECK: sc $15, 18904($19) 0xd8 0x49 0x6f 0xe2 # CHECK: sc $15, 18904($19)
0xcd 0xdf 0xaf 0xf3 # CHECK: scd $15, -8243($sp) 0xcd 0xdf 0xaf 0xf3 # CHECK: scd $15, -8243($sp)
0xcb 0x16 0x4c 0xfd # CHECK: sd $12, 5835($10) 0xcb 0x16 0x4c 0xfd # CHECK: sd $12, 5835($10)
0x1f 0xae 0xc7 0xb3 # CHECK: sdl $7, -20961($fp) 0x1f 0xae 0xc7 0xb3 # CHECK: sdl $7, -20961($fp)
0x39 0xb0 0x8b 0xb5 # CHECK: sdr $11, -20423($12) 0x39 0xb0 0x8b 0xb5 # CHECK: sdr $11, -20423($12)
0x6e 0x77 0xbe 0xf5 # CHECK: sdc1 $f30, 30574($13) 0x6e 0x77 0xbe 0xf5 # CHECK: sdc1 $f30, 30574($13)
0x75 0x5a 0x54 0xfa # CHECK: sdc2 $20, 23157($18) 0x75 0x5a 0x54 0xfa # CHECK: sdc2 $20, 23157($18)
▲ Show 20 Lines • Show All 61 Lines • Show Last 20 Lines

test/MC/Disassembler/Mips/mips4/valid-mips4.txt

Show First 20 Lines • Show All 251 Lines • ▼ Show 20 Lines
0xd8 0x28 0xad 0x43 # CHECK: ldc2 $8, -21181($1) 0xd8 0x28 0xad 0x43 # CHECK: ldc2 $8, -21181($1)
0xe2 0x6f 0x49 0xd8 # CHECK: sc $15, 18904($19) 0xe2 0x6f 0x49 0xd8 # CHECK: sc $15, 18904($19)
0xe7 0x06 0xde 0xef # CHECK: swc1 $f6, -8465($24) 0xe7 0x06 0xde 0xef # CHECK: swc1 $f6, -8465($24)
0xea 0x19 0x61 0x30 # CHECK: swc2 $25, 24880($16) 0xea 0x19 0x61 0x30 # CHECK: swc2 $25, 24880($16)
0xf3 0xaf 0xdf 0xcd # CHECK: scd $15, -8243($sp) 0xf3 0xaf 0xdf 0xcd # CHECK: scd $15, -8243($sp)
0xf5 0xbe 0x77 0x6e # CHECK: sdc1 $f30, 30574($13) 0xf5 0xbe 0x77 0x6e # CHECK: sdc1 $f30, 30574($13)
0xfa 0x54 0x5a 0x75 # CHECK: sdc2 $20, 23157($18) 0xfa 0x54 0x5a 0x75 # CHECK: sdc2 $20, 23157($18)
0xfd 0x4c 0x16 0xcb # CHECK: sd $12, 5835($10) 0xfd 0x4c 0x16 0xcb # CHECK: sd $12, 5835($10)
0x46 0x20 0x34 0xd5 # CHECK: recip.d $f19, $f6
0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
0x46 0x20 0xe0 0xd6 # CHECK: rsqrt.d $f3, $f28
0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8

test/MC/Disassembler/Mips/mips4/valid-xfail-mips4.txt

Show All 30 Lines
0x4e 0x74 0xd4 0xa1 # CHECK: madd.d $f18, $f19, $f26, $f20 0x4e 0x74 0xd4 0xa1 # CHECK: madd.d $f18, $f19, $f26, $f20
0x4f 0xf9 0x98 0x60 # CHECK: madd.s $f1, $f31, $f19, $f25 0x4f 0xf9 0x98 0x60 # CHECK: madd.s $f1, $f31, $f19, $f25
0x4c 0x32 0xfa 0xa9 # CHECK: msub.d $f10, $f1, $f31, $f18 0x4c 0x32 0xfa 0xa9 # CHECK: msub.d $f10, $f1, $f31, $f18
0x4e 0x70 0x53 0x28 # CHECK: msub.s $f12, $f19, $f10, $f16 0x4e 0x70 0x53 0x28 # CHECK: msub.s $f12, $f19, $f10, $f16
0x4d 0x33 0x74 0xb1 # CHECK: nmadd.d $f18, $f9, $f14, $f19 0x4d 0x33 0x74 0xb1 # CHECK: nmadd.d $f18, $f9, $f14, $f19
0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12 0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12
0x4d 0x1e 0x87 0xb9 # CHECK: nmsub.d $f30, $f8, $f16, $f30 0x4d 0x1e 0x87 0xb9 # CHECK: nmsub.d $f30, $f8, $f16, $f30
0x4f 0x04 0x98 0x78 # CHECK: nmsub.s $f1, $f24, $f19, $f4 0x4f 0x04 0x98 0x78 # CHECK: nmsub.s $f1, $f24, $f19, $f4
0x46 0x20 0x34 0xd5 # CHECK: recip.d $f19, $f6
0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
0x46 0x20 0xe0 0xd6 # CHECK: rsqrt.d $f3, $f28
0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8

test/MC/Disassembler/Mips/mips64/valid-mips64-el.txt

Show First 20 Lines • Show All 200 Lines • ▼ Show 20 Lines
0x23 0x20 0x65 0x00 # CHECK: subu $4, $3, $5 0x23 0x20 0x65 0x00 # CHECK: subu $4, $3, $5
0x18 0x00 0xa4 0xac # CHECK: sw $4, 24($5) 0x18 0x00 0xa4 0xac # CHECK: sw $4, 24($5)
0xc6 0x23 0xe9 0xe4 # CHECK: swc1 $f9, 9158($7) 0xc6 0x23 0xe9 0xe4 # CHECK: swc1 $f9, 9158($7)
0x0d 0x60 0xbb 0x4d # CHECK: suxc1 $f12, $27($13) 0x0d 0x60 0xbb 0x4d # CHECK: suxc1 $f12, $27($13)
0x08 0x98 0x4c 0x4f # CHECK: swxc1 $f19, $12($26) 0x08 0x98 0x4c 0x4f # CHECK: swxc1 $f19, $12($26)
0x10 0x00 0xa4 0xa8 # CHECK: swl $4, 16($5) 0x10 0x00 0xa4 0xa8 # CHECK: swl $4, 16($5)
0x10 0x00 0xe6 0xb8 # CHECK: swr $6, 16($7) 0x10 0x00 0xe6 0xb8 # CHECK: swr $6, 16($7)
0xcf 0x01 0x00 0x00 # CHECK: sync 7 0xcf 0x01 0x00 0x00 # CHECK: sync 7
0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6
0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30
0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28
0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8
0xc9 0xbd 0x20 0x46 # CHECK: trunc.l.d $f23, $f23 0xc9 0xbd 0x20 0x46 # CHECK: trunc.l.d $f23, $f23
0x09 0xff 0x00 0x46 # CHECK: trunc.l.s $f28, $f31 0x09 0xff 0x00 0x46 # CHECK: trunc.l.s $f28, $f31
0x0d 0x73 0x20 0x46 # CHECK: trunc.w.d $f12, $f14 0x0d 0x73 0x20 0x46 # CHECK: trunc.w.d $f12, $f14
0x8d 0x39 0x00 0x46 # CHECK: trunc.w.s $f6, $f7 0x8d 0x39 0x00 0x46 # CHECK: trunc.w.s $f6, $f7
0x26 0x18 0x65 0x00 # CHECK: xor $3, $3, $5 0x26 0x18 0x65 0x00 # CHECK: xor $3, $3, $5
0x67 0x45 0xc9 0x38 # CHECK: xori $9, $6, 17767 0x67 0x45 0xc9 0x38 # CHECK: xori $9, $6, 17767
0x3b 0xe8 0x05 0x7c # CHECK: .set push 0x3b 0xe8 0x05 0x7c # CHECK: .set push
# CHECK: .set mips32r2 # CHECK: .set mips32r2
Show All 34 Lines

test/MC/Disassembler/Mips/mips64/valid-mips64-xfail.txt

Show First 20 Lines • Show All 67 Lines • ▼ Show 20 Lines
0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12 0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12
0x4d 0x1e 0x87 0xb9 # CHECK: nmsub.d $f30, $f8, $f16, $f30 0x4d 0x1e 0x87 0xb9 # CHECK: nmsub.d $f30, $f8, $f16, $f30
0x4d 0x91 0x71 0xbe # CHECK: nmsub.ps $f6, $f12, $f14, $f17 0x4d 0x91 0x71 0xbe # CHECK: nmsub.ps $f6, $f12, $f14, $f17
0x4f 0x04 0x98 0x78 # CHECK: nmsub.s $f1, $f24, $f19, $f4 0x4f 0x04 0x98 0x78 # CHECK: nmsub.s $f1, $f24, $f19, $f4
0x46 0xde 0x4e 0x6c # CHECK: pll.ps $f25, $f9, $f30 0x46 0xde 0x4e 0x6c # CHECK: pll.ps $f25, $f9, $f30
0x46 0xdd 0xd0 0x6d # CHECK: plu.ps $f1, $f26, $f29 0x46 0xdd 0xd0 0x6d # CHECK: plu.ps $f1, $f26, $f29
0x46 0xda 0xf2 0x6e # CHECK: pul.ps $f9, $f30, $f26 0x46 0xda 0xf2 0x6e # CHECK: pul.ps $f9, $f30, $f26
0x46 0xc2 0x4e 0x2f # CHECK: puu.ps $f24, $f9, $f2 0x46 0xc2 0x4e 0x2f # CHECK: puu.ps $f24, $f9, $f2
0x46 0x20 0x34 0xd5 # CHECK: recip.d $f19, $f6
0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
0x46 0x20 0xe0 0xd6 # CHECK: rsqrt.d $f3, $f28
0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
0x46 0xda 0x71 0x41 # CHECK: sub.ps $f5, $f14, $f26 0x46 0xda 0x71 0x41 # CHECK: sub.ps $f5, $f14, $f26

test/MC/Disassembler/Mips/mips64/valid-mips64.txt

Show First 20 Lines • Show All 325 Lines • ▼ Show 20 Lines
0x46 0x3c 0x11 0x11 # CHECK: movf.d $f4, $f2, $fcc7 0x46 0x3c 0x11 0x11 # CHECK: movf.d $f4, $f2, $fcc7
0x46 0x3c 0x30 0x00 # CHECK: add.d $f0, $f6, $f28 0x46 0x3c 0x30 0x00 # CHECK: add.d $f0, $f6, $f28
0x46 0x3c 0xe0 0x3b # CHECK: c.ngl.d $f28, $f28 0x46 0x3c 0xe0 0x3b # CHECK: c.ngl.d $f28, $f28
0x46 0x3d 0x11 0x11 # CHECK: movt.d $f4, $f2, $fcc7 0x46 0x3d 0x11 0x11 # CHECK: movt.d $f4, $f2, $fcc7
0x46 0x80 0x39 0xa0 # CHECK: cvt.s.w $f6, $f7 0x46 0x80 0x39 0xa0 # CHECK: cvt.s.w $f6, $f7
0x46 0x80 0x5e 0xa1 # CHECK: cvt.d.w $f26, $f11 0x46 0x80 0x5e 0xa1 # CHECK: cvt.d.w $f26, $f11
0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14 0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14
0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15 0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15
0x46 0x20 0x34 0xd5 # CHECK: recip.d $f19, $f6
0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
0x46 0x20 0xe0 0xd6 # CHECK: rsqrt.d $f3, $f28
0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
0x48 0x20 0x50 0x00 # CHECK: dmfc2 $zero, $10, 0 0x48 0x20 0x50 0x00 # CHECK: dmfc2 $zero, $10, 0
0x48 0xa4 0x50 0x00 # CHECK: dmtc2 $4, $10, 0 0x48 0xa4 0x50 0x00 # CHECK: dmtc2 $4, $10, 0
0x4d 0x0c 0xe0 0x21 # CHECK: madd.d $f0, $f8, $f28, $f12 0x4d 0x0c 0xe0 0x21 # CHECK: madd.d $f0, $f8, $f28, $f12
0x4d 0xbb 0x0d 0xe0 # CHECK: madd.s $f23, $f13, $f1, $f27 0x4d 0xbb 0x0d 0xe0 # CHECK: madd.s $f23, $f13, $f1, $f27
0x51 0xd3 0x0c 0x40 # CHECK: beql $14, $19, 12548 0x51 0xd3 0x0c 0x40 # CHECK: beql $14, $19, 12548
0x57 0x94 0x04 0xfc # CHECK: bnel $gp, $20, 5108 0x57 0x94 0x04 0xfc # CHECK: bnel $gp, $20, 5108
0x58 0xc0 0x02 0xe7 # CHECK: blezl $6, 2976 0x58 0xc0 0x02 0xe7 # CHECK: blezl $6, 2976
0x5d 0x40 0xfc 0x59 # CHECK: bgtzl $10, -3736 0x5d 0x40 0xfc 0x59 # CHECK: bgtzl $10, -3736
▲ Show 20 Lines • Show All 106 Lines • Show Last 20 Lines

test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt

Show First 20 Lines • Show All 187 Lines • ▼ Show 20 Lines
0x07 0x73 0x20 0x46 # CHECK: neg.d $f12, $f14 0x07 0x73 0x20 0x46 # CHECK: neg.d $f12, $f14
0x87 0x39 0x00 0x46 # CHECK: neg.s $f6, $f7 0x87 0x39 0x00 0x46 # CHECK: neg.s $f6, $f7
0x30 0xc8 0xac 0x4c # CHECK: nmadd.s $f0, $f5, $f25, $f12 0x30 0xc8 0xac 0x4c # CHECK: nmadd.s $f0, $f5, $f25, $f12
0x00 0x00 0x00 0x00 # CHECK: nop 0x00 0x00 0x00 0x00 # CHECK: nop
0x27 0x48 0xc7 0x00 # CHECK: nor $9, $6, $7 0x27 0x48 0xc7 0x00 # CHECK: nor $9, $6, $7
0x78 0x98 0x04 0x4f # CHECK: nmsub.s $f1, $f24, $f19, $f4 0x78 0x98 0x04 0x4f # CHECK: nmsub.s $f1, $f24, $f19, $f4
0x25 0x18 0x65 0x00 # CHECK: or $3, $3, $5 0x25 0x18 0x65 0x00 # CHECK: or $3, $3, $5
0x67 0x45 0xc9 0x34 # CHECK: ori $9, $6, 17767 0x67 0x45 0xc9 0x34 # CHECK: ori $9, $6, 17767
0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6
0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30
0xc2 0x49 0x26 0x00 # CHECK: rotr $9, $6, 7 0xc2 0x49 0x26 0x00 # CHECK: rotr $9, $6, 7
0x46 0x48 0xe6 0x00 # CHECK: rotrv $9, $6, $7 0x46 0x48 0xe6 0x00 # CHECK: rotrv $9, $6, $7
0x08 0x0b 0x20 0x46 # CHECK: round.l.d $f12, $f1 0x08 0x0b 0x20 0x46 # CHECK: round.l.d $f12, $f1
0x48 0x2e 0x00 0x46 # CHECK: round.l.s $f25, $f5 0x48 0x2e 0x00 0x46 # CHECK: round.l.s $f25, $f5
0x0c 0x73 0x20 0x46 # CHECK: round.w.d $f12, $f14 0x0c 0x73 0x20 0x46 # CHECK: round.w.d $f12, $f14
0x8c 0x39 0x00 0x46 # CHECK: round.w.s $f6, $f7 0x8c 0x39 0x00 0x46 # CHECK: round.w.s $f6, $f7
0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28
0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8
0xc6 0x23 0xa4 0xa0 # CHECK: sb $4, 9158($5) 0xc6 0x23 0xa4 0xa0 # CHECK: sb $4, 9158($5)
0x06 0x00 0xa4 0xa0 # CHECK: sb $4, 6($5) 0x06 0x00 0xa4 0xa0 # CHECK: sb $4, 6($5)
0xc6 0x23 0xe9 0xe0 # CHECK: sc $9, 9158($7) 0xc6 0x23 0xe9 0xe0 # CHECK: sc $9, 9158($7)
0xcd 0xdf 0xaf 0xf3 # CHECK: scd $15, -8243($sp) 0xcd 0xdf 0xaf 0xf3 # CHECK: scd $15, -8243($sp)
0xcb 0x16 0x4c 0xfd # CHECK: sd $12, 5835($10) 0xcb 0x16 0x4c 0xfd # CHECK: sd $12, 5835($10)
0xc6 0x23 0xe9 0xf4 # CHECK: sdc1 $f9, 9158($7) 0xc6 0x23 0xe9 0xf4 # CHECK: sdc1 $f9, 9158($7)
0x1f 0xae 0xc7 0xb3 # CHECK: sdl $7, -20961($fp) 0x1f 0xae 0xc7 0xb3 # CHECK: sdl $7, -20961($fp)
0x39 0xb0 0x8b 0xb5 # CHECK: sdr $11, -20423($12) 0x39 0xb0 0x8b 0xb5 # CHECK: sdr $11, -20423($12)
▲ Show 20 Lines • Show All 64 Lines • Show Last 20 Lines

test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt

Show First 20 Lines • Show All 357 Lines • ▼ Show 20 Lines
0x4d 0x0c 0xe0 0x21 # CHECK: madd.d $f0, $f8, $f28, $f12 0x4d 0x0c 0xe0 0x21 # CHECK: madd.d $f0, $f8, $f28, $f12
0x4d 0xbb 0x0d 0xe0 # CHECK: madd.s $f23, $f13, $f1, $f27 0x4d 0xbb 0x0d 0xe0 # CHECK: madd.s $f23, $f13, $f1, $f27
0x51 0xd3 0x0c 0x40 # CHECK: beql $14, $19, 12548 0x51 0xd3 0x0c 0x40 # CHECK: beql $14, $19, 12548
0x57 0x94 0x04 0xfc # CHECK: bnel $gp, $20, 5108 0x57 0x94 0x04 0xfc # CHECK: bnel $gp, $20, 5108
0x58 0xc0 0x02 0xe7 # CHECK: blezl $6, 2976 0x58 0xc0 0x02 0xe7 # CHECK: blezl $6, 2976
0x5d 0x40 0xfc 0x59 # CHECK: bgtzl $10, -3736 0x5d 0x40 0xfc 0x59 # CHECK: bgtzl $10, -3736
0x46 0xa0 0x81 0x21 # CHECK: cvt.d.l $f4, $f16 0x46 0xa0 0x81 0x21 # CHECK: cvt.d.l $f4, $f16
0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30 0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30
0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
0x4c 0xa6 0x00 0x05 # CHECK: luxc1 $f0, $6($5) 0x4c 0xa6 0x00 0x05 # CHECK: luxc1 $f0, $6($5)
0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12 0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12
0x4c 0xb8 0x20 0x0d # CHECK: suxc1 $f4, $24($5) 0x4c 0xb8 0x20 0x0d # CHECK: suxc1 $f4, $24($5)
0x4d 0x42 0x00 0x81 # CHECK: ldxc1 $f2, $2($10) 0x4d 0x42 0x00 0x81 # CHECK: ldxc1 $f2, $2($10)
0x4d 0xbb 0x60 0x0d # CHECK: suxc1 $f12, $27($13) 0x4d 0xbb 0x60 0x0d # CHECK: suxc1 $f12, $27($13)
0x4d 0xca 0x58 0x09 # CHECK: sdxc1 $f11, $10($14) 0x4d 0xca 0x58 0x09 # CHECK: sdxc1 $f11, $10($14)
0x4d 0xcc 0x05 0x00 # CHECK: lwxc1 $f20, $12($14) 0x4d 0xcc 0x05 0x00 # CHECK: lwxc1 $f20, $12($14)
0x4d 0xf7 0x02 0x01 # CHECK: ldxc1 $f8, $23($15) 0x4d 0xf7 0x02 0x01 # CHECK: ldxc1 $f8, $23($15)
▲ Show 20 Lines • Show All 112 Lines • Show Last 20 Lines

test/MC/Disassembler/Mips/mips64r2/valid-xfail-mips64r2.txt

Show First 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
0x4c 0x98 0x46 0xb6 # CHECK: nmadd.ps $f26, $f4, $f8, $f24 0x4c 0x98 0x46 0xb6 # CHECK: nmadd.ps $f26, $f4, $f8, $f24
0x4d 0x1e 0x87 0xb9 # CHECK: nmsub.d $f30, $f8, $f16, $f30 0x4d 0x1e 0x87 0xb9 # CHECK: nmsub.d $f30, $f8, $f16, $f30
0x4d 0x90 0x71 0xbe # CHECK: nmsub.ps $f6, $f12, $f14, $f16 0x4d 0x90 0x71 0xbe # CHECK: nmsub.ps $f6, $f12, $f14, $f16
0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30 0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30
0x46 0xdc 0xd0 0x2d # CHECK: plu.ps $f0, $f26, $f28 0x46 0xdc 0xd0 0x2d # CHECK: plu.ps $f0, $f26, $f28
0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26 0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26
0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2 0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2
0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1 0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1
0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5 0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26 0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26
0x41 0xcd 0x00 0x00 # CHECK: wrpgpr zero, t5 0x41 0xcd 0x00 0x00 # CHECK: wrpgpr zero, t5

test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt

Show First 20 Lines • Show All 184 Lines • ▼ Show 20 Lines
0x07 0x73 0x20 0x46 # CHECK: neg.d $f12, $f14 0x07 0x73 0x20 0x46 # CHECK: neg.d $f12, $f14
0x87 0x39 0x00 0x46 # CHECK: neg.s $f6, $f7 0x87 0x39 0x00 0x46 # CHECK: neg.s $f6, $f7
0x30 0xc8 0xac 0x4c # CHECK: nmadd.s $f0, $f5, $f25, $f12 0x30 0xc8 0xac 0x4c # CHECK: nmadd.s $f0, $f5, $f25, $f12
0x00 0x00 0x00 0x00 # CHECK: nop 0x00 0x00 0x00 0x00 # CHECK: nop
0x27 0x48 0xc7 0x00 # CHECK: nor $9, $6, $7 0x27 0x48 0xc7 0x00 # CHECK: nor $9, $6, $7
0x78 0x98 0x04 0x4f # CHECK: nmsub.s $f1, $f24, $f19, $f4 0x78 0x98 0x04 0x4f # CHECK: nmsub.s $f1, $f24, $f19, $f4
0x25 0x18 0x65 0x00 # CHECK: or $3, $3, $5 0x25 0x18 0x65 0x00 # CHECK: or $3, $3, $5
0x67 0x45 0xc9 0x34 # CHECK: ori $9, $6, 17767 0x67 0x45 0xc9 0x34 # CHECK: ori $9, $6, 17767
0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6
0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30
0xc2 0x49 0x26 0x00 # CHECK: rotr $9, $6, 7 0xc2 0x49 0x26 0x00 # CHECK: rotr $9, $6, 7
0x46 0x48 0xe6 0x00 # CHECK: rotrv $9, $6, $7 0x46 0x48 0xe6 0x00 # CHECK: rotrv $9, $6, $7
0x08 0x0b 0x20 0x46 # CHECK: round.l.d $f12, $f1 0x08 0x0b 0x20 0x46 # CHECK: round.l.d $f12, $f1
0x48 0x2e 0x00 0x46 # CHECK: round.l.s $f25, $f5 0x48 0x2e 0x00 0x46 # CHECK: round.l.s $f25, $f5
0x0c 0x73 0x20 0x46 # CHECK: round.w.d $f12, $f14 0x0c 0x73 0x20 0x46 # CHECK: round.w.d $f12, $f14
0x8c 0x39 0x00 0x46 # CHECK: round.w.s $f6, $f7 0x8c 0x39 0x00 0x46 # CHECK: round.w.s $f6, $f7
0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28
0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8
0xc6 0x23 0xa4 0xa0 # CHECK: sb $4, 9158($5) 0xc6 0x23 0xa4 0xa0 # CHECK: sb $4, 9158($5)
0x06 0x00 0xa4 0xa0 # CHECK: sb $4, 6($5) 0x06 0x00 0xa4 0xa0 # CHECK: sb $4, 6($5)
0xc6 0x23 0xe9 0xe0 # CHECK: sc $9, 9158($7) 0xc6 0x23 0xe9 0xe0 # CHECK: sc $9, 9158($7)
0xcd 0xdf 0xaf 0xf3 # CHECK: scd $15, -8243($sp) 0xcd 0xdf 0xaf 0xf3 # CHECK: scd $15, -8243($sp)
0xcb 0x16 0x4c 0xfd # CHECK: sd $12, 5835($10) 0xcb 0x16 0x4c 0xfd # CHECK: sd $12, 5835($10)
0xc6 0x23 0xe9 0xf4 # CHECK: sdc1 $f9, 9158($7) 0xc6 0x23 0xe9 0xf4 # CHECK: sdc1 $f9, 9158($7)
0x1f 0xae 0xc7 0xb3 # CHECK: sdl $7, -20961($fp) 0x1f 0xae 0xc7 0xb3 # CHECK: sdl $7, -20961($fp)
0x39 0xb0 0x8b 0xb5 # CHECK: sdr $11, -20423($12) 0x39 0xb0 0x8b 0xb5 # CHECK: sdr $11, -20423($12)
Show All 34 Lines

test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt

Show First 20 Lines • Show All 345 Lines • ▼ Show 20 Lines
0x46 0x3c 0x11 0x11 # CHECK: movf.d $f4, $f2, $fcc7 0x46 0x3c 0x11 0x11 # CHECK: movf.d $f4, $f2, $fcc7
0x46 0x3c 0x30 0x00 # CHECK: add.d $f0, $f6, $f28 0x46 0x3c 0x30 0x00 # CHECK: add.d $f0, $f6, $f28
0x46 0x3c 0xe0 0x3b # CHECK: c.ngl.d $f28, $f28 0x46 0x3c 0xe0 0x3b # CHECK: c.ngl.d $f28, $f28
0x46 0x3d 0x11 0x11 # CHECK: movt.d $f4, $f2, $fcc7 0x46 0x3d 0x11 0x11 # CHECK: movt.d $f4, $f2, $fcc7
0x46 0x80 0x39 0xa0 # CHECK: cvt.s.w $f6, $f7 0x46 0x80 0x39 0xa0 # CHECK: cvt.s.w $f6, $f7
0x46 0x80 0x5e 0xa1 # CHECK: cvt.d.w $f26, $f11 0x46 0x80 0x5e 0xa1 # CHECK: cvt.d.w $f26, $f11
0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14 0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14
0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15 0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15
0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
0x48 0x20 0x50 0x00 # CHECK: dmfc2 $zero, $10, 0 0x48 0x20 0x50 0x00 # CHECK: dmfc2 $zero, $10, 0
0x48 0xa4 0x50 0x00 # CHECK: dmtc2 $4, $10, 0 0x48 0xa4 0x50 0x00 # CHECK: dmtc2 $4, $10, 0
0x4d 0x0c 0xe0 0x21 # CHECK: madd.d $f0, $f8, $f28, $f12 0x4d 0x0c 0xe0 0x21 # CHECK: madd.d $f0, $f8, $f28, $f12
0x4d 0xbb 0x0d 0xe0 # CHECK: madd.s $f23, $f13, $f1, $f27 0x4d 0xbb 0x0d 0xe0 # CHECK: madd.s $f23, $f13, $f1, $f27
0x51 0xd3 0x0c 0x40 # CHECK: beql $14, $19, 12548 0x51 0xd3 0x0c 0x40 # CHECK: beql $14, $19, 12548
0x57 0x94 0x04 0xfc # CHECK: bnel $gp, $20, 5108 0x57 0x94 0x04 0xfc # CHECK: bnel $gp, $20, 5108
0x58 0xc0 0x02 0xe7 # CHECK: blezl $6, 2976 0x58 0xc0 0x02 0xe7 # CHECK: blezl $6, 2976
0x5d 0x40 0xfc 0x59 # CHECK: bgtzl $10, -3736 0x5d 0x40 0xfc 0x59 # CHECK: bgtzl $10, -3736
0x46 0xa0 0x81 0x21 # CHECK: cvt.d.l $f4, $f16 0x46 0xa0 0x81 0x21 # CHECK: cvt.d.l $f4, $f16
0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30 0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30
▲ Show 20 Lines • Show All 120 Lines • Show Last 20 Lines

test/MC/Disassembler/Mips/mips64r3/valid-xfail-mips64r3.txt

Show First 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
0x4c 0x98 0x46 0xb6 # CHECK: nmadd.ps $f26, $f4, $f8, $f24 0x4c 0x98 0x46 0xb6 # CHECK: nmadd.ps $f26, $f4, $f8, $f24
0x4d 0x1e 0x87 0xb9 # CHECK: nmsub.d $f30, $f8, $f16, $f30 0x4d 0x1e 0x87 0xb9 # CHECK: nmsub.d $f30, $f8, $f16, $f30
0x4d 0x90 0x71 0xbe # CHECK: nmsub.ps $f6, $f12, $f14, $f16 0x4d 0x90 0x71 0xbe # CHECK: nmsub.ps $f6, $f12, $f14, $f16
0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30 0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30
0x46 0xdc 0xd0 0x2d # CHECK: plu.ps $f0, $f26, $f28 0x46 0xdc 0xd0 0x2d # CHECK: plu.ps $f0, $f26, $f28
0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26 0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26
0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2 0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2
0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1 0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1
0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5 0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26 0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26
0x41 0xcd 0x00 0x00 # CHECK: wrpgpr zero, t5 0x41 0xcd 0x00 0x00 # CHECK: wrpgpr zero, t5

test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt

Show First 20 Lines • Show All 184 Lines • ▼ Show 20 Lines
0x07 0x73 0x20 0x46 # CHECK: neg.d $f12, $f14 0x07 0x73 0x20 0x46 # CHECK: neg.d $f12, $f14
0x87 0x39 0x00 0x46 # CHECK: neg.s $f6, $f7 0x87 0x39 0x00 0x46 # CHECK: neg.s $f6, $f7
0x30 0xc8 0xac 0x4c # CHECK: nmadd.s $f0, $f5, $f25, $f12 0x30 0xc8 0xac 0x4c # CHECK: nmadd.s $f0, $f5, $f25, $f12
0x00 0x00 0x00 0x00 # CHECK: nop 0x00 0x00 0x00 0x00 # CHECK: nop
0x27 0x48 0xc7 0x00 # CHECK: nor $9, $6, $7 0x27 0x48 0xc7 0x00 # CHECK: nor $9, $6, $7
0x78 0x98 0x04 0x4f # CHECK: nmsub.s $f1, $f24, $f19, $f4 0x78 0x98 0x04 0x4f # CHECK: nmsub.s $f1, $f24, $f19, $f4
0x25 0x18 0x65 0x00 # CHECK: or $3, $3, $5 0x25 0x18 0x65 0x00 # CHECK: or $3, $3, $5
0x67 0x45 0xc9 0x34 # CHECK: ori $9, $6, 17767 0x67 0x45 0xc9 0x34 # CHECK: ori $9, $6, 17767
0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6
0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30
0xc2 0x49 0x26 0x00 # CHECK: rotr $9, $6, 7 0xc2 0x49 0x26 0x00 # CHECK: rotr $9, $6, 7
0x46 0x48 0xe6 0x00 # CHECK: rotrv $9, $6, $7 0x46 0x48 0xe6 0x00 # CHECK: rotrv $9, $6, $7
0x08 0x0b 0x20 0x46 # CHECK: round.l.d $f12, $f1 0x08 0x0b 0x20 0x46 # CHECK: round.l.d $f12, $f1
0x48 0x2e 0x00 0x46 # CHECK: round.l.s $f25, $f5 0x48 0x2e 0x00 0x46 # CHECK: round.l.s $f25, $f5
0x0c 0x73 0x20 0x46 # CHECK: round.w.d $f12, $f14 0x0c 0x73 0x20 0x46 # CHECK: round.w.d $f12, $f14
0x8c 0x39 0x00 0x46 # CHECK: round.w.s $f6, $f7 0x8c 0x39 0x00 0x46 # CHECK: round.w.s $f6, $f7
0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28
0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8
0xc6 0x23 0xa4 0xa0 # CHECK: sb $4, 9158($5) 0xc6 0x23 0xa4 0xa0 # CHECK: sb $4, 9158($5)
0x06 0x00 0xa4 0xa0 # CHECK: sb $4, 6($5) 0x06 0x00 0xa4 0xa0 # CHECK: sb $4, 6($5)
0xc6 0x23 0xe9 0xe0 # CHECK: sc $9, 9158($7) 0xc6 0x23 0xe9 0xe0 # CHECK: sc $9, 9158($7)
0xcd 0xdf 0xaf 0xf3 # CHECK: scd $15, -8243($sp) 0xcd 0xdf 0xaf 0xf3 # CHECK: scd $15, -8243($sp)
0xcb 0x16 0x4c 0xfd # CHECK: sd $12, 5835($10) 0xcb 0x16 0x4c 0xfd # CHECK: sd $12, 5835($10)
0xc6 0x23 0xe9 0xf4 # CHECK: sdc1 $f9, 9158($7) 0xc6 0x23 0xe9 0xf4 # CHECK: sdc1 $f9, 9158($7)
0x1f 0xae 0xc7 0xb3 # CHECK: sdl $7, -20961($fp) 0x1f 0xae 0xc7 0xb3 # CHECK: sdl $7, -20961($fp)
0x39 0xb0 0x8b 0xb5 # CHECK: sdr $11, -20423($12) 0x39 0xb0 0x8b 0xb5 # CHECK: sdr $11, -20423($12)
Show All 34 Lines

test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt

Show First 20 Lines • Show All 345 Lines • ▼ Show 20 Lines
0x46 0x3c 0x11 0x11 # CHECK: movf.d $f4, $f2, $fcc7 0x46 0x3c 0x11 0x11 # CHECK: movf.d $f4, $f2, $fcc7
0x46 0x3c 0x30 0x00 # CHECK: add.d $f0, $f6, $f28 0x46 0x3c 0x30 0x00 # CHECK: add.d $f0, $f6, $f28
0x46 0x3c 0xe0 0x3b # CHECK: c.ngl.d $f28, $f28 0x46 0x3c 0xe0 0x3b # CHECK: c.ngl.d $f28, $f28
0x46 0x3d 0x11 0x11 # CHECK: movt.d $f4, $f2, $fcc7 0x46 0x3d 0x11 0x11 # CHECK: movt.d $f4, $f2, $fcc7
0x46 0x80 0x39 0xa0 # CHECK: cvt.s.w $f6, $f7 0x46 0x80 0x39 0xa0 # CHECK: cvt.s.w $f6, $f7
0x46 0x80 0x5e 0xa1 # CHECK: cvt.d.w $f26, $f11 0x46 0x80 0x5e 0xa1 # CHECK: cvt.d.w $f26, $f11
0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14 0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14
0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15 0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15
0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
0x48 0x20 0x50 0x00 # CHECK: dmfc2 $zero, $10, 0 0x48 0x20 0x50 0x00 # CHECK: dmfc2 $zero, $10, 0
0x48 0xa4 0x50 0x00 # CHECK: dmtc2 $4, $10, 0 0x48 0xa4 0x50 0x00 # CHECK: dmtc2 $4, $10, 0
0x4d 0x0c 0xe0 0x21 # CHECK: madd.d $f0, $f8, $f28, $f12 0x4d 0x0c 0xe0 0x21 # CHECK: madd.d $f0, $f8, $f28, $f12
0x4d 0xbb 0x0d 0xe0 # CHECK: madd.s $f23, $f13, $f1, $f27 0x4d 0xbb 0x0d 0xe0 # CHECK: madd.s $f23, $f13, $f1, $f27
0x51 0xd3 0x0c 0x40 # CHECK: beql $14, $19, 12548 0x51 0xd3 0x0c 0x40 # CHECK: beql $14, $19, 12548
0x57 0x94 0x04 0xfc # CHECK: bnel $gp, $20, 5108 0x57 0x94 0x04 0xfc # CHECK: bnel $gp, $20, 5108
0x58 0xc0 0x02 0xe7 # CHECK: blezl $6, 2976 0x58 0xc0 0x02 0xe7 # CHECK: blezl $6, 2976
0x5d 0x40 0xfc 0x59 # CHECK: bgtzl $10, -3736 0x5d 0x40 0xfc 0x59 # CHECK: bgtzl $10, -3736
▲ Show 20 Lines • Show All 123 Lines • Show Last 20 Lines

test/MC/Disassembler/Mips/mips64r5/valid-xfail-mips64r5.txt

Show First 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
0x4c 0x98 0x46 0xb6 # CHECK: nmadd.ps $f26, $f4, $f8, $f24 0x4c 0x98 0x46 0xb6 # CHECK: nmadd.ps $f26, $f4, $f8, $f24
0x4d 0x1e 0x87 0xb9 # CHECK: nmsub.d $f30, $f8, $f16, $f30 0x4d 0x1e 0x87 0xb9 # CHECK: nmsub.d $f30, $f8, $f16, $f30
0x4d 0x90 0x71 0xbe # CHECK: nmsub.ps $f6, $f12, $f14, $f16 0x4d 0x90 0x71 0xbe # CHECK: nmsub.ps $f6, $f12, $f14, $f16
0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30 0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30
0x46 0xdc 0xd0 0x2d # CHECK: plu.ps $f0, $f26, $f28 0x46 0xdc 0xd0 0x2d # CHECK: plu.ps $f0, $f26, $f28
0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26 0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26
0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2 0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2
0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1 0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1
0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5 0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26 0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26
0x41 0xcd 0x00 0x00 # CHECK: wrpgpr zero, t5 0x41 0xcd 0x00 0x00 # CHECK: wrpgpr zero, t5

test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt

Show First 20 Lines • Show All 150 Lines • ▼ Show 20 Lines
0x99 0x18 0x24 0x46 # CHECK: msubf.d $f2, $f3, $f4 0x99 0x18 0x24 0x46 # CHECK: msubf.d $f2, $f3, $f4
0x99 0x18 0x04 0x46 # CHECK: msubf.s $f2, $f3, $f4 0x99 0x18 0x04 0x46 # CHECK: msubf.s $f2, $f3, $f4
0xd8 0x10 0x64 0x00 # CHECK: muh $2, $3, $4 0xd8 0x10 0x64 0x00 # CHECK: muh $2, $3, $4
0xd9 0x10 0x64 0x00 # CHECK: muhu $2, $3, $4 0xd9 0x10 0x64 0x00 # CHECK: muhu $2, $3, $4
0x98 0x10 0x64 0x00 # CHECK: mul $2, $3, $4 0x98 0x10 0x64 0x00 # CHECK: mul $2, $3, $4
0x99 0x10 0x64 0x00 # CHECK: mulu $2, $3, $4 0x99 0x10 0x64 0x00 # CHECK: mulu $2, $3, $4
0x04 0x00 0x42 0x34 # CHECK: ori $2, $2, 4 0x04 0x00 0x42 0x34 # CHECK: ori $2, $2, 4
0x35 0x04 0xa1 0x7c # CHECK: pref 1, 8($5) 0x35 0x04 0xa1 0x7c # CHECK: pref 1, 8($5)
0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6
0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30
0x9a 0x20 0x20 0x46 # CHECK: rint.d $f2, $f4 0x9a 0x20 0x20 0x46 # CHECK: rint.d $f2, $f4
0x9a 0x20 0x00 0x46 # CHECK: rint.s $f2, $f4 0x9a 0x20 0x00 0x46 # CHECK: rint.s $f2, $f4
0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28
0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8
0x26 0xec 0x6f 0x7e # CHECK: sc $15, -40($19) 0x26 0xec 0x6f 0x7e # CHECK: sc $15, -40($19)
0xa7 0xe6 0xaf 0x7f # CHECK: scd $15, -51($sp) 0xa7 0xe6 0xaf 0x7f # CHECK: scd $15, -51($sp)
0x0e 0x00 0x00 0x00 # CHECK: sdbbp 0x0e 0x00 0x00 0x00 # CHECK: sdbbp
0x8e 0x08 0x00 0x00 # CHECK: sdbbp 34 0x8e 0x08 0x00 0x00 # CHECK: sdbbp 34
0x75 0x92 0xf4 0x49 # CHECK: sdc2 $20, 629($18) 0x75 0x92 0xf4 0x49 # CHECK: sdc2 $20, 629($18)
0x10 0x08 0x22 0x46 # CHECK: sel.d $f0, $f1, $f2 0x10 0x08 0x22 0x46 # CHECK: sel.d $f0, $f1, $f2
0x10 0x08 0x02 0x46 # CHECK: sel.s $f0, $f1, $f2 0x10 0x08 0x02 0x46 # CHECK: sel.s $f0, $f1, $f2
0x35 0x10 0x64 0x00 # CHECK: seleqz $2, $3, $4 0x35 0x10 0x64 0x00 # CHECK: seleqz $2, $3, $4
Show All 21 Lines

test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt

Show First 20 Lines • Show All 147 Lines • ▼ Show 20 Lines
0x46 0xa4 0x18 0x88 # CHECK: cmp.saf.d $f2, $f3, $f4 0x46 0xa4 0x18 0x88 # CHECK: cmp.saf.d $f2, $f3, $f4
0x46 0xa4 0x18 0x89 # CHECK: cmp.sun.d $f2, $f3, $f4 0x46 0xa4 0x18 0x89 # CHECK: cmp.sun.d $f2, $f3, $f4
0x46 0xa4 0x18 0x8a # CHECK: cmp.seq.d $f2, $f3, $f4 0x46 0xa4 0x18 0x8a # CHECK: cmp.seq.d $f2, $f3, $f4
0x46 0xa4 0x18 0x8b # CHECK: cmp.sueq.d $f2, $f3, $f4 0x46 0xa4 0x18 0x8b # CHECK: cmp.sueq.d $f2, $f3, $f4
0x46 0xa4 0x18 0x8c # CHECK: cmp.slt.d $f2, $f3, $f4 0x46 0xa4 0x18 0x8c # CHECK: cmp.slt.d $f2, $f3, $f4
0x46 0xa4 0x18 0x8d # CHECK: cmp.sult.d $f2, $f3, $f4 0x46 0xa4 0x18 0x8d # CHECK: cmp.sult.d $f2, $f3, $f4
0x46 0xa4 0x18 0x8e # CHECK: cmp.sle.d $f2, $f3, $f4 0x46 0xa4 0x18 0x8e # CHECK: cmp.sle.d $f2, $f3, $f4
0x46 0xa4 0x18 0x8f # CHECK: cmp.sule.d $f2, $f3, $f4 0x46 0xa4 0x18 0x8f # CHECK: cmp.sule.d $f2, $f3, $f4
0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
0x42 0x00 0x00 0x58 # CHECK: eretnc 0x42 0x00 0x00 0x58 # CHECK: eretnc
# FIXME: The encode/decode functions are not inverses of each other. # FIXME: The encode/decode functions are not inverses of each other.
# The immediate should be 8 but the disassembler currently emits 12 # The immediate should be 8 but the disassembler currently emits 12
0x49 0x20 0x00 0x02 # CHECK: bc2eqz $0, 12 0x49 0x20 0x00 0x02 # CHECK: bc2eqz $0, 12
# FIXME: The encode/decode functions are not inverses of each other. # FIXME: The encode/decode functions are not inverses of each other.
# The immediate should be 8 but the disassembler currently emits 12 # The immediate should be 8 but the disassembler currently emits 12
0x49 0x3f 0x00 0x02 # CHECK: bc2eqz $31, 12 0x49 0x3f 0x00 0x02 # CHECK: bc2eqz $31, 12
0x49 0x52 0x34 0xb7 # CHECK: lwc2 $18, -841($6) 0x49 0x52 0x34 0xb7 # CHECK: lwc2 $18, -841($6)
▲ Show 20 Lines • Show All 53 Lines • Show Last 20 Lines

test/MC/Mips/micromips/valid.s

Show First 20 Lines • Show All 197 Lines • ▼ Show 20 Lines
sdc1 $f2, 4($6) # CHECK: sdc1 $f2, 4($6) # encoding: [0xb8,0x46,0x00,0x04] sdc1 $f2, 4($6) # CHECK: sdc1 $f2, 4($6) # encoding: [0xb8,0x46,0x00,0x04]
# FIXME: sdc1 should accept uneven registers # FIXME: sdc1 should accept uneven registers
# sdc1 $f7, 64($10) # -CHECK: sdc1 $f7, 64($10) # encoding: [0xb8,0xea,0x00,0x40] # sdc1 $f7, 64($10) # -CHECK: sdc1 $f7, 64($10) # encoding: [0xb8,0xea,0x00,0x40]
swc1 $f2, 4($6) # CHECK: swc1 $f2, 4($6) # encoding: [0x98,0x46,0x00,0x04] swc1 $f2, 4($6) # CHECK: swc1 $f2, 4($6) # encoding: [0x98,0x46,0x00,0x04]
cfc1 $1, $2 # CHECK: cfc1 $1, $2 # encoding: [0x54,0x22,0x10,0x3b] cfc1 $1, $2 # CHECK: cfc1 $1, $2 # encoding: [0x54,0x22,0x10,0x3b]
cfc2 $3, $4 # CHECK: cfc2 $3, $4 # encoding: [0x00,0x64,0xcd,0x3c] cfc2 $3, $4 # CHECK: cfc2 $3, $4 # encoding: [0x00,0x64,0xcd,0x3c]
ctc1 $5, $6 # CHECK: ctc1 $5, $6 # encoding: [0x54,0xa6,0x18,0x3b] ctc1 $5, $6 # CHECK: ctc1 $5, $6 # encoding: [0x54,0xa6,0x18,0x3b]
ctc2 $7, $8 # CHECK: ctc2 $7, $8 # encoding: [0x00,0xe8,0xdd,0x3c] ctc2 $7, $8 # CHECK: ctc2 $7, $8 # encoding: [0x00,0xe8,0xdd,0x3c]
recip.s $f2, $f4 # CHECK: recip.s $f2, $f4 # encoding: [0x54,0x44,0x12,0x3b]
recip.d $f2, $f4 # CHECK: recip.d $f2, $f4 # encoding: [0x54,0x44,0x52,0x3b]
rsqrt.s $f3, $f5 # CHECK: rsqrt.s $f3, $f5 # encoding: [0x54,0x65,0x02,0x3b]
rsqrt.d $f2, $f4 # CHECK: rsqrt.d $f2, $f4 # encoding: [0x54,0x44,0x42,0x3b]

test/MC/Mips/mips32r2/valid-xfail.s

Show First 20 Lines • Show All 96 Lines • ▼ Show 20 Lines# XFAIL: *
nmsub.ps $f6,$f12,$f14,$f17 nmsub.ps $f6,$f12,$f14,$f17
pll.ps $f25,$f9,$f30 pll.ps $f25,$f9,$f30
plu.ps $f1,$f26,$f29 plu.ps $f1,$f26,$f29
preceq.w.phl $s8,$gp preceq.w.phl $s8,$gp
preceq.w.phr $s5,$15 preceq.w.phr $s5,$15
pul.ps $f9,$f30,$f26 pul.ps $f9,$f30,$f26
puu.ps $f24,$f9,$f2 puu.ps $f24,$f9,$f2
rdpgpr $s3,$9 rdpgpr $s3,$9
recip.d $f19,$f6
recip.s $f3,$f30
rorv $13,$a3,$s5 rorv $13,$a3,$s5
round.l.d $f12,$f1 round.l.d $f12,$f1
round.l.s $f25,$f5 round.l.s $f25,$f5
rsqrt.d $f3,$f28
rsqrt.s $f4,$f8
sbe $s7,33($s1) sbe $s7,33($s1)
sce $sp,189($10) sce $sp,189($10)
she $24,105($v0) she $24,105($v0)
sub.ps $f5,$f14,$f26 sub.ps $f5,$f14,$f26
swe $24,94($k0) swe $24,94($k0)
swle $v1,-209($gp) swle $v1,-209($gp)
swre $k0,-202($s2) swre $k0,-202($s2)
tlbginv tlbginv
Show All 11 Lines

test/MC/Mips/mips32r2/valid.s

Show First 20 Lines • Show All 161 Lines • ▼ Show 20 Linesa:
pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40] pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40]
pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08] pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08]
# FIXME: Use the code generator in order to print the .set directives # FIXME: Use the code generator in order to print the .set directives
# instead of the instruction printer. # instead of the instruction printer.
rdhwr $sp,$11 # CHECK: .set push rdhwr $sp,$11 # CHECK: .set push
# CHECK-NEXT: .set mips32r2 # CHECK-NEXT: .set mips32r2
# CHECK-NEXT: rdhwr $sp, $11 # CHECK-NEXT: rdhwr $sp, $11
# CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b] # CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b]
recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5]
recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5]
rotr $1,15 # CHECK: rotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xc2] rotr $1,15 # CHECK: rotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xc2]
rotr $1,$14,15 # CHECK: rotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xc2] rotr $1,$14,15 # CHECK: rotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xc2]
rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46] rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46]
round.w.d $f6,$f4 round.w.d $f6,$f4
round.w.s $f27,$f28 round.w.s $f27,$f28
rsqrt.s $f0,$f4 # CHECK: rsqrt.s $f0, $f4 # encoding: [0x46,0x00,0x20,0x16]
rsqrt.d $f2,$f6 # CHECK: rsqrt.d $f2, $f6 # encoding: [0x46,0x20,0x30,0x96]
s.s $f2, 8($3) # CHECK: swc1 $f2, 8($3) # encoding: [0xe4,0x62,0x00,0x08] s.s $f2, 8($3) # CHECK: swc1 $f2, 8($3) # encoding: [0xe4,0x62,0x00,0x08]
s.d $f2, 8($3) # CHECK: sdc1 $f2, 8($3) # encoding: [0xf4,0x62,0x00,0x08] s.d $f2, 8($3) # CHECK: sdc1 $f2, 8($3) # encoding: [0xf4,0x62,0x00,0x08]
sb $s6,-19857($14) sb $s6,-19857($14)
sc $15,18904($s3) # CHECK: sc $15, 18904($19) # encoding: [0xe2,0x6f,0x49,0xd8] sc $15,18904($s3) # CHECK: sc $15, 18904($19) # encoding: [0xe2,0x6f,0x49,0xd8]
sdbbp # CHECK: sdbbp # encoding: [0x70,0x00,0x00,0x3f] sdbbp # CHECK: sdbbp # encoding: [0x70,0x00,0x00,0x3f]
sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x70,0x00,0x08,0xbf] sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x70,0x00,0x08,0xbf]
sdc1 $f31,30574($13) sdc1 $f31,30574($13)
sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75] sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75]
▲ Show 20 Lines • Show All 104 Lines • Show Last 20 Lines

test/MC/Mips/mips32r3/valid-xfail.s

Show First 20 Lines • Show All 96 Lines • ▼ Show 20 Lines# XFAIL: *
nmsub.ps $f6,$f12,$f14,$f17 nmsub.ps $f6,$f12,$f14,$f17
pll.ps $f25,$f9,$f30 pll.ps $f25,$f9,$f30
plu.ps $f1,$f26,$f29 plu.ps $f1,$f26,$f29
preceq.w.phl $s8,$gp preceq.w.phl $s8,$gp
preceq.w.phr $s5,$15 preceq.w.phr $s5,$15
pul.ps $f9,$f30,$f26 pul.ps $f9,$f30,$f26
puu.ps $f24,$f9,$f2 puu.ps $f24,$f9,$f2
rdpgpr $s3,$9 rdpgpr $s3,$9
recip.d $f19,$f6
recip.s $f3,$f30
rorv $13,$a3,$s5 rorv $13,$a3,$s5
round.l.d $f12,$f1 round.l.d $f12,$f1
round.l.s $f25,$f5 round.l.s $f25,$f5
rsqrt.d $f3,$f28
rsqrt.s $f4,$f8
sbe $s7,33($s1) sbe $s7,33($s1)
sce $sp,189($10) sce $sp,189($10)
she $24,105($v0) she $24,105($v0)
sub.ps $f5,$f14,$f26 sub.ps $f5,$f14,$f26
swe $24,94($k0) swe $24,94($k0)
swle $v1,-209($gp) swle $v1,-209($gp)
swre $k0,-202($s2) swre $k0,-202($s2)
tlbginv tlbginv
Show All 11 Lines

test/MC/Mips/mips32r3/valid.s

Show First 20 Lines • Show All 161 Lines • ▼ Show 20 Linesa:
pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40] pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40]
pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08] pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08]
# FIXME: Use the code generator in order to print the .set directives # FIXME: Use the code generator in order to print the .set directives
# instead of the instruction printer. # instead of the instruction printer.
rdhwr $sp,$11 # CHECK: .set push rdhwr $sp,$11 # CHECK: .set push
# CHECK-NEXT: .set mips32r2 # CHECK-NEXT: .set mips32r2
# CHECK-NEXT: rdhwr $sp, $11 # CHECK-NEXT: rdhwr $sp, $11
# CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b] # CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b]
recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5]
recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5]
rotr $1,15 # CHECK: rotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xc2] rotr $1,15 # CHECK: rotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xc2]
rotr $1,$14,15 # CHECK: rotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xc2] rotr $1,$14,15 # CHECK: rotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xc2]
rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46] rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46]
round.w.d $f6,$f4 round.w.d $f6,$f4
round.w.s $f27,$f28 round.w.s $f27,$f28
rsqrt.s $f0,$f4 # CHECK: rsqrt.s $f0, $f4 # encoding: [0x46,0x00,0x20,0x16]
rsqrt.d $f2,$f6 # CHECK: rsqrt.d $f2, $f6 # encoding: [0x46,0x20,0x30,0x96]
s.s $f2, 8($3) # CHECK: swc1 $f2, 8($3) # encoding: [0xe4,0x62,0x00,0x08] s.s $f2, 8($3) # CHECK: swc1 $f2, 8($3) # encoding: [0xe4,0x62,0x00,0x08]
s.d $f2, 8($3) # CHECK: sdc1 $f2, 8($3) # encoding: [0xf4,0x62,0x00,0x08] s.d $f2, 8($3) # CHECK: sdc1 $f2, 8($3) # encoding: [0xf4,0x62,0x00,0x08]
sb $s6,-19857($14) sb $s6,-19857($14)
sc $15,18904($s3) # CHECK: sc $15, 18904($19) # encoding: [0xe2,0x6f,0x49,0xd8] sc $15,18904($s3) # CHECK: sc $15, 18904($19) # encoding: [0xe2,0x6f,0x49,0xd8]
sdbbp # CHECK: sdbbp # encoding: [0x70,0x00,0x00,0x3f] sdbbp # CHECK: sdbbp # encoding: [0x70,0x00,0x00,0x3f]
sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x70,0x00,0x08,0xbf] sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x70,0x00,0x08,0xbf]
sdc1 $f31,30574($13) sdc1 $f31,30574($13)
sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75] sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75]
▲ Show 20 Lines • Show All 104 Lines • Show Last 20 Lines

test/MC/Mips/mips32r5/valid-xfail.s

Show First 20 Lines • Show All 96 Lines • ▼ Show 20 Lines# XFAIL: *
nmsub.ps $f6,$f12,$f14,$f17 nmsub.ps $f6,$f12,$f14,$f17
pll.ps $f25,$f9,$f30 pll.ps $f25,$f9,$f30
plu.ps $f1,$f26,$f29 plu.ps $f1,$f26,$f29
preceq.w.phl $s8,$gp preceq.w.phl $s8,$gp
preceq.w.phr $s5,$15 preceq.w.phr $s5,$15
pul.ps $f9,$f30,$f26 pul.ps $f9,$f30,$f26
puu.ps $f24,$f9,$f2 puu.ps $f24,$f9,$f2
rdpgpr $s3,$9 rdpgpr $s3,$9
recip.d $f19,$f6
recip.s $f3,$f30
rorv $13,$a3,$s5 rorv $13,$a3,$s5
round.l.d $f12,$f1 round.l.d $f12,$f1
round.l.s $f25,$f5 round.l.s $f25,$f5
rsqrt.d $f3,$f28
rsqrt.s $f4,$f8
sbe $s7,33($s1) sbe $s7,33($s1)
sce $sp,189($10) sce $sp,189($10)
she $24,105($v0) she $24,105($v0)
sub.ps $f5,$f14,$f26 sub.ps $f5,$f14,$f26
swe $24,94($k0) swe $24,94($k0)
swle $v1,-209($gp) swle $v1,-209($gp)
swre $k0,-202($s2) swre $k0,-202($s2)
tlbginv tlbginv
Show All 11 Lines

test/MC/Mips/mips32r5/valid.s

Show First 20 Lines • Show All 162 Lines • ▼ Show 20 Linesa:
pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40] pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40]
pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08] pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08]
# FIXME: Use the code generator in order to print the .set directives # FIXME: Use the code generator in order to print the .set directives
# instead of the instruction printer. # instead of the instruction printer.
rdhwr $sp,$11 # CHECK: .set push rdhwr $sp,$11 # CHECK: .set push
# CHECK-NEXT: .set mips32r2 # CHECK-NEXT: .set mips32r2
# CHECK-NEXT: rdhwr $sp, $11 # CHECK-NEXT: rdhwr $sp, $11
# CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b] # CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b]
recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5]
recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5]
rotr $1,15 # CHECK: rotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xc2] rotr $1,15 # CHECK: rotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xc2]
rotr $1,$14,15 # CHECK: rotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xc2] rotr $1,$14,15 # CHECK: rotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xc2]
rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46] rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46]
round.w.d $f6,$f4 round.w.d $f6,$f4
round.w.s $f27,$f28 round.w.s $f27,$f28
rsqrt.s $f0,$f4 # CHECK: rsqrt.s $f0, $f4 # encoding: [0x46,0x00,0x20,0x16]
rsqrt.d $f2,$f6 # CHECK: rsqrt.d $f2, $f6 # encoding: [0x46,0x20,0x30,0x96]
s.s $f2, 8($3) # CHECK: swc1 $f2, 8($3) # encoding: [0xe4,0x62,0x00,0x08] s.s $f2, 8($3) # CHECK: swc1 $f2, 8($3) # encoding: [0xe4,0x62,0x00,0x08]
s.d $f2, 8($3) # CHECK: sdc1 $f2, 8($3) # encoding: [0xf4,0x62,0x00,0x08] s.d $f2, 8($3) # CHECK: sdc1 $f2, 8($3) # encoding: [0xf4,0x62,0x00,0x08]
sb $s6,-19857($14) sb $s6,-19857($14)
sc $15,18904($s3) # CHECK: sc $15, 18904($19) # encoding: [0xe2,0x6f,0x49,0xd8] sc $15,18904($s3) # CHECK: sc $15, 18904($19) # encoding: [0xe2,0x6f,0x49,0xd8]
sdbbp # CHECK: sdbbp # encoding: [0x70,0x00,0x00,0x3f] sdbbp # CHECK: sdbbp # encoding: [0x70,0x00,0x00,0x3f]
sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x70,0x00,0x08,0xbf] sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x70,0x00,0x08,0xbf]
sdc1 $f31,30574($13) sdc1 $f31,30574($13)
sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75] sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75]
▲ Show 20 Lines • Show All 104 Lines • Show Last 20 Lines

test/MC/Mips/mips32r6/valid.s

Show First 20 Lines • Show All 133 Lines • ▼ Show 20 Linesa:
negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23] negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23]
pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0x7c,0xa1,0x04,0x35] pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0x7c,0xa1,0x04,0x35]
# FIXME: Use the code generator in order to print the .set directives # FIXME: Use the code generator in order to print the .set directives
# instead of the instruction printer. # instead of the instruction printer.
rdhwr $sp,$11 # CHECK: .set push rdhwr $sp,$11 # CHECK: .set push
# CHECK-NEXT: .set mips32r2 # CHECK-NEXT: .set mips32r2
# CHECK-NEXT: rdhwr $sp, $11 # CHECK-NEXT: rdhwr $sp, $11
# CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b] # CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b]
recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5]
recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5]
s.s $f2, 8($3) # CHECK: swc1 $f2, 8($3) # encoding: [0xe4,0x62,0x00,0x08] s.s $f2, 8($3) # CHECK: swc1 $f2, 8($3) # encoding: [0xe4,0x62,0x00,0x08]
s.d $f2, 8($3) # CHECK: sdc1 $f2, 8($3) # encoding: [0xf4,0x62,0x00,0x08] s.d $f2, 8($3) # CHECK: sdc1 $f2, 8($3) # encoding: [0xf4,0x62,0x00,0x08]
sel.d $f0,$f1,$f2 # CHECK: sel.d $f0, $f1, $f2 # encoding: [0x46,0x22,0x08,0x10] sel.d $f0,$f1,$f2 # CHECK: sel.d $f0, $f1, $f2 # encoding: [0x46,0x22,0x08,0x10]
sel.s $f0,$f1,$f2 # CHECK: sel.s $f0, $f1, $f2 # encoding: [0x46,0x02,0x08,0x10] sel.s $f0,$f1,$f2 # CHECK: sel.s $f0, $f1, $f2 # encoding: [0x46,0x02,0x08,0x10]
seleqz $2,$3,$4 # CHECK: seleqz $2, $3, $4 # encoding: [0x00,0x64,0x10,0x35] seleqz $2,$3,$4 # CHECK: seleqz $2, $3, $4 # encoding: [0x00,0x64,0x10,0x35]
selnez $2,$3,$4 # CHECK: selnez $2, $3, $4 # encoding: [0x00,0x64,0x10,0x37] selnez $2,$3,$4 # CHECK: selnez $2, $3, $4 # encoding: [0x00,0x64,0x10,0x37]
max.s $f0, $f2, $f4 # CHECK: max.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1d] max.s $f0, $f2, $f4 # CHECK: max.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1d]
max.d $f0, $f2, $f4 # CHECK: max.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1d] max.d $f0, $f2, $f4 # CHECK: max.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1d]
Show All 30 Linesa:
ldc2 $8, -701($at) # CHECK: ldc2 $8, -701($1) # encoding: [0x49,0xc8,0x0d,0x43] ldc2 $8, -701($at) # CHECK: ldc2 $8, -701($1) # encoding: [0x49,0xc8,0x0d,0x43]
lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0x49,0x52,0x34,0xb7] lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0x49,0x52,0x34,0xb7]
sdc2 $20,629($s2) # CHECK: sdc2 $20, 629($18) # encoding: [0x49,0xf4,0x92,0x75] sdc2 $20,629($s2) # CHECK: sdc2 $20, 629($18) # encoding: [0x49,0xf4,0x92,0x75]
swc2 $25,304($s0) # CHECK: swc2 $25, 304($16) # encoding: [0x49,0x79,0x81,0x30] swc2 $25,304($s0) # CHECK: swc2 $25, 304($16) # encoding: [0x49,0x79,0x81,0x30]
ll $v0,-153($s2) # CHECK: ll $2, -153($18) # encoding: [0x7e,0x42,0xb3,0xb6] ll $v0,-153($s2) # CHECK: ll $2, -153($18) # encoding: [0x7e,0x42,0xb3,0xb6]
sc $15,-40($s3) # CHECK: sc $15, -40($19) # encoding: [0x7e,0x6f,0xec,0x26] sc $15,-40($s3) # CHECK: sc $15, -40($19) # encoding: [0x7e,0x6f,0xec,0x26]
clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x00,0xa0,0x58,0x51] clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x00,0xa0,0x58,0x51]
clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x03,0x80,0xe8,0x50] clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x03,0x80,0xe8,0x50]
rsqrt.s $f0,$f4 # CHECK: rsqrt.s $f0, $f4 # encoding: [0x46,0x00,0x20,0x16]
rsqrt.d $f2,$f6 # CHECK: rsqrt.d $f2, $f6 # encoding: [0x46,0x20,0x30,0x96]
sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a] sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a] sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b] sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b] sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b]
sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04] sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07] sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07]
srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06] srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06]
ssnop # WARNING: [[@LINE]]:9: warning: ssnop is deprecated for MIPS32r6 and is equivalent to a nop instruction ssnop # WARNING: [[@LINE]]:9: warning: ssnop is deprecated for MIPS32r6 and is equivalent to a nop instruction
▲ Show 20 Lines • Show All 41 Lines • Show Last 20 Lines

test/MC/Mips/mips4/valid-xfail.s

Show All 29 Lines# XFAIL: *
c.ueq.d $fcc4,$f13,$f25 c.ueq.d $fcc4,$f13,$f25
c.ueq.s $fcc6,$f3,$f30 c.ueq.s $fcc6,$f3,$f30
c.ule.d $fcc7,$f25,$f18 c.ule.d $fcc7,$f25,$f18
c.ule.s $fcc7,$f21,$f30 c.ule.s $fcc7,$f21,$f30
c.ult.d $fcc6,$f6,$f17 c.ult.d $fcc6,$f6,$f17
c.ult.s $fcc7,$f24,$f10 c.ult.s $fcc7,$f24,$f10
c.un.d $fcc6,$f23,$f24 c.un.d $fcc6,$f23,$f24
c.un.s $fcc1,$f30,$f4 c.un.s $fcc1,$f30,$f4
recip.d $f19,$f6
recip.s $f3,$f30
rsqrt.d $f3,$f28
rsqrt.s $f4,$f8

test/MC/Mips/mips4/valid.s

Show First 20 Lines • Show All 190 Lines • ▼ Show 20 Linesa:
nmadd.s $f0, $f4, $f24, $f12 # encoding: [0x4c,0x8c,0xc0,0x30] nmadd.s $f0, $f4, $f24, $f12 # encoding: [0x4c,0x8c,0xc0,0x30]
nmsub.d $f30, $f8, $f16, $f30 # encoding: [0x4d,0x1e,0x87,0xb9] nmsub.d $f30, $f8, $f16, $f30 # encoding: [0x4d,0x1e,0x87,0xb9]
nmsub.s $f0, $f24, $f20, $f4 # encoding: [0x4f,0x04,0xa0,0x38] nmsub.s $f0, $f24, $f20, $f4 # encoding: [0x4f,0x04,0xa0,0x38]
nop nop
nor $a3,$zero,$a3 nor $a3,$zero,$a3
or $12,$s0,$sp or $12,$s0,$sp
or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04] or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04]
pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08] pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08]
recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5]
recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5]
round.l.d $f12,$f1 round.l.d $f12,$f1
round.l.s $f25,$f5 round.l.s $f25,$f5
round.w.d $f6,$f4 round.w.d $f6,$f4
round.w.s $f27,$f28 round.w.s $f27,$f28
rsqrt.s $f0,$f4 # CHECK: rsqrt.s $f0, $f4 # encoding: [0x46,0x00,0x20,0x16]
rsqrt.d $f2,$f6 # CHECK: rsqrt.d $f2, $f6 # encoding: [0x46,0x20,0x30,0x96]
s.s $f2, 8($3) # CHECK: swc1 $f2, 8($3) # encoding: [0xe4,0x62,0x00,0x08] s.s $f2, 8($3) # CHECK: swc1 $f2, 8($3) # encoding: [0xe4,0x62,0x00,0x08]
s.d $f2, 8($3) # CHECK: sdc1 $f2, 8($3) # encoding: [0xf4,0x62,0x00,0x08] s.d $f2, 8($3) # CHECK: sdc1 $f2, 8($3) # encoding: [0xf4,0x62,0x00,0x08]
sb $s6,-19857($14) sb $s6,-19857($14)
sc $15,18904($s3) # CHECK: sc $15, 18904($19) # encoding: [0xe2,0x6f,0x49,0xd8] sc $15,18904($s3) # CHECK: sc $15, 18904($19) # encoding: [0xe2,0x6f,0x49,0xd8]
scd $15,-8243($sp) # CHECK: scd $15, -8243($sp) # encoding: [0xf3,0xaf,0xdf,0xcd] scd $15,-8243($sp) # CHECK: scd $15, -8243($sp) # encoding: [0xf3,0xaf,0xdf,0xcd]
sd $12,5835($10) sd $12,5835($10)
sdc1 $f31,30574($13) sdc1 $f31,30574($13)
sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75] sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75]
▲ Show 20 Lines • Show All 109 Lines • Show Last 20 Lines

test/MC/Mips/mips5/valid-xfail.s

Show First 20 Lines • Show All 66 Lines • ▼ Show 20 Lines# XFAIL: *
mul.ps $f14,$f0,$f16 mul.ps $f14,$f0,$f16
neg.ps $f19,$f13 neg.ps $f19,$f13
nmadd.ps $f27,$f4,$f9,$f25 nmadd.ps $f27,$f4,$f9,$f25
nmsub.ps $f6,$f12,$f14,$f17 nmsub.ps $f6,$f12,$f14,$f17
pll.ps $f25,$f9,$f30 pll.ps $f25,$f9,$f30
plu.ps $f1,$f26,$f29 plu.ps $f1,$f26,$f29
pul.ps $f9,$f30,$f26 pul.ps $f9,$f30,$f26
puu.ps $f24,$f9,$f2 puu.ps $f24,$f9,$f2
recip.d $f19,$f6
recip.s $f3,$f30
rsqrt.d $f3,$f28
rsqrt.s $f4,$f8
sub.ps $f5,$f14,$f26 sub.ps $f5,$f14,$f26

test/MC/Mips/mips5/valid.s

Show First 20 Lines • Show All 191 Lines • ▼ Show 20 Linesa:
nmadd.s $f0, $f4, $f24, $f12 # encoding: [0x4c,0x8c,0xc0,0x30] nmadd.s $f0, $f4, $f24, $f12 # encoding: [0x4c,0x8c,0xc0,0x30]
nmsub.d $f30, $f8, $f16, $f30 # encoding: [0x4d,0x1e,0x87,0xb9] nmsub.d $f30, $f8, $f16, $f30 # encoding: [0x4d,0x1e,0x87,0xb9]
nmsub.s $f0, $f24, $f20, $f4 # encoding: [0x4f,0x04,0xa0,0x38] nmsub.s $f0, $f24, $f20, $f4 # encoding: [0x4f,0x04,0xa0,0x38]
nop nop
nor $a3,$zero,$a3 nor $a3,$zero,$a3
or $12,$s0,$sp or $12,$s0,$sp
or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04] or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04]
pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08] pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08]
recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5]
recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5]
round.l.d $f12,$f1 round.l.d $f12,$f1
round.l.s $f25,$f5 round.l.s $f25,$f5
round.w.d $f6,$f4 round.w.d $f6,$f4
round.w.s $f27,$f28 round.w.s $f27,$f28
rsqrt.s $f0,$f4 # CHECK: rsqrt.s $f0, $f4 # encoding: [0x46,0x00,0x20,0x16]
rsqrt.d $f2,$f6 # CHECK: rsqrt.d $f2, $f6 # encoding: [0x46,0x20,0x30,0x96]
s.s $f2, 8($3) # CHECK: swc1 $f2, 8($3) # encoding: [0xe4,0x62,0x00,0x08] s.s $f2, 8($3) # CHECK: swc1 $f2, 8($3) # encoding: [0xe4,0x62,0x00,0x08]
s.d $f2, 8($3) # CHECK: sdc1 $f2, 8($3) # encoding: [0xf4,0x62,0x00,0x08] s.d $f2, 8($3) # CHECK: sdc1 $f2, 8($3) # encoding: [0xf4,0x62,0x00,0x08]
sb $s6,-19857($14) sb $s6,-19857($14)
sc $15,18904($s3) # CHECK: sc $15, 18904($19) # encoding: [0xe2,0x6f,0x49,0xd8] sc $15,18904($s3) # CHECK: sc $15, 18904($19) # encoding: [0xe2,0x6f,0x49,0xd8]
scd $15,-8243($sp) # CHECK: scd $15, -8243($sp) # encoding: [0xf3,0xaf,0xdf,0xcd] scd $15,-8243($sp) # CHECK: scd $15, -8243($sp) # encoding: [0xf3,0xaf,0xdf,0xcd]
sd $12,5835($10) sd $12,5835($10)
sdc1 $f31,30574($13) sdc1 $f31,30574($13)
sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75] sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75]
▲ Show 20 Lines • Show All 110 Lines • Show Last 20 Lines

test/MC/Mips/mips64/valid-xfail.s

Show First 20 Lines • Show All 73 Lines • ▼ Show 20 Lines# XFAIL: *
mul.ps $f14,$f0,$f16 mul.ps $f14,$f0,$f16
neg.ps $f19,$f13 neg.ps $f19,$f13
nmadd.ps $f27,$f4,$f9,$f25 nmadd.ps $f27,$f4,$f9,$f25
nmsub.ps $f6,$f12,$f14,$f17 nmsub.ps $f6,$f12,$f14,$f17
pll.ps $f25,$f9,$f30 pll.ps $f25,$f9,$f30
plu.ps $f1,$f26,$f29 plu.ps $f1,$f26,$f29
pul.ps $f9,$f30,$f26 pul.ps $f9,$f30,$f26
puu.ps $f24,$f9,$f2 puu.ps $f24,$f9,$f2
recip.d $f19,$f6
recip.s $f3,$f30
rsqrt.d $f3,$f28
rsqrt.s $f4,$f8
sub.ps $f5,$f14,$f26 sub.ps $f5,$f14,$f26

test/MC/Mips/mips64/valid.s

Show First 20 Lines • Show All 207 Lines • ▼ Show 20 Linesa:
nmadd.s $f0, $f4, $f24, $f12 # encoding: [0x4c,0x8c,0xc0,0x30] nmadd.s $f0, $f4, $f24, $f12 # encoding: [0x4c,0x8c,0xc0,0x30]
nmsub.d $f30, $f8, $f16, $f30 # encoding: [0x4d,0x1e,0x87,0xb9] nmsub.d $f30, $f8, $f16, $f30 # encoding: [0x4d,0x1e,0x87,0xb9]
nmsub.s $f0, $f24, $f20, $f4 # encoding: [0x4f,0x04,0xa0,0x38] nmsub.s $f0, $f24, $f20, $f4 # encoding: [0x4f,0x04,0xa0,0x38]
nop nop
nor $a3,$zero,$a3 nor $a3,$zero,$a3
or $12,$s0,$sp or $12,$s0,$sp
or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04] or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04]
pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08] pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08]
recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5]
recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5]
round.l.d $f12,$f1 round.l.d $f12,$f1
round.l.s $f25,$f5 round.l.s $f25,$f5
round.w.d $f6,$f4 round.w.d $f6,$f4
round.w.s $f27,$f28 round.w.s $f27,$f28
rsqrt.s $f0,$f4 # CHECK: rsqrt.s $f0, $f4 # encoding: [0x46,0x00,0x20,0x16]
rsqrt.d $f2,$f6 # CHECK: rsqrt.d $f2, $f6 # encoding: [0x46,0x20,0x30,0x96]
s.s $f2, 8($3) # CHECK: swc1 $f2, 8($3) # encoding: [0xe4,0x62,0x00,0x08] s.s $f2, 8($3) # CHECK: swc1 $f2, 8($3) # encoding: [0xe4,0x62,0x00,0x08]
s.d $f2, 8($3) # CHECK: sdc1 $f2, 8($3) # encoding: [0xf4,0x62,0x00,0x08] s.d $f2, 8($3) # CHECK: sdc1 $f2, 8($3) # encoding: [0xf4,0x62,0x00,0x08]
sb $s6,-19857($14) sb $s6,-19857($14)
sc $15,18904($s3) # CHECK: sc $15, 18904($19) # encoding: [0xe2,0x6f,0x49,0xd8] sc $15,18904($s3) # CHECK: sc $15, 18904($19) # encoding: [0xe2,0x6f,0x49,0xd8]
scd $15,-8243($sp) # CHECK: scd $15, -8243($sp) # encoding: [0xf3,0xaf,0xdf,0xcd] scd $15,-8243($sp) # CHECK: scd $15, -8243($sp) # encoding: [0xf3,0xaf,0xdf,0xcd]
sdbbp # CHECK: sdbbp # encoding: [0x70,0x00,0x00,0x3f] sdbbp # CHECK: sdbbp # encoding: [0x70,0x00,0x00,0x3f]
sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x70,0x00,0x08,0xbf] sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x70,0x00,0x08,0xbf]
sd $12,5835($10) sd $12,5835($10)
▲ Show 20 Lines • Show All 113 Lines • Show Last 20 Lines

test/MC/Mips/mips64r2/valid-xfail.s

Show First 20 Lines • Show All 95 Lines • ▼ Show 20 Lines# XFAIL: *
nmsub.ps $f6,$f12,$f14,$f17 nmsub.ps $f6,$f12,$f14,$f17
pll.ps $f25,$f9,$f30 pll.ps $f25,$f9,$f30
plu.ps $f1,$f26,$f29 plu.ps $f1,$f26,$f29
preceq.w.phl $s8,$gp preceq.w.phl $s8,$gp
preceq.w.phr $s5,$15 preceq.w.phr $s5,$15
pul.ps $f9,$f30,$f26 pul.ps $f9,$f30,$f26
puu.ps $f24,$f9,$f2 puu.ps $f24,$f9,$f2
rdpgpr $s3,$9 rdpgpr $s3,$9
recip.d $f19,$f6
recip.s $f3,$f30
rorv $13,$a3,$s5 rorv $13,$a3,$s5
rsqrt.d $f3,$f28
rsqrt.s $f4,$f8
sbe $s7,33($s1) sbe $s7,33($s1)
sce $sp,189($10) sce $sp,189($10)
she $24,105($v0) she $24,105($v0)
sub.ps $f5,$f14,$f26 sub.ps $f5,$f14,$f26
swe $24,94($k0) swe $24,94($k0)
swle $v1,-209($gp) swle $v1,-209($gp)
swre $k0,-202($s2) swre $k0,-202($s2)
tlbginv tlbginv
Show All 9 Lines

test/MC/Mips/mips64r2/valid.s

Show First 20 Lines • Show All 228 Lines • ▼ Show 20 Linesa:
pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40] pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40]
pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08] pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08]
# FIXME: Use the code generator in order to print the .set directives # FIXME: Use the code generator in order to print the .set directives
# instead of the instruction printer. # instead of the instruction printer.
rdhwr $sp,$11 # CHECK: .set push rdhwr $sp,$11 # CHECK: .set push
# CHECK-NEXT: .set mips32r2 # CHECK-NEXT: .set mips32r2
# CHECK-NEXT: rdhwr $sp, $11 # CHECK-NEXT: rdhwr $sp, $11
# CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b] # CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b]
recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5]
recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5]
rotr $1,15 # CHECK: rotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xc2] rotr $1,15 # CHECK: rotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xc2]
rotr $1,$14,15 # CHECK: rotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xc2] rotr $1,$14,15 # CHECK: rotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xc2]
rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46] rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46]
round.l.d $f12,$f1 round.l.d $f12,$f1
round.l.s $f25,$f5 round.l.s $f25,$f5
round.w.d $f6,$f4 round.w.d $f6,$f4
round.w.s $f27,$f28 round.w.s $f27,$f28
rsqrt.s $f0,$f4 # CHECK: rsqrt.s $f0, $f4 # encoding: [0x46,0x00,0x20,0x16]
rsqrt.d $f2,$f6 # CHECK: rsqrt.d $f2, $f6 # encoding: [0x46,0x20,0x30,0x96]
s.s $f2, 8($3) # CHECK: swc1 $f2, 8($3) # encoding: [0xe4,0x62,0x00,0x08] s.s $f2, 8($3) # CHECK: swc1 $f2, 8($3) # encoding: [0xe4,0x62,0x00,0x08]
s.d $f2, 8($3) # CHECK: sdc1 $f2, 8($3) # encoding: [0xf4,0x62,0x00,0x08] s.d $f2, 8($3) # CHECK: sdc1 $f2, 8($3) # encoding: [0xf4,0x62,0x00,0x08]
sb $s6,-19857($14) sb $s6,-19857($14)
sc $15,18904($s3) # CHECK: sc $15, 18904($19) # encoding: [0xe2,0x6f,0x49,0xd8] sc $15,18904($s3) # CHECK: sc $15, 18904($19) # encoding: [0xe2,0x6f,0x49,0xd8]
scd $15,-8243($sp) # CHECK: scd $15, -8243($sp) # encoding: [0xf3,0xaf,0xdf,0xcd] scd $15,-8243($sp) # CHECK: scd $15, -8243($sp) # encoding: [0xf3,0xaf,0xdf,0xcd]
sdbbp # CHECK: sdbbp # encoding: [0x70,0x00,0x00,0x3f] sdbbp # CHECK: sdbbp # encoding: [0x70,0x00,0x00,0x3f]
sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x70,0x00,0x08,0xbf] sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x70,0x00,0x08,0xbf]
sd $12,5835($10) sd $12,5835($10)
▲ Show 20 Lines • Show All 117 Lines • Show Last 20 Lines

test/MC/Mips/mips64r3/valid-xfail.s

Show First 20 Lines • Show All 98 Lines • ▼ Show 20 Lines# XFAIL: *
nmsub.ps $f6,$f12,$f14,$f17 nmsub.ps $f6,$f12,$f14,$f17
pll.ps $f25,$f9,$f30 pll.ps $f25,$f9,$f30
plu.ps $f1,$f26,$f29 plu.ps $f1,$f26,$f29
preceq.w.phl $s8,$gp preceq.w.phl $s8,$gp
preceq.w.phr $s5,$15 preceq.w.phr $s5,$15
pul.ps $f9,$f30,$f26 pul.ps $f9,$f30,$f26
puu.ps $f24,$f9,$f2 puu.ps $f24,$f9,$f2
rdpgpr $s3,$9 rdpgpr $s3,$9
recip.d $f19,$f6
recip.s $f3,$f30
rorv $13,$a3,$s5 rorv $13,$a3,$s5
rsqrt.d $f3,$f28
rsqrt.s $f4,$f8
sbe $s7,33($s1) sbe $s7,33($s1)
sce $sp,189($10) sce $sp,189($10)
she $24,105($v0) she $24,105($v0)
sub.ps $f5,$f14,$f26 sub.ps $f5,$f14,$f26
swe $24,94($k0) swe $24,94($k0)
swle $v1,-209($gp) swle $v1,-209($gp)
swre $k0,-202($s2) swre $k0,-202($s2)
tlbginv tlbginv
Show All 9 Lines

test/MC/Mips/mips64r3/valid.s

Show First 20 Lines • Show All 228 Lines • ▼ Show 20 Linesa:
pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40] pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40]
pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08] pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08]
# FIXME: Use the code generator in order to print the .set directives # FIXME: Use the code generator in order to print the .set directives
# instead of the instruction printer. # instead of the instruction printer.
rdhwr $sp,$11 # CHECK: .set push rdhwr $sp,$11 # CHECK: .set push
# CHECK-NEXT: .set mips32r2 # CHECK-NEXT: .set mips32r2
# CHECK-NEXT: rdhwr $sp, $11 # CHECK-NEXT: rdhwr $sp, $11
# CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b] # CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b]
recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5]
recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5]
rotr $1,15 # CHECK: rotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xc2] rotr $1,15 # CHECK: rotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xc2]
rotr $1,$14,15 # CHECK: rotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xc2] rotr $1,$14,15 # CHECK: rotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xc2]
rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46] rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46]
round.l.d $f12,$f1 round.l.d $f12,$f1
round.l.s $f25,$f5 round.l.s $f25,$f5
round.w.d $f6,$f4 round.w.d $f6,$f4
round.w.s $f27,$f28 round.w.s $f27,$f28
rsqrt.s $f0,$f4 # CHECK: rsqrt.s $f0, $f4 # encoding: [0x46,0x00,0x20,0x16]
rsqrt.d $f2,$f6 # CHECK: rsqrt.d $f2, $f6 # encoding: [0x46,0x20,0x30,0x96]
s.s $f2, 8($3) # CHECK: swc1 $f2, 8($3) # encoding: [0xe4,0x62,0x00,0x08] s.s $f2, 8($3) # CHECK: swc1 $f2, 8($3) # encoding: [0xe4,0x62,0x00,0x08]
s.d $f2, 8($3) # CHECK: sdc1 $f2, 8($3) # encoding: [0xf4,0x62,0x00,0x08] s.d $f2, 8($3) # CHECK: sdc1 $f2, 8($3) # encoding: [0xf4,0x62,0x00,0x08]
sb $s6,-19857($14) sb $s6,-19857($14)
sc $15,18904($s3) # CHECK: sc $15, 18904($19) # encoding: [0xe2,0x6f,0x49,0xd8] sc $15,18904($s3) # CHECK: sc $15, 18904($19) # encoding: [0xe2,0x6f,0x49,0xd8]
scd $15,-8243($sp) # CHECK: scd $15, -8243($sp) # encoding: [0xf3,0xaf,0xdf,0xcd] scd $15,-8243($sp) # CHECK: scd $15, -8243($sp) # encoding: [0xf3,0xaf,0xdf,0xcd]
sdbbp # CHECK: sdbbp # encoding: [0x70,0x00,0x00,0x3f] sdbbp # CHECK: sdbbp # encoding: [0x70,0x00,0x00,0x3f]
sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x70,0x00,0x08,0xbf] sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x70,0x00,0x08,0xbf]
sd $12,5835($10) sd $12,5835($10)
▲ Show 20 Lines • Show All 109 Lines • Show Last 20 Lines

test/MC/Mips/mips64r5/valid-xfail.s

Show First 20 Lines • Show All 98 Lines • ▼ Show 20 Lines# XFAIL: *
nmsub.ps $f6,$f12,$f14,$f17 nmsub.ps $f6,$f12,$f14,$f17
pll.ps $f25,$f9,$f30 pll.ps $f25,$f9,$f30
plu.ps $f1,$f26,$f29 plu.ps $f1,$f26,$f29
preceq.w.phl $s8,$gp preceq.w.phl $s8,$gp
preceq.w.phr $s5,$15 preceq.w.phr $s5,$15
pul.ps $f9,$f30,$f26 pul.ps $f9,$f30,$f26
puu.ps $f24,$f9,$f2 puu.ps $f24,$f9,$f2
rdpgpr $s3,$9 rdpgpr $s3,$9
recip.d $f19,$f6
recip.s $f3,$f30
rorv $13,$a3,$s5 rorv $13,$a3,$s5
rsqrt.d $f3,$f28
rsqrt.s $f4,$f8
sbe $s7,33($s1) sbe $s7,33($s1)
sce $sp,189($10) sce $sp,189($10)
she $24,105($v0) she $24,105($v0)
sub.ps $f5,$f14,$f26 sub.ps $f5,$f14,$f26
swe $24,94($k0) swe $24,94($k0)
swle $v1,-209($gp) swle $v1,-209($gp)
swre $k0,-202($s2) swre $k0,-202($s2)
tlbginv tlbginv
Show All 9 Lines

test/MC/Mips/mips64r5/valid.s

Show First 20 Lines • Show All 229 Lines • ▼ Show 20 Linesa:
pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40] pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40]
pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08] pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08]
# FIXME: Use the code generator in order to print the .set directives # FIXME: Use the code generator in order to print the .set directives
# instead of the instruction printer. # instead of the instruction printer.
rdhwr $sp,$11 # CHECK: .set push rdhwr $sp,$11 # CHECK: .set push
# CHECK-NEXT: .set mips32r2 # CHECK-NEXT: .set mips32r2
# CHECK-NEXT: rdhwr $sp, $11 # CHECK-NEXT: rdhwr $sp, $11
# CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b] # CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b]
recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5]
recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5]
rotr $1,15 # CHECK: rotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xc2] rotr $1,15 # CHECK: rotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xc2]
rotr $1,$14,15 # CHECK: rotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xc2] rotr $1,$14,15 # CHECK: rotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xc2]
rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46] rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46]
round.l.d $f12,$f1 round.l.d $f12,$f1
round.l.s $f25,$f5 round.l.s $f25,$f5
round.w.d $f6,$f4 round.w.d $f6,$f4
round.w.s $f27,$f28 round.w.s $f27,$f28
rsqrt.s $f0,$f4 # CHECK: rsqrt.s $f0, $f4 # encoding: [0x46,0x00,0x20,0x16]
rsqrt.d $f2,$f6 # CHECK: rsqrt.d $f2, $f6 # encoding: [0x46,0x20,0x30,0x96]
s.s $f2, 8($3) # CHECK: swc1 $f2, 8($3) # encoding: [0xe4,0x62,0x00,0x08] s.s $f2, 8($3) # CHECK: swc1 $f2, 8($3) # encoding: [0xe4,0x62,0x00,0x08]
s.d $f2, 8($3) # CHECK: sdc1 $f2, 8($3) # encoding: [0xf4,0x62,0x00,0x08] s.d $f2, 8($3) # CHECK: sdc1 $f2, 8($3) # encoding: [0xf4,0x62,0x00,0x08]
sb $s6,-19857($14) sb $s6,-19857($14)
sc $15,18904($s3) # CHECK: sc $15, 18904($19) # encoding: [0xe2,0x6f,0x49,0xd8] sc $15,18904($s3) # CHECK: sc $15, 18904($19) # encoding: [0xe2,0x6f,0x49,0xd8]
scd $15,-8243($sp) # CHECK: scd $15, -8243($sp) # encoding: [0xf3,0xaf,0xdf,0xcd] scd $15,-8243($sp) # CHECK: scd $15, -8243($sp) # encoding: [0xf3,0xaf,0xdf,0xcd]
sdbbp # CHECK: sdbbp # encoding: [0x70,0x00,0x00,0x3f] sdbbp # CHECK: sdbbp # encoding: [0x70,0x00,0x00,0x3f]
sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x70,0x00,0x08,0xbf] sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x70,0x00,0x08,0xbf]
sd $12,5835($10) sd $12,5835($10)
▲ Show 20 Lines • Show All 116 Lines • Show Last 20 Lines

test/MC/Mips/mips64r6/valid.s

Show First 20 Lines • Show All 188 Lines • ▼ Show 20 Linesa:
or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04] or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04]
pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0x7c,0xa1,0x04,0x35] pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0x7c,0xa1,0x04,0x35]
# FIXME: Use the code generator in order to print the .set directives # FIXME: Use the code generator in order to print the .set directives
# instead of the instruction printer. # instead of the instruction printer.
rdhwr $sp,$11 # CHECK: .set push rdhwr $sp,$11 # CHECK: .set push
# CHECK-NEXT: .set mips32r2 # CHECK-NEXT: .set mips32r2
# CHECK-NEXT: rdhwr $sp, $11 # CHECK-NEXT: rdhwr $sp, $11
# CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b] # CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b]
recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5]
recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5]
rint.d $f2, $f4 # CHECK: rint.d $f2, $f4 # encoding: [0x46,0x20,0x20,0x9a] rint.d $f2, $f4 # CHECK: rint.d $f2, $f4 # encoding: [0x46,0x20,0x20,0x9a]
rint.s $f2, $f4 # CHECK: rint.s $f2, $f4 # encoding: [0x46,0x00,0x20,0x9a] rint.s $f2, $f4 # CHECK: rint.s $f2, $f4 # encoding: [0x46,0x00,0x20,0x9a]
rsqrt.s $f0,$f4 # CHECK: rsqrt.s $f0, $f4 # encoding: [0x46,0x00,0x20,0x16]
rsqrt.d $f2,$f6 # CHECK: rsqrt.d $f2, $f6 # encoding: [0x46,0x20,0x30,0x96]
s.s $f2, 8($3) # CHECK: swc1 $f2, 8($3) # encoding: [0xe4,0x62,0x00,0x08] s.s $f2, 8($3) # CHECK: swc1 $f2, 8($3) # encoding: [0xe4,0x62,0x00,0x08]
s.d $f2, 8($3) # CHECK: sdc1 $f2, 8($3) # encoding: [0xf4,0x62,0x00,0x08] s.d $f2, 8($3) # CHECK: sdc1 $f2, 8($3) # encoding: [0xf4,0x62,0x00,0x08]
sc $15,-40($s3) # CHECK: sc $15, -40($19) # encoding: [0x7e,0x6f,0xec,0x26] sc $15,-40($s3) # CHECK: sc $15, -40($19) # encoding: [0x7e,0x6f,0xec,0x26]
scd $15,-51($sp) # CHECK: scd $15, -51($sp) # encoding: [0x7f,0xaf,0xe6,0xa7] scd $15,-51($sp) # CHECK: scd $15, -51($sp) # encoding: [0x7f,0xaf,0xe6,0xa7]
sdbbp # CHECK: sdbbp # encoding: [0x00,0x00,0x00,0x0e] sdbbp # CHECK: sdbbp # encoding: [0x00,0x00,0x00,0x0e]
sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x00,0x00,0x08,0x8e] sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x00,0x00,0x08,0x8e]
sdc2 $20,629($s2) # CHECK: sdc2 $20, 629($18) # encoding: [0x49,0xf4,0x92,0x75] sdc2 $20,629($s2) # CHECK: sdc2 $20, 629($18) # encoding: [0x49,0xf4,0x92,0x75]
sel.d $f0,$f1,$f2 # CHECK: sel.d $f0, $f1, $f2 # encoding: [0x46,0x22,0x08,0x10] sel.d $f0,$f1,$f2 # CHECK: sel.d $f0, $f1, $f2 # encoding: [0x46,0x22,0x08,0x10]
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