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Commit 0486d58

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author
Simon Dardis
committedSep 27, 2016
[mips] Add rsqrt, recip for MIPS
Add rsqrt.[ds], recip.[ds] for MIPS. Correct the microMIPS definitions for architecture support and register usage. Reviewers: vkalintiris, zoran.jovanoic Differential Review: https://reviews.llvm.org/D24499 llvm-svn: 282485
·
llvmorg-21-initllvmorg-4.0.0-rc1
1 parent 7482e59 commit 0486d58

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61 files changed

+226
-98
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‎llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp

+9-3
Original file line numberDiff line numberDiff line change
@@ -995,7 +995,7 @@ class MipsOperand : public MCParsedAsmOperand {
995995
void addConstantUImmOperands(MCInst &Inst, unsigned N) const {
996996
assert(N == 1 && "Invalid number of operands!");
997997
uint64_t Imm = getConstantImm() - Offset;
998-
Imm &= (1 << Bits) - 1;
998+
Imm &= (1ULL << Bits) - 1;
999999
Imm += Offset;
10001000
Imm += AdjustOffset;
10011001
Inst.addOperand(MCOperand::createImm(Imm));
@@ -1093,7 +1093,8 @@ class MipsOperand : public MCParsedAsmOperand {
10931093
bool isRegIdx() const { return Kind == k_RegisterIndex; }
10941094
bool isImm() const override { return Kind == k_Immediate; }
10951095
bool isConstantImm() const {
1096-
return isImm() && isa<MCConstantExpr>(getImm());
1096+
int64_t Res;
1097+
return isImm() && getImm()->evaluateAsAbsolute(Res);
10971098
}
10981099
bool isConstantImmz() const {
10991100
return isConstantImm() && getConstantImm() == 0;
@@ -1264,7 +1265,9 @@ class MipsOperand : public MCParsedAsmOperand {
12641265

12651266
int64_t getConstantImm() const {
12661267
const MCExpr *Val = getImm();
1267-
return static_cast<const MCConstantExpr *>(Val)->getValue();
1268+
int64_t Value = 0;
1269+
(void)Val->evaluateAsAbsolute(Value);
1270+
return Value;
12681271
}
12691272

12701273
MipsOperand *getMemBase() const {
@@ -4051,6 +4054,9 @@ bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
40514054
case Match_SImm32_Relaxed:
40524055
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
40534056
"expected 32-bit signed immediate");
4057+
case Match_UImm32_Coerced:
4058+
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
4059+
"expected 32-bit immediate");
40544060
case Match_MemSImm9:
40554061
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
40564062
"expected memory with 9-bit signed offset");

‎llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td

-19
Original file line numberDiff line numberDiff line change
@@ -186,8 +186,6 @@ class TRUNC_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.s", 0, 0b10101100>;
186186
class TRUNC_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.d", 1, 0b10101100>;
187187
class SQRT_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.s", 0, 0b00101000>;
188188
class SQRT_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.d", 1, 0b00101000>;
189-
class RSQRT_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"rsqrt.s", 0, 0b00001000>;
190-
class RSQRT_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"rsqrt.d", 1, 0b00001000>;
191189
class SB_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b000110>;
192190
class SBE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b100>;
193191
class SCE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b110>;
@@ -198,8 +196,6 @@ class LWE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b111>;
198196
class LW_MMR6_ENC : LOAD_WORD_FM_MMR6;
199197
class LUI_MMR6_ENC : LOAD_UPPER_IMM_FM_MMR6;
200198
class JALRC_HB_MMR6_ENC : POOL32A_JALRC_FM_MMR6<"jalrc.hb", 0b0001111100>;
201-
class RECIP_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"recip.s", 0, 0b01001000>;
202-
class RECIP_D_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"recip.d", 1, 0b01001000>;
203199
class RINT_S_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.s", 0>;
204200
class RINT_D_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.d", 1>;
205201
class ROUND_L_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.l.s", 0,
@@ -1118,14 +1114,6 @@ class SQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.s", FGR32Opnd, FGR32Opnd,
11181114
II_SQRT_S, fsqrt>;
11191115
class SQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.d", AFGR64Opnd, AFGR64Opnd,
11201116
II_SQRT_D, fsqrt>;
1121-
class RSQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"rsqrt.s", FGR32Opnd,
1122-
FGR32Opnd, II_TRUNC>;
1123-
class RSQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"rsqrt.d", FGR32Opnd,
1124-
AFGR64Opnd, II_TRUNC>;
1125-
class RECIP_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"recip.s", FGR32Opnd,
1126-
FGR32Opnd, II_ROUND>;
1127-
class RECIP_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"recip.d", FGR32Opnd, FGR32Opnd,
1128-
II_ROUND>;
11291117
class ROUND_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.s", FGR64Opnd,
11301118
FGR32Opnd, II_ROUND>;
11311119
class ROUND_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.d", FGR64Opnd,
@@ -1664,10 +1652,6 @@ def SQRT_S_MMR6 : StdMMR6Rel, SQRT_S_MMR6_ENC, SQRT_S_MMR6_DESC,
16641652
ISA_MICROMIPS32R6;
16651653
def SQRT_D_MMR6 : StdMMR6Rel, SQRT_D_MMR6_ENC, SQRT_D_MMR6_DESC,
16661654
ISA_MICROMIPS32R6;
1667-
def RSQRT_S_MMR6 : StdMMR6Rel, RSQRT_S_MMR6_ENC, RSQRT_S_MMR6_DESC,
1668-
ISA_MICROMIPS32R6;
1669-
def RSQRT_D_MMR6 : StdMMR6Rel, RSQRT_D_MMR6_ENC, RSQRT_D_MMR6_DESC,
1670-
ISA_MICROMIPS32R6;
16711655
def SB_MMR6 : StdMMR6Rel, SB_MMR6_DESC, SB_MMR6_ENC, ISA_MICROMIPS32R6;
16721656
def SBE_MMR6 : StdMMR6Rel, SBE_MMR6_DESC, SBE_MMR6_ENC, ISA_MICROMIPS32R6;
16731657
def SCE_MMR6 : StdMMR6Rel, SCE_MMR6_DESC, SCE_MMR6_ENC, ISA_MICROMIPS32R6;
@@ -1708,9 +1692,6 @@ def JALRC_HB_MMR6 : R6MMR6Rel, JALRC_HB_MMR6_ENC, JALRC_HB_MMR6_DESC,
17081692
def EXT_MMR6 : StdMMR6Rel, EXT_MMR6_ENC, EXT_MMR6_DESC, ISA_MICROMIPS32R6;
17091693
def INS_MMR6 : StdMMR6Rel, INS_MMR6_ENC, INS_MMR6_DESC, ISA_MICROMIPS32R6;
17101694
def JALRC_MMR6 : R6MMR6Rel, JALRC_MMR6_ENC, JALRC_MMR6_DESC, ISA_MICROMIPS32R6;
1711-
def RECIP_S_MMR6 : StdMMR6Rel, RECIP_S_MMR6_ENC, RECIP_S_MMR6_DESC,
1712-
ISA_MICROMIPS32R6;
1713-
def RECIP_D_MMR6 : StdMMR6Rel, RECIP_D_MMR6_ENC, RECIP_D_MMR6_DESC, ISA_MICROMIPS32R6;
17141695
def RINT_S_MMR6 : StdMMR6Rel, RINT_S_MMR6_ENC, RINT_S_MMR6_DESC,
17151696
ISA_MICROMIPS32R6;
17161697
def RINT_D_MMR6 : StdMMR6Rel, RINT_D_MMR6_ENC, RINT_D_MMR6_DESC, ISA_MICROMIPS32R6;

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