[WIP] MIR: Support parsing of liveins with lane masks

[arsenm]

Summary

This currently breaks some tests because currently hex constants are treated as floating point. I'm not sure what change should be made to support both, but I think it would be greatly preferable to switch to normal hex constants to be integers and only use c99 hex syntax for FP immediates

[qcolombet]

Hi Matt,

As far as I remember the lane mask in live-ins are only supported when subreg liveness is enabled.
Therefore, I believe we should either force the target to track subreg liveness when we see such construct or reject the entry is the target does not track subreg liveness.

What do you think?

Cheers,
-Quentin

[MatzeB]

This currently breaks some tests because currently hex constants are treated as floating point. I'm not sure what change should be made to support both, but I think it would be greatly preferable to switch to normal hex constants to be integers and only use c99 hex syntax for FP immediates

I would have wanted hex integers to fix the branch probability printing as well. However this looks tricky to solve.

I think C99 hex floats cannot represent all corner cases correctly (NaNs with payloads). However as far as I can see all instances where we want to parse hexfloats are prefixed with a keyword so we could just lex to a "hexnumber" and then interpret that as an integer or hexfloat based on context.

[MatzeB]

This got sorted out by D25530 / r284052. Please close.

lib/CodeGen/MIRParser/MILexer.cpp

static Cursor maybeLexHexFloatingPointLiteral(Cursor C, MIToken &Token) {
   if (isValidHexFloatingPointPrefix(C.peek()))
     C.advance();
   while (isxdigit(C.peek()))
     C.advance();
   Token.reset(MIToken::FloatingPointLiteral, Range.upto(C));
   return C;
 }
 
+static Cursor maybeLexHexIntegerLiteral(Cursor C, MIToken &Token) {
+  if (C.peek() != '0' || C.peek(1) != 'x')
+    return None;
+
+  C.advance(2); // Skip '0x'
+
+  Cursor Range = C;
+  while (isxdigit(C.peek()))
+    C.advance();
+
+  StringRef StrVal = Range.upto(C);
+  Token.reset(MIToken::IntegerLiteral, StrVal)
+    .setIntegerValue(APSInt(APInt(64, StrVal, 16)));
+  return C;
+}
+
 static Cursor lexFloatingPointLiteral(Cursor Range, Cursor C, MIToken &Token) {
   C.advance();
   // Skip over [0-9]*([eE][-+]?[0-9]+)?
   while (isdigit(C.peek()))
     C.advance();
   if ((C.peek() == 'e' || C.peek() == 'E') &&
       (isdigit(C.peek(1)) ||
        ((C.peek(1) == '-' || C.peek(1) == '+') && isdigit(C.peek(2))))) {
StringRef llvm::lexMIToken(StringRef Source, MIToken &Token,
   if (Cursor R = maybeLexIRValue(C, Token, ErrorCallback))
     return R.remaining();
   if (Cursor R = maybeLexRegister(C, Token))
     return R.remaining();
   if (Cursor R = maybeLexGlobalValue(C, Token, ErrorCallback))
     return R.remaining();
   if (Cursor R = maybeLexExternalSymbol(C, Token, ErrorCallback))
     return R.remaining();
+  if (Cursor R = maybeLexHexIntegerLiteral(C, Token))
+    return R.remaining();
   if (Cursor R = maybeLexHexFloatingPointLiteral(C, Token))
     return R.remaining();
   if (Cursor R = maybeLexNumericalLiteral(C, Token))
     return R.remaining();
   if (Cursor R = maybeLexExlaim(C, Token, ErrorCallback))
     return R.remaining();
   if (Cursor R = maybeLexSymbol(C, Token))
     return R.remaining();

lib/CodeGen/MIRParser/MIParser.cpp

bool MIParser::parseBasicBlockLiveins(MachineBasicBlock &MBB) {
   if (Token.isNewlineOrEOF()) // Allow an empty list of liveins.
     return false;
   do {
     if (Token.isNot(MIToken::NamedRegister))
       return error("expected a named register");
     unsigned Reg = 0;
     if (parseRegister(Reg))
       return true;
-    MBB.addLiveIn(Reg);
     lex();
+
+    LaneBitmask LaneMask = ~0u;
+    if (consumeIfPresent(MIToken::colon)) {
+      if (Token.isNot(MIToken::IntegerLiteral))
+        return error("expected an integer literal for lane mask");
+      if (getUnsigned(LaneMask))
+        return true;
+      lex();
+    }
+
+    MBB.addLiveIn(Reg, LaneMask);
   } while (consumeIfPresent(MIToken::comma));
   return false;
 }
 
 bool MIParser::parseBasicBlockSuccessors(MachineBasicBlock &MBB) {
   assert(Token.is(MIToken::kw_successors));
   lex();
   if (expectAndConsume(MIToken::colon))

lib/CodeGen/MIRPrinter.cpp

if (!MBB.livein_empty()) {
     OS.indent(2) << "liveins: ";
     bool First = true;
     for (const auto &LI : MBB.liveins()) {
       if (!First)
         OS << ", ";
       First = false;
       printReg(LI.PhysReg, OS, TRI);
       if (LI.LaneMask != ~0u)
-        OS << ':' << PrintLaneMask(LI.LaneMask);
+        OS << ":0x" << PrintLaneMask(LI.LaneMask);
     }
     OS << "\n";
     HasLineAttributes = true;
   }
 
   if (HasLineAttributes)
     OS << "\n";
   bool IsInBundle = false;

test/CodeGen/MIR/AMDGPU/lane-mask-livein.mir

+# RUN: llc -verify-machineinstrs -march=amdgcn -run-pass none -o - %s | FIleCheck %s
+--- |
+  target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
+
+  define void @lane_mask_livein(i32 addrspace(1)* %out, i32 %cond) #0 {
+  entry:
+    br i1 undef, label %if, label %endif
+
+  if:
+    store i32 0, i32 addrspace(1)* undef
+    br label %endif
+
+  endif:
+    ret void
+  }
+
+  attributes #0 = { nounwind }
+
+...
+---
+# CHECK-LABEL: name: lane_mask_livein
+# CHECK: bb.0.entry:
+# CHECK: liveins: %vgpr0, %sgpr0_sgpr1
+
+# CHECK:  bb.1.if:
+# CHECK: liveins: %sgpr0_sgpr1, %sgpr2_sgpr3, %sgpr4_sgpr5_sgpr6_sgpr7:0x0000000F
+
+# CHECK: bb.2.endif:
+# CHECK: liveins: %sgpr4_sgpr5_sgpr6_sgpr7:0x00000001, %sgpr2_sgpr3
+
+name:            lane_mask_livein
+alignment:       0
+tracksRegLiveness: true
+liveins:
+  - { reg: '%sgpr0_sgpr1' }
+  - { reg: '%vgpr0' }
+body:             |
+  bb.0.entry:
+    successors: %bb.1.if, %bb.3.endif
+    liveins: %vgpr0, %sgpr0_sgpr1
+    S_CMP_LT_I32 killed %sgpr0, 1, implicit-def %scc
+    S_CBRANCH_SCC1 %bb.3.endif, implicit killed %scc
+
+  bb.1.if:
+    successors: %bb.3.endif
+    liveins: %sgpr0_sgpr1, %sgpr2_sgpr3, %sgpr4_sgpr5_sgpr6_sgpr7:0x0000000F
+    %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM %sgpr0_sgpr1, 36 :: (non-temporal invariant load 8 from `i64 addrspace(2)* undef`)
+    %sgpr0 = S_LOAD_DWORD_IMM killed %sgpr0_sgpr1, 44 :: (non-temporal invariant load 4 from `i32 addrspace(2)* undef`)
+    %sgpr7 = S_MOV_B32 61440
+    %sgpr6 = S_MOV_B32 -1
+    %vgpr0 = V_MOV_B32_e32 0, implicit %exec
+    BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec :: (store 4 into %ir.out)
+
+
+  bb.3.endif:
+    liveins: %sgpr4_sgpr5_sgpr6_sgpr7:0x00000001, %sgpr2_sgpr3
+    S_ENDPGM
+
+...