[RegisterScavenger] Remove aliasing registers of operands from the candidate set

[sbaranga]

Summary

In addition to not including the register operand of the current
instruction also don't include any aliasing registers. We can't consider
these as candidates because using them will clobber the corresponding
register operand of the current instruction.

This change doesn't include a test case and it would probably be difficult
to produce a stable one since the bug depends on the results of register
allocation.

[hfinkel]

LGTM

[sbaranga]

Thanks, Hal! r280698

[qcolombet]

Have you investigate using the mir representation to produce a test case?

[sbaranga]

In D24130#534839, @qcolombet wrote:

Have you investigate using the mir representation to produce a test case?

I haven't tried it. I also haven't looked at MIR before but it seems really useful in this case. I'll have a look at it.

There's also a large test case in https://reviews.llvm.org/D24239 for this, but most likely we would want to have something less fragile.

[sbaranga]

I've investigated using MIR for getting a test case. The problem that I currently have with this is that I'm unable to run the PEI pass (where the problem is happening). If I try to do this I get a segfault in the stack protector pass. The problem seems to be that the TargetMachine is null. I'm not sure if this is something specific to PEI - but there doesn't seem to be any other regression tests that tries to run just this pass.

Here are the conditions that would trigger this bug:
We need to have a huge stack frame and a load or store to a stack location such that the location is far enough from the stack pointer and we need to scavenge a register to form the address. In order to avoid the heuristics from the register scavenger, all other registers except the one we want should be live. Our instruction should load or store a sub-register of the address register (for example str w0, [x0]).

lib/CodeGen/RegisterScavenging.cpp

unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
   const MachineFunction &MF = *MI.getParent()->getParent();
   // Consider all allocatable registers in the register class initially
   BitVector Candidates = TRI->getAllocatableSet(MF, RC);
 
   // Exclude all the registers being used by the instruction.
   for (const MachineOperand &MO : MI.operands()) {
     if (MO.isReg() && MO.getReg() != 0 && !(MO.isUse() && MO.isUndef()) &&
         !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
-      Candidates.reset(MO.getReg());
+      for (MCRegAliasIterator AI(MO.getReg(), TRI, true); AI.isValid(); ++AI)
+        Candidates.reset(*AI);
   }
 
   // Try to find a register that's unused if there is one, as then we won't
   // have to spill.
   BitVector Available = getRegsAvailable(RC);
   Available &= Candidates;
   if (Available.any())
     Candidates = Available;