[MC] Defer asm errors to post-statement failure

[niravd]

Summary

Allow errors to be deferred and emitted as part of clean up to simplify
and shorten Assembly parser code. This will allow error messages to be
emitted in helper functions and be modified by the caller which has
better context.

As part of this many minor cleanups to the Parser:

• Unify parser cleanup on error
• Add Workaround for incorrect return values in ParseDirective instances
• Tighten checks on error-signifying return values for parser functions and fix in-tree TargetParsers to be more consistent with the changes.
• Fix AArch64 test cases checking for spurious error messages that are now fixed.

These changes should be backwards compatible with current Target Parsers
so long as the error status are correctly returned in appropriate functions.

[rnk]

Can you provide some motivating examples for how this improves diagnostic quality by eliminating duplicates? Clang's diagnostics aren't buffered, and our recovery is still acceptable.

include/llvm/MC/MCParser/MCAsmParser.h

72 ↗

(On Diff #69733)

Just struct MCPendingError would be more C++-y

74 ↗

(On Diff #69733)

Right now sizeof(Msg) is 256+3*sizeof(void*), and you're putting MCPendingError in a vector. You should drop this down to 64 or use std::string.

75 ↗

(On Diff #69733)

This ArrayRef seems like a good way to create dangling references to local ranges arrays. Does any code actually use this functionality? Maybe we can delete it?

91 ↗

(On Diff #69733)

Maybe move ShowParsedOperands down here if you want to be in the same bitfield, or just make this bool.

[niravd]

In D24047#529392, @rnk wrote:

Can you provide some motivating examples for how this improves diagnostic quality by eliminating duplicates? Clang's diagnostics aren't buffered, and our recovery is still acceptable.

The deferred errors is motivated by sharing in various error messages. For instance, most of the directive errors have a suffix of the form "in directive X". Deferring let's us cut down on all the strings and append a suffix once in ParseDirective (or similar place) or error.

Most of the error duplicate reduction happens not because of the buffering, but because of the improved checking of the return value from ParseInstruction or ParseDirective which causes us to continue to not run through the instruction and emit additional errors. The changes in the neon-diagnostic case is a good example: parsing failed, but we return success.

[niravd]

Cleanup Ranges and other fixes from rnk.

[niravd]

include/llvm/MC/MCParser/MCAsmParser.h

75 ↗

(On Diff #69733)

It looks like at most we use one SMRange anywhere in the Parser, but we definitely use the Range. Looking at the history it's doesn't look like started out with support for multiple SMRange values but never actually used this feature.

I've changed all references to ArrayRef<SMRange> in the Parsers to a single SMRange.

[rnk]

lgtm

llvm/trunk/include/llvm/MC/MCParser/MCAsmLexer.h

class MCAsmLexer {
   std::string Err;
 
   MCAsmLexer(const MCAsmLexer &) = delete;
   void operator=(const MCAsmLexer &) = delete;
 protected: // Can only create subclasses.
   const char *TokStart;
   bool SkipSpace;
   bool AllowAtInIdentifier;
+  bool IsAtStartOfStatement;
 
   MCAsmLexer();
 
   virtual AsmToken LexToken() = 0;
 
   void SetError(SMLoc errLoc, const std::string &err) {
     ErrLoc = errLoc;
     Err = err;
   }
 
 public:
   virtual ~MCAsmLexer();
 
   /// Consume the next token from the input stream and return it.
   ///
   /// The lexer will continuosly return the end-of-file token once the end of
   /// the main input file has been reached.
   const AsmToken &Lex() {
     assert(!CurTok.empty());
+    // Mark if we parsing out a EndOfStatement.
+    IsAtStartOfStatement = CurTok.front().getKind() == AsmToken::EndOfStatement;
     CurTok.erase(CurTok.begin());
     // LexToken may generate multiple tokens via UnLex but will always return
     // the first one. Place returned value at head of CurTok vector.
     if (CurTok.empty()) {
       AsmToken T = LexToken();
       CurTok.insert(CurTok.begin(), T);
     }
     return CurTok.front();
   }
 
   void UnLex(AsmToken const &Token) {
+    IsAtStartOfStatement = false;
     CurTok.insert(CurTok.begin(), Token);
   }
 
+  bool isAtStartOfStatement() { return IsAtStartOfStatement; }
+
   virtual StringRef LexUntilEndOfStatement() = 0;
 
   /// Get the current source location.
   SMLoc getLoc() const;
 
   /// Get the current (last) lexed token.
   const AsmToken &getTok() const {
     return CurTok[0];

llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h

 //===-- llvm/MC/MCAsmParser.h - Abstract Asm Parser Interface ---*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_MC_MCPARSER_MCASMPARSER_H
 #define LLVM_MC_MCPARSER_MCASMPARSER_H
 
 #include "llvm/ADT/ArrayRef.h"
+#include "llvm/ADT/SmallString.h"
 #include "llvm/ADT/StringRef.h"
+#include "llvm/ADT/Twine.h"
 #include "llvm/MC/MCParser/AsmLexer.h"
 #include "llvm/Support/DataTypes.h"
 
 namespace llvm {
 class MCAsmInfo;
 class MCAsmLexer;
 class MCAsmParserExtension;
 class MCContext;

 /// \brief Generic assembler parser interface, for use by target specific
 /// assembly parsers.
 class MCAsmParser {
 public:
   typedef bool (*DirectiveHandler)(MCAsmParserExtension*, StringRef, SMLoc);
   typedef std::pair<MCAsmParserExtension*, DirectiveHandler>
     ExtensionDirectiveHandler;
 
+  struct MCPendingError {
+    SMLoc Loc;
+    SmallString<64> Msg;
+    SMRange Range;
+  };
+
 private:
   MCAsmParser(const MCAsmParser &) = delete;
   void operator=(const MCAsmParser &) = delete;
 
   MCTargetAsmParser *TargetParser;
 
   unsigned ShowParsedOperands : 1;
 
 protected: // Can only create subclasses.
   MCAsmParser();
 
+  bool HadError;
+
+  SmallVector<MCPendingError, 1> PendingErrors;
+  /// Flag tracking whether any errors have been encountered.
+
 public:
   virtual ~MCAsmParser();
 
   virtual void addDirectiveHandler(StringRef Directive,
                                    ExtensionDirectiveHandler Handler) = 0;
 
   virtual void addAliasForDirective(StringRef Directive, StringRef Alias) = 0;
 
public:
   virtual bool parseMSInlineAsm(
       void *AsmLoc, std::string &AsmString, unsigned &NumOutputs,
       unsigned &NumInputs, SmallVectorImpl<std::pair<void *, bool>> &OpDecls,
       SmallVectorImpl<std::string> &Constraints,
       SmallVectorImpl<std::string> &Clobbers, const MCInstrInfo *MII,
       const MCInstPrinter *IP, MCAsmParserSemaCallback &SI) = 0;
 
   /// \brief Emit a note at the location \p L, with the message \p Msg.
-  virtual void Note(SMLoc L, const Twine &Msg,
-                    ArrayRef<SMRange> Ranges = None) = 0;
+  virtual void Note(SMLoc L, const Twine &Msg, SMRange Range = None) = 0;
 
   /// \brief Emit a warning at the location \p L, with the message \p Msg.
   ///
   /// \return The return value is true, if warnings are fatal.
-  virtual bool Warning(SMLoc L, const Twine &Msg,
-                       ArrayRef<SMRange> Ranges = None) = 0;
+  virtual bool Warning(SMLoc L, const Twine &Msg, SMRange Range = None) = 0;
+
+  /// \brief Return an error at the location \p L, with the message \p Msg. This
+  /// may be modified before being emitted.
+  ///
+  /// \return The return value is always true, as an idiomatic convenience to
+  /// clients.
+  bool Error(SMLoc L, const Twine &Msg, SMRange Range = None);
 
   /// \brief Emit an error at the location \p L, with the message \p Msg.
   ///
   /// \return The return value is always true, as an idiomatic convenience to
   /// clients.
-  virtual bool Error(SMLoc L, const Twine &Msg,
-                     ArrayRef<SMRange> Ranges = None) = 0;
+  virtual bool printError(SMLoc L, const Twine &Msg, SMRange Range = None) = 0;
+
+  bool hasPendingError() { return !PendingErrors.empty(); }
+
+  bool printPendingErrors() {
+    bool rv = !PendingErrors.empty();
+    for (auto Err : PendingErrors) {
+      printError(Err.Loc, Twine(Err.Msg), Err.Range);
+    }
+    PendingErrors.clear();
+    return rv;
+  }
 
   /// \brief Get the next AsmToken in the stream, possibly handling file
   /// inclusion first.
   virtual const AsmToken &Lex() = 0;
 
   /// \brief Get the current AsmToken from the stream.
   const AsmToken &getTok() const;
 
   /// \brief Report an error at the current lexer location.
-  bool TokError(const Twine &Msg, ArrayRef<SMRange> Ranges = None);
+  bool TokError(const Twine &Msg, SMRange Range = None);
 
   bool parseTokenLoc(SMLoc &Loc);
   bool parseToken(AsmToken::TokenKind T, const Twine &Msg);
   bool parseOptionalToken(AsmToken::TokenKind T, bool &Present);
 
   bool parseEOL(const Twine &ErrMsg);
 
   bool parseIntToken(int64_t &V, const Twine &ErrMsg);

llvm/trunk/include/llvm/Support/SMLoc.h

 // This file declares the SMLoc class.  This class encapsulates a location in
 // source code for use in diagnostics.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_SUPPORT_SMLOC_H
 #define LLVM_SUPPORT_SMLOC_H
 
+#include "llvm/ADT/None.h"
 #include <cassert>
 
 namespace llvm {
 
 /// Represents a location in source code.
 class SMLoc {
   const char *Ptr;
 

 /// SMRange is implemented using a half-open range, as is the convention in C++.
 /// In the string "abc", the range (1,3] represents the substring "bc", and the
 /// range (2,2] represents an empty range between the characters "b" and "c".
 class SMRange {
 public:
   SMLoc Start, End;
 
   SMRange() {}
+  SMRange(NoneType) : Start(), End() {}
   SMRange(SMLoc St, SMLoc En) : Start(St), End(En) {
     assert(Start.isValid() == End.isValid() &&
            "Start and end should either both be valid or both be invalid!");
   }
 
   bool isValid() const { return Start.isValid(); }
 };
 
 } // end namespace llvm
 
 #endif

llvm/trunk/lib/MC/MCParser/AsmParser.cpp

private:
   std::deque<MCAsmMacro> MacroLikeBodies;
 
   /// Boolean tracking whether macro substitution is enabled.
   unsigned MacrosEnabledFlag : 1;
 
   /// \brief Keeps track of how many .macro's have been instantiated.
   unsigned NumOfMacroInstantiations;
 
-  /// Flag tracking whether any errors have been encountered.
-  unsigned HadError : 1;
-
   /// The values from the last parsed cpp hash file line comment if any.
   struct CppHashInfoTy {
     StringRef Filename;
     int64_t LineNumber = 0;
     SMLoc Loc;
     unsigned Buf = 0;
   };
   CppHashInfoTy CppHashInfo;
if (AssemblerDialect == ~0U)
       return MAI.getAssemblerDialect();
     else
       return AssemblerDialect;
   }
   void setAssemblerDialect(unsigned i) override {
     AssemblerDialect = i;
   }
 
-  void Note(SMLoc L, const Twine &Msg,
-            ArrayRef<SMRange> Ranges = None) override;
-  bool Warning(SMLoc L, const Twine &Msg,
-               ArrayRef<SMRange> Ranges = None) override;
-  bool Error(SMLoc L, const Twine &Msg,
-             ArrayRef<SMRange> Ranges = None) override;
+  void Note(SMLoc L, const Twine &Msg, SMRange Range = None) override;
+  bool Warning(SMLoc L, const Twine &Msg, SMRange Range = None) override;
+  bool printError(SMLoc L, const Twine &Msg, SMRange Range = None) override;
 
   const AsmToken &Lex() override;
 
   void setParsingInlineAsm(bool V) override {
     ParsingInlineAsm = V;
     Lexer.setParsingMSInlineAsm(V);
   }
   bool isParsingInlineAsm() override { return ParsingInlineAsm; }
private:
   /// \brief Extract AsmTokens for a macro argument.
   bool parseMacroArgument(MCAsmMacroArgument &MA, bool Vararg);
 
   /// \brief Parse all macro arguments for a given macro.
   bool parseMacroArguments(const MCAsmMacro *M, MCAsmMacroArguments &A);
 
   void printMacroInstantiations();
   void printMessage(SMLoc Loc, SourceMgr::DiagKind Kind, const Twine &Msg,
-                    ArrayRef<SMRange> Ranges = None) const {
+                    SMRange Range = None) const {
+    ArrayRef<SMRange> Ranges(Range);
     SrcMgr.PrintMessage(Loc, Kind, Msg, Ranges);
   }
   static void DiagHandler(const SMDiagnostic &Diag, void *Context);
 
   /// \brief Enter the specified file. This returns true on failure.
   bool enterIncludeFile(const std::string &Filename);
 
   /// \brief Process the specified file for the .incbin directive.

 } // end namespace llvm
 
 enum { DEFAULT_ADDRSPACE = 0 };
 
 AsmParser::AsmParser(SourceMgr &SM, MCContext &Ctx, MCStreamer &Out,
                      const MCAsmInfo &MAI)
     : Lexer(MAI), Ctx(Ctx), Out(Out), MAI(MAI), SrcMgr(SM),
       PlatformParser(nullptr), CurBuffer(SM.getMainFileID()),
-      MacrosEnabledFlag(true), HadError(false), CppHashInfo(),
-      AssemblerDialect(~0U), IsDarwin(false), ParsingInlineAsm(false) {
+      MacrosEnabledFlag(true), CppHashInfo(), AssemblerDialect(~0U),
+      IsDarwin(false), ParsingInlineAsm(false) {
   // Save the old handler.
   SavedDiagHandler = SrcMgr.getDiagHandler();
   SavedDiagContext = SrcMgr.getDiagContext();
   // Set our own handler which calls the saved handler.
   SrcMgr.setDiagHandler(DiagHandler, this);
   Lexer.setBuffer(SrcMgr.getMemoryBuffer(CurBuffer)->getBuffer());
 
   // Initialize the platform / file format parser.
void AsmParser::printMacroInstantiations() {
   for (std::vector<MacroInstantiation *>::const_reverse_iterator
            it = ActiveMacros.rbegin(),
            ie = ActiveMacros.rend();
        it != ie; ++it)
     printMessage((*it)->InstantiationLoc, SourceMgr::DK_Note,
                  "while in macro instantiation");
 }
 
-void AsmParser::Note(SMLoc L, const Twine &Msg, ArrayRef<SMRange> Ranges) {
-  printMessage(L, SourceMgr::DK_Note, Msg, Ranges);
+void AsmParser::Note(SMLoc L, const Twine &Msg, SMRange Range) {
+  printPendingErrors();
+  printMessage(L, SourceMgr::DK_Note, Msg, Range);
   printMacroInstantiations();
 }
 
-bool AsmParser::Warning(SMLoc L, const Twine &Msg, ArrayRef<SMRange> Ranges) {
+bool AsmParser::Warning(SMLoc L, const Twine &Msg, SMRange Range) {
   if(getTargetParser().getTargetOptions().MCNoWarn)
     return false;
   if (getTargetParser().getTargetOptions().MCFatalWarnings)
-    return Error(L, Msg, Ranges);
-  printMessage(L, SourceMgr::DK_Warning, Msg, Ranges);
+    return Error(L, Msg, Range);
+  printMessage(L, SourceMgr::DK_Warning, Msg, Range);
   printMacroInstantiations();
   return false;
 }
 
-bool AsmParser::Error(SMLoc L, const Twine &Msg, ArrayRef<SMRange> Ranges) {
+bool AsmParser::printError(SMLoc L, const Twine &Msg, SMRange Range) {
   HadError = true;
-  printMessage(L, SourceMgr::DK_Error, Msg, Ranges);
+  printMessage(L, SourceMgr::DK_Error, Msg, Range);
   printMacroInstantiations();
   return true;
 }
 
 bool AsmParser::enterIncludeFile(const std::string &Filename) {
   std::string IncludedFile;
   unsigned NewBuf =
       SrcMgr.AddIncludeFile(Filename, Lexer.getLoc(), IncludedFile);
bool AsmParser::Run(bool NoInitialTextSection, bool NoFinalize) {
   }
 
   // While we have input, parse each statement.
   while (Lexer.isNot(AsmToken::Eof)) {
     ParseStatementInfo Info;
     if (!parseStatement(Info, nullptr))
       continue;
 
-    // If we've failed, but on a Error Token, but did not consume it in
-    // favor of a better message, emit it now.
-    if (Lexer.getTok().is(AsmToken::Error)) {
+    // If we have a Lexer Error we are on an Error Token. Load in Lexer Error
+    // for printing ErrMsg via Lex() only if no (presumably better) parser error
+    // exists.
+    if (!hasPendingError() && Lexer.getTok().is(AsmToken::Error)) {
       Lex();
     }
 
-    // We had an error, validate that one was emitted and recover by skipping to
-    // the next line.
-    assert(HadError && "Parse statement returned an error, but none emitted!");
+    // parseStatement returned true so may need to emit an error.
+    printPendingErrors();
+
+    // Skipping to the next line if needed.
+    if (!getLexer().isAtStartOfStatement())
       eatToEndOfStatement();
   }
 
+  // All errors should have been emitted.
+  assert(!hasPendingError() && "unexpected error from parseStatement");
+
   getTargetParser().flushPendingInstructions(getStreamer());
 
   if (TheCondState.TheCond != StartingCondState.TheCond ||
       TheCondState.Ignore != StartingCondState.Ignore)
-    return TokError("unmatched .ifs or .elses");
-
+    printError(getTok().getLoc(), "unmatched .ifs or .elses");
   // Check to see there are no empty DwarfFile slots.
   const auto &LineTables = getContext().getMCDwarfLineTables();
   if (!LineTables.empty()) {
     unsigned Index = 0;
     for (const auto &File : LineTables.begin()->second.getMCDwarfFiles()) {
       if (File.Name.empty() && Index != 0)
-        TokError("unassigned file number: " + Twine(Index) +
+        printError(getTok().getLoc(), "unassigned file number: " +
+                                          Twine(Index) +
                                           " for .file directives");
       ++Index;
     }
   }
 
   // Check to see that all assembler local symbols were actually defined.
   // Targets that don't do subsections via symbols may not want this, though,
   // so conservatively exclude them. Only do this if we're finalizing, though,
   // as otherwise we won't necessarilly have seen everything yet.
   if (!NoFinalize) {
     if (MAI.hasSubsectionsViaSymbols()) {
       for (const auto &TableEntry : getContext().getSymbols()) {
         MCSymbol *Sym = TableEntry.getValue();
         // Variable symbols may not be marked as defined, so check those
         // explicitly. If we know it's a variable, we have a definition for
         // the purposes of this check.
         if (Sym->isTemporary() && !Sym->isVariable() && !Sym->isDefined())
           // FIXME: We would really like to refer back to where the symbol was
           // first referenced for a source location. We need to add something
           // to track that. Currently, we just point to the end of the file.
-          HadError |=
-              Error(getTok().getLoc(), "assembler local symbol '" +
+          printError(getTok().getLoc(), "assembler local symbol '" +
                                             Sym->getName() + "' not defined");
       }
     }
 
     // Temporary symbols like the ones for directional jumps don't go in the
     // symbol table. They also need to be diagnosed in all (final) cases.
     for (std::tuple<SMLoc, CppHashInfoTy, MCSymbol *> &LocSym : DirLabels) {
       if (std::get<2>(LocSym)->isUndefined()) {
         // Reset the state of any "# line file" directives we've seen to the
         // context as it was at the diagnostic site.
         CppHashInfo = std::get<1>(LocSym);
-        HadError |= Error(std::get<0>(LocSym), "directional label undefined");
+        printError(std::get<0>(LocSym), "directional label undefined");
       }
     }
   }
 
   // Finalize the output stream if there are no errors and if the client wants
   // us to.
   if (!HadError && !NoFinalize)
     Out.Finish();
 
   return HadError || getContext().hadError();
 }
 
 void AsmParser::checkForValidSection() {
   if (!ParsingInlineAsm && !getStreamer().getCurrentSection().first) {
-    TokError("expected section directive before assembly directive");
+    printError(getTok().getLoc(),
+               "expected section directive before assembly directive");
     Out.InitSections(false);
   }
 }
 
 /// \brief Throw away the rest of the line for testing purposes.
 void AsmParser::eatToEndOfStatement() {
   while (Lexer.isNot(AsmToken::EndOfStatement) && Lexer.isNot(AsmToken::Eof))
     Lexer.Lex();

 }
 
 /// ParseStatement:
 ///   ::= EndOfStatement
 ///   ::= Label* Directive ...Operands... EndOfStatement
 ///   ::= Label* Identifier OperandList* EndOfStatement
 bool AsmParser::parseStatement(ParseStatementInfo &Info,
                                MCAsmParserSemaCallback *SI) {
+  assert(!hasPendingError() && "parseStatement started with pending error");
   // Eat initial spaces and comments
   while (Lexer.is(AsmToken::Space))
     Lex();
   if (Lexer.is(AsmToken::EndOfStatement)) {
     // if this is a line comment we can drop it safely
     if (getTok().getString().front() == '\r' ||
         getTok().getString().front() == '\n')
       Out.AddBlankLine();
bool AsmParser::parseStatement(ParseStatementInfo &Info,
   StringRef IDVal;
   int64_t LocalLabelVal = -1;
   if (Lexer.is(AsmToken::HashDirective))
     return parseCppHashLineFilenameComment(IDLoc);
   // Allow an integer followed by a ':' as a directional local label.
   if (Lexer.is(AsmToken::Integer)) {
     LocalLabelVal = getTok().getIntVal();
     if (LocalLabelVal < 0) {
-      if (!TheCondState.Ignore)
-        return TokError("unexpected token at start of statement");
+      if (!TheCondState.Ignore) {
+        Lex(); // always eat a token
+        return Error(IDLoc, "unexpected token at start of statement");
+      }
       IDVal = "";
     } else {
       IDVal = getTok().getString();
       Lex(); // Consume the integer token to be used as an identifier token.
       if (Lexer.getKind() != AsmToken::Colon) {
-        if (!TheCondState.Ignore)
-          return TokError("unexpected token at start of statement");
+        if (!TheCondState.Ignore) {
+          Lex(); // always eat a token
+          return Error(IDLoc, "unexpected token at start of statement");
+        }
       }
     }
   } else if (Lexer.is(AsmToken::Dot)) {
     // Treat '.' as a valid identifier in this context.
     Lex();
     IDVal = ".";
   } else if (Lexer.is(AsmToken::LCurly)) {
     // Treat '{' as a valid identifier in this context.
     Lex();
     IDVal = "{";
 
   } else if (Lexer.is(AsmToken::RCurly)) {
     // Treat '}' as a valid identifier in this context.
     Lex();
     IDVal = "}";
   } else if (parseIdentifier(IDVal)) {
-    if (!TheCondState.Ignore)
-      return TokError("unexpected token at start of statement");
+    if (!TheCondState.Ignore) {
+      Lex(); // always eat a token
+      return Error(IDLoc, "unexpected token at start of statement");
+    }
     IDVal = "";
   }
 
   // Handle conditional assembly here before checking for skipping.  We
   // have to do this so that .endif isn't skipped in a ".if 0" block for
   // example.
   StringMap<DirectiveKind>::const_iterator DirKindIt =
       DirectiveKindMap.find(IDVal);
if (IDVal[0] == '.' && IDVal != ".") {
     //    (like the ELF parser) register themselves as extensions.
     // 3. The generic directive parser implemented by this class. These are
     //    all the directives that behave in a target and platform independent
     //    manner, or at least have a default behavior that's shared between
     //    all targets and platforms.
 
     getTargetParser().flushPendingInstructions(getStreamer());
 
-    // First query the target-specific parser. It will return 'true' if it
-    // isn't interested in this directive.
-    if (!getTargetParser().ParseDirective(ID))
+    SMLoc StartTokLoc = getTok().getLoc();
+    bool TPDirectiveReturn = getTargetParser().ParseDirective(ID);
+
+    if (hasPendingError())
+      return true;
+    // Currently the return value should be true if we are
+    // uninterested but as this is at odds with the standard parsing
+    // convention (return true = error) we have instances of a parsed
+    // directive that fails returning true as an error. Catch these
+    // cases as best as possible errors here.
+    if (TPDirectiveReturn && StartTokLoc != getTok().getLoc())
+      return true;
+    // Return if we did some parsing or believe we succeeded.
+    if (!TPDirectiveReturn || StartTokLoc != getTok().getLoc())
       return false;
 
     // Next, check the extension directive map to see if any extension has
     // registered itself to parse this directive.
     std::pair<MCAsmParserExtension *, DirectiveHandler> Handler =
         ExtensionDirectiveMap.lookup(IDVal);
     if (Handler.first)
       return (*Handler.second)(Handler.first, IDVal, IDLoc);
bool AsmParser::parseStatement(ParseStatementInfo &Info,
 
   if (ParsingInlineAsm && (IDVal == "even"))
     Info.AsmRewrites->emplace_back(AOK_EVEN, IDLoc, 4);
   checkForValidSection();
 
   // Canonicalize the opcode to lower case.
   std::string OpcodeStr = IDVal.lower();
   ParseInstructionInfo IInfo(Info.AsmRewrites);
-  bool HadError = getTargetParser().ParseInstruction(IInfo, OpcodeStr, ID,
+  bool ParseHadError = getTargetParser().ParseInstruction(IInfo, OpcodeStr, ID,
                                                           Info.ParsedOperands);
-  Info.ParseError = HadError;
+  Info.ParseError = ParseHadError;
 
   // Dump the parsed representation, if requested.
   if (getShowParsedOperands()) {
     SmallString<256> Str;
     raw_svector_ostream OS(Str);
     OS << "parsed instruction: [";
     for (unsigned i = 0; i != Info.ParsedOperands.size(); ++i) {
       if (i != 0)
         OS << ", ";
       Info.ParsedOperands[i]->print(OS);
     }
     OS << "]";
 
     printMessage(IDLoc, SourceMgr::DK_Note, OS.str());
   }
 
+  // Fail even if ParseInstruction erroneously returns false.
+  if (hasPendingError() || ParseHadError)
+    return true;
+
   // If we are generating dwarf for the current section then generate a .loc
   // directive for the instruction.
-  if (!HadError && getContext().getGenDwarfForAssembly() &&
+  if (!ParseHadError && getContext().getGenDwarfForAssembly() &&
       getContext().getGenDwarfSectionSyms().count(
           getStreamer().getCurrentSection().first)) {
     unsigned Line;
     if (ActiveMacros.empty())
       Line = SrcMgr.FindLineNumber(IDLoc, CurBuffer);
     else
       Line = SrcMgr.FindLineNumber(ActiveMacros.front()->InstantiationLoc,
                                    ActiveMacros.front()->ExitBuffer);
if (!ParseHadError && getContext().getGenDwarfForAssembly() &&
 
     getStreamer().EmitDwarfLocDirective(
         getContext().getGenDwarfFileNumber(), Line, 0,
         DWARF2_LINE_DEFAULT_IS_STMT ? DWARF2_FLAG_IS_STMT : 0, 0, 0,
         StringRef());
   }
 
   // If parsing succeeded, match the instruction.
-  if (!HadError) {
+  if (!ParseHadError) {
     uint64_t ErrorInfo;
-    getTargetParser().MatchAndEmitInstruction(IDLoc, Info.Opcode,
+    if (getTargetParser().MatchAndEmitInstruction(IDLoc, Info.Opcode,
                                                   Info.ParsedOperands, Out,
-                                              ErrorInfo, ParsingInlineAsm);
+                                                  ErrorInfo, ParsingInlineAsm))
+      return true;
   }
-
-  // Don't skip the rest of the line, the instruction parser is responsible for
-  // that.
   return false;
 }
 
 // Parse and erase curly braces marking block start/end
 bool 
 AsmParser::parseCurlyBlockScope(SmallVectorImpl<AsmRewrite> &AsmStrRewrites) {
   // Identify curly brace marking block start/end
   if (Lexer.isNot(AsmToken::LCurly) && Lexer.isNot(AsmToken::RCurly))
bool AsmParser::parseCppHashLineFilenameComment(SMLoc L) {
   assert(getTok().is(AsmToken::Integer) &&
          "Lexing Cpp line comment: Expected Integer");
   int64_t LineNumber = getTok().getIntVal();
   Lex();
   assert(getTok().is(AsmToken::String) &&
          "Lexing Cpp line comment: Expected String");
   StringRef Filename = getTok().getString();
   Lex();
+
   // Get rid of the enclosing quotes.
   Filename = Filename.substr(1, Filename.size() - 2);
 
   // Save the SMLoc, Filename and LineNumber for later use by diagnostics.
   CppHashInfo.Loc = L;
   CppHashInfo.Filename = Filename;
   CppHashInfo.LineNumber = LineNumber;
   CppHashInfo.Buf = CurBuffer;
bool AsmParser::parseMacroArguments(const MCAsmMacro *M,
   // - macros defined with parameters accept at most that many of them
   bool HasVararg = NParameters ? M->Parameters.back().Vararg : false;
   for (unsigned Parameter = 0; !NParameters || Parameter < NParameters;
        ++Parameter) {
     SMLoc IDLoc = Lexer.getLoc();
     MCAsmMacroParameter FA;
 
     if (Lexer.is(AsmToken::Identifier) && Lexer.peekTok().is(AsmToken::Equal)) {
-      if (parseIdentifier(FA.Name)) {
-        Error(IDLoc, "invalid argument identifier for formal argument");
-        eatToEndOfStatement();
-        return true;
-      }
+      if (parseIdentifier(FA.Name))
+        return Error(IDLoc, "invalid argument identifier for formal argument");
+
+      if (Lexer.isNot(AsmToken::Equal))
+        return TokError("expected '=' after formal parameter identifier");
 
-      if (Lexer.isNot(AsmToken::Equal)) {
-        TokError("expected '=' after formal parameter identifier");
-        eatToEndOfStatement();
-        return true;
-      }
       Lex();
 
       NamedParametersFound = true;
     }
 
-    if (NamedParametersFound && FA.Name.empty()) {
-      Error(IDLoc, "cannot mix positional and keyword arguments");
-      eatToEndOfStatement();
-      return true;
-    }
+    if (NamedParametersFound && FA.Name.empty())
+      return Error(IDLoc, "cannot mix positional and keyword arguments");
 
     bool Vararg = HasVararg && Parameter == (NParameters - 1);
     if (parseMacroArgument(FA.Value, Vararg))
       return true;
 
     unsigned PI = Parameter;
     if (!FA.Name.empty()) {
       unsigned FAI = 0;
       for (FAI = 0; FAI < NParameters; ++FAI)
         if (M->Parameters[FAI].Name == FA.Name)
           break;
 
       if (FAI >= NParameters) {
         assert(M && "expected macro to be defined");
-        Error(IDLoc,
-              "parameter named '" + FA.Name + "' does not exist for macro '" +
-              M->Name + "'");
-        return true;
+        return Error(IDLoc, "parameter named '" + FA.Name +
+                                "' does not exist for macro '" + M->Name + "'");
       }
       PI = FAI;
     }
 
     if (!FA.Value.empty()) {
       if (A.size() <= PI)
         A.resize(PI + 1);
       A[PI] = FA.Value;
bool AsmParser::parseDirectiveAlign(bool IsPow2, unsigned ValueSize) {
   }
 
   if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive"))
     return true;
 
   if (!HasFillExpr)
     FillExpr = 0;
 
+  // Always emit an alignment here even if we thrown an error.
+  bool ReturnVal = false;
+
   // Compute alignment in bytes.
   if (IsPow2) {
     // FIXME: Diagnose overflow.
     if (Alignment >= 32) {
-      Error(AlignmentLoc, "invalid alignment value");
+      ReturnVal |= Error(AlignmentLoc, "invalid alignment value");
       Alignment = 31;
     }
 
     Alignment = 1ULL << Alignment;
   } else {
     // Reject alignments that aren't either a power of two or zero,
     // for gas compatibility. Alignment of zero is silently rounded
     // up to one.
     if (Alignment == 0)
       Alignment = 1;
     if (!isPowerOf2_64(Alignment))
-      Error(AlignmentLoc, "alignment must be a power of 2");
+      ReturnVal |= Error(AlignmentLoc, "alignment must be a power of 2");
   }
 
   // Diagnose non-sensical max bytes to align.
   if (MaxBytesLoc.isValid()) {
     if (MaxBytesToFill < 1) {
-      Error(MaxBytesLoc, "alignment directive can never be satisfied in this "
+      ReturnVal |= Error(MaxBytesLoc,
+                         "alignment directive can never be satisfied in this "
                          "many bytes, ignoring maximum bytes expression");
       MaxBytesToFill = 0;
     }
 
     if (MaxBytesToFill >= Alignment) {
       Warning(MaxBytesLoc, "maximum bytes expression exceeds alignment and "
                            "has no effect");
       MaxBytesToFill = 0;
if ((!HasFillExpr || Lexer.getMAI().getTextAlignFillValue() == FillExpr) &&
       ValueSize == 1 && UseCodeAlign) {
     getStreamer().EmitCodeAlignment(Alignment, MaxBytesToFill);
   } else {
     // FIXME: Target specific behavior about how the "extra" bytes are filled.
     getStreamer().EmitValueToAlignment(Alignment, FillExpr, ValueSize,
                                        MaxBytesToFill);
   }
 
-  return false;
+  return ReturnVal;
 }
 
 /// parseDirectiveFile
 /// ::= .file [number] filename
 /// ::= .file number directory filename
 bool AsmParser::parseDirectiveFile(SMLoc DirectiveLoc) {
   // FIXME: I'm not sure what this is.
   int64_t FileNumber = -1;
if (FileNumber == -1)
     getStreamer().EmitFileDirective(Filename);
   else {
     // If there is -g option as well as debug info from directive file,
     // we turn off -g option, directly use the existing debug info instead.
     if (getContext().getGenDwarfForAssembly())
       getContext().setGenDwarfForAssembly(false);
     else if (getStreamer().EmitDwarfFileDirective(FileNumber, Directory, Filename) ==
         0)
-      Error(FileNumberLoc, "file number already allocated");
+      return Error(FileNumberLoc, "file number already allocated");
   }
 
   return false;
 }
 
 /// parseDirectiveLine
 /// ::= .line [number]
 bool AsmParser::parseDirectiveLine() {
bool AsmParser::parseDirectiveCVInlineSiteId() {
   }
 
   if (parseToken(AsmToken::EndOfStatement,
                  "unexpected token in '.cv_inline_site_id' directive"))
     return true;
 
   if (!getStreamer().EmitCVInlineSiteIdDirective(FunctionId, IAFunc, IAFile,
                                                  IALine, IACol, FunctionIdLoc))
-    Error(FunctionIdLoc, "function id already allocated");
+    return Error(FunctionIdLoc, "function id already allocated");
 
   return false;
 }
 
 /// parseDirectiveCVLoc
 /// ::= .cv_loc FunctionId FileNumber [LineNumber] [ColumnPos] [prologue_end]
 ///                                [is_stmt VALUE]
 /// The first number is a file number, must have been previously assigned with
bool AsmParser::parseDirectiveAbort() {
   SMLoc Loc = getLexer().getLoc();
 
   StringRef Str = parseStringToEndOfStatement();
   if (parseToken(AsmToken::EndOfStatement,
                  "unexpected token in '.abort' directive"))
     return true;
 
   if (Str.empty())
-    Error(Loc, ".abort detected. Assembly stopping.");
+    return Error(Loc, ".abort detected. Assembly stopping.");
   else
-    Error(Loc, ".abort '" + Str + "' detected. Assembly stopping.");
+    return Error(Loc, ".abort '" + Str + "' detected. Assembly stopping.");
   // FIXME: Actually abort assembly here.
 
   return false;
 }
 
 /// parseDirectiveInclude
 ///  ::= .include "filename"
 bool AsmParser::parseDirectiveInclude() {
bool AsmParser::parseDirectiveIfc(SMLoc DirectiveLoc, bool ExpectEqual) {
   return false;
 }
 
 /// parseDirectiveIfeqs
 ///   ::= .ifeqs string1, string2
 bool AsmParser::parseDirectiveIfeqs(SMLoc DirectiveLoc, bool ExpectEqual) {
   if (Lexer.isNot(AsmToken::String)) {
     if (ExpectEqual)
-      TokError("expected string parameter for '.ifeqs' directive");
-    else
-      TokError("expected string parameter for '.ifnes' directive");
-    eatToEndOfStatement();
-    return true;
+      return TokError("expected string parameter for '.ifeqs' directive");
+    return TokError("expected string parameter for '.ifnes' directive");
   }
 
   StringRef String1 = getTok().getStringContents();
   Lex();
 
   if (Lexer.isNot(AsmToken::Comma)) {
     if (ExpectEqual)
-      TokError("expected comma after first string for '.ifeqs' directive");
-    else
-      TokError("expected comma after first string for '.ifnes' directive");
-    eatToEndOfStatement();
-    return true;
+      return TokError(
+          "expected comma after first string for '.ifeqs' directive");
+    return TokError("expected comma after first string for '.ifnes' directive");
   }
 
   Lex();
 
   if (Lexer.isNot(AsmToken::String)) {
     if (ExpectEqual)
-      TokError("expected string parameter for '.ifeqs' directive");
-    else
-      TokError("expected string parameter for '.ifnes' directive");
-    eatToEndOfStatement();
-    return true;
+      return TokError("expected string parameter for '.ifeqs' directive");
+    return TokError("expected string parameter for '.ifnes' directive");
   }
 
   StringRef String2 = getTok().getStringContents();
   Lex();
 
   TheCondStack.push_back(TheCondState);
   TheCondState.TheCond = AsmCond::IfCond;
   TheCondState.CondMet = ExpectEqual == (String1 == String2);
bool AsmParser::parseDirectiveIfdef(SMLoc DirectiveLoc, bool expect_defined) {
   return false;
 }
 
 /// parseDirectiveElseIf
 /// ::= .elseif expression
 bool AsmParser::parseDirectiveElseIf(SMLoc DirectiveLoc) {
   if (TheCondState.TheCond != AsmCond::IfCond &&
       TheCondState.TheCond != AsmCond::ElseIfCond)
-    Error(DirectiveLoc, "Encountered a .elseif that doesn't follow a .if or "
-                        " an .elseif");
+    return Error(DirectiveLoc, "Encountered a .elseif that doesn't follow an"
+                               " .if or  an .elseif");
   TheCondState.TheCond = AsmCond::ElseIfCond;
 
   bool LastIgnoreState = false;
   if (!TheCondStack.empty())
     LastIgnoreState = TheCondStack.back().Ignore;
   if (LastIgnoreState || TheCondState.CondMet) {
     TheCondState.Ignore = true;
     eatToEndOfStatement();

 /// ::= .else
 bool AsmParser::parseDirectiveElse(SMLoc DirectiveLoc) {
   if (parseToken(AsmToken::EndOfStatement,
                  "unexpected token in '.else' directive"))
     return true;
 
   if (TheCondState.TheCond != AsmCond::IfCond &&
       TheCondState.TheCond != AsmCond::ElseIfCond)
-    Error(DirectiveLoc, "Encountered a .else that doesn't follow a .if or an "
-                        ".elseif");
+    return Error(DirectiveLoc, "Encountered a .else that doesn't follow "
+                               " an .if or an .elseif");
   TheCondState.TheCond = AsmCond::ElseCond;
   bool LastIgnoreState = false;
   if (!TheCondStack.empty())
     LastIgnoreState = TheCondStack.back().Ignore;
   if (LastIgnoreState || TheCondState.CondMet)
     TheCondState.Ignore = true;
   else
     TheCondState.Ignore = false;
if (!TheCondStack.empty()) {
     }
   }
 
   if (!WithMessage)
     return Error(L, ".err encountered");
 
   StringRef Message = ".error directive invoked in source file";
   if (Lexer.isNot(AsmToken::EndOfStatement)) {
-    if (Lexer.isNot(AsmToken::String)) {
-      TokError(".error argument must be a string");
-      eatToEndOfStatement();
-      return true;
-    }
+    if (Lexer.isNot(AsmToken::String))
+      return TokError(".error argument must be a string");
 
     Message = getTok().getStringContents();
     Lex();
   }
 
-  Error(L, Message);
-  return true;
+  return Error(L, Message);
 }
 
 /// parseDirectiveWarning
 ///   ::= .warning [string]
 bool AsmParser::parseDirectiveWarning(SMLoc L) {
   if (!TheCondStack.empty()) {
     if (TheCondStack.back().Ignore) {
       eatToEndOfStatement();
       return false;
     }
   }
 
   StringRef Message = ".warning directive invoked in source file";
   if (Lexer.isNot(AsmToken::EndOfStatement)) {
-    if (Lexer.isNot(AsmToken::String)) {
-      TokError(".warning argument must be a string");
-      eatToEndOfStatement();
-      return true;
-    }
+    if (Lexer.isNot(AsmToken::String))
+      return TokError(".warning argument must be a string");
 
     Message = getTok().getStringContents();
     Lex();
   }
 
-  Warning(L, Message);
-  return false;
+  return Warning(L, Message);
 }
 
 /// parseDirectiveEndIf
 /// ::= .endif
 bool AsmParser::parseDirectiveEndIf(SMLoc DirectiveLoc) {
   if (parseToken(AsmToken::EndOfStatement,
                  "unexpected token in '.endif' directive"))
     return true;
 
   if ((TheCondState.TheCond == AsmCond::NoCond) || TheCondStack.empty())
-    Error(DirectiveLoc, "Encountered a .endif that doesn't follow a .if or "
-                        ".else");
+    return Error(DirectiveLoc, "Encountered a .endif that doesn't follow "
+                               "an .if or .else");
   if (!TheCondStack.empty()) {
     TheCondState = TheCondStack.back();
     TheCondStack.pop_back();
   }
 
   return false;
 }
 

 
 MCAsmMacro *AsmParser::parseMacroLikeBody(SMLoc DirectiveLoc) {
   AsmToken EndToken, StartToken = getTok();
 
   unsigned NestLevel = 0;
   while (true) {
     // Check whether we have reached the end of the file.
     if (getLexer().is(AsmToken::Eof)) {
-      Error(DirectiveLoc, "no matching '.endr' in definition");
+      printError(DirectiveLoc, "no matching '.endr' in definition");
       return nullptr;
     }
 
     if (Lexer.is(AsmToken::Identifier) &&
         (getTok().getIdentifier() == ".rept" ||
          getTok().getIdentifier() == ".irp" ||
          getTok().getIdentifier() == ".irpc")) {
       ++NestLevel;
     }
 
     // Otherwise, check whether we have reached the .endr.
     if (Lexer.is(AsmToken::Identifier) && getTok().getIdentifier() == ".endr") {
       if (NestLevel == 0) {
         EndToken = getTok();
         Lex();
         if (Lexer.isNot(AsmToken::EndOfStatement)) {
-          TokError("unexpected token in '.endr' directive");
+          printError(getTok().getLoc(),
+                     "unexpected token in '.endr' directive");
           return nullptr;
         }
         break;
       }
       --NestLevel;
     }
 
     // Otherwise, scan till the end of the statement.

 bool AsmParser::parseDirectiveRept(SMLoc DirectiveLoc, StringRef Dir) {
   const MCExpr *CountExpr;
   SMLoc CountLoc = getTok().getLoc();
   if (parseExpression(CountExpr))
     return true;
 
   int64_t Count;
   if (!CountExpr->evaluateAsAbsolute(Count)) {
-    eatToEndOfStatement();
     return Error(CountLoc, "unexpected token in '" + Dir + "' directive");
   }
 
   if (check(Count < 0, CountLoc, "Count is negative") ||
       parseToken(AsmToken::EndOfStatement,
                  "unexpected token in '" + Dir + "' directive"))
     return true;
 
bool AsmParser::parseMSInlineAsm(
   unsigned InputIdx = 0;
   unsigned OutputIdx = 0;
   while (getLexer().isNot(AsmToken::Eof)) {
     // Parse curly braces marking block start/end
     if (parseCurlyBlockScope(AsmStrRewrites))
       continue;
 
     ParseStatementInfo Info(&AsmStrRewrites);
-    if (parseStatement(Info, &SI))
-      return true;
+    bool StatementErr = parseStatement(Info, &SI);
 
-    if (Info.ParseError)
+    if (StatementErr || Info.ParseError) {
+      // Emit pending errors if any exist.
+      printPendingErrors();
       return true;
+    }
+
+    // No pending error should exist here.
+    assert(!hasPendingError() && "unexpected error from parseStatement");
 
     if (Info.Opcode == ~0U)
       continue;
 
     const MCInstrDesc &Desc = MII->get(Info.Opcode);
 
     // Build the list of clobbers, outputs and inputs.
     for (unsigned i = 1, e = Info.ParsedOperands.size(); i != e; ++i) {
bool parseAssignmentExpression(StringRef Name, bool allow_redef,
                                MCAsmParser &Parser, MCSymbol *&Sym,
                                const MCExpr *&Value) {
 
   // FIXME: Use better location, we should use proper tokens.
   SMLoc EqualLoc = Parser.getTok().getLoc();
 
   if (Parser.parseExpression(Value)) {
     Parser.TokError("missing expression");
-    Parser.eatToEndOfStatement();
     return true;
   }
 
   // Note: we don't count b as used in "a = b". This is to allow
   // a = b
   // b = c
 
   if (Parser.getTok().isNot(AsmToken::EndOfStatement))

llvm/trunk/lib/MC/MCParser/MCAsmLexer.cpp

 //===-- MCAsmLexer.cpp - Abstract Asm Lexer Interface ---------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
 #include "llvm/MC/MCParser/MCAsmLexer.h"
 #include "llvm/Support/SourceMgr.h"
 
 using namespace llvm;
 
-MCAsmLexer::MCAsmLexer() : TokStart(nullptr), SkipSpace(true) {
+MCAsmLexer::MCAsmLexer()
+    : TokStart(nullptr), SkipSpace(true), IsAtStartOfStatement(true) {
   CurTok.emplace_back(AsmToken::Space, StringRef());
 }
 
 MCAsmLexer::~MCAsmLexer() {
 }
 
 SMLoc MCAsmLexer::getLoc() const {
   return SMLoc::getFromPointer(TokStart);

llvm/trunk/lib/MC/MCParser/MCAsmParser.cpp

 #include "llvm/MC/MCParser/MCAsmLexer.h"
 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/SourceMgr.h"
 #include "llvm/Support/raw_ostream.h"
 using namespace llvm;
 
-MCAsmParser::MCAsmParser() : TargetParser(nullptr), ShowParsedOperands(0) {
-}
+MCAsmParser::MCAsmParser()
+    : TargetParser(nullptr), ShowParsedOperands(0), PendingErrors() {}
 
 MCAsmParser::~MCAsmParser() {
 }
 
 void MCAsmParser::setTargetParser(MCTargetAsmParser &P) {
   assert(!TargetParser && "Target parser is already initialized!");
   TargetParser = &P;
   TargetParser->Initialize(*this);

 }
 
 bool MCAsmParser::check(bool P, SMLoc Loc, const Twine &Msg) {
   if (P)
     return Error(Loc, Msg);
   return false;
 }
 
-bool MCAsmParser::TokError(const Twine &Msg, ArrayRef<SMRange> Ranges) {
-  Error(getLexer().getLoc(), Msg, Ranges);
+bool MCAsmParser::TokError(const Twine &Msg, SMRange Range) {
+  return Error(getLexer().getLoc(), Msg, Range);
+}
+
+bool MCAsmParser::Error(SMLoc L, const Twine &Msg, SMRange Range) {
+  HadError = true;
+
+  MCPendingError PErr;
+  PErr.Loc = L;
+  Msg.toVector(PErr.Msg);
+  PErr.Range = Range;
+  PendingErrors.push_back(PErr);
   return true;
 }
 
 bool MCAsmParser::parseExpression(const MCExpr *&Res) {
   SMLoc L;
   return parseExpression(Res, L);
 }
 
 LLVM_DUMP_METHOD void MCParsedAsmOperand::dump() const {
   dbgs() << "  " << *this;
 }

llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

if (getLexer().is(AsmToken::Comma)) {
 
     if (Tok.isNot(AsmToken::Identifier) || parseRegister(Operands))
       return TokError("expected register operand");
 
     HasRegister = true;
   }
 
   if (getLexer().isNot(AsmToken::EndOfStatement)) {
-    Parser.eatToEndOfStatement();
     return TokError("unexpected token in argument list");
   }
 
   if (ExpectRegister && !HasRegister) {
     return TokError("specified " + Mnemonic + " op requires a register");
   }
   else if (!ExpectRegister && HasRegister) {
     return TokError("specified " + Mnemonic + " op does not use a register");
bool AArch64AsmParser::ParseInstruction(ParseInstructionInfo &Info,
 
   // Create the leading tokens for the mnemonic, split by '.' characters.
   size_t Start = 0, Next = Name.find('.');
   StringRef Head = Name.slice(Start, Next);
 
   // IC, DC, AT, and TLBI instructions are aliases for the SYS instruction.
   if (Head == "ic" || Head == "dc" || Head == "at" || Head == "tlbi") {
     bool IsError = parseSysAlias(Head, NameLoc, Operands);
-    if (IsError && getLexer().isNot(AsmToken::EndOfStatement))
-      Parser.eatToEndOfStatement();
     return IsError;
   }
 
   Operands.push_back(
       AArch64Operand::CreateToken(Head, false, NameLoc, getContext()));
   Mnemonic = Head;
 
   // Handle condition codes for a branch mnemonic
bool AArch64AsmParser::ParseInstruction(ParseInstructionInfo &Info,
   bool condCodeSecondOperand = (Head == "cset" || Head == "csetm");
   bool condCodeThirdOperand =
       (Head == "cinc" || Head == "cinv" || Head == "cneg");
 
   // Read the remaining operands.
   if (getLexer().isNot(AsmToken::EndOfStatement)) {
     // Read the first operand.
     if (parseOperand(Operands, false, false)) {
-      Parser.eatToEndOfStatement();
       return true;
     }
 
     unsigned N = 2;
     while (getLexer().is(AsmToken::Comma)) {
       Parser.Lex(); // Eat the comma.
 
       // Parse and remember the operand.
       if (parseOperand(Operands, (N == 4 && condCodeFourthOperand) ||
                                      (N == 3 && condCodeThirdOperand) ||
                                      (N == 2 && condCodeSecondOperand),
                        condCodeSecondOperand || condCodeThirdOperand)) {
-        Parser.eatToEndOfStatement();
         return true;
       }
 
       // After successfully parsing some operands there are two special cases to
       // consider (i.e. notional operands not separated by commas). Both are due
       // to memory specifiers:
       //  + An RBrac will end an address for load/store/prefetch
       //  + An '!' will indicate a pre-indexed operation.
while (getLexer().is(AsmToken::Comma)) {
       }
 
       ++N;
     }
   }
 
   if (getLexer().isNot(AsmToken::EndOfStatement)) {
     SMLoc Loc = Parser.getTok().getLoc();
-    Parser.eatToEndOfStatement();
     return Error(Loc, "unexpected token in argument list");
   }
 
   Parser.Lex(); // Consume the EndOfStatement
   return false;
 }
 
 // FIXME: This entire function is a giant hack to provide us with decent
if (IDVal == ".ltorg" || IDVal == ".pool")
     return parseDirectiveLtorg(Loc);
   if (IDVal == ".unreq")
     return parseDirectiveUnreq(Loc);
 
   if (!IsMachO && !IsCOFF) {
     if (IDVal == ".inst")
       return parseDirectiveInst(Loc);
   }
-
+  if (IDVal == MCLOHDirectiveName())
     return parseDirectiveLOH(IDVal, Loc);
+
+  return true;
 }
 
 static const struct {
   const char *Name;
   const FeatureBitset Features;
 } ExtensionMap[] = {
   { "crc", {AArch64::FeatureCRC} },
   { "crypto", {AArch64::FeatureCrypto} },
bool AArch64AsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
   return false;
 }
 
 /// parseDirectiveInst
 ///  ::= .inst opcode [, ...]
 bool AArch64AsmParser::parseDirectiveInst(SMLoc Loc) {
   MCAsmParser &Parser = getParser();
   if (getLexer().is(AsmToken::EndOfStatement)) {
-    Parser.eatToEndOfStatement();
     Error(Loc, "expected expression following directive");
     return false;
   }
 
   for (;;) {
     const MCExpr *Expr;
 
     if (getParser().parseExpression(Expr)) {
bool AArch64AsmParser::parseDirectiveTLSDescCall(SMLoc L) {
 
   getParser().getStreamer().EmitInstruction(Inst, getSTI());
   return false;
 }
 
 /// ::= .loh <lohName | lohId> label1, ..., labelN
 /// The number of arguments depends on the loh identifier.
 bool AArch64AsmParser::parseDirectiveLOH(StringRef IDVal, SMLoc Loc) {
-  if (IDVal != MCLOHDirectiveName())
-    return true;
   MCLOHType Kind;
   if (getParser().getTok().isNot(AsmToken::Identifier)) {
     if (getParser().getTok().isNot(AsmToken::Integer))
       return TokError("expected an identifier or a number in directive");
     // We successfully get a numeric value for the identifier.
     // Check if it is valid.
     int64_t Id = getParser().getTok().getIntVal();
-    if (Id <= -1U && !isValidMCLOHType(Id))
-      return TokError("invalid numeric identifier in directive");
+    if (Id <= -1U && !isValidMCLOHType(Id)) {
+      TokError("invalid numeric identifier in directive");
+      return false;
+    }
     Kind = (MCLOHType)Id;
   } else {
     StringRef Name = getTok().getIdentifier();
     // We successfully parse an identifier.
     // Check if it is a recognized one.
     int Id = MCLOHNameToId(Name);
 
     if (Id == -1)
bool AArch64AsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
   Parser.Lex(); // Eat the '.req' token.
   SMLoc SRegLoc = getLoc();
   unsigned RegNum = tryParseRegister();
   bool IsVector = false;
 
   if (RegNum == static_cast<unsigned>(-1)) {
     StringRef Kind;
     RegNum = tryMatchVectorRegister(Kind, false);
-    if (!Kind.empty()) {
-      Error(SRegLoc, "vector register without type specifier expected");
-      return false;
-    }
+    if (!Kind.empty())
+      return Error(SRegLoc, "vector register without type specifier expected");
     IsVector = true;
   }
 
-  if (RegNum == static_cast<unsigned>(-1)) {
-    Parser.eatToEndOfStatement();
-    Error(SRegLoc, "register name or alias expected");
-    return false;
-  }
+  if (RegNum == static_cast<unsigned>(-1))
+    return Error(SRegLoc, "register name or alias expected");
 
   // Shouldn't be anything else.
-  if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
-    Error(Parser.getTok().getLoc(), "unexpected input in .req directive");
-    Parser.eatToEndOfStatement();
-    return false;
-  }
+  if (Parser.getTok().isNot(AsmToken::EndOfStatement))
+    return Error(Parser.getTok().getLoc(),
+                 "unexpected input in .req directive");
 
   Parser.Lex(); // Consume the EndOfStatement
 
   auto pair = std::make_pair(IsVector, RegNum);
   if (RegisterReqs.insert(std::make_pair(Name, pair)).first->second != pair)
     Warning(L, "ignoring redefinition of register alias '" + Name + "'");
 
-  return true;
+  return false;
 }
 
 /// parseDirectiveUneq
 ///  ::= .unreq registername
 bool AArch64AsmParser::parseDirectiveUnreq(SMLoc L) {
   MCAsmParser &Parser = getParser();
   if (Parser.getTok().isNot(AsmToken::Identifier)) {
     Error(Parser.getTok().getLoc(), "unexpected input in .unreq directive.");
-    Parser.eatToEndOfStatement();
     return false;
   }
   RegisterReqs.erase(Parser.getTok().getIdentifier().lower());
   Parser.Lex(); // Eat the identifier.
   return false;
 }
 
 bool

llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

void startExplicitITBlock(ARMCC::CondCodes Cond, unsigned Mask) {
     assert(!inITBlock());
     ITState.Cond = Cond;
     ITState.Mask = Mask;
     ITState.CurPosition = 0;
     ITState.IsExplicit = true;
     return;
   }
 
-  void Note(SMLoc L, const Twine &Msg, ArrayRef<SMRange> Ranges = None) {
-    return getParser().Note(L, Msg, Ranges);
+  void Note(SMLoc L, const Twine &Msg, SMRange Range = None) {
+    return getParser().Note(L, Msg, Range);
   }
-  bool Warning(SMLoc L, const Twine &Msg,
-               ArrayRef<SMRange> Ranges = None) {
-    return getParser().Warning(L, Msg, Ranges);
-  }
-  bool Error(SMLoc L, const Twine &Msg,
-             ArrayRef<SMRange> Ranges = None) {
-    return getParser().Error(L, Msg, Ranges);
+  bool Warning(SMLoc L, const Twine &Msg, SMRange Range = None) {
+    return getParser().Warning(L, Msg, Range);
+  }
+  bool Error(SMLoc L, const Twine &Msg, SMRange Range = None) {
+    return getParser().Error(L, Msg, Range);
   }
 
   bool validatetLDMRegList(const MCInst &Inst, const OperandVector &Operands,
                            unsigned ListNo, bool IsARPop = false);
   bool validatetSTMRegList(const MCInst &Inst, const OperandVector &Operands,
                            unsigned ListNo);
 
   int tryParseRegister();
bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
   unsigned ProcessorIMod;
   bool CarrySetting;
   StringRef ITMask;
   Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
                            ProcessorIMod, ITMask);
 
   // In Thumb1, only the branch (B) instruction can be predicated.
   if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
-    Parser.eatToEndOfStatement();
     return Error(NameLoc, "conditional execution not supported in Thumb1");
   }
 
   Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
 
   // Handle the IT instruction ITMask. Convert it to a bitmask. This
   // is the mask as it will be for the IT encoding if the conditional
   // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
   // where the conditional bit0 is zero, the instruction post-processing
   // will adjust the mask accordingly.
   if (Mnemonic == "it") {
     SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
     if (ITMask.size() > 3) {
-      Parser.eatToEndOfStatement();
       return Error(Loc, "too many conditions on IT instruction");
     }
     unsigned Mask = 8;
     for (unsigned i = ITMask.size(); i != 0; --i) {
       char pos = ITMask[i - 1];
       if (pos != 't' && pos != 'e') {
-        Parser.eatToEndOfStatement();
         return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
       }
       Mask >>= 1;
       if (ITMask[i - 1] == 't')
         Mask |= 8;
     }
     Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
   }
bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
   // the matcher deal with finding the right instruction or generating an
   // appropriate error.
   bool CanAcceptCarrySet, CanAcceptPredicationCode;
   getMnemonicAcceptInfo(Mnemonic, Name, CanAcceptCarrySet, CanAcceptPredicationCode);
 
   // If we had a carry-set on an instruction that can't do that, issue an
   // error.
   if (!CanAcceptCarrySet && CarrySetting) {
-    Parser.eatToEndOfStatement();
     return Error(NameLoc, "instruction '" + Mnemonic +
                  "' can not set flags, but 's' suffix specified");
   }
   // If we had a predication code on an instruction that can't do that, issue an
   // error.
   if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
-    Parser.eatToEndOfStatement();
     return Error(NameLoc, "instruction '" + Mnemonic +
                  "' is not predicable, but condition code specified");
   }
 
   // Add the carry setting operand, if necessary.
   if (CanAcceptCarrySet) {
     SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
     Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
while (Next != StringRef::npos) {
     // completely ignored. Check for that.
     if (isDataTypeToken(ExtraToken) &&
         doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
       continue;
 
     // For for ARM mode generate an error if the .n qualifier is used.
     if (ExtraToken == ".n" && !isThumb()) {
       SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
-      Parser.eatToEndOfStatement();
       return Error(Loc, "instruction with .n (narrow) qualifier not allowed in "
                    "arm mode");
     }
 
     // The .n qualifier is always discarded as that is what the tables
     // and matcher expect.  In ARM mode the .w qualifier has no effect,
     // so discard it to avoid errors that can be caused by the matcher.
     if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) {
       SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
       Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
     }
   }
 
   // Read the remaining operands.
   if (getLexer().isNot(AsmToken::EndOfStatement)) {
     // Read the first operand.
     if (parseOperand(Operands, Mnemonic)) {
-      Parser.eatToEndOfStatement();
       return true;
     }
 
     while (getLexer().is(AsmToken::Comma)) {
       Parser.Lex();  // Eat the comma.
 
       // Parse and remember the operand.
       if (parseOperand(Operands, Mnemonic)) {
-        Parser.eatToEndOfStatement();
         return true;
       }
     }
   }
 
   if (getLexer().isNot(AsmToken::EndOfStatement)) {
-    SMLoc Loc = getLexer().getLoc();
-    Parser.eatToEndOfStatement();
-    return Error(Loc, "unexpected token in argument list");
+    return TokError("unexpected token in argument list");
   }
 
   Parser.Lex(); // Consume the EndOfStatement
 
   if (RequireVFPRegisterListCheck) {
     ARMOperand &Op = static_cast<ARMOperand &>(*Operands.back());
     if (AcceptSinglePrecisionOnly && !Op.isSPRRegList())
       return Error(Op.getStartLoc(),

 ///  ::= .short expression [, expression]*
 ///  ::= .word expression [, expression]*
 bool ARMAsmParser::parseLiteralValues(unsigned Size, SMLoc L) {
   MCAsmParser &Parser = getParser();
   if (getLexer().isNot(AsmToken::EndOfStatement)) {
     for (;;) {
       const MCExpr *Value;
       if (getParser().parseExpression(Value)) {
-        Parser.eatToEndOfStatement();
         return false;
       }
 
       getParser().getStreamer().EmitValue(Value, Size, L);
 
       if (getLexer().is(AsmToken::EndOfStatement))
         break;
 
if (Tok.isNot(AsmToken::EndOfStatement)) {
       getParser().getStreamer().EmitThumbFunc(Func);
       Parser.Lex(); // Consume the identifier token.
       return false;
     }
   }
 
   if (getLexer().isNot(AsmToken::EndOfStatement)) {
     Error(Parser.getTok().getLoc(), "unexpected token in directive");
-    Parser.eatToEndOfStatement();
     return false;
   }
 
   NextSymbolIsThumb = true;
   return false;
 }
 
 /// parseDirectiveSyntax

 /// parseDirectiveReq
 ///  ::= name .req registername
 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
   MCAsmParser &Parser = getParser();
   Parser.Lex(); // Eat the '.req' token.
   unsigned Reg;
   SMLoc SRegLoc, ERegLoc;
   if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
-    Parser.eatToEndOfStatement();
     Error(SRegLoc, "register name expected");
     return false;
   }
 
   // Shouldn't be anything else.
   if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
-    Parser.eatToEndOfStatement();
     Error(Parser.getTok().getLoc(), "unexpected input in .req directive.");
     return false;
   }
 
   Parser.Lex(); // Consume the EndOfStatement
 
   if (RegisterReqs.insert(std::make_pair(Name, Reg)).first->second != Reg) {
     Error(SRegLoc, "redefinition of '" + Name + "' does not match original.");
     return false;
   }
 
   return false;
 }
 
 /// parseDirectiveUneq
 ///  ::= .unreq registername
 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
   MCAsmParser &Parser = getParser();
   if (Parser.getTok().isNot(AsmToken::Identifier)) {
-    Parser.eatToEndOfStatement();
     Error(L, "unexpected input in .unreq directive.");
     return false;
   }
   RegisterReqs.erase(Parser.getTok().getIdentifier().lower());
   Parser.Lex(); // Eat the identifier.
   return false;
 }
 
bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
   int64_t Tag;
   SMLoc TagLoc;
   TagLoc = Parser.getTok().getLoc();
   if (Parser.getTok().is(AsmToken::Identifier)) {
     StringRef Name = Parser.getTok().getIdentifier();
     Tag = ARMBuildAttrs::AttrTypeFromString(Name);
     if (Tag == -1) {
       Error(TagLoc, "attribute name not recognised: " + Name);
-      Parser.eatToEndOfStatement();
       return false;
     }
     Parser.Lex();
   } else {
     const MCExpr *AttrExpr;
 
     TagLoc = Parser.getTok().getLoc();
     if (Parser.parseExpression(AttrExpr)) {
-      Parser.eatToEndOfStatement();
       return false;
     }
 
     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(AttrExpr);
     if (!CE) {
       Error(TagLoc, "expected numeric constant");
-      Parser.eatToEndOfStatement();
       return false;
     }
 
     Tag = CE->getValue();
   }
 
   if (Parser.getTok().isNot(AsmToken::Comma)) {
     Error(Parser.getTok().getLoc(), "comma expected");
-    Parser.eatToEndOfStatement();
     return false;
   }
   Parser.Lex(); // skip comma
 
   StringRef StringValue = "";
   bool IsStringValue = false;
 
   int64_t IntegerValue = 0;
else if (Tag % 2 == 1)
     IsStringValue = true;
   else
     llvm_unreachable("invalid tag type");
 
   if (IsIntegerValue) {
     const MCExpr *ValueExpr;
     SMLoc ValueExprLoc = Parser.getTok().getLoc();
     if (Parser.parseExpression(ValueExpr)) {
-      Parser.eatToEndOfStatement();
       return false;
     }
 
     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ValueExpr);
     if (!CE) {
       Error(ValueExprLoc, "expected numeric constant");
-      Parser.eatToEndOfStatement();
       return false;
     }
 
     IntegerValue = CE->getValue();
   }
 
   if (Tag == ARMBuildAttrs::compatibility) {
     if (Parser.getTok().isNot(AsmToken::Comma))
       IsStringValue = false;
     if (Parser.getTok().isNot(AsmToken::Comma)) {
       Error(Parser.getTok().getLoc(), "comma expected");
-      Parser.eatToEndOfStatement();
       return false;
     } else {
        Parser.Lex();
     }
   }
 
   if (IsStringValue) {
     if (Parser.getTok().isNot(AsmToken::String)) {
       Error(Parser.getTok().getLoc(), "bad string constant");
-      Parser.eatToEndOfStatement();
       return false;
     }
 
     StringValue = Parser.getTok().getStringContents();
     Parser.Lex();
   }
 
   if (IsIntegerValue && IsStringValue) {
if (UC.cantUnwind()) {
     return false;
   }
   if (UC.hasHandlerData()) {
     Error(L, ".personality must precede .handlerdata directive");
     UC.emitHandlerDataLocNotes();
     return false;
   }
   if (HasExistingPersonality) {
-    Parser.eatToEndOfStatement();
     Error(L, "multiple personality directives");
     UC.emitPersonalityLocNotes();
     return false;
   }
 
   // Parse the name of the personality routine
   if (Parser.getTok().isNot(AsmToken::Identifier)) {
-    Parser.eatToEndOfStatement();
     Error(L, "unexpected input in .personality directive.");
     return false;
   }
   StringRef Name(Parser.getTok().getIdentifier());
   Parser.Lex();
 
   MCSymbol *PR = getParser().getContext().getOrCreateSymbol(Name);
   getTargetStreamer().emitPersonality(PR);
if (isThumb()) {
     switch (Suffix) {
     case 'n':
       Width = 2;
       break;
     case 'w':
       Width = 4;
       break;
     default:
-      Parser.eatToEndOfStatement();
       Error(Loc, "cannot determine Thumb instruction size, "
                  "use inst.n/inst.w instead");
       return false;
     }
   } else {
     if (Suffix) {
-      Parser.eatToEndOfStatement();
       Error(Loc, "width suffixes are invalid in ARM mode");
       return false;
     }
     Width = 4;
   }
 
   if (getLexer().is(AsmToken::EndOfStatement)) {
-    Parser.eatToEndOfStatement();
     Error(Loc, "expected expression following directive");
     return false;
   }
 
   for (;;) {
     const MCExpr *Expr;
 
     if (getParser().parseExpression(Expr)) {

 ///   ::= .personalityindex index
 bool ARMAsmParser::parseDirectivePersonalityIndex(SMLoc L) {
   MCAsmParser &Parser = getParser();
   bool HasExistingPersonality = UC.hasPersonality();
 
   UC.recordPersonalityIndex(L);
 
   if (!UC.hasFnStart()) {
-    Parser.eatToEndOfStatement();
     Error(L, ".fnstart must precede .personalityindex directive");
     return false;
   }
   if (UC.cantUnwind()) {
-    Parser.eatToEndOfStatement();
     Error(L, ".personalityindex cannot be used with .cantunwind");
     UC.emitCantUnwindLocNotes();
     return false;
   }
   if (UC.hasHandlerData()) {
-    Parser.eatToEndOfStatement();
     Error(L, ".personalityindex must precede .handlerdata directive");
     UC.emitHandlerDataLocNotes();
     return false;
   }
   if (HasExistingPersonality) {
-    Parser.eatToEndOfStatement();
     Error(L, "multiple personality directives");
     UC.emitPersonalityLocNotes();
     return false;
   }
 
   const MCExpr *IndexExpression;
   SMLoc IndexLoc = Parser.getTok().getLoc();
   if (Parser.parseExpression(IndexExpression)) {
-    Parser.eatToEndOfStatement();
     return false;
   }
 
   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(IndexExpression);
   if (!CE) {
-    Parser.eatToEndOfStatement();
     Error(IndexLoc, "index must be a constant number");
     return false;
   }
   if (CE->getValue() < 0 ||
       CE->getValue() >= ARM::EHABI::NUM_PERSONALITY_INDEX) {
-    Parser.eatToEndOfStatement();
     Error(IndexLoc, "personality routine index should be in range [0-3]");
     return false;
   }
 
   getTargetStreamer().emitPersonalityIndex(CE->getValue());
   return false;
 }
 
 /// parseDirectiveUnwindRaw
 ///   ::= .unwind_raw offset, opcode [, opcode...]
 bool ARMAsmParser::parseDirectiveUnwindRaw(SMLoc L) {
   MCAsmParser &Parser = getParser();
   if (!UC.hasFnStart()) {
-    Parser.eatToEndOfStatement();
     Error(L, ".fnstart must precede .unwind_raw directives");
     return false;
   }
 
   int64_t StackOffset;
 
   const MCExpr *OffsetExpr;
   SMLoc OffsetLoc = getLexer().getLoc();
   if (getLexer().is(AsmToken::EndOfStatement) ||
       getParser().parseExpression(OffsetExpr)) {
     Error(OffsetLoc, "expected expression");
-    Parser.eatToEndOfStatement();
     return false;
   }
 
   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
   if (!CE) {
     Error(OffsetLoc, "offset must be a constant");
-    Parser.eatToEndOfStatement();
     return false;
   }
 
   StackOffset = CE->getValue();
 
   if (getLexer().isNot(AsmToken::Comma)) {
     Error(getLexer().getLoc(), "expected comma");
-    Parser.eatToEndOfStatement();
     return false;
   }
   Parser.Lex();
 
   SmallVector<uint8_t, 16> Opcodes;
   for (;;) {
     const MCExpr *OE;
 
     SMLoc OpcodeLoc = getLexer().getLoc();
     if (getLexer().is(AsmToken::EndOfStatement) || Parser.parseExpression(OE)) {
       Error(OpcodeLoc, "expected opcode expression");
-      Parser.eatToEndOfStatement();
       return false;
     }
 
     const MCConstantExpr *OC = dyn_cast<MCConstantExpr>(OE);
     if (!OC) {
       Error(OpcodeLoc, "opcode value must be a constant");
-      Parser.eatToEndOfStatement();
       return false;
     }
 
     const int64_t Opcode = OC->getValue();
     if (Opcode & ~0xff) {
       Error(OpcodeLoc, "invalid opcode");
-      Parser.eatToEndOfStatement();
       return false;
     }
 
     Opcodes.push_back(uint8_t(Opcode));
 
     if (getLexer().is(AsmToken::EndOfStatement))
       break;
 
     if (getLexer().isNot(AsmToken::Comma)) {
       Error(getLexer().getLoc(), "unexpected token in directive");
-      Parser.eatToEndOfStatement();
       return false;
     }
 
     Parser.Lex();
   }
 
   getTargetStreamer().emitUnwindRaw(StackOffset, Opcodes);
 
   Parser.Lex();
   return false;
 }
 
 /// parseDirectiveTLSDescSeq
 ///   ::= .tlsdescseq tls-variable
 bool ARMAsmParser::parseDirectiveTLSDescSeq(SMLoc L) {
   MCAsmParser &Parser = getParser();
 
   if (getLexer().isNot(AsmToken::Identifier)) {
     TokError("expected variable after '.tlsdescseq' directive");
-    Parser.eatToEndOfStatement();
     return false;
   }
 
   const MCSymbolRefExpr *SRE =
     MCSymbolRefExpr::create(Parser.getTok().getIdentifier(),
                             MCSymbolRefExpr::VK_ARM_TLSDESCSEQ, getContext());
   Lex();
 
   if (getLexer().isNot(AsmToken::EndOfStatement)) {
     Error(Parser.getTok().getLoc(), "unexpected token");
-    Parser.eatToEndOfStatement();
     return false;
   }
 
   getTargetStreamer().AnnotateTLSDescriptorSequence(SRE);
   return false;
 }
 
 /// parseDirectiveMovSP
 ///  ::= .movsp reg [, #offset]
 bool ARMAsmParser::parseDirectiveMovSP(SMLoc L) {
   MCAsmParser &Parser = getParser();
   if (!UC.hasFnStart()) {
-    Parser.eatToEndOfStatement();
     Error(L, ".fnstart must precede .movsp directives");
     return false;
   }
   if (UC.getFPReg() != ARM::SP) {
-    Parser.eatToEndOfStatement();
     Error(L, "unexpected .movsp directive");
     return false;
   }
 
   SMLoc SPRegLoc = Parser.getTok().getLoc();
   int SPReg = tryParseRegister();
   if (SPReg == -1) {
-    Parser.eatToEndOfStatement();
     Error(SPRegLoc, "register expected");
     return false;
   }
 
   if (SPReg == ARM::SP || SPReg == ARM::PC) {
-    Parser.eatToEndOfStatement();
     Error(SPRegLoc, "sp and pc are not permitted in .movsp directive");
     return false;
   }
 
   int64_t Offset = 0;
   if (Parser.getTok().is(AsmToken::Comma)) {
     Parser.Lex();
 
     if (Parser.getTok().isNot(AsmToken::Hash)) {
       Error(Parser.getTok().getLoc(), "expected #constant");
-      Parser.eatToEndOfStatement();
       return false;
     }
     Parser.Lex();
 
     const MCExpr *OffsetExpr;
     SMLoc OffsetLoc = Parser.getTok().getLoc();
     if (Parser.parseExpression(OffsetExpr)) {
-      Parser.eatToEndOfStatement();
       Error(OffsetLoc, "malformed offset expression");
       return false;
     }
 
     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
     if (!CE) {
-      Parser.eatToEndOfStatement();
       Error(OffsetLoc, "offset must be an immediate constant");
       return false;
     }
 
     Offset = CE->getValue();
   }
 
   getTargetStreamer().emitMovSP(SPReg, Offset);
   UC.saveFPReg(SPReg);
 
   return false;
 }
 
 /// parseDirectiveObjectArch
 ///   ::= .object_arch name
 bool ARMAsmParser::parseDirectiveObjectArch(SMLoc L) {
   MCAsmParser &Parser = getParser();
   if (getLexer().isNot(AsmToken::Identifier)) {
     Error(getLexer().getLoc(), "unexpected token");
-    Parser.eatToEndOfStatement();
     return false;
   }
 
   StringRef Arch = Parser.getTok().getString();
   SMLoc ArchLoc = Parser.getTok().getLoc();
   Lex();
 
   unsigned ID = ARM::parseArch(Arch);
 
   if (ID == ARM::AK_INVALID) {
     Error(ArchLoc, "unknown architecture '" + Arch + "'");
-    Parser.eatToEndOfStatement();
     return false;
   }
 
   getTargetStreamer().emitObjectArch(ID);
 
   if (getLexer().isNot(AsmToken::EndOfStatement)) {
     Error(getLexer().getLoc(), "unexpected token");
-    Parser.eatToEndOfStatement();
   }
 
   return false;
 }
 
 /// parseDirectiveAlign
 ///   ::= .align
 bool ARMAsmParser::parseDirectiveAlign(SMLoc L) {

 /// parseDirectiveThumbSet
 ///  ::= .thumb_set name, value
 bool ARMAsmParser::parseDirectiveThumbSet(SMLoc L) {
   MCAsmParser &Parser = getParser();
 
   StringRef Name;
   if (Parser.parseIdentifier(Name)) {
     TokError("expected identifier after '.thumb_set'");
-    Parser.eatToEndOfStatement();
     return false;
   }
 
   if (getLexer().isNot(AsmToken::Comma)) {
     TokError("expected comma after name '" + Name + "'");
-    Parser.eatToEndOfStatement();
     return false;
   }
   Lex();
 
   MCSymbol *Sym;
   const MCExpr *Value;
   if (MCParserUtils::parseAssignmentExpression(Name, /* allow_redef */ true,
                                                Parser, Sym, Value))

 
 /// parseDirectiveArchExtension
 ///   ::= .arch_extension [no]feature
 bool ARMAsmParser::parseDirectiveArchExtension(SMLoc L) {
   MCAsmParser &Parser = getParser();
 
   if (getLexer().isNot(AsmToken::Identifier)) {
     Error(getLexer().getLoc(), "expected architecture extension name");
-    Parser.eatToEndOfStatement();
     return false;
   }
 
   StringRef Name = Parser.getTok().getString();
   SMLoc ExtLoc = Parser.getTok().getLoc();
   Lex();
 
   bool EnableFeature = true;
for (const auto &Extension : Extensions) {
 
     uint64_t Features =
         ComputeAvailableFeatures(STI.ToggleFeature(ToggleFeatures));
     setAvailableFeatures(Features);
     return false;
   }
 
   Error(ExtLoc, "unknown architectural extension: " + Name);
-  Parser.eatToEndOfStatement();
   return false;
 }
 
 // Define this matcher function after the auto-generated include so we
 // have the match class enum definitions.
 unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
                                                   unsigned Kind) {
   ARMOperand &Op = static_cast<ARMOperand &>(AsmOp);

llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp

bool matchOneInstruction(MCInst &MCB, SMLoc IDLoc,
                            OperandVector &InstOperands, uint64_t &ErrorInfo,
                            bool MatchingInlineAsm);
 
   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
                                OperandVector &Operands, MCStreamer &Out,
                                uint64_t &ErrorInfo, bool MatchingInlineAsm) override;
 
   unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, unsigned Kind) override;
-  void OutOfRange(SMLoc IDLoc, long long Val, long long Max);
+  bool OutOfRange(SMLoc IDLoc, long long Val, long long Max);
   int processInstruction(MCInst &Inst, OperandVector const &Operands,
                          SMLoc IDLoc);
 
   // Check if we have an assembler and, if so, set the ELF e_header flags.
   void chksetELFHeaderEFlags(unsigned flags) {
     if (getAssembler())
       getAssembler()->setELFHeaderEFlags(flags);
   }
bool HexagonAsmParser::finishBundle(SMLoc IDLoc, MCStreamer &Out) {
 
   while (Check.getNextErrInfo() == true) {
     unsigned Reg = Check.getErrRegister();
     Twine R(RI->getName(Reg));
 
     uint64_t Err = Check.getError();
     if (Err != HexagonMCErrInfo::CHECK_SUCCESS) {
       if (HexagonMCErrInfo::CHECK_ERROR_BRANCHES & Err)
-        Error(IDLoc,
-              "unconditional branch cannot precede another branch in packet");
+        return Error(
+            IDLoc,
 
       if (HexagonMCErrInfo::CHECK_ERROR_NEWP & Err ||
           HexagonMCErrInfo::CHECK_ERROR_NEWV & Err)
-        Error(IDLoc, "register `" + R +
+        return Error(IDLoc, "register `" + R +
                                 "' used with `.new' "
                                 "but not validly modified in the same packet");
 
       if (HexagonMCErrInfo::CHECK_ERROR_REGISTERS & Err)
-        Error(IDLoc, "register `" + R + "' modified more than once");
+        return Error(IDLoc, "register `" + R + "' modified more than once");
 
       if (HexagonMCErrInfo::CHECK_ERROR_READONLY & Err)
-        Error(IDLoc, "cannot write to read-only register `" + R + "'");
+        return Error(IDLoc, "cannot write to read-only register `" + R + "'");
 
       if (HexagonMCErrInfo::CHECK_ERROR_LOOP & Err)
-        Error(IDLoc, "loop-setup and some branch instructions "
+        return Error(IDLoc, "loop-setup and some branch instructions "
                             "cannot be in the same packet");
 
       if (HexagonMCErrInfo::CHECK_ERROR_ENDLOOP & Err) {
         Twine N(HexagonMCInstrInfo::isInnerLoop(MCB) ? '0' : '1');
-        Error(IDLoc, "packet marked with `:endloop" + N + "' " +
+        return Error(IDLoc,
+                     "packet marked with `:endloop" + N + "' " +
                          "cannot contain instructions that modify register " +
                          "`" + R + "'");
       }
 
       if (HexagonMCErrInfo::CHECK_ERROR_SOLO & Err)
-        Error(IDLoc,
-              "instruction cannot appear in packet with other instructions");
+        return Error(
+            IDLoc,
 
       if (HexagonMCErrInfo::CHECK_ERROR_NOSLOTS & Err)
-        Error(IDLoc, "too many slots used in packet");
+        return Error(IDLoc, "too many slots used in packet");
 
       if (Err & HexagonMCErrInfo::CHECK_ERROR_SHUFFLE) {
         uint64_t Erm = Check.getShuffleError();
 
         if (HexagonShuffler::SHUFFLE_ERROR_INVALID == Erm)
-          Error(IDLoc, "invalid instruction packet");
+          return Error(IDLoc, "invalid instruction packet");
         else if (HexagonShuffler::SHUFFLE_ERROR_STORES == Erm)
-          Error(IDLoc, "invalid instruction packet: too many stores");
+          return Error(IDLoc, "invalid instruction packet: too many stores");
         else if (HexagonShuffler::SHUFFLE_ERROR_LOADS == Erm)
-          Error(IDLoc, "invalid instruction packet: too many loads");
+          return Error(IDLoc, "invalid instruction packet: too many loads");
         else if (HexagonShuffler::SHUFFLE_ERROR_BRANCHES == Erm)
-          Error(IDLoc, "too many branches in packet");
+          return Error(IDLoc, "too many branches in packet");
         else if (HexagonShuffler::SHUFFLE_ERROR_NOSLOTS == Erm)
-          Error(IDLoc, "invalid instruction packet: out of slots");
+          return Error(IDLoc, "invalid instruction packet: out of slots");
         else if (HexagonShuffler::SHUFFLE_ERROR_SLOTS == Erm)
-          Error(IDLoc, "invalid instruction packet: slot error");
+          return Error(IDLoc, "invalid instruction packet: slot error");
         else if (HexagonShuffler::SHUFFLE_ERROR_ERRATA2 == Erm)
-          Error(IDLoc, "v60 packet violation");
+          return Error(IDLoc, "v60 packet violation");
         else if (HexagonShuffler::SHUFFLE_ERROR_STORE_LOAD_CONFLICT == Erm)
-          Error(IDLoc, "slot 0 instruction does not allow slot 1 store");
+          return Error(IDLoc, "slot 0 instruction does not allow slot 1 store");
         else
-          Error(IDLoc, "unknown error in instruction packet");
+          return Error(IDLoc, "unknown error in instruction packet");
       }
     }
 
     unsigned Warn = Check.getWarning();
     if (Warn != HexagonMCErrInfo::CHECK_SUCCESS) {
       if (HexagonMCErrInfo::CHECK_WARN_CURRENT & Warn)
         Warning(IDLoc, "register `" + R + "' used with `.cur' "
                                           "but not used in the same packet");
unsigned HexagonAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
 
   DEBUG(dbgs() << "Unmatched Operand:");
   DEBUG(Op->dump());
   DEBUG(dbgs() << "\n");
 
   return Match_InvalidOperand;
 }
 
-void HexagonAsmParser::OutOfRange(SMLoc IDLoc, long long Val, long long Max) {
+// FIXME: Calls to OutOfRange shoudl propagate failure up to parseStatement.
+bool HexagonAsmParser::OutOfRange(SMLoc IDLoc, long long Val, long long Max) {
   std::string errStr;
   raw_string_ostream ES(errStr);
   ES << "value " << Val << "(" << format_hex(Val, 0) << ") out of range: ";
   if (Max >= 0)
     ES << "0-" << Max;
   else
     ES << Max << "-" << (-Max - 1);
-  Error(IDLoc, ES.str().c_str());
+  return Parser.printError(IDLoc, ES.str().c_str());
 }
 
 int HexagonAsmParser::processInstruction(MCInst &Inst,
                                          OperandVector const &Operands,
                                          SMLoc IDLoc) {
   MCContext &Context = getParser().getContext();
   const MCRegisterInfo *RI = getContext().getRegisterInfo();
   std::string r = "r";

llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp

void addFGR64AsmRegOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::createReg(getFGR64Reg()));
   }
 
   void addFGR32AsmRegOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::createReg(getFGR32Reg()));
     // FIXME: We ought to do this for -integrated-as without -via-file-asm too.
+    // FIXME: This should propagate failure up to parseStatement.
     if (!AsmParser.useOddSPReg() && RegIdx.Index & 1)
-      AsmParser.Error(StartLoc, "-mno-odd-spreg prohibits the use of odd FPU "
-                                "registers");
+      AsmParser.getParser().printError(
+          StartLoc, "-mno-odd-spreg prohibits the use of odd FPU "
   }
 
   void addFGRH32AsmRegOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::createReg(getFGRH32Reg()));
   }
 
   void addFCCAsmRegOperands(MCInst &Inst, unsigned N) const {
for (unsigned i = 0; i < MCID.getNumOperands(); i++) {
       if ((OpInfo.OperandType == MCOI::OPERAND_MEMORY) ||
           (OpInfo.OperandType == MCOI::OPERAND_UNKNOWN)) {
         MCOperand &Op = Inst.getOperand(i);
         if (Op.isImm()) {
           int MemOffset = Op.getImm();
           if (MemOffset < -32768 || MemOffset > 32767) {
             // Offset can't exceed 16bit value.
             expandMemInst(Inst, IDLoc, Out, STI, MCID.mayLoad(), true);
-            return false;
+            return getParser().hasPendingError();
           }
         } else if (Op.isExpr()) {
           const MCExpr *Expr = Op.getExpr();
           if (Expr->getKind() == MCExpr::SymbolRef) {
             const MCSymbolRefExpr *SR =
                 static_cast<const MCSymbolRefExpr *>(Expr);
             if (SR->getKind() == MCSymbolRefExpr::VK_None) {
               // Expand symbol.
               expandMemInst(Inst, IDLoc, Out, STI, MCID.mayLoad(), false);
-              return false;
+              return getParser().hasPendingError();
             }
           } else if (!isEvaluated(Expr)) {
             expandMemInst(Inst, IDLoc, Out, STI, MCID.mayLoad(), false);
-            return false;
+            return getParser().hasPendingError();
           }
         }
       }
     } // for
   }   // if load/store
 
   if (inMicroMipsMode()) {
     if (MCID.mayLoad()) {
bool MipsAsmParser::expandLoadAddress(unsigned DstReg, unsigned BaseReg,
   // la can't produce a usable address when addresses are 64-bit.
   if (Is32BitAddress && ABI.ArePtrs64bit()) {
     // FIXME: Demote this to a warning and continue as if we had 'dla' instead.
     //        We currently can't do this because we depend on the equality
     //        operator and N64 can end up with a GPR32/GPR64 mismatch.
     Error(IDLoc, "la used to load 64-bit address");
     // Continue as if we had 'dla' instead.
     Is32BitAddress = false;
+    return true;
   }
 
   // dla requires 64-bit addresses.
   if (!Is32BitAddress && !hasMips3()) {
     Error(IDLoc, "instruction requires a 64-bit architecture");
     return true;
   }
 
if (Offset.isExpr()) {
     assert(Offset.isImm() && "expected immediate operand kind");
     if (isInt<11>(Offset.getImm())) {
       // If offset fits into 11 bits then this instruction becomes microMIPS
       // 16-bit unconditional branch instruction.
       if (inMicroMipsMode())
         Inst.setOpcode(hasMips32r6() ? Mips::BC16_MMR6 : Mips::B16_MM);
     } else {
       if (!isInt<17>(Offset.getImm()))
-        Error(IDLoc, "branch target out of range");
+        return Error(IDLoc, "branch target out of range");
       if (OffsetToAlignment(Offset.getImm(), 1LL << 1))
-        Error(IDLoc, "branch to misaligned address");
+        return Error(IDLoc, "branch to misaligned address");
       Inst.clear();
       Inst.setOpcode(Mips::BEQ_MM);
       Inst.addOperand(MCOperand::createReg(Mips::ZERO));
       Inst.addOperand(MCOperand::createReg(Mips::ZERO));
       Inst.addOperand(MCOperand::createImm(Offset.getImm()));
     }
   }
   Out.EmitInstruction(Inst, *STI);
bool MipsAsmParser::expandTrunc(MCInst &Inst, bool IsDouble, bool Is64FPU,
   return false;
 }
 
 bool MipsAsmParser::expandUlh(MCInst &Inst, bool Signed, SMLoc IDLoc,
                               MCStreamer &Out, const MCSubtargetInfo *STI) {
   MipsTargetStreamer &TOut = getTargetStreamer();
 
   if (hasMips32r6() || hasMips64r6()) {
-    Error(IDLoc, "instruction not supported on mips32r6 or mips64r6");
-    return false;
+    return Error(IDLoc, "instruction not supported on mips32r6 or mips64r6");
   }
 
   warnIfNoMacro(IDLoc);
 
   const MCOperand &DstRegOp = Inst.getOperand(0);
   assert(DstRegOp.isReg() && "expected register operand kind");
 
   const MCOperand &SrcRegOp = Inst.getOperand(1);
bool MipsAsmParser::expandUlh(MCInst &Inst, bool Signed, SMLoc IDLoc,
 
   return false;
 }
 
 bool MipsAsmParser::expandUlw(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                               const MCSubtargetInfo *STI) {
   MipsTargetStreamer &TOut = getTargetStreamer();
 
-  if (hasMips32r6() || hasMips64r6()) {
-    Error(IDLoc, "instruction not supported on mips32r6 or mips64r6");
-    return false;
-  }
+  if (hasMips32r6() || hasMips64r6())
+    return Error(IDLoc, "instruction not supported on mips32r6 or mips64r6");
 
   const MCOperand &DstRegOp = Inst.getOperand(0);
   assert(DstRegOp.isReg() && "expected register operand kind");
 
   const MCOperand &SrcRegOp = Inst.getOperand(1);
   assert(SrcRegOp.isReg() && "expected register operand kind");
 
   const MCOperand &OffsetImmOp = Inst.getOperand(2);

 bool MipsAsmParser::parseParenSuffix(StringRef Name, OperandVector &Operands) {
   MCAsmParser &Parser = getParser();
   if (getLexer().is(AsmToken::LParen)) {
     Operands.push_back(
         MipsOperand::CreateToken("(", getLexer().getLoc(), *this));
     Parser.Lex();
     if (parseOperand(Operands, Name)) {
       SMLoc Loc = getLexer().getLoc();
-      Parser.eatToEndOfStatement();
       return Error(Loc, "unexpected token in argument list");
     }
     if (Parser.getTok().isNot(AsmToken::RParen)) {
       SMLoc Loc = getLexer().getLoc();
-      Parser.eatToEndOfStatement();
       return Error(Loc, "unexpected token, expected ')'");
     }
     Operands.push_back(
         MipsOperand::CreateToken(")", getLexer().getLoc(), *this));
     Parser.Lex();
   }
   return false;
 }
 
 /// Sometimes (i.e. in MSA) the operand may be followed immediately by
 /// either one of these.
 /// ::= '[', register, ']'
 /// ::= '[', integer, ']'
 /// handle it before we iterate so we don't get tripped up by the lack of
 /// a comma.
 bool MipsAsmParser::parseBracketSuffix(StringRef Name,
                                        OperandVector &Operands) {
   MCAsmParser &Parser = getParser();
   if (getLexer().is(AsmToken::LBrac)) {
     Operands.push_back(
         MipsOperand::CreateToken("[", getLexer().getLoc(), *this));
     Parser.Lex();
     if (parseOperand(Operands, Name)) {
       SMLoc Loc = getLexer().getLoc();
-      Parser.eatToEndOfStatement();
       return Error(Loc, "unexpected token in argument list");
     }
     if (Parser.getTok().isNot(AsmToken::RBrac)) {
       SMLoc Loc = getLexer().getLoc();
-      Parser.eatToEndOfStatement();
       return Error(Loc, "unexpected token, expected ']'");
     }
     Operands.push_back(
         MipsOperand::CreateToken("]", getLexer().getLoc(), *this));
     Parser.Lex();
   }
   return false;
 }
 
 bool MipsAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
                                      SMLoc NameLoc, OperandVector &Operands) {
   MCAsmParser &Parser = getParser();
   DEBUG(dbgs() << "ParseInstruction\n");
 
   // We have reached first instruction, module directive are now forbidden.
   getTargetStreamer().forbidModuleDirective();
 
   // Check if we have valid mnemonic
   if (!mnemonicIsValid(Name, 0)) {
-    Parser.eatToEndOfStatement();
     return Error(NameLoc, "unknown instruction");
   }
   // First operand in MCInst is instruction mnemonic.
   Operands.push_back(MipsOperand::CreateToken(Name, NameLoc, *this));
 
   // Read the remaining operands.
   if (getLexer().isNot(AsmToken::EndOfStatement)) {
     // Read the first operand.
     if (parseOperand(Operands, Name)) {
       SMLoc Loc = getLexer().getLoc();
-      Parser.eatToEndOfStatement();
       return Error(Loc, "unexpected token in argument list");
     }
     if (getLexer().is(AsmToken::LBrac) && parseBracketSuffix(Name, Operands))
       return true;
     // AFAIK, parenthesis suffixes are never on the first operand
 
     while (getLexer().is(AsmToken::Comma)) {
       Parser.Lex(); // Eat the comma.
       // Parse and remember the operand.
       if (parseOperand(Operands, Name)) {
         SMLoc Loc = getLexer().getLoc();
-        Parser.eatToEndOfStatement();
         return Error(Loc, "unexpected token in argument list");
       }
       // Parse bracket and parenthesis suffixes before we iterate
       if (getLexer().is(AsmToken::LBrac)) {
         if (parseBracketSuffix(Name, Operands))
           return true;
       } else if (getLexer().is(AsmToken::LParen) &&
                  parseParenSuffix(Name, Operands))
         return true;
     }
   }
   if (getLexer().isNot(AsmToken::EndOfStatement)) {
     SMLoc Loc = getLexer().getLoc();
-    Parser.eatToEndOfStatement();
     return Error(Loc, "unexpected token in argument list");
   }
   Parser.Lex(); // Consume the EndOfStatement.
   return false;
 }
 
 // FIXME: Given that these have the same name, these should both be
 // consistent on affecting the Parser.
 bool MipsAsmParser::reportParseError(Twine ErrorMsg) {
-  MCAsmParser &Parser = getParser();
   SMLoc Loc = getLexer().getLoc();
-  Parser.eatToEndOfStatement();
   return Error(Loc, ErrorMsg);
 }
 
 bool MipsAsmParser::reportParseError(SMLoc Loc, Twine ErrorMsg) {
   return Error(Loc, ErrorMsg);
 }
 
 bool MipsAsmParser::parseSetNoAtDirective() {
bool MipsAsmParser::parseSetFeature(uint64_t Feature) {
   }
   return false;
 }
 
 bool MipsAsmParser::eatComma(StringRef ErrorStr) {
   MCAsmParser &Parser = getParser();
   if (getLexer().isNot(AsmToken::Comma)) {
     SMLoc Loc = getLexer().getLoc();
-    Parser.eatToEndOfStatement();
     return Error(Loc, ErrorStr);
   }
 
   Parser.Lex(); // Eat the comma.
   return true;
 }
 
 // Used to determine if .cpload, .cprestore, and .cpsetup have any effect.
bool MipsAsmParser::parseDirectiveCPSetup() {
   if (ResTy == MatchOperand_NoMatch) {
     reportParseError("expected register containing function address");
     return false;
   }
 
   MipsOperand &FuncRegOpnd = static_cast<MipsOperand &>(*TmpReg[0]);
   if (!FuncRegOpnd.isGPRAsmReg()) {
     reportParseError(FuncRegOpnd.getStartLoc(), "invalid register");
-    Parser.eatToEndOfStatement();
     return false;
   }
 
   FuncReg = FuncRegOpnd.getGPR32Reg();
   TmpReg.clear();
 
   if (!eatComma("unexpected token, expected comma"))
     return true;
 
   ResTy = parseAnyRegister(TmpReg);
   if (ResTy == MatchOperand_NoMatch) {
     const MCExpr *OffsetExpr;
     int64_t OffsetVal;
     SMLoc ExprLoc = getLexer().getLoc();
 
     if (Parser.parseExpression(OffsetExpr) ||
         !OffsetExpr->evaluateAsAbsolute(OffsetVal)) {
       reportParseError(ExprLoc, "expected save register or stack offset");
-      Parser.eatToEndOfStatement();
       return false;
     }
 
     Save = OffsetVal;
     SaveIsReg = false;
   } else {
     MipsOperand &SaveOpnd = static_cast<MipsOperand &>(*TmpReg[0]);
     if (!SaveOpnd.isGPRAsmReg()) {
       reportParseError(SaveOpnd.getStartLoc(), "invalid register");
-      Parser.eatToEndOfStatement();
       return false;
     }
     Save = SaveOpnd.getGPR32Reg();
   }
 
   if (!eatComma("unexpected token, expected comma"))
     return true;
 

 }
 
 bool MipsAsmParser::parseDirectiveOption() {
   MCAsmParser &Parser = getParser();
   // Get the option token.
   AsmToken Tok = Parser.getTok();
   // At the moment only identifiers are supported.
   if (Tok.isNot(AsmToken::Identifier)) {
-    Error(Parser.getTok().getLoc(), "unexpected token, expected identifier");
-    Parser.eatToEndOfStatement();
-    return false;
+    return Error(Parser.getTok().getLoc(),
+                 "unexpected token, expected identifier");
   }
 
   StringRef Option = Tok.getIdentifier();
 
   if (Option == "pic0") {
     // MipsAsmParser needs to know if the current PIC mode changes.
     IsPicEnabled = false;
 
     getTargetStreamer().emitDirectiveOptionPic0();
     Parser.Lex();
     if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
-      Error(Parser.getTok().getLoc(),
+      return Error(Parser.getTok().getLoc(),
                    "unexpected token, expected end of statement");
-      Parser.eatToEndOfStatement();
     }
     return false;
   }
 
   if (Option == "pic2") {
     // MipsAsmParser needs to know if the current PIC mode changes.
     IsPicEnabled = true;
 
     getTargetStreamer().emitDirectiveOptionPic2();
     Parser.Lex();
     if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
-      Error(Parser.getTok().getLoc(),
+      return Error(Parser.getTok().getLoc(),
                    "unexpected token, expected end of statement");
-      Parser.eatToEndOfStatement();
     }
     return false;
   }
 
   // Unknown option.
   Warning(Parser.getTok().getLoc(), 
           "unknown option, expected 'pic0' or 'pic2'");
   Parser.eatToEndOfStatement();
if (Option == "oddspreg") {
     if (getLexer().isNot(AsmToken::EndOfStatement)) {
       reportParseError("unexpected token, expected end of statement");
       return false;
     }
 
     return false; // parseDirectiveModule has finished successfully.
   } else if (Option == "nooddspreg") {
     if (!isABI_O32()) {
-      Error(L, "'.module nooddspreg' requires the O32 ABI");
-      return false;
+      return Error(L, "'.module nooddspreg' requires the O32 ABI");
     }
 
     setModuleFeatureBits(Mips::FeatureNoOddSPReg, "nooddspreg");
 
     // Synchronize the abiflags information with the FeatureBits information we
     // changed above.
     getTargetStreamer().updateABIInfo(*this);
 
if (IDVal == ".option") {
     return false;
   }
 
   if (IDVal == ".abicalls") {
     getTargetStreamer().emitDirectiveAbiCalls();
     if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
       Error(Parser.getTok().getLoc(), 
             "unexpected token, expected end of statement");
-      // Clear line
-      Parser.eatToEndOfStatement();
     }
     return false;
   }
 
   if (IDVal == ".cpsetup") {
     parseDirectiveCPSetup();
     return false;
   }

llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp

#include "SparcGenAsmMatcher.inc"
 
   bool matchSparcAsmModifiers(const MCExpr *&EVal, SMLoc &EndLoc);
   bool parseDirectiveWord(unsigned Size, SMLoc L);
 
   bool is64Bit() const {
     return getSTI().getTargetTriple().getArch() == Triple::sparcv9;
   }
 
-  void expandSET(MCInst &Inst, SMLoc IDLoc,
+  bool expandSET(MCInst &Inst, SMLoc IDLoc,
                  SmallVectorImpl<MCInst> &Instructions);
 
 public:
   SparcAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
                 const MCInstrInfo &MII,
                 const MCTargetOptions &Options)
       : MCTargetAsmParser(Options, sti), Parser(parser) {
     // Initialize the set of available features.
MorphToMEMri(unsigned Base, std::unique_ptr<SparcOperand> Op) {
     Op->Mem.OffsetReg = 0;
     Op->Mem.Off = Imm;
     return Op;
   }
 };
 
 } // end namespace
 
-void SparcAsmParser::expandSET(MCInst &Inst, SMLoc IDLoc,
+bool SparcAsmParser::expandSET(MCInst &Inst, SMLoc IDLoc,
                                SmallVectorImpl<MCInst> &Instructions) {
   MCOperand MCRegOp = Inst.getOperand(0);
   MCOperand MCValOp = Inst.getOperand(1);
   assert(MCRegOp.isReg());
   assert(MCValOp.isImm() || MCValOp.isExpr());
 
   // the imm operand can be either an expression or an immediate.
   bool IsImm = Inst.getOperand(1).isImm();
   int64_t RawImmValue = IsImm ? MCValOp.getImm() : 0;
 
   // Allow either a signed or unsigned 32-bit immediate.
   if (RawImmValue < -2147483648LL || RawImmValue > 4294967295LL) {
-    Error(IDLoc, "set: argument must be between -2147483648 and 4294967295");
-    return;
+    return Error(IDLoc,
+                 "set: argument must be between -2147483648 and 4294967295");
   }
 
   // If the value was expressed as a large unsigned number, that's ok.
   // We want to see if it "looks like" a small signed number.
   int32_t ImmValue = RawImmValue;
   // For 'set' you can't use 'or' with a negative operand on V9 because
   // that would splat the sign bit across the upper half of the destination
   // register, whereas 'set' is defined to zero the high 32 bits.
else
       Expr = adjustPICRelocation(SparcMCExpr::VK_Sparc_LO, ValExpr);
     TmpInst.setLoc(IDLoc);
     TmpInst.setOpcode(SP::ORri);
     TmpInst.addOperand(MCRegOp);
     TmpInst.addOperand(PrevReg);
     TmpInst.addOperand(MCOperand::createExpr(Expr));
     Instructions.push_back(TmpInst);
   }
+  return false;
 }
 
 bool SparcAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
                                              OperandVector &Operands,
                                              MCStreamer &Out,
                                              uint64_t &ErrorInfo,
                                              bool MatchingInlineAsm) {
   MCInst Inst;
   SmallVector<MCInst, 8> Instructions;
   unsigned MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
                                               MatchingInlineAsm);
   switch (MatchResult) {
   case Match_Success: {
     switch (Inst.getOpcode()) {
     default:
       Inst.setLoc(IDLoc);
       Instructions.push_back(Inst);
       break;
     case SP::SET:
-      expandSET(Inst, IDLoc, Instructions);
+      if (expandSET(Inst, IDLoc, Instructions))
+        return true;
       break;
     }
 
     for (const MCInst &I : Instructions) {
       Out.EmitInstruction(I, getSTI());
     }
     return false;
   }
bool SparcAsmParser::ParseInstruction(ParseInstructionInfo &Info,
   // apply mnemonic aliases, if any, so that we can parse operands correctly.
   applyMnemonicAliases(Name, getAvailableFeatures(), 0);
 
   if (getLexer().isNot(AsmToken::EndOfStatement)) {
     // Read the first operand.
     if (getLexer().is(AsmToken::Comma)) {
       if (parseBranchModifiers(Operands) != MatchOperand_Success) {
         SMLoc Loc = getLexer().getLoc();
-        Parser.eatToEndOfStatement();
         return Error(Loc, "unexpected token");
       }
     }
     if (parseOperand(Operands, Name) != MatchOperand_Success) {
       SMLoc Loc = getLexer().getLoc();
-      Parser.eatToEndOfStatement();
       return Error(Loc, "unexpected token");
     }
 
     while (getLexer().is(AsmToken::Comma) || getLexer().is(AsmToken::Plus)) {
       if (getLexer().is(AsmToken::Plus)) {
       // Plus tokens are significant in software_traps (p83, sparcv8.pdf). We must capture them.
         Operands.push_back(SparcOperand::CreateToken("+", Parser.getTok().getLoc()));
       }
       Parser.Lex(); // Eat the comma or plus.
       // Parse and remember the operand.
       if (parseOperand(Operands, Name) != MatchOperand_Success) {
         SMLoc Loc = getLexer().getLoc();
-        Parser.eatToEndOfStatement();
         return Error(Loc, "unexpected token");
       }
     }
   }
   if (getLexer().isNot(AsmToken::EndOfStatement)) {
     SMLoc Loc = getLexer().getLoc();
-    Parser.eatToEndOfStatement();
     return Error(Loc, "unexpected token");
   }
   Parser.Lex(); // Consume the EndOfStatement.
   return false;
 }
 
 bool SparcAsmParser::
 ParseDirective(AsmToken DirectiveID)

llvm/trunk/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp

bool SystemZAsmParser::ParseInstruction(ParseInstructionInfo &Info,
                                         StringRef Name, SMLoc NameLoc,
                                         OperandVector &Operands) {
   Operands.push_back(SystemZOperand::createToken(Name, NameLoc));
 
   // Read the remaining operands.
   if (getLexer().isNot(AsmToken::EndOfStatement)) {
     // Read the first operand.
     if (parseOperand(Operands, Name)) {
-      Parser.eatToEndOfStatement();
       return true;
     }
 
     // Read any subsequent operands.
     while (getLexer().is(AsmToken::Comma)) {
       Parser.Lex();
       if (parseOperand(Operands, Name)) {
-        Parser.eatToEndOfStatement();
         return true;
       }
     }
     if (getLexer().isNot(AsmToken::EndOfStatement)) {
       SMLoc Loc = getLexer().getLoc();
-      Parser.eatToEndOfStatement();
       return Error(Loc, "unexpected token in argument list");
     }
   }
 
   // Consume the EndOfStatement.
   Parser.Lex();
   return false;
 }

llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp

void onRParen() {
       case IES_RPAREN:
         State = IES_RPAREN;
         IC.pushOperator(IC_RPAREN);
         break;
       }
     }
   };
 
-  bool Error(SMLoc L, const Twine &Msg,
-             ArrayRef<SMRange> Ranges = None,
-             bool MatchingInlineAsm = false) {
-    MCAsmParser &Parser = getParser();
-    if (MatchingInlineAsm) return true;
-    return Parser.Error(L, Msg, Ranges);
-  }
-
-  bool ErrorAndEatStatement(SMLoc L, const Twine &Msg,
-          ArrayRef<SMRange> Ranges = None,
+  bool Error(SMLoc L, const Twine &Msg, SMRange Range = None,
              bool MatchingInlineAsm = false) {
     MCAsmParser &Parser = getParser();
+    if (MatchingInlineAsm) {
       Parser.eatToEndOfStatement();
-    return Error(L, Msg, Ranges, MatchingInlineAsm);
+      return false;
+    }
+    return Parser.Error(L, Msg, Range);
   }
 
   std::nullptr_t ErrorOperand(SMLoc Loc, StringRef Msg) {
     Error(Loc, Msg);
     return nullptr;
   }
 
   std::unique_ptr<X86Operand> DefaultMemSIOperand(SMLoc Loc);
bool X86AsmParser::HandleAVX512Operand(OperandVector &Operands,
   if(getSTI().getFeatureBits()[X86::FeatureAVX512]) {
     if (getLexer().is(AsmToken::LCurly)) {
       // Eat "{" and mark the current place.
       const SMLoc consumedToken = consumeToken();
       // Distinguish {1to<NUM>} from {%k<NUM>}.
       if(getLexer().is(AsmToken::Integer)) {
         // Parse memory broadcasting ({1to<NUM>}).
         if (getLexer().getTok().getIntVal() != 1)
-          return !ErrorAndEatStatement(getLexer().getLoc(),
-                                       "Expected 1to<NUM> at this point");
+          return !TokError("Expected 1to<NUM> at this point");
         Parser.Lex();  // Eat "1" of 1to8
         if (!getLexer().is(AsmToken::Identifier) ||
             !getLexer().getTok().getIdentifier().startswith("to"))
-          return !ErrorAndEatStatement(getLexer().getLoc(),
-                                       "Expected 1to<NUM> at this point");
+          return !TokError("Expected 1to<NUM> at this point");
         // Recognize only reasonable suffixes.
         const char *BroadcastPrimitive =
           StringSwitch<const char*>(getLexer().getTok().getIdentifier())
             .Case("to2",  "{1to2}")
             .Case("to4",  "{1to4}")
             .Case("to8",  "{1to8}")
             .Case("to16", "{1to16}")
             .Default(nullptr);
         if (!BroadcastPrimitive)
-          return !ErrorAndEatStatement(getLexer().getLoc(),
-                                       "Invalid memory broadcast primitive.");
+          return !TokError("Invalid memory broadcast primitive.");
         Parser.Lex();  // Eat "toN" of 1toN
         if (!getLexer().is(AsmToken::RCurly))
-          return !ErrorAndEatStatement(getLexer().getLoc(),
-                                       "Expected } at this point");
+          return !TokError("Expected } at this point");
         Parser.Lex();  // Eat "}"
         Operands.push_back(X86Operand::CreateToken(BroadcastPrimitive,
                                                    consumedToken));
         // No AVX512 specific primitives can pass
         // after memory broadcasting, so return.
         return true;
       } else {
         // Parse mask register {%k1}
         Operands.push_back(X86Operand::CreateToken("{", consumedToken));
         if (std::unique_ptr<X86Operand> Op = ParseOperand()) {
           Operands.push_back(std::move(Op));
           if (!getLexer().is(AsmToken::RCurly))
-            return !ErrorAndEatStatement(getLexer().getLoc(),
-                                         "Expected } at this point");
+            return !TokError("Expected } at this point");
           Operands.push_back(X86Operand::CreateToken("}", consumeToken()));
 
           // Parse "zeroing non-masked" semantic {z}
           if (getLexer().is(AsmToken::LCurly)) {
             Operands.push_back(X86Operand::CreateToken("{z}", consumeToken()));
             if (!getLexer().is(AsmToken::Identifier) ||
                 getLexer().getTok().getIdentifier() != "z")
-              return !ErrorAndEatStatement(getLexer().getLoc(),
-                                           "Expected z at this point");
+              return !TokError("Expected z at this point");
             Parser.Lex();  // Eat the z
             if (!getLexer().is(AsmToken::RCurly))
-              return !ErrorAndEatStatement(getLexer().getLoc(),
-                                           "Expected } at this point");
+              return !TokError("Expected } at this point");
             Parser.Lex();  // Eat the }
           }
         }
       }
     }
   }
   return true;
 }
if (getLexer().isNot(AsmToken::EndOfStatement) && !isPrefix) {
 
     // Read the operands.
     while(1) {
       if (std::unique_ptr<X86Operand> Op = ParseOperand()) {
         Operands.push_back(std::move(Op));
         if (!HandleAVX512Operand(Operands, *Operands.back()))
           return true;
       } else {
-         Parser.eatToEndOfStatement();
          return true;
       }
       // check for comma and eat it
       if (getLexer().is(AsmToken::Comma))
         Parser.Lex();
       else
         break;
      }
 
     // In MS inline asm curly braces mark the begining/end of a block, therefore
     // they should be interepreted as end of statement
     CurlyAsEndOfStatement =
         isParsingIntelSyntax() && isParsingInlineAsm() &&
         (getLexer().is(AsmToken::LCurly) || getLexer().is(AsmToken::RCurly));
     if (getLexer().isNot(AsmToken::EndOfStatement) && !CurlyAsEndOfStatement)
-      return ErrorAndEatStatement(getLexer().getLoc(),
-                                  "unexpected token in argument list");
+      return TokError("unexpected token in argument list");
    }
 
   // Consume the EndOfStatement or the prefix separator Slash
   if (getLexer().is(AsmToken::EndOfStatement) ||
       (isPrefix && getLexer().is(AsmToken::Slash)))
     Parser.Lex();
   else if (CurlyAsEndOfStatement)
     // Add an actual EndOfStatement before the curly brace
if (!MatchingInlineAsm)
       EmitInstruction(Inst, Operands, Out);
     Operands[0] = X86Operand::CreateToken(Repl, IDLoc);
   }
 }
 
 bool X86AsmParser::ErrorMissingFeature(SMLoc IDLoc, uint64_t ErrorInfo,
                                        bool MatchingInlineAsm) {
   assert(ErrorInfo && "Unknown missing feature!");
-  ArrayRef<SMRange> EmptyRanges = None;
   SmallString<126> Msg;
   raw_svector_ostream OS(Msg);
   OS << "instruction requires:";
   uint64_t Mask = 1;
   for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
     if (ErrorInfo & Mask)
       OS << ' ' << getSubtargetFeatureName(ErrorInfo & Mask);
     Mask <<= 1;
   }
-  return Error(IDLoc, OS.str(), EmptyRanges, MatchingInlineAsm);
+  return Error(IDLoc, OS.str(), SMRange(), MatchingInlineAsm);
 }
 
 bool X86AsmParser::MatchAndEmitATTInstruction(SMLoc IDLoc, unsigned &Opcode,
                                               OperandVector &Operands,
                                               MCStreamer &Out,
                                               uint64_t &ErrorInfo,
                                               bool MatchingInlineAsm) {
   assert(!Operands.empty() && "Unexpect empty operand list!");
   X86Operand &Op = static_cast<X86Operand &>(*Operands[0]);
   assert(Op.isToken() && "Leading operand should always be a mnemonic!");
-  ArrayRef<SMRange> EmptyRanges = None;
+  SMRange EmptyRange = None;
 
   // First, handle aliases that expand to multiple instructions.
   MatchFPUWaitAlias(IDLoc, Op, Operands, Out, MatchingInlineAsm);
 
   bool WasOriginallyInvalidOperand = false;
   MCInst Inst;
 
   // First, try a direct match.
if (NumSuccessfulMatches > 1) {
     for (unsigned i = 0; i != NumMatches; ++i) {
       if (i != 0)
         OS << ", ";
       if (i + 1 == NumMatches)
         OS << "or ";
       OS << "'" << Base << MatchChars[i] << "'";
     }
     OS << ")";
-    Error(IDLoc, OS.str(), EmptyRanges, MatchingInlineAsm);
+    Error(IDLoc, OS.str(), EmptyRange, MatchingInlineAsm);
     return true;
   }
 
   // Okay, we know that none of the variants matched successfully.
 
   // If all of the instructions reported an invalid mnemonic, then the original
   // mnemonic was invalid.
   if (std::count(std::begin(Match), std::end(Match), Match_MnemonicFail) == 4) {
     if (!WasOriginallyInvalidOperand) {
-      SMRange OpRange = Op.getLocRange();
-      ArrayRef<SMRange> Ranges = MatchingInlineAsm ? EmptyRanges : OpRange;
       return Error(IDLoc, "invalid instruction mnemonic '" + Base + "'",
-                   Ranges, MatchingInlineAsm);
+                   Op.getLocRange(), MatchingInlineAsm);
     }
 
     // Recover location info for the operand if we know which was the problem.
     if (ErrorInfo != ~0ULL) {
       if (ErrorInfo >= Operands.size())
-        return Error(IDLoc, "too few operands for instruction",
-                     EmptyRanges, MatchingInlineAsm);
+        return Error(IDLoc, "too few operands for instruction", EmptyRange,
+                     MatchingInlineAsm);
 
       X86Operand &Operand = (X86Operand &)*Operands[ErrorInfo];
       if (Operand.getStartLoc().isValid()) {
         SMRange OperandRange = Operand.getLocRange();
         return Error(Operand.getStartLoc(), "invalid operand for instruction",
                      OperandRange, MatchingInlineAsm);
       }
     }
 
-    return Error(IDLoc, "invalid operand for instruction", EmptyRanges,
+    return Error(IDLoc, "invalid operand for instruction", EmptyRange,
                  MatchingInlineAsm);
   }
 
   // If one instruction matched with a missing feature, report this as a
   // missing feature.
   if (std::count(std::begin(Match), std::end(Match),
                  Match_MissingFeature) == 1) {
     ErrorInfo = ErrorInfoMissingFeature;
     return ErrorMissingFeature(IDLoc, ErrorInfoMissingFeature,
                                MatchingInlineAsm);
   }
 
   // If one instruction matched with an invalid operand, report this as an
   // operand failure.
   if (std::count(std::begin(Match), std::end(Match),
                  Match_InvalidOperand) == 1) {
-    return Error(IDLoc, "invalid operand for instruction", EmptyRanges,
+    return Error(IDLoc, "invalid operand for instruction", EmptyRange,
                  MatchingInlineAsm);
   }
 
   // If all of these were an outright failure, report it in a useless way.
   Error(IDLoc, "unknown use of instruction mnemonic without a size suffix",
-        EmptyRanges, MatchingInlineAsm);
+        EmptyRange, MatchingInlineAsm);
   return true;
 }
 
 bool X86AsmParser::MatchAndEmitIntelInstruction(SMLoc IDLoc, unsigned &Opcode,
                                                 OperandVector &Operands,
                                                 MCStreamer &Out,
                                                 uint64_t &ErrorInfo,
                                                 bool MatchingInlineAsm) {
   assert(!Operands.empty() && "Unexpect empty operand list!");
   X86Operand &Op = static_cast<X86Operand &>(*Operands[0]);
   assert(Op.isToken() && "Leading operand should always be a mnemonic!");
   StringRef Mnemonic = Op.getToken();
-  ArrayRef<SMRange> EmptyRanges = None;
+  SMRange EmptyRange = None;
 
   // First, handle aliases that expand to multiple instructions.
   MatchFPUWaitAlias(IDLoc, Op, Operands, Out, MatchingInlineAsm);
 
   MCInst Inst;
 
   // Find one unsized memory operand, if present.
   X86Operand *UnsizedMemOp = nullptr;
bool X86AsmParser::MatchAndEmitIntelInstruction(SMLoc IDLoc, unsigned &Opcode,
   }
 
   // Restore the size of the unsized memory operand if we modified it.
   if (UnsizedMemOp)
     UnsizedMemOp->Mem.Size = 0;
 
   // If it's a bad mnemonic, all results will be the same.
   if (Match.back() == Match_MnemonicFail) {
-    ArrayRef<SMRange> Ranges =
-        MatchingInlineAsm ? EmptyRanges : Op.getLocRange();
     return Error(IDLoc, "invalid instruction mnemonic '" + Mnemonic + "'",
-                 Ranges, MatchingInlineAsm);
+                 Op.getLocRange(), MatchingInlineAsm);
   }
 
   // If exactly one matched, then we treat that as a successful match (and the
   // instruction will already have been filled in correctly, since the failing
   // matches won't have modified it).
   unsigned NumSuccessfulMatches =
       std::count(std::begin(Match), std::end(Match), Match_Success);
   if (NumSuccessfulMatches == 1) {
     // Some instructions need post-processing to, for example, tweak which
     // encoding is selected. Loop on it while changes happen so the individual
     // transformations can chain off each other.
     if (!MatchingInlineAsm)
       while (processInstruction(Inst, Operands))
         ;
     Inst.setLoc(IDLoc);
     if (!MatchingInlineAsm)
       EmitInstruction(Inst, Operands, Out);
     Opcode = Inst.getOpcode();
     return false;
   } else if (NumSuccessfulMatches > 1) {
     assert(UnsizedMemOp &&
            "multiple matches only possible with unsized memory operands");
-    SMRange OpRange = UnsizedMemOp->getLocRange();
-    ArrayRef<SMRange> Ranges = MatchingInlineAsm ? EmptyRanges : OpRange;
     return Error(UnsizedMemOp->getStartLoc(),
                  "ambiguous operand size for instruction '" + Mnemonic + "\'",
-                 Ranges, MatchingInlineAsm);
+                 UnsizedMemOp->getLocRange(), MatchingInlineAsm);
   }
 
   // If one instruction matched with a missing feature, report this as a
   // missing feature.
   if (std::count(std::begin(Match), std::end(Match),
                  Match_MissingFeature) == 1) {
     ErrorInfo = ErrorInfoMissingFeature;
     return ErrorMissingFeature(IDLoc, ErrorInfoMissingFeature,
                                MatchingInlineAsm);
   }
 
   // If one instruction matched with an invalid operand, report this as an
   // operand failure.
   if (std::count(std::begin(Match), std::end(Match),
                  Match_InvalidOperand) == 1) {
-    return Error(IDLoc, "invalid operand for instruction", EmptyRanges,
+    return Error(IDLoc, "invalid operand for instruction", EmptyRange,
                  MatchingInlineAsm);
   }
 
   // If all of these were an outright failure, report it in a useless way.
-  return Error(IDLoc, "unknown instruction mnemonic", EmptyRanges,
+  return Error(IDLoc, "unknown instruction mnemonic", EmptyRange,
                MatchingInlineAsm);
 }
 
 bool X86AsmParser::OmitRegisterFromClobberLists(unsigned RegNo) {
   return X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(RegNo);
 }
 
 bool X86AsmParser::ParseDirective(AsmToken DirectiveID) {

llvm/trunk/test/MC/AArch64/armv8.1a-rdma.s

 // CHECK: sqrdmlah  v0.2s, v1.2s, v2.2s // encoding: [0x20,0x84,0x82,0x2e]
 // CHECK: sqrdmlsh  v0.2s, v1.2s, v2.2s // encoding: [0x20,0x8c,0x82,0x2e]
 // CHECK: sqrdmlah  v0.4s, v1.4s, v2.4s // encoding: [0x20,0x84,0x82,0x6e]
 // CHECK: sqrdmlsh  v0.4s, v1.4s, v2.4s // encoding: [0x20,0x8c,0x82,0x6e]
 // CHECK: sqrdmlah  v0.8h, v1.8h, v2.8h // encoding: [0x20,0x84,0x42,0x6e]
 // CHECK: sqrdmlsh  v0.8h, v1.8h, v2.8h // encoding: [0x20,0x8c,0x42,0x6e]
 
   sqrdmlah v0.2h, v1.2h, v2.2h
+// CHECK-ERROR: [[@LINE-1]]:12: error: invalid operand for instruction
   sqrdmlsh v0.2h, v1.2h, v2.2h
+// CHECK-ERROR: [[@LINE-1]]:12: error: invalid operand for instruction
   sqrdmlah v0.8s, v1.8s, v2.8s
+// CHECK-ERROR: [[@LINE-1]]:12: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-2]]:19: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-3]]:26: error: invalid vector kind qualifier
   sqrdmlsh v0.8s, v1.8s, v2.8s
+// CHECK-ERROR: [[@LINE-1]]:12: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-2]]:19: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-3]]:26: error: invalid vector kind qualifier
   sqrdmlah v0.2s, v1.4h, v2.8h
+// CHECK-ERROR: [[@LINE-1]]:19: error: invalid operand for instruction
   sqrdmlsh v0.4s, v1.8h, v2.2s
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR:   sqrdmlah v0.2h, v1.2h, v2.2h
-// CHECK-ERROR:            ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR:   sqrdmlsh v0.2h, v1.2h, v2.2h
-// CHECK-ERROR:            ^
-// CHECK-ERROR: error: invalid vector kind qualifier
-// CHECK-ERROR:   sqrdmlah v0.8s, v1.8s, v2.8s
-// CHECK-ERROR:            ^
-// CHECK-ERROR: error: invalid vector kind qualifier
-// CHECK-ERROR:   sqrdmlah v0.8s, v1.8s, v2.8s
-// CHECK-ERROR:                   ^
-// CHECK-ERROR: error: invalid vector kind qualifier
-// CHECK-ERROR:   sqrdmlah v0.8s, v1.8s, v2.8s
-// CHECK-ERROR:                          ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR:   sqrdmlah v0.8s, v1.8s, v2.8s
-// CHECK-ERROR:            ^
-// CHECK-ERROR: error: invalid vector kind qualifier
-// CHECK-ERROR:   sqrdmlsh v0.8s, v1.8s, v2.8s
-// CHECK-ERROR:            ^
-// CHECK-ERROR: error: invalid vector kind qualifier
-// CHECK-ERROR:   sqrdmlsh v0.8s, v1.8s, v2.8s
-// CHECK-ERROR:                   ^
-// CHECK-ERROR: error: invalid vector kind qualifier
-// CHECK-ERROR:   sqrdmlsh v0.8s, v1.8s, v2.8s
-// CHECK-ERROR:                          ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR:   sqrdmlsh v0.8s, v1.8s, v2.8s
-// CHECK-ERROR:            ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR:   sqrdmlah v0.2s, v1.4h, v2.8h
-// CHECK-ERROR:                   ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR:   sqrdmlsh v0.4s, v1.8h, v2.2s
-// CHECK-ERROR:                   ^
+// CHECK-ERROR: [[@LINE-1]]:19: error: invalid operand for instruction
 
   //AdvSIMD RDMA scalar
   sqrdmlah h0, h1, h2
   sqrdmlsh h0, h1, h2
   sqrdmlah s0, s1, s2
   sqrdmlsh s0, s1, s2
 // CHECK: sqrdmlah h0, h1, h2  // encoding: [0x20,0x84,0x42,0x7e]
 // CHECK: sqrdmlsh h0, h1, h2  // encoding: [0x20,0x8c,0x42,0x7e]

llvm/trunk/test/MC/AArch64/inst-directive-diagnostic.s

// CHECK-ERROR: expected expression following directive
     .inst 0x5e104020,
 // CHECK-ERROR: expected expression
 
     .inst .Label
 // CHECK-ERROR: expected constant expression
 
     .inst 0x5e104020 0x5e104020
 // CHECK-ERROR: unexpected token in directive
+
+// CHECK-ERROR-NOT: unexpected token at start of statement  

llvm/trunk/test/MC/AArch64/neon-diagnostics.s

//----------------------------------------------------------------------
         ushll2 v0.2d, v1.4s, #33
 
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        sshll v0.4s, v15.2s, #3
 // CHECK-ERROR:                         ^
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        ushll v1.16b, v25.16b, #6
 // CHECK-ERROR:                 ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid vector kind qualifier
 // CHECK-ERROR:        sshll2 v0.2d, v3.8s, #15
 // CHECK-ERROR:                      ^
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        ushll2 v1.4s, v25.4s, #7
 // CHECK-ERROR:                          ^
 // CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 7]
 // CHECK-ERROR:        sshll v0.8h, v1.8b, #-1
 // CHECK-ERROR:                            ^

 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        saddl v0.2d, v1.2d, v2.2s
 // CHECK-ERROR:                        ^
 
         saddl2 v0.4s, v1.8s, v2.8h
         saddl2 v0.8h, v1.16h, v2.16b
         saddl2 v0.2d, v1.4d, v2.4s
 
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid vector kind qualifier
 // CHECK-ERROR:        saddl2 v0.4s, v1.8s, v2.8h
 // CHECK-ERROR:                      ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid vector kind qualifier
 // CHECK-ERROR:        saddl2 v0.8h, v1.16h, v2.16b
 // CHECK-ERROR:                      ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid vector kind qualifier
 // CHECK-ERROR:        saddl2 v0.2d, v1.4d, v2.4s
 // CHECK-ERROR:                      ^
 
         uaddl v0.8h, v1.8h, v2.8b
         uaddl v0.4s, v1.4s, v2.4h
         uaddl v0.2d, v1.2d, v2.2s
 
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        uaddl v0.8h, v1.8h, v2.8b
 // CHECK-ERROR:                        ^
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        uaddl v0.4s, v1.4s, v2.4h
 // CHECK-ERROR:                        ^
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        uaddl v0.2d, v1.2d, v2.2s
 // CHECK-ERROR:                        ^
 
         uaddl2 v0.8h, v1.16h, v2.16b
         uaddl2 v0.4s, v1.8s, v2.8h
         uaddl2 v0.2d, v1.4d, v2.4s
 
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR:        uaddl2 v0.8h, v1.16h, v2.16b
-// CHECK-ERROR:                      ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR:        uaddl2 v0.4s, v1.8s, v2.8h
-// CHECK-ERROR:                      ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR:        uaddl2 v0.2d, v1.4d, v2.4s
-// CHECK-ERROR:                      ^
+// CHECK-ERROR: [[@LINE-4]]:23: error: invalid vector kind qualifier
+// CHECK-ERROR-NEXT:        uaddl2 v0.8h, v1.16h, v2.16b
+// CHECK-ERROR: [[@LINE-5]]:23: error: invalid vector kind qualifier
+// CHECK-ERROR-NEXT:        uaddl2 v0.4s, v1.8s, v2.8h
+// CHECK-ERROR: [[@LINE-6]]:23: error: invalid vector kind qualifier
+// CHECK-ERROR-NEXT:        uaddl2 v0.2d, v1.4d, v2.4s
 
         ssubl v0.8h, v1.8h, v2.8b
         ssubl v0.4s, v1.4s, v2.4h
         ssubl v0.2d, v1.2d, v2.2s
 
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR:        ssubl v0.8h, v1.8h, v2.8b
-// CHECK-ERROR:                        ^
+// CHECK-ERROR: [[@LINE-4]]:22: error: invalid operand for instruction
+// CHECK-ERROR-NEXT:        ssubl v0.8h, v1.8h, v2.8b
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        ssubl v0.4s, v1.4s, v2.4h
 // CHECK-ERROR:                        ^
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        ssubl v0.2d, v1.2d, v2.2s
 // CHECK-ERROR:                        ^
 
         ssubl2 v0.8h, v1.16h, v2.16b
         ssubl2 v0.4s, v1.8s, v2.8h
         ssubl2 v0.2d, v1.4d, v2.4s
 
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-4]]:23: error: invalid vector kind qualifier
 // CHECK-ERROR:        ssubl2 v0.8h, v1.16h, v2.16b
 // CHECK-ERROR:                      ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid vector kind qualifier
 // CHECK-ERROR:        ssubl2 v0.4s, v1.8s, v2.8h
 // CHECK-ERROR:                      ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid vector kind qualifier
 // CHECK-ERROR:        ssubl2 v0.2d, v1.4d, v2.4s
 // CHECK-ERROR:                      ^
 
         usubl v0.8h, v1.8h, v2.8b
         usubl v0.4s, v1.4s, v2.4h
         usubl v0.2d, v1.2d, v2.2s
 
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        usubl v0.8h, v1.8h, v2.8b
 // CHECK-ERROR:                        ^
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        usubl v0.4s, v1.4s, v2.4h
 // CHECK-ERROR:                        ^
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        usubl v0.2d, v1.2d, v2.2s
 // CHECK-ERROR:                        ^
 
         usubl2 v0.8h, v1.16h, v2.16b
         usubl2 v0.4s, v1.8s, v2.8h
         usubl2 v0.2d, v1.4d, v2.4s
 
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-4]]:23: error: invalid vector kind qualifier
 // CHECK-ERROR:        usubl2 v0.8h, v1.16h, v2.16b
-// CHECK-ERROR:                      ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-5]]:23: error: invalid vector kind qualifier
 // CHECK-ERROR:        usubl2 v0.4s, v1.8s, v2.8h
-// CHECK-ERROR:                      ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-6]]:23: error: invalid vector kind qualifier
 // CHECK-ERROR:        usubl2 v0.2d, v1.4d, v2.4s
-// CHECK-ERROR:                      ^
 
         sabal v0.8h, v1.8h, v2.8b
         sabal v0.4s, v1.4s, v2.4h
         sabal v0.2d, v1.2d, v2.2s
 
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        sabal v0.8h, v1.8h, v2.8b
 // CHECK-ERROR:                        ^
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        sabal v0.4s, v1.4s, v2.4h
 // CHECK-ERROR:                        ^
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        sabal v0.2d, v1.2d, v2.2s
 // CHECK-ERROR:                        ^
 
         sabal2 v0.8h, v1.16h, v2.16b
         sabal2 v0.4s, v1.8s, v2.8h
         sabal2 v0.2d, v1.4d, v2.4s
 
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid vector kind qualifier
 // CHECK-ERROR:        sabal2 v0.8h, v1.16h, v2.16b
 // CHECK-ERROR:                      ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid vector kind qualifier
 // CHECK-ERROR:        sabal2 v0.4s, v1.8s, v2.8h
 // CHECK-ERROR:                      ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid vector kind qualifier
 // CHECK-ERROR:        sabal2 v0.2d, v1.4d, v2.4s
 // CHECK-ERROR:                      ^
 
         uabal v0.8h, v1.8h, v2.8b
         uabal v0.4s, v1.4s, v2.4h
         uabal v0.2d, v1.2d, v2.2s
 
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        uabal v0.8h, v1.8h, v2.8b
 // CHECK-ERROR:                        ^
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        uabal v0.4s, v1.4s, v2.4h
 // CHECK-ERROR:                        ^
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        uabal v0.2d, v1.2d, v2.2s
 // CHECK-ERROR:                        ^
 
         uabal2 v0.8h, v1.16h, v2.16b
         uabal2 v0.4s, v1.8s, v2.8h
         uabal2 v0.2d, v1.4d, v2.4s
 
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-4]]:23: error: invalid vector kind qualifier
 // CHECK-ERROR:        uabal2 v0.8h, v1.16h, v2.16b
-// CHECK-ERROR:                      ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-5]]:23: error: invalid vector kind qualifier
 // CHECK-ERROR:        uabal2 v0.4s, v1.8s, v2.8h
-// CHECK-ERROR:                      ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-6]]:23: error: invalid vector kind qualifier
 // CHECK-ERROR:        uabal2 v0.2d, v1.4d, v2.4s
-// CHECK-ERROR:                      ^
 
         sabdl v0.8h, v1.8h, v2.8b
         sabdl v0.4s, v1.4s, v2.4h
         sabdl v0.2d, v1.2d, v2.2s
 
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        sabdl v0.8h, v1.8h, v2.8b
 // CHECK-ERROR:                        ^
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        sabdl v0.4s, v1.4s, v2.4h
 // CHECK-ERROR:                        ^
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        sabdl v0.2d, v1.2d, v2.2s
 // CHECK-ERROR:                        ^
 
         sabdl2 v0.8h, v1.16h, v2.16b
         sabdl2 v0.4s, v1.8s, v2.8h
         sabdl2 v0.2d, v1.4d, v2.4s
 
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-4]]:23: error: invalid vector kind qualifier
 // CHECK-ERROR:        sabdl2 v0.8h, v1.16h, v2.16b
-// CHECK-ERROR:                      ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-5]]:23: error: invalid vector kind qualifier
 // CHECK-ERROR:        sabdl2 v0.4s, v1.8s, v2.8h
-// CHECK-ERROR:                      ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-6]]:23: error: invalid vector kind qualifier
 // CHECK-ERROR:        sabdl2 v0.2d, v1.4d, v2.4s
-// CHECK-ERROR:                      ^
 
         uabdl v0.8h, v1.8h, v2.8b
         uabdl v0.4s, v1.4s, v2.4h
         uabdl v0.2d, v1.2d, v2.2s
 
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        uabdl v0.8h, v1.8h, v2.8b
 // CHECK-ERROR:                        ^
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        uabdl v0.4s, v1.4s, v2.4h
 // CHECK-ERROR:                        ^
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        uabdl v0.2d, v1.2d, v2.2s
 // CHECK-ERROR:                        ^
 
         uabdl2 v0.8h, v1.16h, v2.16b
         uabdl2 v0.4s, v1.8s, v2.8h
         uabdl2 v0.2d, v1.4d, v2.4s
 
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-4]]:23: error: invalid vector kind qualifier
 // CHECK-ERROR:        uabdl2 v0.8h, v1.16h, v2.16b
-// CHECK-ERROR:                      ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-5]]:23: error: invalid vector kind qualifier
 // CHECK-ERROR:        uabdl2 v0.4s, v1.8s, v2.8h
-// CHECK-ERROR:                      ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-6]]:23: error: invalid vector kind qualifier
 // CHECK-ERROR:        uabdl2 v0.2d, v1.4d, v2.4s
-// CHECK-ERROR:                      ^
 
         smlal v0.8h, v1.8h, v2.8b
         smlal v0.4s, v1.4s, v2.4h
         smlal v0.2d, v1.2d, v2.2s
 
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        smlal v0.8h, v1.8h, v2.8b
 // CHECK-ERROR:                        ^
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        smlal v0.4s, v1.4s, v2.4h
 // CHECK-ERROR:                        ^
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        smlal v0.2d, v1.2d, v2.2s
 // CHECK-ERROR:                        ^
 
         smlal2 v0.8h, v1.16h, v2.16b
         smlal2 v0.4s, v1.8s, v2.8h
         smlal2 v0.2d, v1.4d, v2.4s
 
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-4]]:23: error: invalid vector kind qualifier
 // CHECK-ERROR:        smlal2 v0.8h, v1.16h, v2.16b
-// CHECK-ERROR:                      ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-5]]:23: error: invalid vector kind qualifier
 // CHECK-ERROR:        smlal2 v0.4s, v1.8s, v2.8h
-// CHECK-ERROR:                      ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-6]]:23: error: invalid vector kind qualifier
 // CHECK-ERROR:        smlal2 v0.2d, v1.4d, v2.4s
-// CHECK-ERROR:                      ^
 
         umlal v0.8h, v1.8h, v2.8b
         umlal v0.4s, v1.4s, v2.4h
         umlal v0.2d, v1.2d, v2.2s
 
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-4]]:22: error: invalid operand for instruction
 // CHECK-ERROR:        umlal v0.8h, v1.8h, v2.8b
-// CHECK-ERROR:                        ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-5]]:22: error: invalid operand for instruction
 // CHECK-ERROR:        umlal v0.4s, v1.4s, v2.4h
-// CHECK-ERROR:                        ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-6]]:22: error: invalid operand for instruction
 // CHECK-ERROR:        umlal v0.2d, v1.2d, v2.2s
-// CHECK-ERROR:                        ^
 
         umlal2 v0.8h, v1.16h, v2.16b
         umlal2 v0.4s, v1.8s, v2.8h
         umlal2 v0.2d, v1.4d, v2.4s
 
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-4]]:23: error: invalid vector kind qualifier
 // CHECK-ERROR:        umlal2 v0.8h, v1.16h, v2.16b
-// CHECK-ERROR:                      ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-5]]:23: error: invalid vector kind qualifier
 // CHECK-ERROR:        umlal2 v0.4s, v1.8s, v2.8h
-// CHECK-ERROR:                      ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-6]]:23: error: invalid vector kind qualifier
 // CHECK-ERROR:        umlal2 v0.2d, v1.4d, v2.4s
-// CHECK-ERROR:                      ^
 
         smlsl v0.8h, v1.8h, v2.8b
         smlsl v0.4s, v1.4s, v2.4h
         smlsl v0.2d, v1.2d, v2.2s
 
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-4]]:22: error: invalid operand for instruction
 // CHECK-ERROR:        smlsl v0.8h, v1.8h, v2.8b
-// CHECK-ERROR:                        ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-5]]:22: error: invalid operand for instruction
 // CHECK-ERROR:        smlsl v0.4s, v1.4s, v2.4h
-// CHECK-ERROR:                        ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-6]]:22: error: invalid operand for instruction
 // CHECK-ERROR:        smlsl v0.2d, v1.2d, v2.2s
-// CHECK-ERROR:                        ^
 
         smlsl2 v0.8h, v1.16h, v2.16b
         smlsl2 v0.4s, v1.8s, v2.8h
         smlsl2 v0.2d, v1.4d, v2.4s
 
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-4]]:23: error: invalid vector kind qualifier
 // CHECK-ERROR:        smlsl2 v0.8h, v1.16h, v2.16b
-// CHECK-ERROR:                      ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-5]]:23: error: invalid vector kind qualifier
 // CHECK-ERROR:        smlsl2 v0.4s, v1.8s, v2.8h
-// CHECK-ERROR:                      ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-6]]:23: error: invalid vector kind qualifier
 // CHECK-ERROR:        smlsl2 v0.2d, v1.4d, v2.4s
-// CHECK-ERROR:                      ^
 
         umlsl v0.8h, v1.8h, v2.8b
         umlsl v0.4s, v1.4s, v2.4h
         umlsl v0.2d, v1.2d, v2.2s
 
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        umlsl v0.8h, v1.8h, v2.8b
 // CHECK-ERROR:                        ^
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        umlsl v0.4s, v1.4s, v2.4h
 // CHECK-ERROR:                        ^
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        umlsl v0.2d, v1.2d, v2.2s
 // CHECK-ERROR:                        ^
 
         umlsl2 v0.8h, v1.16h, v2.16b
         umlsl2 v0.4s, v1.8s, v2.8h
         umlsl2 v0.2d, v1.4d, v2.4s
 
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-4]]:23: error: invalid vector kind qualifier
 // CHECK-ERROR:        umlsl2 v0.8h, v1.16h, v2.16b
-// CHECK-ERROR:                      ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-5]]:23: error: invalid vector kind qualifier
 // CHECK-ERROR:        umlsl2 v0.4s, v1.8s, v2.8h
-// CHECK-ERROR:                      ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-6]]:23: error: invalid vector kind qualifier
 // CHECK-ERROR:        umlsl2 v0.2d, v1.4d, v2.4s
-// CHECK-ERROR:                      ^
 
         smull v0.8h, v1.8h, v2.8b
         smull v0.4s, v1.4s, v2.4h
         smull v0.2d, v1.2d, v2.2s
 
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        smull v0.8h, v1.8h, v2.8b
 // CHECK-ERROR:                        ^
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        smull v0.4s, v1.4s, v2.4h
 // CHECK-ERROR:                        ^
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        smull v0.2d, v1.2d, v2.2s
 // CHECK-ERROR:                        ^
 
         smull2 v0.8h, v1.16h, v2.16b
         smull2 v0.4s, v1.8s, v2.8h
         smull2 v0.2d, v1.4d, v2.4s
 
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-4]]:23: error: invalid vector kind qualifier
 // CHECK-ERROR:        smull2 v0.8h, v1.16h, v2.16b
-// CHECK-ERROR:                      ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-5]]:23: error: invalid vector kind qualifier
 // CHECK-ERROR:        smull2 v0.4s, v1.8s, v2.8h
-// CHECK-ERROR:                      ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-6]]:23: error: invalid vector kind qualifier
 // CHECK-ERROR:        smull2 v0.2d, v1.4d, v2.4s
-// CHECK-ERROR:                      ^
 
         umull v0.8h, v1.8h, v2.8b
         umull v0.4s, v1.4s, v2.4h
         umull v0.2d, v1.2d, v2.2s
 
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        umull v0.8h, v1.8h, v2.8b
 // CHECK-ERROR:                        ^
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        umull v0.4s, v1.4s, v2.4h
 // CHECK-ERROR:                        ^
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        umull v0.2d, v1.2d, v2.2s
 // CHECK-ERROR:                        ^
 
         umull2 v0.8h, v1.16h, v2.16b
         umull2 v0.4s, v1.8s, v2.8h
         umull2 v0.2d, v1.4d, v2.4s
 
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-4]]:23: error: invalid vector kind qualifier
 // CHECK-ERROR:        umull2 v0.8h, v1.16h, v2.16b
-// CHECK-ERROR:                      ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-5]]:23: error: invalid vector kind qualifier
 // CHECK-ERROR:        umull2 v0.4s, v1.8s, v2.8h
-// CHECK-ERROR:                      ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-6]]:23: error: invalid vector kind qualifier
 // CHECK-ERROR:        umull2 v0.2d, v1.4d, v2.4s
-// CHECK-ERROR:                      ^
 
 //------------------------------------------------------------------------------
 // Long - Variant 2
 //------------------------------------------------------------------------------
 
         sqdmlal v0.4s, v1.4s, v2.4h
         sqdmlal v0.2d, v1.2d, v2.2s
 
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        sqdmlal v0.4s, v1.4s, v2.4h
 // CHECK-ERROR:                          ^
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        sqdmlal v0.2d, v1.2d, v2.2s
 // CHECK-ERROR:                          ^
 
         sqdmlal2 v0.4s, v1.8s, v2.8h
         sqdmlal2 v0.2d, v1.4d, v2.4s
 
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-3]]:25: error: invalid vector kind qualifier
 // CHECK-ERROR:        sqdmlal2 v0.4s, v1.8s, v2.8h
-// CHECK-ERROR:                        ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-4]]:25: error: invalid vector kind qualifier
 // CHECK-ERROR:        sqdmlal2 v0.2d, v1.4d, v2.4s
-// CHECK-ERROR:                        ^
 
         // Mismatched vector types
         sqdmlal v0.8h, v1.8b, v2.8b
         sqdmlal2 v0.8h, v1.16b, v2.16b
 
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        sqdmlal v0.8h, v1.8b, v2.8b
 // CHECK-ERROR:                   ^

 // CHECK-ERROR:                          ^
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        sqdmlsl v0.2d, v1.2d, v2.2s
 // CHECK-ERROR:                          ^
 
         sqdmlsl2 v0.4s, v1.8s, v2.8h
         sqdmlsl2 v0.2d, v1.4d, v2.4s
 
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-3]]:25: error: invalid vector kind qualifier
 // CHECK-ERROR:        sqdmlsl2 v0.4s, v1.8s, v2.8h
-// CHECK-ERROR:                        ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-4]]:25: error: invalid vector kind qualifier
 // CHECK-ERROR:        sqdmlsl2 v0.2d, v1.4d, v2.4s
-// CHECK-ERROR:                        ^
 
         // Mismatched vector types
         sqdmlsl v0.8h, v1.8b, v2.8b
         sqdmlsl2 v0.8h, v1.16b, v2.16b
 
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        sqdmlsl v0.8h, v1.8b, v2.8b
 // CHECK-ERROR:                   ^

 // CHECK-ERROR:                          ^
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        sqdmull v0.2d, v1.2d, v2.2s
 // CHECK-ERROR:                          ^
 
         sqdmull2 v0.4s, v1.8s, v2.8h
         sqdmull2 v0.2d, v1.4d, v2.4s
 
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-3]]:25: error: invalid vector kind qualifier
 // CHECK-ERROR:        sqdmull2 v0.4s, v1.8s, v2.8h
-// CHECK-ERROR:                        ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-4]]:25: error: invalid vector kind qualifier
 // CHECK-ERROR:        sqdmull2 v0.2d, v1.4d, v2.4s
-// CHECK-ERROR:                        ^
 
         // Mismatched vector types
         sqdmull v0.8h, v1.8b, v2.8b
         sqdmull2 v0.8h, v1.16b, v2.16b
 
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        sqdmull v0.8h, v1.8b, v2.8b
 // CHECK-ERROR:                   ^

 // CHECK-ERROR:        pmull v0.4s, v1.4h, v2.4h
 // CHECK-ERROR:                 ^
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        pmull v0.2d, v1.2s, v2.2s
 // CHECK-ERROR:                 ^
 
 
         pmull2 v0.8h, v1.16h, v2.16b
-
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-1]]:23: error: invalid vector kind qualifier
 // CHECK-ERROR:        pmull2 v0.8h, v1.16h, v2.16b
-// CHECK-ERROR:                      ^
 
         pmull2 v0.q, v1.2d, v2.2d
-        
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-1]]:16: error: invalid vector kind qualifier
 // CHECK-ERROR:        pmull2 v0.q, v1.2d, v2.2d
-// CHECK-ERROR:                  ^
 
         // Mismatched vector types
         pmull2 v0.4s, v1.8h v2.8h
         pmull2 v0.2d, v1.4s, v2.4s
 
 
 // CHECK-ERROR: error: unexpected token in argument list
 // CHECK-ERROR:        pmull2 v0.4s, v1.8h v2.8h

 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        saddw v0.2d, v1.2d, v2.2d
 // CHECK-ERROR:                               ^
 
         saddw2 v0.8h, v1.8h, v2.16h
         saddw2 v0.4s, v1.4s, v2.8s
         saddw2 v0.2d, v1.2d, v2.4d
 
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-4]]:30: error: invalid vector kind qualifier
 // CHECK-ERROR:        saddw2 v0.8h, v1.8h, v2.16h
-// CHECK-ERROR:                             ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-5]]:30: error: invalid vector kind qualifier
 // CHECK-ERROR:        saddw2 v0.4s, v1.4s, v2.8s
-// CHECK-ERROR:                             ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-6]]:30: error: invalid vector kind qualifier
 // CHECK-ERROR:        saddw2 v0.2d, v1.2d, v2.4d
-// CHECK-ERROR:                             ^
 
         uaddw v0.8h, v1.8h, v2.8h
         uaddw v0.4s, v1.4s, v2.4s
         uaddw v0.2d, v1.2d, v2.2d
 
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        uaddw v0.8h, v1.8h, v2.8h
 // CHECK-ERROR:                               ^
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        uaddw v0.4s, v1.4s, v2.4s
 // CHECK-ERROR:                               ^
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        uaddw v0.2d, v1.2d, v2.2d
 // CHECK-ERROR:                               ^
 
         uaddw2 v0.8h, v1.8h, v2.16h
         uaddw2 v0.4s, v1.4s, v2.8s
         uaddw2 v0.2d, v1.2d, v2.4d
 
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-4]]:30: error: invalid vector kind qualifier
 // CHECK-ERROR:        uaddw2 v0.8h, v1.8h, v2.16h
-// CHECK-ERROR:                             ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-5]]:30: error: invalid vector kind qualifier
 // CHECK-ERROR:        uaddw2 v0.4s, v1.4s, v2.8s
-// CHECK-ERROR:                             ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-6]]:30: error: invalid vector kind qualifier
 // CHECK-ERROR:        uaddw2 v0.2d, v1.2d, v2.4d
-// CHECK-ERROR:                             ^
 
         ssubw v0.8h, v1.8h, v2.8h
         ssubw v0.4s, v1.4s, v2.4s
         ssubw v0.2d, v1.2d, v2.2d
 
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        ssubw v0.8h, v1.8h, v2.8h
 // CHECK-ERROR:                               ^
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        ssubw v0.4s, v1.4s, v2.4s
 // CHECK-ERROR:                               ^
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        ssubw v0.2d, v1.2d, v2.2d
 // CHECK-ERROR:                               ^
 
         ssubw2 v0.8h, v1.8h, v2.16h
         ssubw2 v0.4s, v1.4s, v2.8s
         ssubw2 v0.2d, v1.2d, v2.4d
 
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-4]]:30: error: invalid vector kind qualifier
 // CHECK-ERROR:        ssubw2 v0.8h, v1.8h, v2.16h
-// CHECK-ERROR:                             ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-5]]:30: error: invalid vector kind qualifier
 // CHECK-ERROR:        ssubw2 v0.4s, v1.4s, v2.8s
-// CHECK-ERROR:                             ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-6]]:30: error: invalid vector kind qualifier
 // CHECK-ERROR:        ssubw2 v0.2d, v1.2d, v2.4d
-// CHECK-ERROR:                             ^
 
         usubw v0.8h, v1.8h, v2.8h
         usubw v0.4s, v1.4s, v2.4s
         usubw v0.2d, v1.2d, v2.2d
 
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        usubw v0.8h, v1.8h, v2.8h
 // CHECK-ERROR:                               ^
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        usubw v0.4s, v1.4s, v2.4s
 // CHECK-ERROR:                               ^
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        usubw v0.2d, v1.2d, v2.2d
 // CHECK-ERROR:                               ^
 
         usubw2 v0.8h, v1.8h, v2.16h
         usubw2 v0.4s, v1.4s, v2.8s
         usubw2 v0.2d, v1.2d, v2.4d
 
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-4]]:30: error: invalid vector kind qualifier
 // CHECK-ERROR:        usubw2 v0.8h, v1.8h, v2.16h
-// CHECK-ERROR:                             ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-5]]:30: error: invalid vector kind qualifier
 // CHECK-ERROR:        usubw2 v0.4s, v1.4s, v2.8s
-// CHECK-ERROR:                             ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-6]]:30: error: invalid vector kind qualifier
 // CHECK-ERROR:        usubw2 v0.2d, v1.2d, v2.4d
-// CHECK-ERROR:                             ^
 
 //------------------------------------------------------------------------------
 // Narrow
 //------------------------------------------------------------------------------
 
         addhn v0.8b, v1.8h, v2.8d
         addhn v0.4h, v1.4s, v2.4h
         addhn v0.2s, v1.2d, v2.2s
 
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-4]]:29: error: invalid vector kind qualifier
 // CHECK-ERROR:        addhn v0.8b, v1.8h, v2.8d
-// CHECK-ERROR:                            ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-5]]:29: error: invalid operand for instruction
 // CHECK-ERROR:        addhn v0.4h, v1.4s, v2.4h
-// CHECK-ERROR:                               ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: [[@LINE-6]]:29: error: invalid operand for instruction
 // CHECK-ERROR:        addhn v0.2s, v1.2d, v2.2s
-// CHECK-ERROR:                               ^
 
         addhn2 v0.16b, v1.8h, v2.8b
         addhn2 v0.8h, v1.4s, v2.4h
         addhn2 v0.4s, v1.2d, v2.2s
 
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        addhn2 v0.16b, v1.8h, v2.8b
 // CHECK-ERROR:                                 ^

 // CHECK-ERROR:         dup v11.4h, h14
 // CHECK-ERROR:                     ^
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:         dup v17.2s, s30
 // CHECK-ERROR:                     ^
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:         dup v1.16b, d2
 // CHECK-ERROR:                     ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid vector kind qualifier
 // CHECK-ERROR:         dup v11.8s, w16
 // CHECK-ERROR:             ^
-// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid vector kind qualifier
 // CHECK-ERROR:         dup v17.4d, w28
 // CHECK-ERROR:             ^
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:         dup v5.2d, w0
 // CHECK-ERROR:                    ^
 
 //----------------------------------------------------------------------
 // Scalar Compare Bitwise Equal

 // CHECK-ERROR:                ^
 
 
 //----------------------------------------------------------------------
 // Permutation with 3 vectors
 //----------------------------------------------------------------------
 
         uzp1 v0.16b, v1.8b, v2.8b
+// CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction
         uzp1 v0.8b, v1.4b, v2.4b
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
         uzp1 v0.8h, v1.4h, v2.4h
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         uzp1 v0.4h, v1.2h, v2.2h
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         uzp1 v0.4s, v1.2s, v2.2s
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         uzp1 v0.2s, v1.1s, v2.1s
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
         uzp1 v0.2d, v1.1d, v2.1d
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         uzp1 v0.1d, v1.1d, v2.1d
+// CHECK-ERROR: [[@LINE-1]]:14: error: invalid operand for instruction
+
 
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         uzp1 v0.16b, v1.8b, v2.8b
-// CHECK-ERROR:                      ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         uzp1 v0.8b, v1.4b, v2.4b
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         uzp1 v0.8h, v1.4h, v2.4h
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         uzp1 v0.4h, v1.2h, v2.2h
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         uzp1 v0.4s, v1.2s, v2.2s
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         uzp1 v0.2s, v1.1s, v2.1s
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         uzp1 v0.2d, v1.1d, v2.1d
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         uzp1 v0.1d, v1.1d, v2.1d
-// CHECK-ERROR:                 ^
 
         uzp2 v0.16b, v1.8b, v2.8b
+// CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction
         uzp2 v0.8b, v1.4b, v2.4b
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
         uzp2 v0.8h, v1.4h, v2.4h
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         uzp2 v0.4h, v1.2h, v2.2h
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         uzp2 v0.4s, v1.2s, v2.2s
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         uzp2 v0.2s, v1.1s, v2.1s
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
         uzp2 v0.2d, v1.1d, v2.1d
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         uzp2 v0.1d, v1.1d, v2.1d
+// CHECK-ERROR: [[@LINE-1]]:14: error: invalid operand for instruction
+
 
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         uzp2 v0.16b, v1.8b, v2.8b
-// CHECK-ERROR:                      ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         uzp2 v0.8b, v1.4b, v2.4b
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         uzp2 v0.8h, v1.4h, v2.4h
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         uzp2 v0.4h, v1.2h, v2.2h
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         uzp2 v0.4s, v1.2s, v2.2s
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         uzp2 v0.2s, v1.1s, v2.1s
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         uzp2 v0.2d, v1.1d, v2.1d
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         uzp2 v0.1d, v1.1d, v2.1d
-// CHECK-ERROR:                 ^
 
         zip1 v0.16b, v1.8b, v2.8b
+// CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction
         zip1 v0.8b, v1.4b, v2.4b
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
         zip1 v0.8h, v1.4h, v2.4h
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         zip1 v0.4h, v1.2h, v2.2h
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         zip1 v0.4s, v1.2s, v2.2s
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         zip1 v0.2s, v1.1s, v2.1s
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
         zip1 v0.2d, v1.1d, v2.1d
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         zip1 v0.1d, v1.1d, v2.1d
+// CHECK-ERROR: [[@LINE-1]]:14: error: invalid operand for instruction
 
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         zip1 v0.16b, v1.8b, v2.8b
-// CHECK-ERROR:                      ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         zip1 v0.8b, v1.4b, v2.4b
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         zip1 v0.8h, v1.4h, v2.4h
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         zip1 v0.4h, v1.2h, v2.2h
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         zip1 v0.4s, v1.2s, v2.2s
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         zip1 v0.2s, v1.1s, v2.1s
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         zip1 v0.2d, v1.1d, v2.1d
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         zip1 v0.1d, v1.1d, v2.1d
-// CHECK-ERROR:                 ^
 
+\
         zip2 v0.16b, v1.8b, v2.8b
+// CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction
         zip2 v0.8b, v1.4b, v2.4b
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
         zip2 v0.8h, v1.4h, v2.4h
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         zip2 v0.4h, v1.2h, v2.2h
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         zip2 v0.4s, v1.2s, v2.2s
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         zip2 v0.2s, v1.1s, v2.1s
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
         zip2 v0.2d, v1.1d, v2.1d
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         zip2 v0.1d, v1.1d, v2.1d
+// CHECK-ERROR: [[@LINE-1]]:14: error: invalid operand for instruction
+
 
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         zip2 v0.16b, v1.8b, v2.8b
-// CHECK-ERROR:                      ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         zip2 v0.8b, v1.4b, v2.4b
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         zip2 v0.8h, v1.4h, v2.4h
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         zip2 v0.4h, v1.2h, v2.2h
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         zip2 v0.4s, v1.2s, v2.2s
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         zip2 v0.2s, v1.1s, v2.1s
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         zip2 v0.2d, v1.1d, v2.1d
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         zip2 v0.1d, v1.1d, v2.1d
-// CHECK-ERROR:                 ^
 
         trn1 v0.16b, v1.8b, v2.8b
+// CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction
         trn1 v0.8b, v1.4b, v2.4b
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
         trn1 v0.8h, v1.4h, v2.4h
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         trn1 v0.4h, v1.2h, v2.2h
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         trn1 v0.4s, v1.2s, v2.2s
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         trn1 v0.2s, v1.1s, v2.1s
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
         trn1 v0.2d, v1.1d, v2.1d
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         trn1 v0.1d, v1.1d, v2.1d
+// CHECK-ERROR: [[@LINE-1]]:14: error: invalid operand for instruction
+
 
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         trn1 v0.16b, v1.8b, v2.8b
-// CHECK-ERROR:                      ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         trn1 v0.8b, v1.4b, v2.4b
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         trn1 v0.8h, v1.4h, v2.4h
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         trn1 v0.4h, v1.2h, v2.2h
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         trn1 v0.4s, v1.2s, v2.2s
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         trn1 v0.2s, v1.1s, v2.1s
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         trn1 v0.2d, v1.1d, v2.1d
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         trn1 v0.1d, v1.1d, v2.1d
-// CHECK-ERROR:                 ^
 
         trn2 v0.16b, v1.8b, v2.8b
+// CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction
         trn2 v0.8b, v1.4b, v2.4b
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
         trn2 v0.8h, v1.4h, v2.4h
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         trn2 v0.4h, v1.2h, v2.2h
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         trn2 v0.4s, v1.2s, v2.2s
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         trn2 v0.2s, v1.1s, v2.1s
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
         trn2 v0.2d, v1.1d, v2.1d
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         trn2 v0.1d, v1.1d, v2.1d
-
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         trn2 v0.16b, v1.8b, v2.8b
-// CHECK-ERROR:                      ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         trn2 v0.8b, v1.4b, v2.4b
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         trn2 v0.8h, v1.4h, v2.4h
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         trn2 v0.4h, v1.2h, v2.2h
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         trn2 v0.4s, v1.2s, v2.2s
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         trn2 v0.2s, v1.1s, v2.1s
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         trn2 v0.2d, v1.1d, v2.1d
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         trn2 v0.1d, v1.1d, v2.1d
-// CHECK-ERROR:                 ^
+// CHECK-ERROR: [[@LINE-1]]:14: error: invalid operand for instruction
 
 //----------------------------------------------------------------------
 // Permutation with 3 vectors
 //----------------------------------------------------------------------
 
         uzp1 v0.16b, v1.8b, v2.8b
+// CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction
         uzp1 v0.8b, v1.4b, v2.4b
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
         uzp1 v0.8h, v1.4h, v2.4h
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         uzp1 v0.4h, v1.2h, v2.2h
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         uzp1 v0.4s, v1.2s, v2.2s
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         uzp1 v0.2s, v1.1s, v2.1s
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
         uzp1 v0.2d, v1.1d, v2.1d
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         uzp1 v0.1d, v1.1d, v2.1d
-
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         uzp1 v0.16b, v1.8b, v2.8b
-// CHECK-ERROR:                      ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         uzp1 v0.8b, v1.4b, v2.4b
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         uzp1 v0.8h, v1.4h, v2.4h
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         uzp1 v0.4h, v1.2h, v2.2h
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         uzp1 v0.4s, v1.2s, v2.2s
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         uzp1 v0.2s, v1.1s, v2.1s
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         uzp1 v0.2d, v1.1d, v2.1d
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         uzp1 v0.1d, v1.1d, v2.1d
-// CHECK-ERROR:                 ^
+// CHECK-ERROR: [[@LINE-1]]:14: error: invalid operand for instruction
 
         uzp2 v0.16b, v1.8b, v2.8b
+// CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction
         uzp2 v0.8b, v1.4b, v2.4b
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
         uzp2 v0.8h, v1.4h, v2.4h
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         uzp2 v0.4h, v1.2h, v2.2h
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         uzp2 v0.4s, v1.2s, v2.2s
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         uzp2 v0.2s, v1.1s, v2.1s
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
         uzp2 v0.2d, v1.1d, v2.1d
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         uzp2 v0.1d, v1.1d, v2.1d
-
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         uzp2 v0.16b, v1.8b, v2.8b
-// CHECK-ERROR:                      ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         uzp2 v0.8b, v1.4b, v2.4b
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         uzp2 v0.8h, v1.4h, v2.4h
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         uzp2 v0.4h, v1.2h, v2.2h
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         uzp2 v0.4s, v1.2s, v2.2s
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         uzp2 v0.2s, v1.1s, v2.1s
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         uzp2 v0.2d, v1.1d, v2.1d
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         uzp2 v0.1d, v1.1d, v2.1d
-// CHECK-ERROR:                 ^
+// CHECK-ERROR: [[@LINE-1]]:14: error: invalid operand for instruction
 
         zip1 v0.16b, v1.8b, v2.8b
+// CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction
         zip1 v0.8b, v1.4b, v2.4b
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
         zip1 v0.8h, v1.4h, v2.4h
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         zip1 v0.4h, v1.2h, v2.2h
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         zip1 v0.4s, v1.2s, v2.2s
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         zip1 v0.2s, v1.1s, v2.1s
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
         zip1 v0.2d, v1.1d, v2.1d
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         zip1 v0.1d, v1.1d, v2.1d
+// CHECK-ERROR: [[@LINE-1]]:14: error: invalid operand for instruction
+
+
+
 
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         zip1 v0.16b, v1.8b, v2.8b
-// CHECK-ERROR:                      ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         zip1 v0.8b, v1.4b, v2.4b
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         zip1 v0.8h, v1.4h, v2.4h
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         zip1 v0.4h, v1.2h, v2.2h
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         zip1 v0.4s, v1.2s, v2.2s
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         zip1 v0.2s, v1.1s, v2.1s
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         zip1 v0.2d, v1.1d, v2.1d
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         zip1 v0.1d, v1.1d, v2.1d
-// CHECK-ERROR:                 ^
 
         zip2 v0.16b, v1.8b, v2.8b
+// CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction
         zip2 v0.8b, v1.4b, v2.4b
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
         zip2 v0.8h, v1.4h, v2.4h
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         zip2 v0.4h, v1.2h, v2.2h
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         zip2 v0.4s, v1.2s, v2.2s
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         zip2 v0.2s, v1.1s, v2.1s
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
         zip2 v0.2d, v1.1d, v2.1d
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         zip2 v0.1d, v1.1d, v2.1d
+// CHECK-ERROR: [[@LINE-1]]:14: error: invalid operand for instruction
+
+
 
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         zip2 v0.16b, v1.8b, v2.8b
-// CHECK-ERROR:                      ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         zip2 v0.8b, v1.4b, v2.4b
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         zip2 v0.8h, v1.4h, v2.4h
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         zip2 v0.4h, v1.2h, v2.2h
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         zip2 v0.4s, v1.2s, v2.2s
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         zip2 v0.2s, v1.1s, v2.1s
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         zip2 v0.2d, v1.1d, v2.1d
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         zip2 v0.1d, v1.1d, v2.1d
-// CHECK-ERROR:                 ^
 
         trn1 v0.16b, v1.8b, v2.8b
+// CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction
         trn1 v0.8b, v1.4b, v2.4b
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
         trn1 v0.8h, v1.4h, v2.4h
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         trn1 v0.4h, v1.2h, v2.2h
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         trn1 v0.4s, v1.2s, v2.2s
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         trn1 v0.2s, v1.1s, v2.1s
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
         trn1 v0.2d, v1.1d, v2.1d
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         trn1 v0.1d, v1.1d, v2.1d
+// CHECK-ERROR: [[@LINE-1]]:14: error: invalid operand for instruction
+
 
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         trn1 v0.16b, v1.8b, v2.8b
-// CHECK-ERROR:                      ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         trn1 v0.8b, v1.4b, v2.4b
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         trn1 v0.8h, v1.4h, v2.4h
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         trn1 v0.4h, v1.2h, v2.2h
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         trn1 v0.4s, v1.2s, v2.2s
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         trn1 v0.2s, v1.1s, v2.1s
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         trn1 v0.2d, v1.1d, v2.1d
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         trn1 v0.1d, v1.1d, v2.1d
-// CHECK-ERROR:                 ^
 
         trn2 v0.16b, v1.8b, v2.8b
+// CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction
         trn2 v0.8b, v1.4b, v2.4b
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
         trn2 v0.8h, v1.4h, v2.4h
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         trn2 v0.4h, v1.2h, v2.2h
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         trn2 v0.4s, v1.2s, v2.2s
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         trn2 v0.2s, v1.1s, v2.1s
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
         trn2 v0.2d, v1.1d, v2.1d
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         trn2 v0.1d, v1.1d, v2.1d
+// CHECK-ERROR: [[@LINE-1]]:14: error: invalid operand for instruction
+
 
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         trn2 v0.16b, v1.8b, v2.8b
-// CHECK-ERROR:                      ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         trn2 v0.8b, v1.4b, v2.4b
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         trn2 v0.8h, v1.4h, v2.4h
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         trn2 v0.4h, v1.2h, v2.2h
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         trn2 v0.4s, v1.2s, v2.2s
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         trn2 v0.2s, v1.1s, v2.1s
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         trn2 v0.2d, v1.1d, v2.1d
-// CHECK-ERROR:                     ^
-// CHECK-ERROR:  error: invalid operand for instruction
-// CHECK-ERROR:         trn2 v0.1d, v1.1d, v2.1d
-// CHECK-ERROR:                 ^
 
 //----------------------------------------------------------------------
 // Floating Point  multiply (scalar, by element)
 //----------------------------------------------------------------------
       // mismatched and invalid vector types
       fmul    s0, s1, v1.h[0]
       fmul    h0, h1, v1.s[0]
       // invalid lane